1 /*
2 * rcar_du_group.c -- R-Car Display Unit Channels Pair
3 *
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
5 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 /*
15 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
16 * unit, timings generator, ...) and device-global resources (start/stop
17 * control, planes, ...) shared between the two CRTCs.
18 *
19 * The R8A7790 introduced a third CRTC with its own set of global resources.
20 * This would be modeled as two separate DU device instances if it wasn't for
21 * a handful or resources that are shared between the three CRTCs (mostly
22 * related to input and output routing). For this reason the R8A7790 DU must be
23 * modeled as a single device with three CRTCs, two sets of "semi-global"
24 * resources, and a few device-global resources.
25 *
26 * The rcar_du_group object is a driver specific object, without any real
27 * counterpart in the DU documentation, that models those semi-global resources.
28 */
29
30 #include <linux/clk.h>
31 #include <linux/io.h>
32
33 #include "rcar_du_drv.h"
34 #include "rcar_du_group.h"
35 #include "rcar_du_regs.h"
36
rcar_du_group_read(struct rcar_du_group * rgrp,u32 reg)37 u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
38 {
39 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
40 }
41
rcar_du_group_write(struct rcar_du_group * rgrp,u32 reg,u32 data)42 void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
43 {
44 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
45 }
46
rcar_du_group_setup_pins(struct rcar_du_group * rgrp)47 static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
48 {
49 u32 defr6 = DEFR6_CODE;
50
51 if (rgrp->channels_mask & BIT(0))
52 defr6 |= DEFR6_ODPM02_DISP;
53
54 if (rgrp->channels_mask & BIT(1))
55 defr6 |= DEFR6_ODPM12_DISP;
56
57 rcar_du_group_write(rgrp, DEFR6, defr6);
58 }
59
rcar_du_group_setup_defr8(struct rcar_du_group * rgrp)60 static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
61 {
62 struct rcar_du_device *rcdu = rgrp->dev;
63 unsigned int possible_crtcs =
64 rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
65 u32 defr8 = DEFR8_CODE;
66
67 if (rcdu->info->gen < 3) {
68 defr8 |= DEFR8_DEFE8;
69
70 /*
71 * On Gen2 the DEFR8 register for the first group also controls
72 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for
73 * DU instances that support it.
74 */
75 if (rgrp->index == 0) {
76 if (possible_crtcs > 1)
77 defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
78 if (rgrp->dev->vspd1_sink == 2)
79 defr8 |= DEFR8_VSCS;
80 }
81 } else {
82 /*
83 * On Gen3 VSPD routing can't be configured, but DPAD routing
84 * needs to be set despite having a single option available.
85 */
86 unsigned int rgb_crtc = ffs(possible_crtcs) - 1;
87 struct rcar_du_crtc *crtc = &rcdu->crtcs[rgb_crtc];
88
89 if (crtc->index / 2 == rgrp->index)
90 defr8 |= DEFR8_DRGBS_DU(crtc->index);
91 }
92
93 rcar_du_group_write(rgrp, DEFR8, defr8);
94 }
95
rcar_du_group_setup(struct rcar_du_group * rgrp)96 static void rcar_du_group_setup(struct rcar_du_group *rgrp)
97 {
98 struct rcar_du_device *rcdu = rgrp->dev;
99
100 /* Enable extended features */
101 rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
102 if (rcdu->info->gen < 3) {
103 rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
104 rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
105 rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
106 }
107 rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
108
109 rcar_du_group_setup_pins(rgrp);
110
111 if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
112 rcar_du_group_setup_defr8(rgrp);
113
114 /*
115 * Configure input dot clock routing. We currently hardcode the
116 * configuration to routing DOTCLKINn to DUn. Register fields
117 * depend on the DU generation, but the resulting value is 0 in
118 * all cases.
119 *
120 * On Gen2 a single register in the first group controls dot
121 * clock selection for all channels, while on Gen3 dot clocks
122 * are setup through per-group registers, only available when
123 * the group has two channels.
124 */
125 if ((rcdu->info->gen < 3 && rgrp->index == 0) ||
126 (rcdu->info->gen == 3 && rgrp->num_crtcs > 1))
127 rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE);
128 }
129
130 if (rcdu->info->gen >= 3)
131 rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
132
133 /*
134 * Use DS1PR and DS2PR to configure planes priorities and connects the
135 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
136 */
137 rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
138
139 /* Apply planes to CRTCs association. */
140 mutex_lock(&rgrp->lock);
141 rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
142 rgrp->dptsr_planes);
143 mutex_unlock(&rgrp->lock);
144 }
145
146 /*
147 * rcar_du_group_get - Acquire a reference to the DU channels group
148 *
149 * Acquiring the first reference setups core registers. A reference must be held
150 * before accessing any hardware registers.
151 *
152 * This function must be called with the DRM mode_config lock held.
153 *
154 * Return 0 in case of success or a negative error code otherwise.
155 */
rcar_du_group_get(struct rcar_du_group * rgrp)156 int rcar_du_group_get(struct rcar_du_group *rgrp)
157 {
158 if (rgrp->use_count)
159 goto done;
160
161 rcar_du_group_setup(rgrp);
162
163 done:
164 rgrp->use_count++;
165 return 0;
166 }
167
168 /*
169 * rcar_du_group_put - Release a reference to the DU
170 *
171 * This function must be called with the DRM mode_config lock held.
172 */
rcar_du_group_put(struct rcar_du_group * rgrp)173 void rcar_du_group_put(struct rcar_du_group *rgrp)
174 {
175 --rgrp->use_count;
176 }
177
__rcar_du_group_start_stop(struct rcar_du_group * rgrp,bool start)178 static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
179 {
180 rcar_du_group_write(rgrp, DSYSR,
181 (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
182 (start ? DSYSR_DEN : DSYSR_DRES));
183 }
184
rcar_du_group_start_stop(struct rcar_du_group * rgrp,bool start)185 void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
186 {
187 /*
188 * Many of the configuration bits are only updated when the display
189 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
190 * of those bits could be pre-configured, but others (especially the
191 * bits related to plane assignment to display timing controllers) need
192 * to be modified at runtime.
193 *
194 * Restart the display controller if a start is requested. Sorry for the
195 * flicker. It should be possible to move most of the "DRES-update" bits
196 * setup to driver initialization time and minimize the number of cases
197 * when the display controller will have to be restarted.
198 */
199 if (start) {
200 if (rgrp->used_crtcs++ != 0)
201 __rcar_du_group_start_stop(rgrp, false);
202 __rcar_du_group_start_stop(rgrp, true);
203 } else {
204 if (--rgrp->used_crtcs == 0)
205 __rcar_du_group_start_stop(rgrp, false);
206 }
207 }
208
rcar_du_group_restart(struct rcar_du_group * rgrp)209 void rcar_du_group_restart(struct rcar_du_group *rgrp)
210 {
211 rgrp->need_restart = false;
212
213 __rcar_du_group_start_stop(rgrp, false);
214 __rcar_du_group_start_stop(rgrp, true);
215 }
216
rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device * rcdu)217 int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
218 {
219 struct rcar_du_group *rgrp;
220 struct rcar_du_crtc *crtc;
221 unsigned int index;
222 int ret;
223
224 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
225 return 0;
226
227 /*
228 * RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
229 * configured in the DEFR8 register of the first group on Gen2 and the
230 * last group on Gen3. As this function can be called with the DU
231 * channels of the corresponding CRTCs disabled, we need to enable the
232 * group clock before accessing the register.
233 */
234 index = rcdu->info->gen < 3 ? 0 : DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1;
235 rgrp = &rcdu->groups[index];
236 crtc = &rcdu->crtcs[index * 2];
237
238 ret = clk_prepare_enable(crtc->clock);
239 if (ret < 0)
240 return ret;
241
242 rcar_du_group_setup_defr8(rgrp);
243
244 clk_disable_unprepare(crtc->clock);
245
246 return 0;
247 }
248
rcar_du_group_set_routing(struct rcar_du_group * rgrp)249 int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
250 {
251 struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
252 u32 dorcr = rcar_du_group_read(rgrp, DORCR);
253
254 dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
255
256 /*
257 * Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
258 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
259 * by default.
260 */
261 if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
262 dorcr |= DORCR_PG2D_DS1;
263 else
264 dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
265
266 rcar_du_group_write(rgrp, DORCR, dorcr);
267
268 return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
269 }
270
