1 // SPDX-License-Identifier: MIT
2 
3 #include <drm/drm_debugfs.h>
4 #include <drm/drm_dp_mst_helper.h>
5 #include <drm/drm_fb_helper.h>
6 #include <drm/drm_file.h>
7 #include <drm/drm_probe_helper.h>
8 
9 #include "atom.h"
10 #include "ni_reg.h"
11 #include "radeon.h"
12 
13 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
14 
radeon_atom_set_enc_offset(int id)15 static int radeon_atom_set_enc_offset(int id)
16 {
17 	static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
18 				       EVERGREEN_CRTC1_REGISTER_OFFSET,
19 				       EVERGREEN_CRTC2_REGISTER_OFFSET,
20 				       EVERGREEN_CRTC3_REGISTER_OFFSET,
21 				       EVERGREEN_CRTC4_REGISTER_OFFSET,
22 				       EVERGREEN_CRTC5_REGISTER_OFFSET,
23 				       0x13830 - 0x7030 };
24 
25 	return offsets[id];
26 }
27 
radeon_dp_mst_set_be_cntl(struct radeon_encoder * primary,struct radeon_encoder_mst * mst_enc,enum radeon_hpd_id hpd,bool enable)28 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
29 				     struct radeon_encoder_mst *mst_enc,
30 				     enum radeon_hpd_id hpd, bool enable)
31 {
32 	struct drm_device *dev = primary->base.dev;
33 	struct radeon_device *rdev = dev->dev_private;
34 	uint32_t reg;
35 	int retries = 0;
36 	uint32_t temp;
37 
38 	reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
39 
40 	/* set MST mode */
41 	reg &= ~NI_DIG_FE_DIG_MODE(7);
42 	reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
43 
44 	if (enable)
45 		reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
46 	else
47 		reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
48 
49 	reg |= NI_DIG_HPD_SELECT(hpd);
50 	DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
51 	WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
52 
53 	if (enable) {
54 		uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
55 
56 		do {
57 			temp = RREG32(NI_DIG_FE_CNTL + offset);
58 		} while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
59 		if (retries == 10000)
60 			DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
61 	}
62 	return 0;
63 }
64 
radeon_dp_mst_set_stream_attrib(struct radeon_encoder * primary,int stream_number,int fe,int slots)65 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
66 					   int stream_number,
67 					   int fe,
68 					   int slots)
69 {
70 	struct drm_device *dev = primary->base.dev;
71 	struct radeon_device *rdev = dev->dev_private;
72 	u32 temp, val;
73 	int retries  = 0;
74 	int satreg, satidx;
75 
76 	satreg = stream_number >> 1;
77 	satidx = stream_number & 1;
78 
79 	temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
80 
81 	val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
82 
83 	val <<= (16 * satidx);
84 
85 	temp &= ~(0xffff << (16 * satidx));
86 
87 	temp |= val;
88 
89 	DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
90 	WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
91 
92 	WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
93 
94 	do {
95 		unsigned value1, value2;
96 		udelay(10);
97 		temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
98 
99 		value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
100 		value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
101 
102 		if (!value1 && !value2)
103 			break;
104 	} while (retries++ < 50);
105 
106 	if (retries == 10000)
107 		DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
108 
109 	/* MTP 16 ? */
110 	return 0;
111 }
112 
radeon_dp_mst_update_stream_attribs(struct radeon_connector * mst_conn,struct radeon_encoder * primary)113 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
114 					       struct radeon_encoder *primary)
115 {
116 	struct drm_device *dev = mst_conn->base.dev;
117 	struct stream_attribs new_attribs[6];
118 	int i;
119 	int idx = 0;
120 	struct radeon_connector *radeon_connector;
121 	struct drm_connector *connector;
122 
123 	memset(new_attribs, 0, sizeof(new_attribs));
124 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
125 		struct radeon_encoder *subenc;
126 		struct radeon_encoder_mst *mst_enc;
127 
128 		radeon_connector = to_radeon_connector(connector);
129 		if (!radeon_connector->is_mst_connector)
130 			continue;
131 
132 		if (radeon_connector->mst_port != mst_conn)
133 			continue;
134 
135 		subenc = radeon_connector->mst_encoder;
136 		mst_enc = subenc->enc_priv;
137 
138 		if (!mst_enc->enc_active)
139 			continue;
140 
141 		new_attribs[idx].fe = mst_enc->fe;
142 		new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
143 		idx++;
144 	}
145 
146 	for (i = 0; i < idx; i++) {
147 		if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
148 		    new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
149 			radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
150 			mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
151 			mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
152 		}
153 	}
154 
155 	for (i = idx; i < mst_conn->enabled_attribs; i++) {
156 		radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
157 		mst_conn->cur_stream_attribs[i].fe = 0;
158 		mst_conn->cur_stream_attribs[i].slots = 0;
159 	}
160 	mst_conn->enabled_attribs = idx;
161 	return 0;
162 }
163 
radeon_dp_mst_set_vcp_size(struct radeon_encoder * mst,s64 avg_time_slots_per_mtp)164 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
165 {
166 	struct drm_device *dev = mst->base.dev;
167 	struct radeon_device *rdev = dev->dev_private;
168 	struct radeon_encoder_mst *mst_enc = mst->enc_priv;
169 	uint32_t val, temp;
170 	uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
171 	int retries = 0;
172 	uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
173 	uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
174 
175 	val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
176 
177 	WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
178 
179 	do {
180 		temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
181 		udelay(10);
182 	} while ((temp & 0x1) && (retries++ < 10000));
183 
184 	if (retries >= 10000)
185 		DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
186 	return 0;
187 }
188 
radeon_dp_mst_get_ddc_modes(struct drm_connector * connector)189 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
190 {
191 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
192 	struct radeon_connector *master = radeon_connector->mst_port;
193 	struct edid *edid;
194 	int ret = 0;
195 
196 	edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
197 	radeon_connector->edid = edid;
198 	DRM_DEBUG_KMS("edid retrieved %p\n", edid);
199 	if (radeon_connector->edid) {
200 		drm_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
201 		ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
202 		return ret;
203 	}
204 	drm_connector_update_edid_property(&radeon_connector->base, NULL);
205 
206 	return ret;
207 }
208 
radeon_dp_mst_get_modes(struct drm_connector * connector)209 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
210 {
211 	return radeon_dp_mst_get_ddc_modes(connector);
212 }
213 
214 static enum drm_mode_status
radeon_dp_mst_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)215 radeon_dp_mst_mode_valid(struct drm_connector *connector,
216 			struct drm_display_mode *mode)
217 {
218 	/* TODO - validate mode against available PBN for link */
219 	if (mode->clock < 10000)
220 		return MODE_CLOCK_LOW;
221 
222 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
223 		return MODE_H_ILLEGAL;
224 
225 	return MODE_OK;
226 }
227 
228 static struct
radeon_mst_best_encoder(struct drm_connector * connector)229 drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
230 {
231 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
232 
233 	return &radeon_connector->mst_encoder->base;
234 }
235 
236 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
237 	.get_modes = radeon_dp_mst_get_modes,
238 	.mode_valid = radeon_dp_mst_mode_valid,
239 	.best_encoder = radeon_mst_best_encoder,
240 };
241 
242 static enum drm_connector_status
radeon_dp_mst_detect(struct drm_connector * connector,bool force)243 radeon_dp_mst_detect(struct drm_connector *connector, bool force)
244 {
245 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
246 	struct radeon_connector *master = radeon_connector->mst_port;
247 
248 	return drm_dp_mst_detect_port(connector, &master->mst_mgr, radeon_connector->port);
249 }
250 
251 static void
radeon_dp_mst_connector_destroy(struct drm_connector * connector)252 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
253 {
254 	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
255 	struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
256 
257 	drm_encoder_cleanup(&radeon_encoder->base);
258 	kfree(radeon_encoder);
259 	drm_connector_cleanup(connector);
260 	kfree(radeon_connector);
261 }
262 
263 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
264 	.dpms = drm_helper_connector_dpms,
265 	.detect = radeon_dp_mst_detect,
266 	.fill_modes = drm_helper_probe_single_connector_modes,
267 	.destroy = radeon_dp_mst_connector_destroy,
268 };
269 
radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)270 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
271 							 struct drm_dp_mst_port *port,
272 							 const char *pathprop)
273 {
274 	struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
275 	struct drm_device *dev = master->base.dev;
276 	struct radeon_connector *radeon_connector;
277 	struct drm_connector *connector;
278 
279 	radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
280 	if (!radeon_connector)
281 		return NULL;
282 
283 	radeon_connector->is_mst_connector = true;
284 	connector = &radeon_connector->base;
285 	radeon_connector->port = port;
286 	radeon_connector->mst_port = master;
287 	DRM_DEBUG_KMS("\n");
288 
289 	drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
290 	drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
291 	radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
292 
293 	drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
294 	drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
295 	drm_connector_set_path_property(connector, pathprop);
296 
297 	return connector;
298 }
299 
radeon_dp_register_mst_connector(struct drm_connector * connector)300 static void radeon_dp_register_mst_connector(struct drm_connector *connector)
301 {
302 	struct drm_device *dev = connector->dev;
303 	struct radeon_device *rdev = dev->dev_private;
304 
305 	radeon_fb_add_connector(rdev, connector);
306 
307 	drm_connector_register(connector);
308 }
309 
radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_connector * connector)310 static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
311 					    struct drm_connector *connector)
312 {
313 	struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
314 	struct drm_device *dev = master->base.dev;
315 	struct radeon_device *rdev = dev->dev_private;
316 
317 	drm_connector_unregister(connector);
318 	radeon_fb_remove_connector(rdev, connector);
319 	drm_connector_cleanup(connector);
320 
321 	kfree(connector);
322 	DRM_DEBUG_KMS("\n");
323 }
324 
325 static const struct drm_dp_mst_topology_cbs mst_cbs = {
326 	.add_connector = radeon_dp_add_mst_connector,
327 	.register_connector = radeon_dp_register_mst_connector,
328 	.destroy_connector = radeon_dp_destroy_mst_connector,
329 };
330 
331 static struct
radeon_mst_find_connector(struct drm_encoder * encoder)332 radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
333 {
334 	struct drm_device *dev = encoder->dev;
335 	struct drm_connector *connector;
336 
337 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
338 		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
339 		if (!connector->encoder)
340 			continue;
341 		if (!radeon_connector->is_mst_connector)
342 			continue;
343 
344 		DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
345 		if (connector->encoder == encoder)
346 			return radeon_connector;
347 	}
348 	return NULL;
349 }
350 
radeon_dp_mst_prepare_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)351 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
352 {
353 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
354 	struct drm_device *dev = crtc->dev;
355 	struct radeon_device *rdev = dev->dev_private;
356 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
357 	struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
358 	struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
359 	int dp_clock;
360 	struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
361 
362 	if (radeon_connector) {
363 		radeon_connector->pixelclock_for_modeset = mode->clock;
364 		if (radeon_connector->base.display_info.bpc)
365 			radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
366 		else
367 			radeon_crtc->bpc = 8;
368 	}
369 
370 	DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
371 	dp_clock = dig_connector->dp_clock;
372 	radeon_crtc->ss_enabled =
373 		radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
374 						 ASIC_INTERNAL_SS_ON_DP,
375 						 dp_clock);
376 }
377 
378 static void
radeon_mst_encoder_dpms(struct drm_encoder * encoder,int mode)379 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
380 {
381 	struct drm_device *dev = encoder->dev;
382 	struct radeon_device *rdev = dev->dev_private;
383 	struct radeon_encoder *radeon_encoder, *primary;
384 	struct radeon_encoder_mst *mst_enc;
385 	struct radeon_encoder_atom_dig *dig_enc;
386 	struct radeon_connector *radeon_connector;
387 	struct drm_crtc *crtc;
388 	struct radeon_crtc *radeon_crtc;
389 	int ret, slots;
390 	s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
391 	if (!ASIC_IS_DCE5(rdev)) {
392 		DRM_ERROR("got mst dpms on non-DCE5\n");
393 		return;
394 	}
395 
396 	radeon_connector = radeon_mst_find_connector(encoder);
397 	if (!radeon_connector)
398 		return;
399 
400 	radeon_encoder = to_radeon_encoder(encoder);
401 
402 	mst_enc = radeon_encoder->enc_priv;
403 
404 	primary = mst_enc->primary;
405 
406 	dig_enc = primary->enc_priv;
407 
408 	crtc = encoder->crtc;
409 	DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
410 
411 	switch (mode) {
412 	case DRM_MODE_DPMS_ON:
413 		dig_enc->active_mst_links++;
414 
415 		radeon_crtc = to_radeon_crtc(crtc);
416 
417 		if (dig_enc->active_mst_links == 1) {
418 			mst_enc->fe = dig_enc->dig_encoder;
419 			mst_enc->fe_from_be = true;
420 			atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
421 
422 			atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
423 			atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
424 							0, 0, dig_enc->dig_encoder);
425 
426 			if (radeon_dp_needs_link_train(mst_enc->connector) ||
427 			    dig_enc->active_mst_links == 1) {
428 				radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
429 			}
430 
431 		} else {
432 			mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
433 			if (mst_enc->fe == -1)
434 				DRM_ERROR("failed to get frontend for dig encoder\n");
435 			mst_enc->fe_from_be = false;
436 			atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
437 		}
438 
439 		DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
440 			      dig_enc->linkb, radeon_crtc->crtc_id);
441 
442 		slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr,
443 					       mst_enc->pbn);
444 		ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
445 					       radeon_connector->port,
446 					       mst_enc->pbn, slots);
447 		ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
448 
449 		radeon_dp_mst_set_be_cntl(primary, mst_enc,
450 					  radeon_connector->mst_port->hpd.hpd, true);
451 
452 		mst_enc->enc_active = true;
453 		radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
454 
455 		fixed_pbn = drm_int2fixp(mst_enc->pbn);
456 		fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
457 		avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
458 		radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
459 
460 		atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
461 					    mst_enc->fe);
462 		ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
463 
464 		ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
465 
466 		break;
467 	case DRM_MODE_DPMS_STANDBY:
468 	case DRM_MODE_DPMS_SUSPEND:
469 	case DRM_MODE_DPMS_OFF:
470 		DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
471 
472 		if (!mst_enc->enc_active)
473 			return;
474 
475 		drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
476 		ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
477 
478 		drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
479 		/* and this can also fail */
480 		drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
481 
482 		drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
483 
484 		mst_enc->enc_active = false;
485 		radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
486 
487 		radeon_dp_mst_set_be_cntl(primary, mst_enc,
488 					  radeon_connector->mst_port->hpd.hpd, false);
489 		atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
490 					    mst_enc->fe);
491 
492 		if (!mst_enc->fe_from_be)
493 			radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
494 
495 		mst_enc->fe_from_be = false;
496 		dig_enc->active_mst_links--;
497 		if (dig_enc->active_mst_links == 0) {
498 			/* drop link */
499 		}
500 
501 		break;
502 	}
503 
504 }
505 
radeon_mst_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)506 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
507 				   const struct drm_display_mode *mode,
508 				   struct drm_display_mode *adjusted_mode)
509 {
510 	struct radeon_encoder_mst *mst_enc;
511 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
512 	struct radeon_connector_atom_dig *dig_connector;
513 	int bpp = 24;
514 
515 	mst_enc = radeon_encoder->enc_priv;
516 
517 	mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
518 
519 	mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
520 	DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
521 		      mst_enc->primary->active_device, mst_enc->primary->devices,
522 		      mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
523 
524 
525 	drm_mode_set_crtcinfo(adjusted_mode, 0);
526 	dig_connector = mst_enc->connector->con_priv;
527 	dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
528 	dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
529 	DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
530 		      dig_connector->dp_lane_count, dig_connector->dp_clock);
531 	return true;
532 }
533 
radeon_mst_encoder_prepare(struct drm_encoder * encoder)534 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
535 {
536 	struct radeon_connector *radeon_connector;
537 	struct radeon_encoder *radeon_encoder, *primary;
538 	struct radeon_encoder_mst *mst_enc;
539 	struct radeon_encoder_atom_dig *dig_enc;
540 
541 	radeon_connector = radeon_mst_find_connector(encoder);
542 	if (!radeon_connector) {
543 		DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
544 		return;
545 	}
546 	radeon_encoder = to_radeon_encoder(encoder);
547 
548 	radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
549 
550 	mst_enc = radeon_encoder->enc_priv;
551 
552 	primary = mst_enc->primary;
553 
554 	dig_enc = primary->enc_priv;
555 
556 	mst_enc->port = radeon_connector->port;
557 
558 	if (dig_enc->dig_encoder == -1) {
559 		dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
560 		primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
561 		atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
562 
563 
564 	}
565 	DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
566 }
567 
568 static void
radeon_mst_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)569 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
570 			     struct drm_display_mode *mode,
571 			     struct drm_display_mode *adjusted_mode)
572 {
573 	DRM_DEBUG_KMS("\n");
574 }
575 
radeon_mst_encoder_commit(struct drm_encoder * encoder)576 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
577 {
578 	radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
579 	DRM_DEBUG_KMS("\n");
580 }
581 
582 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
583 	.dpms = radeon_mst_encoder_dpms,
584 	.mode_fixup = radeon_mst_mode_fixup,
585 	.prepare = radeon_mst_encoder_prepare,
586 	.mode_set = radeon_mst_encoder_mode_set,
587 	.commit = radeon_mst_encoder_commit,
588 };
589 
radeon_dp_mst_encoder_destroy(struct drm_encoder * encoder)590 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
591 {
592 	drm_encoder_cleanup(encoder);
593 	kfree(encoder);
594 }
595 
596 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
597 	.destroy = radeon_dp_mst_encoder_destroy,
598 };
599 
600 static struct radeon_encoder *
radeon_dp_create_fake_mst_encoder(struct radeon_connector * connector)601 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
602 {
603 	struct drm_device *dev = connector->base.dev;
604 	struct radeon_device *rdev = dev->dev_private;
605 	struct radeon_encoder *radeon_encoder;
606 	struct radeon_encoder_mst *mst_enc;
607 	struct drm_encoder *encoder;
608 	const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
609 	struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
610 
611 	DRM_DEBUG_KMS("enc master is %p\n", enc_master);
612 	radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
613 	if (!radeon_encoder)
614 		return NULL;
615 
616 	radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
617 	if (!radeon_encoder->enc_priv) {
618 		kfree(radeon_encoder);
619 		return NULL;
620 	}
621 	encoder = &radeon_encoder->base;
622 	switch (rdev->num_crtc) {
623 	case 1:
624 		encoder->possible_crtcs = 0x1;
625 		break;
626 	case 2:
627 	default:
628 		encoder->possible_crtcs = 0x3;
629 		break;
630 	case 4:
631 		encoder->possible_crtcs = 0xf;
632 		break;
633 	case 6:
634 		encoder->possible_crtcs = 0x3f;
635 		break;
636 	}
637 
638 	drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
639 			 DRM_MODE_ENCODER_DPMST, NULL);
640 	drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
641 
642 	mst_enc = radeon_encoder->enc_priv;
643 	mst_enc->connector = connector;
644 	mst_enc->primary = to_radeon_encoder(enc_master);
645 	radeon_encoder->is_mst_encoder = true;
646 	return radeon_encoder;
647 }
648 
649 int
radeon_dp_mst_init(struct radeon_connector * radeon_connector)650 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
651 {
652 	struct drm_device *dev = radeon_connector->base.dev;
653 
654 	if (!radeon_connector->ddc_bus->has_aux)
655 		return 0;
656 
657 	radeon_connector->mst_mgr.cbs = &mst_cbs;
658 	return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
659 					    &radeon_connector->ddc_bus->aux, 16, 6,
660 					    radeon_connector->base.base.id);
661 }
662 
663 int
radeon_dp_mst_probe(struct radeon_connector * radeon_connector)664 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
665 {
666 	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
667 	struct drm_device *dev = radeon_connector->base.dev;
668 	struct radeon_device *rdev = dev->dev_private;
669 	int ret;
670 	u8 msg[1];
671 
672 	if (!radeon_mst)
673 		return 0;
674 
675 	if (!ASIC_IS_DCE5(rdev))
676 		return 0;
677 
678 	if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
679 		return 0;
680 
681 	ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
682 			       1);
683 	if (ret) {
684 		if (msg[0] & DP_MST_CAP) {
685 			DRM_DEBUG_KMS("Sink is MST capable\n");
686 			dig_connector->is_mst = true;
687 		} else {
688 			DRM_DEBUG_KMS("Sink is not MST capable\n");
689 			dig_connector->is_mst = false;
690 		}
691 
692 	}
693 	drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
694 					dig_connector->is_mst);
695 	return dig_connector->is_mst;
696 }
697 
698 int
radeon_dp_mst_check_status(struct radeon_connector * radeon_connector)699 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
700 {
701 	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
702 	int retry;
703 
704 	if (dig_connector->is_mst) {
705 		u8 esi[16] = { 0 };
706 		int dret;
707 		int ret = 0;
708 		bool handled;
709 
710 		dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
711 				       DP_SINK_COUNT_ESI, esi, 8);
712 go_again:
713 		if (dret == 8) {
714 			DRM_DEBUG_KMS("got esi %3ph\n", esi);
715 			ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
716 
717 			if (handled) {
718 				for (retry = 0; retry < 3; retry++) {
719 					int wret;
720 					wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
721 								 DP_SINK_COUNT_ESI + 1, &esi[1], 3);
722 					if (wret == 3)
723 						break;
724 				}
725 
726 				dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
727 							DP_SINK_COUNT_ESI, esi, 8);
728 				if (dret == 8) {
729 					DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
730 					goto go_again;
731 				}
732 			} else
733 				ret = 0;
734 
735 			return ret;
736 		} else {
737 			DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
738 			dig_connector->is_mst = false;
739 			drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
740 							dig_connector->is_mst);
741 			/* send a hotplug event */
742 		}
743 	}
744 	return -EINVAL;
745 }
746 
747 #if defined(CONFIG_DEBUG_FS)
748 
radeon_debugfs_mst_info(struct seq_file * m,void * data)749 static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
750 {
751 	struct drm_info_node *node = (struct drm_info_node *)m->private;
752 	struct drm_device *dev = node->minor->dev;
753 	struct drm_connector *connector;
754 	struct radeon_connector *radeon_connector;
755 	struct radeon_connector_atom_dig *dig_connector;
756 	int i;
757 
758 	drm_modeset_lock_all(dev);
759 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
760 		if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
761 			continue;
762 
763 		radeon_connector = to_radeon_connector(connector);
764 		dig_connector = radeon_connector->con_priv;
765 		if (radeon_connector->is_mst_connector)
766 			continue;
767 		if (!dig_connector->is_mst)
768 			continue;
769 		drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
770 
771 		for (i = 0; i < radeon_connector->enabled_attribs; i++)
772 			seq_printf(m, "attrib %d: %d %d\n", i,
773 				   radeon_connector->cur_stream_attribs[i].fe,
774 				   radeon_connector->cur_stream_attribs[i].slots);
775 	}
776 	drm_modeset_unlock_all(dev);
777 	return 0;
778 }
779 
780 static struct drm_info_list radeon_debugfs_mst_list[] = {
781 	{"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
782 };
783 #endif
784 
radeon_mst_debugfs_init(struct radeon_device * rdev)785 int radeon_mst_debugfs_init(struct radeon_device *rdev)
786 {
787 #if defined(CONFIG_DEBUG_FS)
788 	return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);
789 #endif
790 	return 0;
791 }
792