1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
69 #include <linux/dma-fence.h>
70
71 #ifdef CONFIG_MMU_NOTIFIER
72 #include <linux/mmu_notifier.h>
73 #endif
74
75 #include <drm/ttm/ttm_bo_api.h>
76 #include <drm/ttm/ttm_bo_driver.h>
77 #include <drm/ttm/ttm_placement.h>
78 #include <drm/ttm/ttm_module.h>
79 #include <drm/ttm/ttm_execbuf_util.h>
80
81 #include <drm/drm_gem.h>
82
83 #include "radeon_family.h"
84 #include "radeon_mode.h"
85 #include "radeon_reg.h"
86
87 /*
88 * Modules parameters.
89 */
90 extern int radeon_no_wb;
91 extern int radeon_modeset;
92 extern int radeon_dynclks;
93 extern int radeon_r4xx_atom;
94 extern int radeon_agpmode;
95 extern int radeon_vram_limit;
96 extern int radeon_gart_size;
97 extern int radeon_benchmarking;
98 extern int radeon_testing;
99 extern int radeon_connector_table;
100 extern int radeon_tv;
101 extern int radeon_audio;
102 extern int radeon_disp_priority;
103 extern int radeon_hw_i2c;
104 extern int radeon_pcie_gen2;
105 extern int radeon_msi;
106 extern int radeon_lockup_timeout;
107 extern int radeon_fastfb;
108 extern int radeon_dpm;
109 extern int radeon_aspm;
110 extern int radeon_runtime_pm;
111 extern int radeon_hard_reset;
112 extern int radeon_vm_size;
113 extern int radeon_vm_block_size;
114 extern int radeon_deep_color;
115 extern int radeon_use_pflipirq;
116 extern int radeon_bapm;
117 extern int radeon_backlight;
118 extern int radeon_auxch;
119 extern int radeon_mst;
120 extern int radeon_uvd;
121 extern int radeon_vce;
122 extern int radeon_si_support;
123 extern int radeon_cik_support;
124
125 /*
126 * Copy from radeon_drv.h so we don't have to include both and have conflicting
127 * symbol;
128 */
129 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
130 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
131 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
132 /* RADEON_IB_POOL_SIZE must be a power of 2 */
133 #define RADEON_IB_POOL_SIZE 16
134 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
135 #define RADEONFB_CONN_LIMIT 4
136 #define RADEON_BIOS_NUM_SCRATCH 8
137
138 /* internal ring indices */
139 /* r1xx+ has gfx CP ring */
140 #define RADEON_RING_TYPE_GFX_INDEX 0
141
142 /* cayman has 2 compute CP rings */
143 #define CAYMAN_RING_TYPE_CP1_INDEX 1
144 #define CAYMAN_RING_TYPE_CP2_INDEX 2
145
146 /* R600+ has an async dma ring */
147 #define R600_RING_TYPE_DMA_INDEX 3
148 /* cayman add a second async dma ring */
149 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
150
151 /* R600+ */
152 #define R600_RING_TYPE_UVD_INDEX 5
153
154 /* TN+ */
155 #define TN_RING_TYPE_VCE1_INDEX 6
156 #define TN_RING_TYPE_VCE2_INDEX 7
157
158 /* max number of rings */
159 #define RADEON_NUM_RINGS 8
160
161 /* number of hw syncs before falling back on blocking */
162 #define RADEON_NUM_SYNCS 4
163
164 /* hardcode those limit for now */
165 #define RADEON_VA_IB_OFFSET (1 << 20)
166 #define RADEON_VA_RESERVED_SIZE (8 << 20)
167 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
168
169 /* hard reset data */
170 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
171
172 /* reset flags */
173 #define RADEON_RESET_GFX (1 << 0)
174 #define RADEON_RESET_COMPUTE (1 << 1)
175 #define RADEON_RESET_DMA (1 << 2)
176 #define RADEON_RESET_CP (1 << 3)
177 #define RADEON_RESET_GRBM (1 << 4)
178 #define RADEON_RESET_DMA1 (1 << 5)
179 #define RADEON_RESET_RLC (1 << 6)
180 #define RADEON_RESET_SEM (1 << 7)
181 #define RADEON_RESET_IH (1 << 8)
182 #define RADEON_RESET_VMC (1 << 9)
183 #define RADEON_RESET_MC (1 << 10)
184 #define RADEON_RESET_DISPLAY (1 << 11)
185
186 /* CG block flags */
187 #define RADEON_CG_BLOCK_GFX (1 << 0)
188 #define RADEON_CG_BLOCK_MC (1 << 1)
189 #define RADEON_CG_BLOCK_SDMA (1 << 2)
190 #define RADEON_CG_BLOCK_UVD (1 << 3)
191 #define RADEON_CG_BLOCK_VCE (1 << 4)
192 #define RADEON_CG_BLOCK_HDP (1 << 5)
193 #define RADEON_CG_BLOCK_BIF (1 << 6)
194
195 /* CG flags */
196 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
197 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
198 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
199 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
200 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
201 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
202 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
203 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
204 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
205 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
206 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
207 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
208 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
209 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
210 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
211 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
212 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
213
214 /* PG flags */
215 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
216 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
217 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
218 #define RADEON_PG_SUPPORT_UVD (1 << 3)
219 #define RADEON_PG_SUPPORT_VCE (1 << 4)
220 #define RADEON_PG_SUPPORT_CP (1 << 5)
221 #define RADEON_PG_SUPPORT_GDS (1 << 6)
222 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
223 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
224 #define RADEON_PG_SUPPORT_ACP (1 << 9)
225 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
226
227 /* max cursor sizes (in pixels) */
228 #define CURSOR_WIDTH 64
229 #define CURSOR_HEIGHT 64
230
231 #define CIK_CURSOR_WIDTH 128
232 #define CIK_CURSOR_HEIGHT 128
233
234 /*
235 * Errata workarounds.
236 */
237 enum radeon_pll_errata {
238 CHIP_ERRATA_R300_CG = 0x00000001,
239 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
240 CHIP_ERRATA_PLL_DELAY = 0x00000004
241 };
242
243
244 struct radeon_device;
245
246
247 /*
248 * BIOS.
249 */
250 bool radeon_get_bios(struct radeon_device *rdev);
251
252 /*
253 * Dummy page
254 */
255 struct radeon_dummy_page {
256 uint64_t entry;
257 struct page *page;
258 dma_addr_t addr;
259 };
260 int radeon_dummy_page_init(struct radeon_device *rdev);
261 void radeon_dummy_page_fini(struct radeon_device *rdev);
262
263
264 /*
265 * Clocks
266 */
267 struct radeon_clock {
268 struct radeon_pll p1pll;
269 struct radeon_pll p2pll;
270 struct radeon_pll dcpll;
271 struct radeon_pll spll;
272 struct radeon_pll mpll;
273 /* 10 Khz units */
274 uint32_t default_mclk;
275 uint32_t default_sclk;
276 uint32_t default_dispclk;
277 uint32_t current_dispclk;
278 uint32_t dp_extclk;
279 uint32_t max_pixel_clock;
280 uint32_t vco_freq;
281 };
282
283 /*
284 * Power management
285 */
286 int radeon_pm_init(struct radeon_device *rdev);
287 int radeon_pm_late_init(struct radeon_device *rdev);
288 void radeon_pm_fini(struct radeon_device *rdev);
289 void radeon_pm_compute_clocks(struct radeon_device *rdev);
290 void radeon_pm_suspend(struct radeon_device *rdev);
291 void radeon_pm_resume(struct radeon_device *rdev);
292 void radeon_combios_get_power_modes(struct radeon_device *rdev);
293 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
294 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
295 u8 clock_type,
296 u32 clock,
297 bool strobe_mode,
298 struct atom_clock_dividers *dividers);
299 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
300 u32 clock,
301 bool strobe_mode,
302 struct atom_mpll_param *mpll_param);
303 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
304 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
305 u16 voltage_level, u8 voltage_type,
306 u32 *gpio_value, u32 *gpio_mask);
307 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
308 u32 eng_clock, u32 mem_clock);
309 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
310 u8 voltage_type, u16 *voltage_step);
311 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
312 u16 voltage_id, u16 *voltage);
313 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
314 u16 *voltage,
315 u16 leakage_idx);
316 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
317 u16 *leakage_id);
318 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
319 u16 *vddc, u16 *vddci,
320 u16 virtual_voltage_id,
321 u16 vbios_voltage_id);
322 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
323 u16 virtual_voltage_id,
324 u16 *voltage);
325 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
326 u8 voltage_type,
327 u16 nominal_voltage,
328 u16 *true_voltage);
329 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
330 u8 voltage_type, u16 *min_voltage);
331 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
332 u8 voltage_type, u16 *max_voltage);
333 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
334 u8 voltage_type, u8 voltage_mode,
335 struct atom_voltage_table *voltage_table);
336 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
337 u8 voltage_type, u8 voltage_mode);
338 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
339 u8 voltage_type,
340 u8 *svd_gpio_id, u8 *svc_gpio_id);
341 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
342 u32 mem_clock);
343 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
344 u32 mem_clock);
345 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
346 u8 module_index,
347 struct atom_mc_reg_table *reg_table);
348 int radeon_atom_get_memory_info(struct radeon_device *rdev,
349 u8 module_index, struct atom_memory_info *mem_info);
350 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
351 bool gddr5, u8 module_index,
352 struct atom_memory_clock_range_table *mclk_range_table);
353 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
354 u16 voltage_id, u16 *voltage);
355 void rs690_pm_info(struct radeon_device *rdev);
356 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
357 unsigned *bankh, unsigned *mtaspect,
358 unsigned *tile_split);
359
360 /*
361 * Fences.
362 */
363 struct radeon_fence_driver {
364 struct radeon_device *rdev;
365 uint32_t scratch_reg;
366 uint64_t gpu_addr;
367 volatile uint32_t *cpu_addr;
368 /* sync_seq is protected by ring emission lock */
369 uint64_t sync_seq[RADEON_NUM_RINGS];
370 atomic64_t last_seq;
371 bool initialized, delayed_irq;
372 struct delayed_work lockup_work;
373 };
374
375 struct radeon_fence {
376 struct dma_fence base;
377
378 struct radeon_device *rdev;
379 uint64_t seq;
380 /* RB, DMA, etc. */
381 unsigned ring;
382 bool is_vm_update;
383
384 wait_queue_entry_t fence_wake;
385 };
386
387 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
388 int radeon_fence_driver_init(struct radeon_device *rdev);
389 void radeon_fence_driver_fini(struct radeon_device *rdev);
390 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
391 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
392 void radeon_fence_process(struct radeon_device *rdev, int ring);
393 bool radeon_fence_signaled(struct radeon_fence *fence);
394 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
395 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
396 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
397 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
398 int radeon_fence_wait_any(struct radeon_device *rdev,
399 struct radeon_fence **fences,
400 bool intr);
401 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
402 void radeon_fence_unref(struct radeon_fence **fence);
403 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
404 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
405 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
radeon_fence_later(struct radeon_fence * a,struct radeon_fence * b)406 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
407 struct radeon_fence *b)
408 {
409 if (!a) {
410 return b;
411 }
412
413 if (!b) {
414 return a;
415 }
416
417 BUG_ON(a->ring != b->ring);
418
419 if (a->seq > b->seq) {
420 return a;
421 } else {
422 return b;
423 }
424 }
425
radeon_fence_is_earlier(struct radeon_fence * a,struct radeon_fence * b)426 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
427 struct radeon_fence *b)
428 {
429 if (!a) {
430 return false;
431 }
432
433 if (!b) {
434 return true;
435 }
436
437 BUG_ON(a->ring != b->ring);
438
439 return a->seq < b->seq;
440 }
441
442 /*
443 * Tiling registers
444 */
445 struct radeon_surface_reg {
446 struct radeon_bo *bo;
447 };
448
449 #define RADEON_GEM_MAX_SURFACES 8
450
451 /*
452 * TTM.
453 */
454 struct radeon_mman {
455 struct ttm_bo_device bdev;
456 bool initialized;
457
458 #if defined(CONFIG_DEBUG_FS)
459 struct dentry *vram;
460 struct dentry *gtt;
461 #endif
462 };
463
464 struct radeon_bo_list {
465 struct radeon_bo *robj;
466 struct ttm_validate_buffer tv;
467 uint64_t gpu_offset;
468 unsigned preferred_domains;
469 unsigned allowed_domains;
470 uint32_t tiling_flags;
471 };
472
473 /* bo virtual address in a specific vm */
474 struct radeon_bo_va {
475 /* protected by bo being reserved */
476 struct list_head bo_list;
477 uint32_t flags;
478 struct radeon_fence *last_pt_update;
479 unsigned ref_count;
480
481 /* protected by vm mutex */
482 struct interval_tree_node it;
483 struct list_head vm_status;
484
485 /* constant after initialization */
486 struct radeon_vm *vm;
487 struct radeon_bo *bo;
488 };
489
490 struct radeon_bo {
491 /* Protected by gem.mutex */
492 struct list_head list;
493 /* Protected by tbo.reserved */
494 u32 initial_domain;
495 struct ttm_place placements[4];
496 struct ttm_placement placement;
497 struct ttm_buffer_object tbo;
498 struct ttm_bo_kmap_obj kmap;
499 u32 flags;
500 unsigned pin_count;
501 void *kptr;
502 u32 tiling_flags;
503 u32 pitch;
504 int surface_reg;
505 unsigned prime_shared_count;
506 /* list of all virtual address to which this bo
507 * is associated to
508 */
509 struct list_head va;
510 /* Constant after initialization */
511 struct radeon_device *rdev;
512
513 struct ttm_bo_kmap_obj dma_buf_vmap;
514 pid_t pid;
515
516 #ifdef CONFIG_MMU_NOTIFIER
517 struct mmu_interval_notifier notifier;
518 #endif
519 };
520 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
521
522 int radeon_gem_debugfs_init(struct radeon_device *rdev);
523
524 /* sub-allocation manager, it has to be protected by another lock.
525 * By conception this is an helper for other part of the driver
526 * like the indirect buffer or semaphore, which both have their
527 * locking.
528 *
529 * Principe is simple, we keep a list of sub allocation in offset
530 * order (first entry has offset == 0, last entry has the highest
531 * offset).
532 *
533 * When allocating new object we first check if there is room at
534 * the end total_size - (last_object_offset + last_object_size) >=
535 * alloc_size. If so we allocate new object there.
536 *
537 * When there is not enough room at the end, we start waiting for
538 * each sub object until we reach object_offset+object_size >=
539 * alloc_size, this object then become the sub object we return.
540 *
541 * Alignment can't be bigger than page size.
542 *
543 * Hole are not considered for allocation to keep things simple.
544 * Assumption is that there won't be hole (all object on same
545 * alignment).
546 */
547 struct radeon_sa_manager {
548 wait_queue_head_t wq;
549 struct radeon_bo *bo;
550 struct list_head *hole;
551 struct list_head flist[RADEON_NUM_RINGS];
552 struct list_head olist;
553 unsigned size;
554 uint64_t gpu_addr;
555 void *cpu_ptr;
556 uint32_t domain;
557 uint32_t align;
558 };
559
560 struct radeon_sa_bo;
561
562 /* sub-allocation buffer */
563 struct radeon_sa_bo {
564 struct list_head olist;
565 struct list_head flist;
566 struct radeon_sa_manager *manager;
567 unsigned soffset;
568 unsigned eoffset;
569 struct radeon_fence *fence;
570 };
571
572 /*
573 * GEM objects.
574 */
575 struct radeon_gem {
576 struct mutex mutex;
577 struct list_head objects;
578 };
579
580 int radeon_gem_init(struct radeon_device *rdev);
581 void radeon_gem_fini(struct radeon_device *rdev);
582 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
583 int alignment, int initial_domain,
584 u32 flags, bool kernel,
585 struct drm_gem_object **obj);
586
587 int radeon_mode_dumb_create(struct drm_file *file_priv,
588 struct drm_device *dev,
589 struct drm_mode_create_dumb *args);
590 int radeon_mode_dumb_mmap(struct drm_file *filp,
591 struct drm_device *dev,
592 uint32_t handle, uint64_t *offset_p);
593
594 /*
595 * Semaphores.
596 */
597 struct radeon_semaphore {
598 struct radeon_sa_bo *sa_bo;
599 signed waiters;
600 uint64_t gpu_addr;
601 };
602
603 int radeon_semaphore_create(struct radeon_device *rdev,
604 struct radeon_semaphore **semaphore);
605 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
606 struct radeon_semaphore *semaphore);
607 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
608 struct radeon_semaphore *semaphore);
609 void radeon_semaphore_free(struct radeon_device *rdev,
610 struct radeon_semaphore **semaphore,
611 struct radeon_fence *fence);
612
613 /*
614 * Synchronization
615 */
616 struct radeon_sync {
617 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
618 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
619 struct radeon_fence *last_vm_update;
620 };
621
622 void radeon_sync_create(struct radeon_sync *sync);
623 void radeon_sync_fence(struct radeon_sync *sync,
624 struct radeon_fence *fence);
625 int radeon_sync_resv(struct radeon_device *rdev,
626 struct radeon_sync *sync,
627 struct dma_resv *resv,
628 bool shared);
629 int radeon_sync_rings(struct radeon_device *rdev,
630 struct radeon_sync *sync,
631 int waiting_ring);
632 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
633 struct radeon_fence *fence);
634
635 /*
636 * GART structures, functions & helpers
637 */
638 struct radeon_mc;
639
640 #define RADEON_GPU_PAGE_SIZE 4096
641 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
642 #define RADEON_GPU_PAGE_SHIFT 12
643 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
644
645 #define RADEON_GART_PAGE_DUMMY 0
646 #define RADEON_GART_PAGE_VALID (1 << 0)
647 #define RADEON_GART_PAGE_READ (1 << 1)
648 #define RADEON_GART_PAGE_WRITE (1 << 2)
649 #define RADEON_GART_PAGE_SNOOP (1 << 3)
650
651 struct radeon_gart {
652 dma_addr_t table_addr;
653 struct radeon_bo *robj;
654 void *ptr;
655 unsigned num_gpu_pages;
656 unsigned num_cpu_pages;
657 unsigned table_size;
658 struct page **pages;
659 uint64_t *pages_entry;
660 bool ready;
661 };
662
663 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
664 void radeon_gart_table_ram_free(struct radeon_device *rdev);
665 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
666 void radeon_gart_table_vram_free(struct radeon_device *rdev);
667 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
668 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
669 int radeon_gart_init(struct radeon_device *rdev);
670 void radeon_gart_fini(struct radeon_device *rdev);
671 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
672 int pages);
673 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
674 int pages, struct page **pagelist,
675 dma_addr_t *dma_addr, uint32_t flags);
676
677
678 /*
679 * GPU MC structures, functions & helpers
680 */
681 struct radeon_mc {
682 resource_size_t aper_size;
683 resource_size_t aper_base;
684 resource_size_t agp_base;
685 /* for some chips with <= 32MB we need to lie
686 * about vram size near mc fb location */
687 u64 mc_vram_size;
688 u64 visible_vram_size;
689 u64 gtt_size;
690 u64 gtt_start;
691 u64 gtt_end;
692 u64 vram_start;
693 u64 vram_end;
694 unsigned vram_width;
695 u64 real_vram_size;
696 int vram_mtrr;
697 bool vram_is_ddr;
698 bool igp_sideport_enabled;
699 u64 gtt_base_align;
700 u64 mc_mask;
701 };
702
703 bool radeon_combios_sideport_present(struct radeon_device *rdev);
704 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
705
706 /*
707 * GPU scratch registers structures, functions & helpers
708 */
709 struct radeon_scratch {
710 unsigned num_reg;
711 uint32_t reg_base;
712 bool free[32];
713 uint32_t reg[32];
714 };
715
716 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
717 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
718
719 /*
720 * GPU doorbell structures, functions & helpers
721 */
722 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
723
724 struct radeon_doorbell {
725 /* doorbell mmio */
726 resource_size_t base;
727 resource_size_t size;
728 u32 __iomem *ptr;
729 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
730 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
731 };
732
733 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
734 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
735
736 /*
737 * IRQS.
738 */
739
740 struct radeon_flip_work {
741 struct work_struct flip_work;
742 struct work_struct unpin_work;
743 struct radeon_device *rdev;
744 int crtc_id;
745 u32 target_vblank;
746 uint64_t base;
747 struct drm_pending_vblank_event *event;
748 struct radeon_bo *old_rbo;
749 struct dma_fence *fence;
750 bool async;
751 };
752
753 struct r500_irq_stat_regs {
754 u32 disp_int;
755 u32 hdmi0_status;
756 };
757
758 struct r600_irq_stat_regs {
759 u32 disp_int;
760 u32 disp_int_cont;
761 u32 disp_int_cont2;
762 u32 d1grph_int;
763 u32 d2grph_int;
764 u32 hdmi0_status;
765 u32 hdmi1_status;
766 };
767
768 struct evergreen_irq_stat_regs {
769 u32 disp_int[6];
770 u32 grph_int[6];
771 u32 afmt_status[6];
772 };
773
774 struct cik_irq_stat_regs {
775 u32 disp_int;
776 u32 disp_int_cont;
777 u32 disp_int_cont2;
778 u32 disp_int_cont3;
779 u32 disp_int_cont4;
780 u32 disp_int_cont5;
781 u32 disp_int_cont6;
782 u32 d1grph_int;
783 u32 d2grph_int;
784 u32 d3grph_int;
785 u32 d4grph_int;
786 u32 d5grph_int;
787 u32 d6grph_int;
788 };
789
790 union radeon_irq_stat_regs {
791 struct r500_irq_stat_regs r500;
792 struct r600_irq_stat_regs r600;
793 struct evergreen_irq_stat_regs evergreen;
794 struct cik_irq_stat_regs cik;
795 };
796
797 struct radeon_irq {
798 bool installed;
799 spinlock_t lock;
800 atomic_t ring_int[RADEON_NUM_RINGS];
801 bool crtc_vblank_int[RADEON_MAX_CRTCS];
802 atomic_t pflip[RADEON_MAX_CRTCS];
803 wait_queue_head_t vblank_queue;
804 bool hpd[RADEON_MAX_HPD_PINS];
805 bool afmt[RADEON_MAX_AFMT_BLOCKS];
806 union radeon_irq_stat_regs stat_regs;
807 bool dpm_thermal;
808 };
809
810 int radeon_irq_kms_init(struct radeon_device *rdev);
811 void radeon_irq_kms_fini(struct radeon_device *rdev);
812 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
813 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
814 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
815 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
816 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
817 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
818 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
819 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
820 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
821
822 /*
823 * CP & rings.
824 */
825
826 struct radeon_ib {
827 struct radeon_sa_bo *sa_bo;
828 uint32_t length_dw;
829 uint64_t gpu_addr;
830 uint32_t *ptr;
831 int ring;
832 struct radeon_fence *fence;
833 struct radeon_vm *vm;
834 bool is_const_ib;
835 struct radeon_sync sync;
836 };
837
838 struct radeon_ring {
839 struct radeon_bo *ring_obj;
840 volatile uint32_t *ring;
841 unsigned rptr_offs;
842 unsigned rptr_save_reg;
843 u64 next_rptr_gpu_addr;
844 volatile u32 *next_rptr_cpu_addr;
845 unsigned wptr;
846 unsigned wptr_old;
847 unsigned ring_size;
848 unsigned ring_free_dw;
849 int count_dw;
850 atomic_t last_rptr;
851 atomic64_t last_activity;
852 uint64_t gpu_addr;
853 uint32_t align_mask;
854 uint32_t ptr_mask;
855 bool ready;
856 u32 nop;
857 u32 idx;
858 u64 last_semaphore_signal_addr;
859 u64 last_semaphore_wait_addr;
860 /* for CIK queues */
861 u32 me;
862 u32 pipe;
863 u32 queue;
864 struct radeon_bo *mqd_obj;
865 u32 doorbell_index;
866 unsigned wptr_offs;
867 };
868
869 struct radeon_mec {
870 struct radeon_bo *hpd_eop_obj;
871 u64 hpd_eop_gpu_addr;
872 u32 num_pipe;
873 u32 num_mec;
874 u32 num_queue;
875 };
876
877 /*
878 * VM
879 */
880
881 /* maximum number of VMIDs */
882 #define RADEON_NUM_VM 16
883
884 /* number of entries in page table */
885 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
886
887 /* PTBs (Page Table Blocks) need to be aligned to 32K */
888 #define RADEON_VM_PTB_ALIGN_SIZE 32768
889 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
890 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
891
892 #define R600_PTE_VALID (1 << 0)
893 #define R600_PTE_SYSTEM (1 << 1)
894 #define R600_PTE_SNOOPED (1 << 2)
895 #define R600_PTE_READABLE (1 << 5)
896 #define R600_PTE_WRITEABLE (1 << 6)
897
898 /* PTE (Page Table Entry) fragment field for different page sizes */
899 #define R600_PTE_FRAG_4KB (0 << 7)
900 #define R600_PTE_FRAG_64KB (4 << 7)
901 #define R600_PTE_FRAG_256KB (6 << 7)
902
903 /* flags needed to be set so we can copy directly from the GART table */
904 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
905 R600_PTE_SYSTEM | R600_PTE_VALID )
906
907 struct radeon_vm_pt {
908 struct radeon_bo *bo;
909 uint64_t addr;
910 };
911
912 struct radeon_vm_id {
913 unsigned id;
914 uint64_t pd_gpu_addr;
915 /* last flushed PD/PT update */
916 struct radeon_fence *flushed_updates;
917 /* last use of vmid */
918 struct radeon_fence *last_id_use;
919 };
920
921 struct radeon_vm {
922 struct mutex mutex;
923
924 struct rb_root_cached va;
925
926 /* protecting invalidated and freed */
927 spinlock_t status_lock;
928
929 /* BOs moved, but not yet updated in the PT */
930 struct list_head invalidated;
931
932 /* BOs freed, but not yet updated in the PT */
933 struct list_head freed;
934
935 /* BOs cleared in the PT */
936 struct list_head cleared;
937
938 /* contains the page directory */
939 struct radeon_bo *page_directory;
940 unsigned max_pde_used;
941
942 /* array of page tables, one for each page directory entry */
943 struct radeon_vm_pt *page_tables;
944
945 struct radeon_bo_va *ib_bo_va;
946
947 /* for id and flush management per ring */
948 struct radeon_vm_id ids[RADEON_NUM_RINGS];
949 };
950
951 struct radeon_vm_manager {
952 struct radeon_fence *active[RADEON_NUM_VM];
953 uint32_t max_pfn;
954 /* number of VMIDs */
955 unsigned nvm;
956 /* vram base address for page table entry */
957 u64 vram_base_offset;
958 /* is vm enabled? */
959 bool enabled;
960 /* for hw to save the PD addr on suspend/resume */
961 uint32_t saved_table_addr[RADEON_NUM_VM];
962 };
963
964 /*
965 * file private structure
966 */
967 struct radeon_fpriv {
968 struct radeon_vm vm;
969 };
970
971 /*
972 * R6xx+ IH ring
973 */
974 struct r600_ih {
975 struct radeon_bo *ring_obj;
976 volatile uint32_t *ring;
977 unsigned rptr;
978 unsigned ring_size;
979 uint64_t gpu_addr;
980 uint32_t ptr_mask;
981 atomic_t lock;
982 bool enabled;
983 };
984
985 /*
986 * RLC stuff
987 */
988 #include "clearstate_defs.h"
989
990 struct radeon_rlc {
991 /* for power gating */
992 struct radeon_bo *save_restore_obj;
993 uint64_t save_restore_gpu_addr;
994 volatile uint32_t *sr_ptr;
995 const u32 *reg_list;
996 u32 reg_list_size;
997 /* for clear state */
998 struct radeon_bo *clear_state_obj;
999 uint64_t clear_state_gpu_addr;
1000 volatile uint32_t *cs_ptr;
1001 const struct cs_section_def *cs_data;
1002 u32 clear_state_size;
1003 /* for cp tables */
1004 struct radeon_bo *cp_table_obj;
1005 uint64_t cp_table_gpu_addr;
1006 volatile uint32_t *cp_table_ptr;
1007 u32 cp_table_size;
1008 };
1009
1010 int radeon_ib_get(struct radeon_device *rdev, int ring,
1011 struct radeon_ib *ib, struct radeon_vm *vm,
1012 unsigned size);
1013 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1014 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1015 struct radeon_ib *const_ib, bool hdp_flush);
1016 int radeon_ib_pool_init(struct radeon_device *rdev);
1017 void radeon_ib_pool_fini(struct radeon_device *rdev);
1018 int radeon_ib_ring_tests(struct radeon_device *rdev);
1019 /* Ring access between begin & end cannot sleep */
1020 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1021 struct radeon_ring *ring);
1022 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1023 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1024 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1025 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1026 bool hdp_flush);
1027 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1028 bool hdp_flush);
1029 void radeon_ring_undo(struct radeon_ring *ring);
1030 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1031 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1032 void radeon_ring_lockup_update(struct radeon_device *rdev,
1033 struct radeon_ring *ring);
1034 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1035 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1036 uint32_t **data);
1037 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1038 unsigned size, uint32_t *data);
1039 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1040 unsigned rptr_offs, u32 nop);
1041 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1042
1043
1044 /* r600 async dma */
1045 void r600_dma_stop(struct radeon_device *rdev);
1046 int r600_dma_resume(struct radeon_device *rdev);
1047 void r600_dma_fini(struct radeon_device *rdev);
1048
1049 void cayman_dma_stop(struct radeon_device *rdev);
1050 int cayman_dma_resume(struct radeon_device *rdev);
1051 void cayman_dma_fini(struct radeon_device *rdev);
1052
1053 /*
1054 * CS.
1055 */
1056 struct radeon_cs_chunk {
1057 uint32_t length_dw;
1058 uint32_t *kdata;
1059 void __user *user_ptr;
1060 };
1061
1062 struct radeon_cs_parser {
1063 struct device *dev;
1064 struct radeon_device *rdev;
1065 struct drm_file *filp;
1066 /* chunks */
1067 unsigned nchunks;
1068 struct radeon_cs_chunk *chunks;
1069 uint64_t *chunks_array;
1070 /* IB */
1071 unsigned idx;
1072 /* relocations */
1073 unsigned nrelocs;
1074 struct radeon_bo_list *relocs;
1075 struct radeon_bo_list *vm_bos;
1076 struct list_head validated;
1077 unsigned dma_reloc_idx;
1078 /* indices of various chunks */
1079 struct radeon_cs_chunk *chunk_ib;
1080 struct radeon_cs_chunk *chunk_relocs;
1081 struct radeon_cs_chunk *chunk_flags;
1082 struct radeon_cs_chunk *chunk_const_ib;
1083 struct radeon_ib ib;
1084 struct radeon_ib const_ib;
1085 void *track;
1086 unsigned family;
1087 int parser_error;
1088 u32 cs_flags;
1089 u32 ring;
1090 s32 priority;
1091 struct ww_acquire_ctx ticket;
1092 };
1093
radeon_get_ib_value(struct radeon_cs_parser * p,int idx)1094 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1095 {
1096 struct radeon_cs_chunk *ibc = p->chunk_ib;
1097
1098 if (ibc->kdata)
1099 return ibc->kdata[idx];
1100 return p->ib.ptr[idx];
1101 }
1102
1103
1104 struct radeon_cs_packet {
1105 unsigned idx;
1106 unsigned type;
1107 unsigned reg;
1108 unsigned opcode;
1109 int count;
1110 unsigned one_reg_wr;
1111 };
1112
1113 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1114 struct radeon_cs_packet *pkt,
1115 unsigned idx, unsigned reg);
1116 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1117 struct radeon_cs_packet *pkt);
1118
1119
1120 /*
1121 * AGP
1122 */
1123 int radeon_agp_init(struct radeon_device *rdev);
1124 void radeon_agp_resume(struct radeon_device *rdev);
1125 void radeon_agp_suspend(struct radeon_device *rdev);
1126 void radeon_agp_fini(struct radeon_device *rdev);
1127
1128
1129 /*
1130 * Writeback
1131 */
1132 struct radeon_wb {
1133 struct radeon_bo *wb_obj;
1134 volatile uint32_t *wb;
1135 uint64_t gpu_addr;
1136 bool enabled;
1137 bool use_event;
1138 };
1139
1140 #define RADEON_WB_SCRATCH_OFFSET 0
1141 #define RADEON_WB_RING0_NEXT_RPTR 256
1142 #define RADEON_WB_CP_RPTR_OFFSET 1024
1143 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1144 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1145 #define R600_WB_DMA_RPTR_OFFSET 1792
1146 #define R600_WB_IH_WPTR_OFFSET 2048
1147 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1148 #define R600_WB_EVENT_OFFSET 3072
1149 #define CIK_WB_CP1_WPTR_OFFSET 3328
1150 #define CIK_WB_CP2_WPTR_OFFSET 3584
1151 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1152 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1153
1154 /**
1155 * struct radeon_pm - power management datas
1156 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1157 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1158 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1159 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1160 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1161 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1162 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1163 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1164 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1165 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1166 * @needed_bandwidth: current bandwidth needs
1167 *
1168 * It keeps track of various data needed to take powermanagement decision.
1169 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1170 * Equation between gpu/memory clock and available bandwidth is hw dependent
1171 * (type of memory, bus size, efficiency, ...)
1172 */
1173
1174 enum radeon_pm_method {
1175 PM_METHOD_PROFILE,
1176 PM_METHOD_DYNPM,
1177 PM_METHOD_DPM,
1178 };
1179
1180 enum radeon_dynpm_state {
1181 DYNPM_STATE_DISABLED,
1182 DYNPM_STATE_MINIMUM,
1183 DYNPM_STATE_PAUSED,
1184 DYNPM_STATE_ACTIVE,
1185 DYNPM_STATE_SUSPENDED,
1186 };
1187 enum radeon_dynpm_action {
1188 DYNPM_ACTION_NONE,
1189 DYNPM_ACTION_MINIMUM,
1190 DYNPM_ACTION_DOWNCLOCK,
1191 DYNPM_ACTION_UPCLOCK,
1192 DYNPM_ACTION_DEFAULT
1193 };
1194
1195 enum radeon_voltage_type {
1196 VOLTAGE_NONE = 0,
1197 VOLTAGE_GPIO,
1198 VOLTAGE_VDDC,
1199 VOLTAGE_SW
1200 };
1201
1202 enum radeon_pm_state_type {
1203 /* not used for dpm */
1204 POWER_STATE_TYPE_DEFAULT,
1205 POWER_STATE_TYPE_POWERSAVE,
1206 /* user selectable states */
1207 POWER_STATE_TYPE_BATTERY,
1208 POWER_STATE_TYPE_BALANCED,
1209 POWER_STATE_TYPE_PERFORMANCE,
1210 /* internal states */
1211 POWER_STATE_TYPE_INTERNAL_UVD,
1212 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1213 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1214 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1215 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1216 POWER_STATE_TYPE_INTERNAL_BOOT,
1217 POWER_STATE_TYPE_INTERNAL_THERMAL,
1218 POWER_STATE_TYPE_INTERNAL_ACPI,
1219 POWER_STATE_TYPE_INTERNAL_ULV,
1220 POWER_STATE_TYPE_INTERNAL_3DPERF,
1221 };
1222
1223 enum radeon_pm_profile_type {
1224 PM_PROFILE_DEFAULT,
1225 PM_PROFILE_AUTO,
1226 PM_PROFILE_LOW,
1227 PM_PROFILE_MID,
1228 PM_PROFILE_HIGH,
1229 };
1230
1231 #define PM_PROFILE_DEFAULT_IDX 0
1232 #define PM_PROFILE_LOW_SH_IDX 1
1233 #define PM_PROFILE_MID_SH_IDX 2
1234 #define PM_PROFILE_HIGH_SH_IDX 3
1235 #define PM_PROFILE_LOW_MH_IDX 4
1236 #define PM_PROFILE_MID_MH_IDX 5
1237 #define PM_PROFILE_HIGH_MH_IDX 6
1238 #define PM_PROFILE_MAX 7
1239
1240 struct radeon_pm_profile {
1241 int dpms_off_ps_idx;
1242 int dpms_on_ps_idx;
1243 int dpms_off_cm_idx;
1244 int dpms_on_cm_idx;
1245 };
1246
1247 enum radeon_int_thermal_type {
1248 THERMAL_TYPE_NONE,
1249 THERMAL_TYPE_EXTERNAL,
1250 THERMAL_TYPE_EXTERNAL_GPIO,
1251 THERMAL_TYPE_RV6XX,
1252 THERMAL_TYPE_RV770,
1253 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1254 THERMAL_TYPE_EVERGREEN,
1255 THERMAL_TYPE_SUMO,
1256 THERMAL_TYPE_NI,
1257 THERMAL_TYPE_SI,
1258 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1259 THERMAL_TYPE_CI,
1260 THERMAL_TYPE_KV,
1261 };
1262
1263 struct radeon_voltage {
1264 enum radeon_voltage_type type;
1265 /* gpio voltage */
1266 struct radeon_gpio_rec gpio;
1267 u32 delay; /* delay in usec from voltage drop to sclk change */
1268 bool active_high; /* voltage drop is active when bit is high */
1269 /* VDDC voltage */
1270 u8 vddc_id; /* index into vddc voltage table */
1271 u8 vddci_id; /* index into vddci voltage table */
1272 bool vddci_enabled;
1273 /* r6xx+ sw */
1274 u16 voltage;
1275 /* evergreen+ vddci */
1276 u16 vddci;
1277 };
1278
1279 /* clock mode flags */
1280 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1281
1282 struct radeon_pm_clock_info {
1283 /* memory clock */
1284 u32 mclk;
1285 /* engine clock */
1286 u32 sclk;
1287 /* voltage info */
1288 struct radeon_voltage voltage;
1289 /* standardized clock flags */
1290 u32 flags;
1291 };
1292
1293 /* state flags */
1294 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1295
1296 struct radeon_power_state {
1297 enum radeon_pm_state_type type;
1298 struct radeon_pm_clock_info *clock_info;
1299 /* number of valid clock modes in this power state */
1300 int num_clock_modes;
1301 struct radeon_pm_clock_info *default_clock_mode;
1302 /* standardized state flags */
1303 u32 flags;
1304 u32 misc; /* vbios specific flags */
1305 u32 misc2; /* vbios specific flags */
1306 int pcie_lanes; /* pcie lanes */
1307 };
1308
1309 /*
1310 * Some modes are overclocked by very low value, accept them
1311 */
1312 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1313
1314 enum radeon_dpm_auto_throttle_src {
1315 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1316 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1317 };
1318
1319 enum radeon_dpm_event_src {
1320 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1321 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1322 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1323 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1324 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1325 };
1326
1327 #define RADEON_MAX_VCE_LEVELS 6
1328
1329 enum radeon_vce_level {
1330 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1331 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1332 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1333 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1334 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1335 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1336 };
1337
1338 struct radeon_ps {
1339 u32 caps; /* vbios flags */
1340 u32 class; /* vbios flags */
1341 u32 class2; /* vbios flags */
1342 /* UVD clocks */
1343 u32 vclk;
1344 u32 dclk;
1345 /* VCE clocks */
1346 u32 evclk;
1347 u32 ecclk;
1348 bool vce_active;
1349 enum radeon_vce_level vce_level;
1350 /* asic priv */
1351 void *ps_priv;
1352 };
1353
1354 struct radeon_dpm_thermal {
1355 /* thermal interrupt work */
1356 struct work_struct work;
1357 /* low temperature threshold */
1358 int min_temp;
1359 /* high temperature threshold */
1360 int max_temp;
1361 /* was interrupt low to high or high to low */
1362 bool high_to_low;
1363 };
1364
1365 enum radeon_clk_action
1366 {
1367 RADEON_SCLK_UP = 1,
1368 RADEON_SCLK_DOWN
1369 };
1370
1371 struct radeon_blacklist_clocks
1372 {
1373 u32 sclk;
1374 u32 mclk;
1375 enum radeon_clk_action action;
1376 };
1377
1378 struct radeon_clock_and_voltage_limits {
1379 u32 sclk;
1380 u32 mclk;
1381 u16 vddc;
1382 u16 vddci;
1383 };
1384
1385 struct radeon_clock_array {
1386 u32 count;
1387 u32 *values;
1388 };
1389
1390 struct radeon_clock_voltage_dependency_entry {
1391 u32 clk;
1392 u16 v;
1393 };
1394
1395 struct radeon_clock_voltage_dependency_table {
1396 u32 count;
1397 struct radeon_clock_voltage_dependency_entry *entries;
1398 };
1399
1400 union radeon_cac_leakage_entry {
1401 struct {
1402 u16 vddc;
1403 u32 leakage;
1404 };
1405 struct {
1406 u16 vddc1;
1407 u16 vddc2;
1408 u16 vddc3;
1409 };
1410 };
1411
1412 struct radeon_cac_leakage_table {
1413 u32 count;
1414 union radeon_cac_leakage_entry *entries;
1415 };
1416
1417 struct radeon_phase_shedding_limits_entry {
1418 u16 voltage;
1419 u32 sclk;
1420 u32 mclk;
1421 };
1422
1423 struct radeon_phase_shedding_limits_table {
1424 u32 count;
1425 struct radeon_phase_shedding_limits_entry *entries;
1426 };
1427
1428 struct radeon_uvd_clock_voltage_dependency_entry {
1429 u32 vclk;
1430 u32 dclk;
1431 u16 v;
1432 };
1433
1434 struct radeon_uvd_clock_voltage_dependency_table {
1435 u8 count;
1436 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1437 };
1438
1439 struct radeon_vce_clock_voltage_dependency_entry {
1440 u32 ecclk;
1441 u32 evclk;
1442 u16 v;
1443 };
1444
1445 struct radeon_vce_clock_voltage_dependency_table {
1446 u8 count;
1447 struct radeon_vce_clock_voltage_dependency_entry *entries;
1448 };
1449
1450 struct radeon_ppm_table {
1451 u8 ppm_design;
1452 u16 cpu_core_number;
1453 u32 platform_tdp;
1454 u32 small_ac_platform_tdp;
1455 u32 platform_tdc;
1456 u32 small_ac_platform_tdc;
1457 u32 apu_tdp;
1458 u32 dgpu_tdp;
1459 u32 dgpu_ulv_power;
1460 u32 tj_max;
1461 };
1462
1463 struct radeon_cac_tdp_table {
1464 u16 tdp;
1465 u16 configurable_tdp;
1466 u16 tdc;
1467 u16 battery_power_limit;
1468 u16 small_power_limit;
1469 u16 low_cac_leakage;
1470 u16 high_cac_leakage;
1471 u16 maximum_power_delivery_limit;
1472 };
1473
1474 struct radeon_dpm_dynamic_state {
1475 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1476 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1477 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1478 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1479 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1480 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1481 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1482 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1483 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1484 struct radeon_clock_array valid_sclk_values;
1485 struct radeon_clock_array valid_mclk_values;
1486 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1487 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1488 u32 mclk_sclk_ratio;
1489 u32 sclk_mclk_delta;
1490 u16 vddc_vddci_delta;
1491 u16 min_vddc_for_pcie_gen2;
1492 struct radeon_cac_leakage_table cac_leakage_table;
1493 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1494 struct radeon_ppm_table *ppm_table;
1495 struct radeon_cac_tdp_table *cac_tdp_table;
1496 };
1497
1498 struct radeon_dpm_fan {
1499 u16 t_min;
1500 u16 t_med;
1501 u16 t_high;
1502 u16 pwm_min;
1503 u16 pwm_med;
1504 u16 pwm_high;
1505 u8 t_hyst;
1506 u32 cycle_delay;
1507 u16 t_max;
1508 u8 control_mode;
1509 u16 default_max_fan_pwm;
1510 u16 default_fan_output_sensitivity;
1511 u16 fan_output_sensitivity;
1512 bool ucode_fan_control;
1513 };
1514
1515 enum radeon_pcie_gen {
1516 RADEON_PCIE_GEN1 = 0,
1517 RADEON_PCIE_GEN2 = 1,
1518 RADEON_PCIE_GEN3 = 2,
1519 RADEON_PCIE_GEN_INVALID = 0xffff
1520 };
1521
1522 enum radeon_dpm_forced_level {
1523 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1524 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1525 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1526 };
1527
1528 struct radeon_vce_state {
1529 /* vce clocks */
1530 u32 evclk;
1531 u32 ecclk;
1532 /* gpu clocks */
1533 u32 sclk;
1534 u32 mclk;
1535 u8 clk_idx;
1536 u8 pstate;
1537 };
1538
1539 struct radeon_dpm {
1540 struct radeon_ps *ps;
1541 /* number of valid power states */
1542 int num_ps;
1543 /* current power state that is active */
1544 struct radeon_ps *current_ps;
1545 /* requested power state */
1546 struct radeon_ps *requested_ps;
1547 /* boot up power state */
1548 struct radeon_ps *boot_ps;
1549 /* default uvd power state */
1550 struct radeon_ps *uvd_ps;
1551 /* vce requirements */
1552 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1553 enum radeon_vce_level vce_level;
1554 enum radeon_pm_state_type state;
1555 enum radeon_pm_state_type user_state;
1556 u32 platform_caps;
1557 u32 voltage_response_time;
1558 u32 backbias_response_time;
1559 void *priv;
1560 u32 new_active_crtcs;
1561 int new_active_crtc_count;
1562 u32 current_active_crtcs;
1563 int current_active_crtc_count;
1564 bool single_display;
1565 struct radeon_dpm_dynamic_state dyn_state;
1566 struct radeon_dpm_fan fan;
1567 u32 tdp_limit;
1568 u32 near_tdp_limit;
1569 u32 near_tdp_limit_adjusted;
1570 u32 sq_ramping_threshold;
1571 u32 cac_leakage;
1572 u16 tdp_od_limit;
1573 u32 tdp_adjustment;
1574 u16 load_line_slope;
1575 bool power_control;
1576 bool ac_power;
1577 /* special states active */
1578 bool thermal_active;
1579 bool uvd_active;
1580 bool vce_active;
1581 /* thermal handling */
1582 struct radeon_dpm_thermal thermal;
1583 /* forced levels */
1584 enum radeon_dpm_forced_level forced_level;
1585 /* track UVD streams */
1586 unsigned sd;
1587 unsigned hd;
1588 };
1589
1590 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1591 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1592
1593 struct radeon_pm {
1594 struct mutex mutex;
1595 /* write locked while reprogramming mclk */
1596 struct rw_semaphore mclk_lock;
1597 u32 active_crtcs;
1598 int active_crtc_count;
1599 int req_vblank;
1600 bool vblank_sync;
1601 fixed20_12 max_bandwidth;
1602 fixed20_12 igp_sideport_mclk;
1603 fixed20_12 igp_system_mclk;
1604 fixed20_12 igp_ht_link_clk;
1605 fixed20_12 igp_ht_link_width;
1606 fixed20_12 k8_bandwidth;
1607 fixed20_12 sideport_bandwidth;
1608 fixed20_12 ht_bandwidth;
1609 fixed20_12 core_bandwidth;
1610 fixed20_12 sclk;
1611 fixed20_12 mclk;
1612 fixed20_12 needed_bandwidth;
1613 struct radeon_power_state *power_state;
1614 /* number of valid power states */
1615 int num_power_states;
1616 int current_power_state_index;
1617 int current_clock_mode_index;
1618 int requested_power_state_index;
1619 int requested_clock_mode_index;
1620 int default_power_state_index;
1621 u32 current_sclk;
1622 u32 current_mclk;
1623 u16 current_vddc;
1624 u16 current_vddci;
1625 u32 default_sclk;
1626 u32 default_mclk;
1627 u16 default_vddc;
1628 u16 default_vddci;
1629 struct radeon_i2c_chan *i2c_bus;
1630 /* selected pm method */
1631 enum radeon_pm_method pm_method;
1632 /* dynpm power management */
1633 struct delayed_work dynpm_idle_work;
1634 enum radeon_dynpm_state dynpm_state;
1635 enum radeon_dynpm_action dynpm_planned_action;
1636 unsigned long dynpm_action_timeout;
1637 bool dynpm_can_upclock;
1638 bool dynpm_can_downclock;
1639 /* profile-based power management */
1640 enum radeon_pm_profile_type profile;
1641 int profile_index;
1642 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1643 /* internal thermal controller on rv6xx+ */
1644 enum radeon_int_thermal_type int_thermal_type;
1645 struct device *int_hwmon_dev;
1646 /* fan control parameters */
1647 bool no_fan;
1648 u8 fan_pulses_per_revolution;
1649 u8 fan_min_rpm;
1650 u8 fan_max_rpm;
1651 /* dpm */
1652 bool dpm_enabled;
1653 bool sysfs_initialized;
1654 struct radeon_dpm dpm;
1655 };
1656
1657 #define RADEON_PCIE_SPEED_25 1
1658 #define RADEON_PCIE_SPEED_50 2
1659 #define RADEON_PCIE_SPEED_80 4
1660
1661 int radeon_pm_get_type_index(struct radeon_device *rdev,
1662 enum radeon_pm_state_type ps_type,
1663 int instance);
1664 /*
1665 * UVD
1666 */
1667 #define RADEON_DEFAULT_UVD_HANDLES 10
1668 #define RADEON_MAX_UVD_HANDLES 30
1669 #define RADEON_UVD_STACK_SIZE (200*1024)
1670 #define RADEON_UVD_HEAP_SIZE (256*1024)
1671 #define RADEON_UVD_SESSION_SIZE (50*1024)
1672
1673 struct radeon_uvd {
1674 bool fw_header_present;
1675 struct radeon_bo *vcpu_bo;
1676 void *cpu_addr;
1677 uint64_t gpu_addr;
1678 unsigned max_handles;
1679 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1680 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1681 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1682 struct delayed_work idle_work;
1683 };
1684
1685 int radeon_uvd_init(struct radeon_device *rdev);
1686 void radeon_uvd_fini(struct radeon_device *rdev);
1687 int radeon_uvd_suspend(struct radeon_device *rdev);
1688 int radeon_uvd_resume(struct radeon_device *rdev);
1689 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1690 uint32_t handle, struct radeon_fence **fence);
1691 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1692 uint32_t handle, struct radeon_fence **fence);
1693 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1694 uint32_t allowed_domains);
1695 void radeon_uvd_free_handles(struct radeon_device *rdev,
1696 struct drm_file *filp);
1697 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1698 void radeon_uvd_note_usage(struct radeon_device *rdev);
1699 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1700 unsigned vclk, unsigned dclk,
1701 unsigned vco_min, unsigned vco_max,
1702 unsigned fb_factor, unsigned fb_mask,
1703 unsigned pd_min, unsigned pd_max,
1704 unsigned pd_even,
1705 unsigned *optimal_fb_div,
1706 unsigned *optimal_vclk_div,
1707 unsigned *optimal_dclk_div);
1708 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1709 unsigned cg_upll_func_cntl);
1710
1711 /*
1712 * VCE
1713 */
1714 #define RADEON_MAX_VCE_HANDLES 16
1715
1716 struct radeon_vce {
1717 struct radeon_bo *vcpu_bo;
1718 uint64_t gpu_addr;
1719 unsigned fw_version;
1720 unsigned fb_version;
1721 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1722 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1723 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1724 struct delayed_work idle_work;
1725 uint32_t keyselect;
1726 };
1727
1728 int radeon_vce_init(struct radeon_device *rdev);
1729 void radeon_vce_fini(struct radeon_device *rdev);
1730 int radeon_vce_suspend(struct radeon_device *rdev);
1731 int radeon_vce_resume(struct radeon_device *rdev);
1732 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1733 uint32_t handle, struct radeon_fence **fence);
1734 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1735 uint32_t handle, struct radeon_fence **fence);
1736 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1737 void radeon_vce_note_usage(struct radeon_device *rdev);
1738 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1739 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1740 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1741 struct radeon_ring *ring,
1742 struct radeon_semaphore *semaphore,
1743 bool emit_wait);
1744 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1745 void radeon_vce_fence_emit(struct radeon_device *rdev,
1746 struct radeon_fence *fence);
1747 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1748 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1749
1750 struct r600_audio_pin {
1751 int channels;
1752 int rate;
1753 int bits_per_sample;
1754 u8 status_bits;
1755 u8 category_code;
1756 u32 offset;
1757 bool connected;
1758 u32 id;
1759 };
1760
1761 struct r600_audio {
1762 bool enabled;
1763 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1764 int num_pins;
1765 struct radeon_audio_funcs *hdmi_funcs;
1766 struct radeon_audio_funcs *dp_funcs;
1767 struct radeon_audio_basic_funcs *funcs;
1768 };
1769
1770 /*
1771 * Benchmarking
1772 */
1773 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1774
1775
1776 /*
1777 * Testing
1778 */
1779 void radeon_test_moves(struct radeon_device *rdev);
1780 void radeon_test_ring_sync(struct radeon_device *rdev,
1781 struct radeon_ring *cpA,
1782 struct radeon_ring *cpB);
1783 void radeon_test_syncing(struct radeon_device *rdev);
1784
1785 /*
1786 * MMU Notifier
1787 */
1788 #if defined(CONFIG_MMU_NOTIFIER)
1789 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1790 void radeon_mn_unregister(struct radeon_bo *bo);
1791 #else
radeon_mn_register(struct radeon_bo * bo,unsigned long addr)1792 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1793 {
1794 return -ENODEV;
1795 }
radeon_mn_unregister(struct radeon_bo * bo)1796 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1797 #endif
1798
1799 /*
1800 * Debugfs
1801 */
1802 struct radeon_debugfs {
1803 struct drm_info_list *files;
1804 unsigned num_files;
1805 };
1806
1807 int radeon_debugfs_add_files(struct radeon_device *rdev,
1808 struct drm_info_list *files,
1809 unsigned nfiles);
1810 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1811
1812 /*
1813 * ASIC ring specific functions.
1814 */
1815 struct radeon_asic_ring {
1816 /* ring read/write ptr handling */
1817 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1818 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1819 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1820
1821 /* validating and patching of IBs */
1822 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1823 int (*cs_parse)(struct radeon_cs_parser *p);
1824
1825 /* command emmit functions */
1826 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1827 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1828 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1829 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1830 struct radeon_semaphore *semaphore, bool emit_wait);
1831 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1832 unsigned vm_id, uint64_t pd_addr);
1833
1834 /* testing functions */
1835 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1836 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1837 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1838
1839 /* deprecated */
1840 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1841 };
1842
1843 /*
1844 * ASIC specific functions.
1845 */
1846 struct radeon_asic {
1847 int (*init)(struct radeon_device *rdev);
1848 void (*fini)(struct radeon_device *rdev);
1849 int (*resume)(struct radeon_device *rdev);
1850 int (*suspend)(struct radeon_device *rdev);
1851 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1852 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1853 /* Flush the HDP cache via MMIO */
1854 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1855 /* check if 3D engine is idle */
1856 bool (*gui_idle)(struct radeon_device *rdev);
1857 /* wait for mc_idle */
1858 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1859 /* get the reference clock */
1860 u32 (*get_xclk)(struct radeon_device *rdev);
1861 /* get the gpu clock counter */
1862 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1863 /* get register for info ioctl */
1864 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1865 /* gart */
1866 struct {
1867 void (*tlb_flush)(struct radeon_device *rdev);
1868 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1869 void (*set_page)(struct radeon_device *rdev, unsigned i,
1870 uint64_t entry);
1871 } gart;
1872 struct {
1873 int (*init)(struct radeon_device *rdev);
1874 void (*fini)(struct radeon_device *rdev);
1875 void (*copy_pages)(struct radeon_device *rdev,
1876 struct radeon_ib *ib,
1877 uint64_t pe, uint64_t src,
1878 unsigned count);
1879 void (*write_pages)(struct radeon_device *rdev,
1880 struct radeon_ib *ib,
1881 uint64_t pe,
1882 uint64_t addr, unsigned count,
1883 uint32_t incr, uint32_t flags);
1884 void (*set_pages)(struct radeon_device *rdev,
1885 struct radeon_ib *ib,
1886 uint64_t pe,
1887 uint64_t addr, unsigned count,
1888 uint32_t incr, uint32_t flags);
1889 void (*pad_ib)(struct radeon_ib *ib);
1890 } vm;
1891 /* ring specific callbacks */
1892 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1893 /* irqs */
1894 struct {
1895 int (*set)(struct radeon_device *rdev);
1896 int (*process)(struct radeon_device *rdev);
1897 } irq;
1898 /* displays */
1899 struct {
1900 /* display watermarks */
1901 void (*bandwidth_update)(struct radeon_device *rdev);
1902 /* get frame count */
1903 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1904 /* wait for vblank */
1905 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1906 /* set backlight level */
1907 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1908 /* get backlight level */
1909 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1910 /* audio callbacks */
1911 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1912 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1913 } display;
1914 /* copy functions for bo handling */
1915 struct {
1916 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1917 uint64_t src_offset,
1918 uint64_t dst_offset,
1919 unsigned num_gpu_pages,
1920 struct dma_resv *resv);
1921 u32 blit_ring_index;
1922 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1923 uint64_t src_offset,
1924 uint64_t dst_offset,
1925 unsigned num_gpu_pages,
1926 struct dma_resv *resv);
1927 u32 dma_ring_index;
1928 /* method used for bo copy */
1929 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1930 uint64_t src_offset,
1931 uint64_t dst_offset,
1932 unsigned num_gpu_pages,
1933 struct dma_resv *resv);
1934 /* ring used for bo copies */
1935 u32 copy_ring_index;
1936 } copy;
1937 /* surfaces */
1938 struct {
1939 int (*set_reg)(struct radeon_device *rdev, int reg,
1940 uint32_t tiling_flags, uint32_t pitch,
1941 uint32_t offset, uint32_t obj_size);
1942 void (*clear_reg)(struct radeon_device *rdev, int reg);
1943 } surface;
1944 /* hotplug detect */
1945 struct {
1946 void (*init)(struct radeon_device *rdev);
1947 void (*fini)(struct radeon_device *rdev);
1948 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1949 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1950 } hpd;
1951 /* static power management */
1952 struct {
1953 void (*misc)(struct radeon_device *rdev);
1954 void (*prepare)(struct radeon_device *rdev);
1955 void (*finish)(struct radeon_device *rdev);
1956 void (*init_profile)(struct radeon_device *rdev);
1957 void (*get_dynpm_state)(struct radeon_device *rdev);
1958 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1959 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1960 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1961 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1962 int (*get_pcie_lanes)(struct radeon_device *rdev);
1963 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1964 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1965 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1966 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1967 int (*get_temperature)(struct radeon_device *rdev);
1968 } pm;
1969 /* dynamic power management */
1970 struct {
1971 int (*init)(struct radeon_device *rdev);
1972 void (*setup_asic)(struct radeon_device *rdev);
1973 int (*enable)(struct radeon_device *rdev);
1974 int (*late_enable)(struct radeon_device *rdev);
1975 void (*disable)(struct radeon_device *rdev);
1976 int (*pre_set_power_state)(struct radeon_device *rdev);
1977 int (*set_power_state)(struct radeon_device *rdev);
1978 void (*post_set_power_state)(struct radeon_device *rdev);
1979 void (*display_configuration_changed)(struct radeon_device *rdev);
1980 void (*fini)(struct radeon_device *rdev);
1981 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1982 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1983 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1984 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1985 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1986 bool (*vblank_too_short)(struct radeon_device *rdev);
1987 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1988 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1989 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1990 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1991 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1992 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1993 u32 (*get_current_sclk)(struct radeon_device *rdev);
1994 u32 (*get_current_mclk)(struct radeon_device *rdev);
1995 } dpm;
1996 /* pageflipping */
1997 struct {
1998 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
1999 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2000 } pflip;
2001 };
2002
2003 /*
2004 * Asic structures
2005 */
2006 struct r100_asic {
2007 const unsigned *reg_safe_bm;
2008 unsigned reg_safe_bm_size;
2009 u32 hdp_cntl;
2010 };
2011
2012 struct r300_asic {
2013 const unsigned *reg_safe_bm;
2014 unsigned reg_safe_bm_size;
2015 u32 resync_scratch;
2016 u32 hdp_cntl;
2017 };
2018
2019 struct r600_asic {
2020 unsigned max_pipes;
2021 unsigned max_tile_pipes;
2022 unsigned max_simds;
2023 unsigned max_backends;
2024 unsigned max_gprs;
2025 unsigned max_threads;
2026 unsigned max_stack_entries;
2027 unsigned max_hw_contexts;
2028 unsigned max_gs_threads;
2029 unsigned sx_max_export_size;
2030 unsigned sx_max_export_pos_size;
2031 unsigned sx_max_export_smx_size;
2032 unsigned sq_num_cf_insts;
2033 unsigned tiling_nbanks;
2034 unsigned tiling_npipes;
2035 unsigned tiling_group_size;
2036 unsigned tile_config;
2037 unsigned backend_map;
2038 unsigned active_simds;
2039 };
2040
2041 struct rv770_asic {
2042 unsigned max_pipes;
2043 unsigned max_tile_pipes;
2044 unsigned max_simds;
2045 unsigned max_backends;
2046 unsigned max_gprs;
2047 unsigned max_threads;
2048 unsigned max_stack_entries;
2049 unsigned max_hw_contexts;
2050 unsigned max_gs_threads;
2051 unsigned sx_max_export_size;
2052 unsigned sx_max_export_pos_size;
2053 unsigned sx_max_export_smx_size;
2054 unsigned sq_num_cf_insts;
2055 unsigned sx_num_of_sets;
2056 unsigned sc_prim_fifo_size;
2057 unsigned sc_hiz_tile_fifo_size;
2058 unsigned sc_earlyz_tile_fifo_fize;
2059 unsigned tiling_nbanks;
2060 unsigned tiling_npipes;
2061 unsigned tiling_group_size;
2062 unsigned tile_config;
2063 unsigned backend_map;
2064 unsigned active_simds;
2065 };
2066
2067 struct evergreen_asic {
2068 unsigned num_ses;
2069 unsigned max_pipes;
2070 unsigned max_tile_pipes;
2071 unsigned max_simds;
2072 unsigned max_backends;
2073 unsigned max_gprs;
2074 unsigned max_threads;
2075 unsigned max_stack_entries;
2076 unsigned max_hw_contexts;
2077 unsigned max_gs_threads;
2078 unsigned sx_max_export_size;
2079 unsigned sx_max_export_pos_size;
2080 unsigned sx_max_export_smx_size;
2081 unsigned sq_num_cf_insts;
2082 unsigned sx_num_of_sets;
2083 unsigned sc_prim_fifo_size;
2084 unsigned sc_hiz_tile_fifo_size;
2085 unsigned sc_earlyz_tile_fifo_size;
2086 unsigned tiling_nbanks;
2087 unsigned tiling_npipes;
2088 unsigned tiling_group_size;
2089 unsigned tile_config;
2090 unsigned backend_map;
2091 unsigned active_simds;
2092 };
2093
2094 struct cayman_asic {
2095 unsigned max_shader_engines;
2096 unsigned max_pipes_per_simd;
2097 unsigned max_tile_pipes;
2098 unsigned max_simds_per_se;
2099 unsigned max_backends_per_se;
2100 unsigned max_texture_channel_caches;
2101 unsigned max_gprs;
2102 unsigned max_threads;
2103 unsigned max_gs_threads;
2104 unsigned max_stack_entries;
2105 unsigned sx_num_of_sets;
2106 unsigned sx_max_export_size;
2107 unsigned sx_max_export_pos_size;
2108 unsigned sx_max_export_smx_size;
2109 unsigned max_hw_contexts;
2110 unsigned sq_num_cf_insts;
2111 unsigned sc_prim_fifo_size;
2112 unsigned sc_hiz_tile_fifo_size;
2113 unsigned sc_earlyz_tile_fifo_size;
2114
2115 unsigned num_shader_engines;
2116 unsigned num_shader_pipes_per_simd;
2117 unsigned num_tile_pipes;
2118 unsigned num_simds_per_se;
2119 unsigned num_backends_per_se;
2120 unsigned backend_disable_mask_per_asic;
2121 unsigned backend_map;
2122 unsigned num_texture_channel_caches;
2123 unsigned mem_max_burst_length_bytes;
2124 unsigned mem_row_size_in_kb;
2125 unsigned shader_engine_tile_size;
2126 unsigned num_gpus;
2127 unsigned multi_gpu_tile_size;
2128
2129 unsigned tile_config;
2130 unsigned active_simds;
2131 };
2132
2133 struct si_asic {
2134 unsigned max_shader_engines;
2135 unsigned max_tile_pipes;
2136 unsigned max_cu_per_sh;
2137 unsigned max_sh_per_se;
2138 unsigned max_backends_per_se;
2139 unsigned max_texture_channel_caches;
2140 unsigned max_gprs;
2141 unsigned max_gs_threads;
2142 unsigned max_hw_contexts;
2143 unsigned sc_prim_fifo_size_frontend;
2144 unsigned sc_prim_fifo_size_backend;
2145 unsigned sc_hiz_tile_fifo_size;
2146 unsigned sc_earlyz_tile_fifo_size;
2147
2148 unsigned num_tile_pipes;
2149 unsigned backend_enable_mask;
2150 unsigned backend_disable_mask_per_asic;
2151 unsigned backend_map;
2152 unsigned num_texture_channel_caches;
2153 unsigned mem_max_burst_length_bytes;
2154 unsigned mem_row_size_in_kb;
2155 unsigned shader_engine_tile_size;
2156 unsigned num_gpus;
2157 unsigned multi_gpu_tile_size;
2158
2159 unsigned tile_config;
2160 uint32_t tile_mode_array[32];
2161 uint32_t active_cus;
2162 };
2163
2164 struct cik_asic {
2165 unsigned max_shader_engines;
2166 unsigned max_tile_pipes;
2167 unsigned max_cu_per_sh;
2168 unsigned max_sh_per_se;
2169 unsigned max_backends_per_se;
2170 unsigned max_texture_channel_caches;
2171 unsigned max_gprs;
2172 unsigned max_gs_threads;
2173 unsigned max_hw_contexts;
2174 unsigned sc_prim_fifo_size_frontend;
2175 unsigned sc_prim_fifo_size_backend;
2176 unsigned sc_hiz_tile_fifo_size;
2177 unsigned sc_earlyz_tile_fifo_size;
2178
2179 unsigned num_tile_pipes;
2180 unsigned backend_enable_mask;
2181 unsigned backend_disable_mask_per_asic;
2182 unsigned backend_map;
2183 unsigned num_texture_channel_caches;
2184 unsigned mem_max_burst_length_bytes;
2185 unsigned mem_row_size_in_kb;
2186 unsigned shader_engine_tile_size;
2187 unsigned num_gpus;
2188 unsigned multi_gpu_tile_size;
2189
2190 unsigned tile_config;
2191 uint32_t tile_mode_array[32];
2192 uint32_t macrotile_mode_array[16];
2193 uint32_t active_cus;
2194 };
2195
2196 union radeon_asic_config {
2197 struct r300_asic r300;
2198 struct r100_asic r100;
2199 struct r600_asic r600;
2200 struct rv770_asic rv770;
2201 struct evergreen_asic evergreen;
2202 struct cayman_asic cayman;
2203 struct si_asic si;
2204 struct cik_asic cik;
2205 };
2206
2207 /*
2208 * asic initizalization from radeon_asic.c
2209 */
2210 void radeon_agp_disable(struct radeon_device *rdev);
2211 int radeon_asic_init(struct radeon_device *rdev);
2212
2213
2214 /*
2215 * IOCTL.
2216 */
2217 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2218 struct drm_file *filp);
2219 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2220 struct drm_file *filp);
2221 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2222 struct drm_file *filp);
2223 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2224 struct drm_file *file_priv);
2225 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2226 struct drm_file *file_priv);
2227 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2228 struct drm_file *file_priv);
2229 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2230 struct drm_file *file_priv);
2231 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2232 struct drm_file *filp);
2233 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2234 struct drm_file *filp);
2235 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2236 struct drm_file *filp);
2237 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2238 struct drm_file *filp);
2239 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2240 struct drm_file *filp);
2241 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2242 struct drm_file *filp);
2243 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2244 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2245 struct drm_file *filp);
2246 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2247 struct drm_file *filp);
2248
2249 /* VRAM scratch page for HDP bug, default vram page */
2250 struct r600_vram_scratch {
2251 struct radeon_bo *robj;
2252 volatile uint32_t *ptr;
2253 u64 gpu_addr;
2254 };
2255
2256 /*
2257 * ACPI
2258 */
2259 struct radeon_atif_notification_cfg {
2260 bool enabled;
2261 int command_code;
2262 };
2263
2264 struct radeon_atif_notifications {
2265 bool display_switch;
2266 bool expansion_mode_change;
2267 bool thermal_state;
2268 bool forced_power_state;
2269 bool system_power_state;
2270 bool display_conf_change;
2271 bool px_gfx_switch;
2272 bool brightness_change;
2273 bool dgpu_display_event;
2274 };
2275
2276 struct radeon_atif_functions {
2277 bool system_params;
2278 bool sbios_requests;
2279 bool select_active_disp;
2280 bool lid_state;
2281 bool get_tv_standard;
2282 bool set_tv_standard;
2283 bool get_panel_expansion_mode;
2284 bool set_panel_expansion_mode;
2285 bool temperature_change;
2286 bool graphics_device_types;
2287 };
2288
2289 struct radeon_atif {
2290 struct radeon_atif_notifications notifications;
2291 struct radeon_atif_functions functions;
2292 struct radeon_atif_notification_cfg notification_cfg;
2293 struct radeon_encoder *encoder_for_bl;
2294 };
2295
2296 struct radeon_atcs_functions {
2297 bool get_ext_state;
2298 bool pcie_perf_req;
2299 bool pcie_dev_rdy;
2300 bool pcie_bus_width;
2301 };
2302
2303 struct radeon_atcs {
2304 struct radeon_atcs_functions functions;
2305 };
2306
2307 /*
2308 * Core structure, functions and helpers.
2309 */
2310 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2311 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2312
2313 struct radeon_device {
2314 struct device *dev;
2315 struct drm_device *ddev;
2316 struct pci_dev *pdev;
2317 struct rw_semaphore exclusive_lock;
2318 /* ASIC */
2319 union radeon_asic_config config;
2320 enum radeon_family family;
2321 unsigned long flags;
2322 int usec_timeout;
2323 enum radeon_pll_errata pll_errata;
2324 int num_gb_pipes;
2325 int num_z_pipes;
2326 int disp_priority;
2327 /* BIOS */
2328 uint8_t *bios;
2329 bool is_atom_bios;
2330 uint16_t bios_header_start;
2331 struct radeon_bo *stolen_vga_memory;
2332 /* Register mmio */
2333 resource_size_t rmmio_base;
2334 resource_size_t rmmio_size;
2335 /* protects concurrent MM_INDEX/DATA based register access */
2336 spinlock_t mmio_idx_lock;
2337 /* protects concurrent SMC based register access */
2338 spinlock_t smc_idx_lock;
2339 /* protects concurrent PLL register access */
2340 spinlock_t pll_idx_lock;
2341 /* protects concurrent MC register access */
2342 spinlock_t mc_idx_lock;
2343 /* protects concurrent PCIE register access */
2344 spinlock_t pcie_idx_lock;
2345 /* protects concurrent PCIE_PORT register access */
2346 spinlock_t pciep_idx_lock;
2347 /* protects concurrent PIF register access */
2348 spinlock_t pif_idx_lock;
2349 /* protects concurrent CG register access */
2350 spinlock_t cg_idx_lock;
2351 /* protects concurrent UVD register access */
2352 spinlock_t uvd_idx_lock;
2353 /* protects concurrent RCU register access */
2354 spinlock_t rcu_idx_lock;
2355 /* protects concurrent DIDT register access */
2356 spinlock_t didt_idx_lock;
2357 /* protects concurrent ENDPOINT (audio) register access */
2358 spinlock_t end_idx_lock;
2359 void __iomem *rmmio;
2360 radeon_rreg_t mc_rreg;
2361 radeon_wreg_t mc_wreg;
2362 radeon_rreg_t pll_rreg;
2363 radeon_wreg_t pll_wreg;
2364 uint32_t pcie_reg_mask;
2365 radeon_rreg_t pciep_rreg;
2366 radeon_wreg_t pciep_wreg;
2367 /* io port */
2368 void __iomem *rio_mem;
2369 resource_size_t rio_mem_size;
2370 struct radeon_clock clock;
2371 struct radeon_mc mc;
2372 struct radeon_gart gart;
2373 struct radeon_mode_info mode_info;
2374 struct radeon_scratch scratch;
2375 struct radeon_doorbell doorbell;
2376 struct radeon_mman mman;
2377 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2378 wait_queue_head_t fence_queue;
2379 u64 fence_context;
2380 struct mutex ring_lock;
2381 struct radeon_ring ring[RADEON_NUM_RINGS];
2382 bool ib_pool_ready;
2383 struct radeon_sa_manager ring_tmp_bo;
2384 struct radeon_irq irq;
2385 struct radeon_asic *asic;
2386 struct radeon_gem gem;
2387 struct radeon_pm pm;
2388 struct radeon_uvd uvd;
2389 struct radeon_vce vce;
2390 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2391 struct radeon_wb wb;
2392 struct radeon_dummy_page dummy_page;
2393 bool shutdown;
2394 bool need_swiotlb;
2395 bool accel_working;
2396 bool fastfb_working; /* IGP feature*/
2397 bool needs_reset, in_reset;
2398 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2399 const struct firmware *me_fw; /* all family ME firmware */
2400 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2401 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2402 const struct firmware *mc_fw; /* NI MC firmware */
2403 const struct firmware *ce_fw; /* SI CE firmware */
2404 const struct firmware *mec_fw; /* CIK MEC firmware */
2405 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2406 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2407 const struct firmware *smc_fw; /* SMC firmware */
2408 const struct firmware *uvd_fw; /* UVD firmware */
2409 const struct firmware *vce_fw; /* VCE firmware */
2410 bool new_fw;
2411 struct r600_vram_scratch vram_scratch;
2412 int msi_enabled; /* msi enabled */
2413 struct r600_ih ih; /* r6/700 interrupt ring */
2414 struct radeon_rlc rlc;
2415 struct radeon_mec mec;
2416 struct delayed_work hotplug_work;
2417 struct work_struct dp_work;
2418 struct work_struct audio_work;
2419 int num_crtc; /* number of crtcs */
2420 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2421 bool has_uvd;
2422 bool has_vce;
2423 struct r600_audio audio; /* audio stuff */
2424 struct notifier_block acpi_nb;
2425 /* only one userspace can use Hyperz features or CMASK at a time */
2426 struct drm_file *hyperz_filp;
2427 struct drm_file *cmask_filp;
2428 /* i2c buses */
2429 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2430 /* debugfs */
2431 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2432 unsigned debugfs_count;
2433 /* virtual memory */
2434 struct radeon_vm_manager vm_manager;
2435 struct mutex gpu_clock_mutex;
2436 /* memory stats */
2437 atomic64_t vram_usage;
2438 atomic64_t gtt_usage;
2439 atomic64_t num_bytes_moved;
2440 atomic_t gpu_reset_counter;
2441 /* ACPI interface */
2442 struct radeon_atif atif;
2443 struct radeon_atcs atcs;
2444 /* srbm instance registers */
2445 struct mutex srbm_mutex;
2446 /* clock, powergating flags */
2447 u32 cg_flags;
2448 u32 pg_flags;
2449
2450 struct dev_pm_domain vga_pm_domain;
2451 bool have_disp_power_ref;
2452 u32 px_quirk_flags;
2453
2454 /* tracking pinned memory */
2455 u64 vram_pin_size;
2456 u64 gart_pin_size;
2457 };
2458
2459 bool radeon_is_px(struct drm_device *dev);
2460 int radeon_device_init(struct radeon_device *rdev,
2461 struct drm_device *ddev,
2462 struct pci_dev *pdev,
2463 uint32_t flags);
2464 void radeon_device_fini(struct radeon_device *rdev);
2465 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2466
2467 #define RADEON_MIN_MMIO_SIZE 0x10000
2468
2469 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2470 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
r100_mm_rreg(struct radeon_device * rdev,uint32_t reg,bool always_indirect)2471 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2472 bool always_indirect)
2473 {
2474 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2475 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2476 return readl(((void __iomem *)rdev->rmmio) + reg);
2477 else
2478 return r100_mm_rreg_slow(rdev, reg);
2479 }
r100_mm_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v,bool always_indirect)2480 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2481 bool always_indirect)
2482 {
2483 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2484 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2485 else
2486 r100_mm_wreg_slow(rdev, reg, v);
2487 }
2488
2489 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2490 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2491
2492 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2493 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2494
2495 /*
2496 * Cast helper
2497 */
2498 extern const struct dma_fence_ops radeon_fence_ops;
2499
to_radeon_fence(struct dma_fence * f)2500 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2501 {
2502 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2503
2504 if (__f->base.ops == &radeon_fence_ops)
2505 return __f;
2506
2507 return NULL;
2508 }
2509
2510 /*
2511 * Registers read & write functions.
2512 */
2513 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2514 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2515 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2516 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2517 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2518 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2519 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2520 r100_mm_rreg(rdev, (reg), false))
2521 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2522 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2523 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2524 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2525 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2526 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2527 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2528 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2529 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2530 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2531 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2532 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2533 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2534 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2535 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2536 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2537 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2538 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2539 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2540 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2541 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2542 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2543 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2544 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2545 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2546 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2547 #define WREG32_P(reg, val, mask) \
2548 do { \
2549 uint32_t tmp_ = RREG32(reg); \
2550 tmp_ &= (mask); \
2551 tmp_ |= ((val) & ~(mask)); \
2552 WREG32(reg, tmp_); \
2553 } while (0)
2554 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2555 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2556 #define WREG32_PLL_P(reg, val, mask) \
2557 do { \
2558 uint32_t tmp_ = RREG32_PLL(reg); \
2559 tmp_ &= (mask); \
2560 tmp_ |= ((val) & ~(mask)); \
2561 WREG32_PLL(reg, tmp_); \
2562 } while (0)
2563 #define WREG32_SMC_P(reg, val, mask) \
2564 do { \
2565 uint32_t tmp_ = RREG32_SMC(reg); \
2566 tmp_ &= (mask); \
2567 tmp_ |= ((val) & ~(mask)); \
2568 WREG32_SMC(reg, tmp_); \
2569 } while (0)
2570 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2571 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2572 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2573
2574 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2575 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2576
2577 /*
2578 * Indirect registers accessors.
2579 * They used to be inlined, but this increases code size by ~65 kbytes.
2580 * Since each performs a pair of MMIO ops
2581 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2582 * the cost of call+ret is almost negligible. MMIO and locking
2583 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2584 */
2585 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2586 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2587 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2588 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2589 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2590 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2591 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2592 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2593 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2594 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2595 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2596 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2597 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2598 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2599 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2600 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2601
2602 void r100_pll_errata_after_index(struct radeon_device *rdev);
2603
2604
2605 /*
2606 * ASICs helpers.
2607 */
2608 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2609 (rdev->pdev->device == 0x5969))
2610 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2611 (rdev->family == CHIP_RV200) || \
2612 (rdev->family == CHIP_RS100) || \
2613 (rdev->family == CHIP_RS200) || \
2614 (rdev->family == CHIP_RV250) || \
2615 (rdev->family == CHIP_RV280) || \
2616 (rdev->family == CHIP_RS300))
2617 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2618 (rdev->family == CHIP_RV350) || \
2619 (rdev->family == CHIP_R350) || \
2620 (rdev->family == CHIP_RV380) || \
2621 (rdev->family == CHIP_R420) || \
2622 (rdev->family == CHIP_R423) || \
2623 (rdev->family == CHIP_RV410) || \
2624 (rdev->family == CHIP_RS400) || \
2625 (rdev->family == CHIP_RS480))
2626 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2627 (rdev->ddev->pdev->device == 0x9443) || \
2628 (rdev->ddev->pdev->device == 0x944B) || \
2629 (rdev->ddev->pdev->device == 0x9506) || \
2630 (rdev->ddev->pdev->device == 0x9509) || \
2631 (rdev->ddev->pdev->device == 0x950F) || \
2632 (rdev->ddev->pdev->device == 0x689C) || \
2633 (rdev->ddev->pdev->device == 0x689D))
2634 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2635 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2636 (rdev->family == CHIP_RS690) || \
2637 (rdev->family == CHIP_RS740) || \
2638 (rdev->family >= CHIP_R600))
2639 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2640 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2641 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2642 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2643 (rdev->flags & RADEON_IS_IGP))
2644 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2645 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2646 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2647 (rdev->flags & RADEON_IS_IGP))
2648 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2649 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2650 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2651 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2652 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2653 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2654 (rdev->family == CHIP_MULLINS))
2655
2656 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2657 (rdev->ddev->pdev->device == 0x6850) || \
2658 (rdev->ddev->pdev->device == 0x6858) || \
2659 (rdev->ddev->pdev->device == 0x6859) || \
2660 (rdev->ddev->pdev->device == 0x6840) || \
2661 (rdev->ddev->pdev->device == 0x6841) || \
2662 (rdev->ddev->pdev->device == 0x6842) || \
2663 (rdev->ddev->pdev->device == 0x6843))
2664
2665 /*
2666 * BIOS helpers.
2667 */
2668 #define RBIOS8(i) (rdev->bios[i])
2669 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2670 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2671
2672 int radeon_combios_init(struct radeon_device *rdev);
2673 void radeon_combios_fini(struct radeon_device *rdev);
2674 int radeon_atombios_init(struct radeon_device *rdev);
2675 void radeon_atombios_fini(struct radeon_device *rdev);
2676
2677
2678 /*
2679 * RING helpers.
2680 */
2681
2682 /**
2683 * radeon_ring_write - write a value to the ring
2684 *
2685 * @ring: radeon_ring structure holding ring information
2686 * @v: dword (dw) value to write
2687 *
2688 * Write a value to the requested ring buffer (all asics).
2689 */
radeon_ring_write(struct radeon_ring * ring,uint32_t v)2690 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2691 {
2692 if (ring->count_dw <= 0)
2693 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2694
2695 ring->ring[ring->wptr++] = v;
2696 ring->wptr &= ring->ptr_mask;
2697 ring->count_dw--;
2698 ring->ring_free_dw--;
2699 }
2700
2701 /*
2702 * ASICs macro.
2703 */
2704 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2705 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2706 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2707 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2708 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2709 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2710 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2711 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2712 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2713 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2714 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2715 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2716 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2717 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2718 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2719 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2720 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2721 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2722 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2723 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2724 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2725 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2726 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2727 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2728 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2729 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2730 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2731 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2732 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2733 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2734 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2735 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2736 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2737 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2738 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2739 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2740 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2741 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2742 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2743 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2744 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2745 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2746 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2747 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2748 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2749 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2750 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2751 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2752 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2753 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2754 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2755 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2756 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2757 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2758 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2759 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2760 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2761 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2762 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2763 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2764 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2765 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2766 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2767 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2768 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2769 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2770 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2771 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2772 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2773 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2774 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2775 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2776 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2777 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2778 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2779 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2780 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2781 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2782 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2783 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2784 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2785 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2786 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2787 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2788 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2789 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2790 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2791 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2792 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2793 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2794 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2795
2796 /* Common functions */
2797 /* AGP */
2798 extern int radeon_gpu_reset(struct radeon_device *rdev);
2799 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2800 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2801 extern void radeon_agp_disable(struct radeon_device *rdev);
2802 extern int radeon_modeset_init(struct radeon_device *rdev);
2803 extern void radeon_modeset_fini(struct radeon_device *rdev);
2804 extern bool radeon_card_posted(struct radeon_device *rdev);
2805 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2806 extern void radeon_update_display_priority(struct radeon_device *rdev);
2807 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2808 extern void radeon_scratch_init(struct radeon_device *rdev);
2809 extern void radeon_wb_fini(struct radeon_device *rdev);
2810 extern int radeon_wb_init(struct radeon_device *rdev);
2811 extern void radeon_wb_disable(struct radeon_device *rdev);
2812 extern void radeon_surface_init(struct radeon_device *rdev);
2813 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2814 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2815 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2816 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2817 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2818 extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
2819 struct ttm_tt *ttm, uint64_t addr,
2820 uint32_t flags);
2821 extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm);
2822 extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm);
2823 bool radeon_ttm_tt_is_bound(struct ttm_bo_device *bdev, struct ttm_tt *ttm);
2824 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2825 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2826 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2827 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2828 bool fbcon, bool freeze);
2829 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2830 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2831 const u32 *registers,
2832 const u32 array_size);
2833 struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev);
2834
2835 /*
2836 * vm
2837 */
2838 int radeon_vm_manager_init(struct radeon_device *rdev);
2839 void radeon_vm_manager_fini(struct radeon_device *rdev);
2840 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2841 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2842 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2843 struct radeon_vm *vm,
2844 struct list_head *head);
2845 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2846 struct radeon_vm *vm, int ring);
2847 void radeon_vm_flush(struct radeon_device *rdev,
2848 struct radeon_vm *vm,
2849 int ring, struct radeon_fence *fence);
2850 void radeon_vm_fence(struct radeon_device *rdev,
2851 struct radeon_vm *vm,
2852 struct radeon_fence *fence);
2853 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2854 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2855 struct radeon_vm *vm);
2856 int radeon_vm_clear_freed(struct radeon_device *rdev,
2857 struct radeon_vm *vm);
2858 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2859 struct radeon_vm *vm);
2860 int radeon_vm_bo_update(struct radeon_device *rdev,
2861 struct radeon_bo_va *bo_va,
2862 struct ttm_resource *mem);
2863 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2864 struct radeon_bo *bo);
2865 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2866 struct radeon_bo *bo);
2867 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2868 struct radeon_vm *vm,
2869 struct radeon_bo *bo);
2870 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2871 struct radeon_bo_va *bo_va,
2872 uint64_t offset,
2873 uint32_t flags);
2874 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2875 struct radeon_bo_va *bo_va);
2876
2877 /* audio */
2878 void r600_audio_update_hdmi(struct work_struct *work);
2879 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2880 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2881 void r600_audio_enable(struct radeon_device *rdev,
2882 struct r600_audio_pin *pin,
2883 u8 enable_mask);
2884 void dce6_audio_enable(struct radeon_device *rdev,
2885 struct r600_audio_pin *pin,
2886 u8 enable_mask);
2887
2888 /*
2889 * R600 vram scratch functions
2890 */
2891 int r600_vram_scratch_init(struct radeon_device *rdev);
2892 void r600_vram_scratch_fini(struct radeon_device *rdev);
2893
2894 /*
2895 * r600 cs checking helper
2896 */
2897 unsigned r600_mip_minify(unsigned size, unsigned level);
2898 bool r600_fmt_is_valid_color(u32 format);
2899 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2900 int r600_fmt_get_blocksize(u32 format);
2901 int r600_fmt_get_nblocksx(u32 format, u32 w);
2902 int r600_fmt_get_nblocksy(u32 format, u32 h);
2903
2904 /*
2905 * r600 functions used by radeon_encoder.c
2906 */
2907 struct radeon_hdmi_acr {
2908 u32 clock;
2909
2910 int n_32khz;
2911 int cts_32khz;
2912
2913 int n_44_1khz;
2914 int cts_44_1khz;
2915
2916 int n_48khz;
2917 int cts_48khz;
2918
2919 };
2920
2921 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2922
2923 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2924 u32 tiling_pipe_num,
2925 u32 max_rb_num,
2926 u32 total_max_rb_num,
2927 u32 enabled_rb_mask);
2928
2929 /*
2930 * evergreen functions used by radeon_encoder.c
2931 */
2932
2933 extern int ni_init_microcode(struct radeon_device *rdev);
2934 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2935
2936 /* radeon_acpi.c */
2937 #if defined(CONFIG_ACPI)
2938 extern int radeon_acpi_init(struct radeon_device *rdev);
2939 extern void radeon_acpi_fini(struct radeon_device *rdev);
2940 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2941 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2942 u8 perf_req, bool advertise);
2943 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2944 #else
radeon_acpi_init(struct radeon_device * rdev)2945 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
radeon_acpi_fini(struct radeon_device * rdev)2946 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2947 #endif
2948
2949 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2950 struct radeon_cs_packet *pkt,
2951 unsigned idx);
2952 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2953 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2954 struct radeon_cs_packet *pkt);
2955 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2956 struct radeon_bo_list **cs_reloc,
2957 int nomm);
2958 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2959 uint32_t *vline_start_end,
2960 uint32_t *vline_status);
2961
2962 /* interrupt control register helpers */
2963 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
2964 u32 reg, u32 mask,
2965 bool enable, const char *name,
2966 unsigned n);
2967
2968 #include "radeon_object.h"
2969
2970 #endif
2971
