1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
69 #include <linux/dma-fence.h>
70
71 #include <drm/ttm/ttm_bo_api.h>
72 #include <drm/ttm/ttm_bo_driver.h>
73 #include <drm/ttm/ttm_placement.h>
74 #include <drm/ttm/ttm_module.h>
75 #include <drm/ttm/ttm_execbuf_util.h>
76
77 #include <drm/drm_gem.h>
78
79 #include "radeon_family.h"
80 #include "radeon_mode.h"
81 #include "radeon_reg.h"
82
83 /*
84 * Modules parameters.
85 */
86 extern int radeon_no_wb;
87 extern int radeon_modeset;
88 extern int radeon_dynclks;
89 extern int radeon_r4xx_atom;
90 extern int radeon_agpmode;
91 extern int radeon_vram_limit;
92 extern int radeon_gart_size;
93 extern int radeon_benchmarking;
94 extern int radeon_testing;
95 extern int radeon_connector_table;
96 extern int radeon_tv;
97 extern int radeon_audio;
98 extern int radeon_disp_priority;
99 extern int radeon_hw_i2c;
100 extern int radeon_pcie_gen2;
101 extern int radeon_msi;
102 extern int radeon_lockup_timeout;
103 extern int radeon_fastfb;
104 extern int radeon_dpm;
105 extern int radeon_aspm;
106 extern int radeon_runtime_pm;
107 extern int radeon_hard_reset;
108 extern int radeon_vm_size;
109 extern int radeon_vm_block_size;
110 extern int radeon_deep_color;
111 extern int radeon_use_pflipirq;
112 extern int radeon_bapm;
113 extern int radeon_backlight;
114 extern int radeon_auxch;
115 extern int radeon_mst;
116 extern int radeon_uvd;
117 extern int radeon_vce;
118 extern int radeon_si_support;
119 extern int radeon_cik_support;
120
121 /*
122 * Copy from radeon_drv.h so we don't have to include both and have conflicting
123 * symbol;
124 */
125 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
126 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
127 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
128 /* RADEON_IB_POOL_SIZE must be a power of 2 */
129 #define RADEON_IB_POOL_SIZE 16
130 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
131 #define RADEONFB_CONN_LIMIT 4
132 #define RADEON_BIOS_NUM_SCRATCH 8
133
134 /* internal ring indices */
135 /* r1xx+ has gfx CP ring */
136 #define RADEON_RING_TYPE_GFX_INDEX 0
137
138 /* cayman has 2 compute CP rings */
139 #define CAYMAN_RING_TYPE_CP1_INDEX 1
140 #define CAYMAN_RING_TYPE_CP2_INDEX 2
141
142 /* R600+ has an async dma ring */
143 #define R600_RING_TYPE_DMA_INDEX 3
144 /* cayman add a second async dma ring */
145 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
146
147 /* R600+ */
148 #define R600_RING_TYPE_UVD_INDEX 5
149
150 /* TN+ */
151 #define TN_RING_TYPE_VCE1_INDEX 6
152 #define TN_RING_TYPE_VCE2_INDEX 7
153
154 /* max number of rings */
155 #define RADEON_NUM_RINGS 8
156
157 /* number of hw syncs before falling back on blocking */
158 #define RADEON_NUM_SYNCS 4
159
160 /* hardcode those limit for now */
161 #define RADEON_VA_IB_OFFSET (1 << 20)
162 #define RADEON_VA_RESERVED_SIZE (8 << 20)
163 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
164
165 /* hard reset data */
166 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
167
168 /* reset flags */
169 #define RADEON_RESET_GFX (1 << 0)
170 #define RADEON_RESET_COMPUTE (1 << 1)
171 #define RADEON_RESET_DMA (1 << 2)
172 #define RADEON_RESET_CP (1 << 3)
173 #define RADEON_RESET_GRBM (1 << 4)
174 #define RADEON_RESET_DMA1 (1 << 5)
175 #define RADEON_RESET_RLC (1 << 6)
176 #define RADEON_RESET_SEM (1 << 7)
177 #define RADEON_RESET_IH (1 << 8)
178 #define RADEON_RESET_VMC (1 << 9)
179 #define RADEON_RESET_MC (1 << 10)
180 #define RADEON_RESET_DISPLAY (1 << 11)
181
182 /* CG block flags */
183 #define RADEON_CG_BLOCK_GFX (1 << 0)
184 #define RADEON_CG_BLOCK_MC (1 << 1)
185 #define RADEON_CG_BLOCK_SDMA (1 << 2)
186 #define RADEON_CG_BLOCK_UVD (1 << 3)
187 #define RADEON_CG_BLOCK_VCE (1 << 4)
188 #define RADEON_CG_BLOCK_HDP (1 << 5)
189 #define RADEON_CG_BLOCK_BIF (1 << 6)
190
191 /* CG flags */
192 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
193 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
194 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
195 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
196 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
197 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
198 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
199 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
200 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
201 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
202 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
203 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
204 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
205 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
206 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
207 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
208 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
209
210 /* PG flags */
211 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
212 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
213 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
214 #define RADEON_PG_SUPPORT_UVD (1 << 3)
215 #define RADEON_PG_SUPPORT_VCE (1 << 4)
216 #define RADEON_PG_SUPPORT_CP (1 << 5)
217 #define RADEON_PG_SUPPORT_GDS (1 << 6)
218 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
219 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
220 #define RADEON_PG_SUPPORT_ACP (1 << 9)
221 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
222
223 /* max cursor sizes (in pixels) */
224 #define CURSOR_WIDTH 64
225 #define CURSOR_HEIGHT 64
226
227 #define CIK_CURSOR_WIDTH 128
228 #define CIK_CURSOR_HEIGHT 128
229
230 /*
231 * Errata workarounds.
232 */
233 enum radeon_pll_errata {
234 CHIP_ERRATA_R300_CG = 0x00000001,
235 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
236 CHIP_ERRATA_PLL_DELAY = 0x00000004
237 };
238
239
240 struct radeon_device;
241
242
243 /*
244 * BIOS.
245 */
246 bool radeon_get_bios(struct radeon_device *rdev);
247
248 /*
249 * Dummy page
250 */
251 struct radeon_dummy_page {
252 uint64_t entry;
253 struct page *page;
254 dma_addr_t addr;
255 };
256 int radeon_dummy_page_init(struct radeon_device *rdev);
257 void radeon_dummy_page_fini(struct radeon_device *rdev);
258
259
260 /*
261 * Clocks
262 */
263 struct radeon_clock {
264 struct radeon_pll p1pll;
265 struct radeon_pll p2pll;
266 struct radeon_pll dcpll;
267 struct radeon_pll spll;
268 struct radeon_pll mpll;
269 /* 10 Khz units */
270 uint32_t default_mclk;
271 uint32_t default_sclk;
272 uint32_t default_dispclk;
273 uint32_t current_dispclk;
274 uint32_t dp_extclk;
275 uint32_t max_pixel_clock;
276 uint32_t vco_freq;
277 };
278
279 /*
280 * Power management
281 */
282 int radeon_pm_init(struct radeon_device *rdev);
283 int radeon_pm_late_init(struct radeon_device *rdev);
284 void radeon_pm_fini(struct radeon_device *rdev);
285 void radeon_pm_compute_clocks(struct radeon_device *rdev);
286 void radeon_pm_suspend(struct radeon_device *rdev);
287 void radeon_pm_resume(struct radeon_device *rdev);
288 void radeon_combios_get_power_modes(struct radeon_device *rdev);
289 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
290 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
291 u8 clock_type,
292 u32 clock,
293 bool strobe_mode,
294 struct atom_clock_dividers *dividers);
295 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
296 u32 clock,
297 bool strobe_mode,
298 struct atom_mpll_param *mpll_param);
299 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
300 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
301 u16 voltage_level, u8 voltage_type,
302 u32 *gpio_value, u32 *gpio_mask);
303 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
304 u32 eng_clock, u32 mem_clock);
305 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
306 u8 voltage_type, u16 *voltage_step);
307 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
308 u16 voltage_id, u16 *voltage);
309 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
310 u16 *voltage,
311 u16 leakage_idx);
312 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
313 u16 *leakage_id);
314 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
315 u16 *vddc, u16 *vddci,
316 u16 virtual_voltage_id,
317 u16 vbios_voltage_id);
318 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
319 u16 virtual_voltage_id,
320 u16 *voltage);
321 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
322 u8 voltage_type,
323 u16 nominal_voltage,
324 u16 *true_voltage);
325 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
326 u8 voltage_type, u16 *min_voltage);
327 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
328 u8 voltage_type, u16 *max_voltage);
329 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
330 u8 voltage_type, u8 voltage_mode,
331 struct atom_voltage_table *voltage_table);
332 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
333 u8 voltage_type, u8 voltage_mode);
334 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
335 u8 voltage_type,
336 u8 *svd_gpio_id, u8 *svc_gpio_id);
337 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
338 u32 mem_clock);
339 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
340 u32 mem_clock);
341 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
342 u8 module_index,
343 struct atom_mc_reg_table *reg_table);
344 int radeon_atom_get_memory_info(struct radeon_device *rdev,
345 u8 module_index, struct atom_memory_info *mem_info);
346 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
347 bool gddr5, u8 module_index,
348 struct atom_memory_clock_range_table *mclk_range_table);
349 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
350 u16 voltage_id, u16 *voltage);
351 void rs690_pm_info(struct radeon_device *rdev);
352 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
353 unsigned *bankh, unsigned *mtaspect,
354 unsigned *tile_split);
355
356 /*
357 * Fences.
358 */
359 struct radeon_fence_driver {
360 struct radeon_device *rdev;
361 uint32_t scratch_reg;
362 uint64_t gpu_addr;
363 volatile uint32_t *cpu_addr;
364 /* sync_seq is protected by ring emission lock */
365 uint64_t sync_seq[RADEON_NUM_RINGS];
366 atomic64_t last_seq;
367 bool initialized, delayed_irq;
368 struct delayed_work lockup_work;
369 };
370
371 struct radeon_fence {
372 struct dma_fence base;
373
374 struct radeon_device *rdev;
375 uint64_t seq;
376 /* RB, DMA, etc. */
377 unsigned ring;
378 bool is_vm_update;
379
380 wait_queue_entry_t fence_wake;
381 };
382
383 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
384 int radeon_fence_driver_init(struct radeon_device *rdev);
385 void radeon_fence_driver_fini(struct radeon_device *rdev);
386 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
387 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
388 void radeon_fence_process(struct radeon_device *rdev, int ring);
389 bool radeon_fence_signaled(struct radeon_fence *fence);
390 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
391 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
392 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
393 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
394 int radeon_fence_wait_any(struct radeon_device *rdev,
395 struct radeon_fence **fences,
396 bool intr);
397 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
398 void radeon_fence_unref(struct radeon_fence **fence);
399 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
400 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
401 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
radeon_fence_later(struct radeon_fence * a,struct radeon_fence * b)402 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
403 struct radeon_fence *b)
404 {
405 if (!a) {
406 return b;
407 }
408
409 if (!b) {
410 return a;
411 }
412
413 BUG_ON(a->ring != b->ring);
414
415 if (a->seq > b->seq) {
416 return a;
417 } else {
418 return b;
419 }
420 }
421
radeon_fence_is_earlier(struct radeon_fence * a,struct radeon_fence * b)422 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
423 struct radeon_fence *b)
424 {
425 if (!a) {
426 return false;
427 }
428
429 if (!b) {
430 return true;
431 }
432
433 BUG_ON(a->ring != b->ring);
434
435 return a->seq < b->seq;
436 }
437
438 /*
439 * Tiling registers
440 */
441 struct radeon_surface_reg {
442 struct radeon_bo *bo;
443 };
444
445 #define RADEON_GEM_MAX_SURFACES 8
446
447 /*
448 * TTM.
449 */
450 struct radeon_mman {
451 struct ttm_bo_global_ref bo_global_ref;
452 struct drm_global_reference mem_global_ref;
453 struct ttm_bo_device bdev;
454 bool mem_global_referenced;
455 bool initialized;
456
457 #if defined(CONFIG_DEBUG_FS)
458 struct dentry *vram;
459 struct dentry *gtt;
460 #endif
461 };
462
463 struct radeon_bo_list {
464 struct radeon_bo *robj;
465 struct ttm_validate_buffer tv;
466 uint64_t gpu_offset;
467 unsigned preferred_domains;
468 unsigned allowed_domains;
469 uint32_t tiling_flags;
470 };
471
472 /* bo virtual address in a specific vm */
473 struct radeon_bo_va {
474 /* protected by bo being reserved */
475 struct list_head bo_list;
476 uint32_t flags;
477 struct radeon_fence *last_pt_update;
478 unsigned ref_count;
479
480 /* protected by vm mutex */
481 struct interval_tree_node it;
482 struct list_head vm_status;
483
484 /* constant after initialization */
485 struct radeon_vm *vm;
486 struct radeon_bo *bo;
487 };
488
489 struct radeon_bo {
490 /* Protected by gem.mutex */
491 struct list_head list;
492 /* Protected by tbo.reserved */
493 u32 initial_domain;
494 struct ttm_place placements[4];
495 struct ttm_placement placement;
496 struct ttm_buffer_object tbo;
497 struct ttm_bo_kmap_obj kmap;
498 u32 flags;
499 unsigned pin_count;
500 void *kptr;
501 u32 tiling_flags;
502 u32 pitch;
503 int surface_reg;
504 unsigned prime_shared_count;
505 /* list of all virtual address to which this bo
506 * is associated to
507 */
508 struct list_head va;
509 /* Constant after initialization */
510 struct radeon_device *rdev;
511 struct drm_gem_object gem_base;
512
513 struct ttm_bo_kmap_obj dma_buf_vmap;
514 pid_t pid;
515
516 struct radeon_mn *mn;
517 struct list_head mn_list;
518 };
519 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
520
521 int radeon_gem_debugfs_init(struct radeon_device *rdev);
522
523 /* sub-allocation manager, it has to be protected by another lock.
524 * By conception this is an helper for other part of the driver
525 * like the indirect buffer or semaphore, which both have their
526 * locking.
527 *
528 * Principe is simple, we keep a list of sub allocation in offset
529 * order (first entry has offset == 0, last entry has the highest
530 * offset).
531 *
532 * When allocating new object we first check if there is room at
533 * the end total_size - (last_object_offset + last_object_size) >=
534 * alloc_size. If so we allocate new object there.
535 *
536 * When there is not enough room at the end, we start waiting for
537 * each sub object until we reach object_offset+object_size >=
538 * alloc_size, this object then become the sub object we return.
539 *
540 * Alignment can't be bigger than page size.
541 *
542 * Hole are not considered for allocation to keep things simple.
543 * Assumption is that there won't be hole (all object on same
544 * alignment).
545 */
546 struct radeon_sa_manager {
547 wait_queue_head_t wq;
548 struct radeon_bo *bo;
549 struct list_head *hole;
550 struct list_head flist[RADEON_NUM_RINGS];
551 struct list_head olist;
552 unsigned size;
553 uint64_t gpu_addr;
554 void *cpu_ptr;
555 uint32_t domain;
556 uint32_t align;
557 };
558
559 struct radeon_sa_bo;
560
561 /* sub-allocation buffer */
562 struct radeon_sa_bo {
563 struct list_head olist;
564 struct list_head flist;
565 struct radeon_sa_manager *manager;
566 unsigned soffset;
567 unsigned eoffset;
568 struct radeon_fence *fence;
569 };
570
571 /*
572 * GEM objects.
573 */
574 struct radeon_gem {
575 struct mutex mutex;
576 struct list_head objects;
577 };
578
579 int radeon_gem_init(struct radeon_device *rdev);
580 void radeon_gem_fini(struct radeon_device *rdev);
581 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
582 int alignment, int initial_domain,
583 u32 flags, bool kernel,
584 struct drm_gem_object **obj);
585
586 int radeon_mode_dumb_create(struct drm_file *file_priv,
587 struct drm_device *dev,
588 struct drm_mode_create_dumb *args);
589 int radeon_mode_dumb_mmap(struct drm_file *filp,
590 struct drm_device *dev,
591 uint32_t handle, uint64_t *offset_p);
592
593 /*
594 * Semaphores.
595 */
596 struct radeon_semaphore {
597 struct radeon_sa_bo *sa_bo;
598 signed waiters;
599 uint64_t gpu_addr;
600 };
601
602 int radeon_semaphore_create(struct radeon_device *rdev,
603 struct radeon_semaphore **semaphore);
604 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
605 struct radeon_semaphore *semaphore);
606 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
607 struct radeon_semaphore *semaphore);
608 void radeon_semaphore_free(struct radeon_device *rdev,
609 struct radeon_semaphore **semaphore,
610 struct radeon_fence *fence);
611
612 /*
613 * Synchronization
614 */
615 struct radeon_sync {
616 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
617 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
618 struct radeon_fence *last_vm_update;
619 };
620
621 void radeon_sync_create(struct radeon_sync *sync);
622 void radeon_sync_fence(struct radeon_sync *sync,
623 struct radeon_fence *fence);
624 int radeon_sync_resv(struct radeon_device *rdev,
625 struct radeon_sync *sync,
626 struct reservation_object *resv,
627 bool shared);
628 int radeon_sync_rings(struct radeon_device *rdev,
629 struct radeon_sync *sync,
630 int waiting_ring);
631 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
632 struct radeon_fence *fence);
633
634 /*
635 * GART structures, functions & helpers
636 */
637 struct radeon_mc;
638
639 #define RADEON_GPU_PAGE_SIZE 4096
640 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
641 #define RADEON_GPU_PAGE_SHIFT 12
642 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
643
644 #define RADEON_GART_PAGE_DUMMY 0
645 #define RADEON_GART_PAGE_VALID (1 << 0)
646 #define RADEON_GART_PAGE_READ (1 << 1)
647 #define RADEON_GART_PAGE_WRITE (1 << 2)
648 #define RADEON_GART_PAGE_SNOOP (1 << 3)
649
650 struct radeon_gart {
651 dma_addr_t table_addr;
652 struct radeon_bo *robj;
653 void *ptr;
654 unsigned num_gpu_pages;
655 unsigned num_cpu_pages;
656 unsigned table_size;
657 struct page **pages;
658 uint64_t *pages_entry;
659 bool ready;
660 };
661
662 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
663 void radeon_gart_table_ram_free(struct radeon_device *rdev);
664 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
665 void radeon_gart_table_vram_free(struct radeon_device *rdev);
666 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
667 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
668 int radeon_gart_init(struct radeon_device *rdev);
669 void radeon_gart_fini(struct radeon_device *rdev);
670 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
671 int pages);
672 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
673 int pages, struct page **pagelist,
674 dma_addr_t *dma_addr, uint32_t flags);
675
676
677 /*
678 * GPU MC structures, functions & helpers
679 */
680 struct radeon_mc {
681 resource_size_t aper_size;
682 resource_size_t aper_base;
683 resource_size_t agp_base;
684 /* for some chips with <= 32MB we need to lie
685 * about vram size near mc fb location */
686 u64 mc_vram_size;
687 u64 visible_vram_size;
688 u64 gtt_size;
689 u64 gtt_start;
690 u64 gtt_end;
691 u64 vram_start;
692 u64 vram_end;
693 unsigned vram_width;
694 u64 real_vram_size;
695 int vram_mtrr;
696 bool vram_is_ddr;
697 bool igp_sideport_enabled;
698 u64 gtt_base_align;
699 u64 mc_mask;
700 };
701
702 bool radeon_combios_sideport_present(struct radeon_device *rdev);
703 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
704
705 /*
706 * GPU scratch registers structures, functions & helpers
707 */
708 struct radeon_scratch {
709 unsigned num_reg;
710 uint32_t reg_base;
711 bool free[32];
712 uint32_t reg[32];
713 };
714
715 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
716 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
717
718 /*
719 * GPU doorbell structures, functions & helpers
720 */
721 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
722
723 struct radeon_doorbell {
724 /* doorbell mmio */
725 resource_size_t base;
726 resource_size_t size;
727 u32 __iomem *ptr;
728 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
729 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
730 };
731
732 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
733 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
734
735 /*
736 * IRQS.
737 */
738
739 struct radeon_flip_work {
740 struct work_struct flip_work;
741 struct work_struct unpin_work;
742 struct radeon_device *rdev;
743 int crtc_id;
744 u32 target_vblank;
745 uint64_t base;
746 struct drm_pending_vblank_event *event;
747 struct radeon_bo *old_rbo;
748 struct dma_fence *fence;
749 bool async;
750 };
751
752 struct r500_irq_stat_regs {
753 u32 disp_int;
754 u32 hdmi0_status;
755 };
756
757 struct r600_irq_stat_regs {
758 u32 disp_int;
759 u32 disp_int_cont;
760 u32 disp_int_cont2;
761 u32 d1grph_int;
762 u32 d2grph_int;
763 u32 hdmi0_status;
764 u32 hdmi1_status;
765 };
766
767 struct evergreen_irq_stat_regs {
768 u32 disp_int[6];
769 u32 grph_int[6];
770 u32 afmt_status[6];
771 };
772
773 struct cik_irq_stat_regs {
774 u32 disp_int;
775 u32 disp_int_cont;
776 u32 disp_int_cont2;
777 u32 disp_int_cont3;
778 u32 disp_int_cont4;
779 u32 disp_int_cont5;
780 u32 disp_int_cont6;
781 u32 d1grph_int;
782 u32 d2grph_int;
783 u32 d3grph_int;
784 u32 d4grph_int;
785 u32 d5grph_int;
786 u32 d6grph_int;
787 };
788
789 union radeon_irq_stat_regs {
790 struct r500_irq_stat_regs r500;
791 struct r600_irq_stat_regs r600;
792 struct evergreen_irq_stat_regs evergreen;
793 struct cik_irq_stat_regs cik;
794 };
795
796 struct radeon_irq {
797 bool installed;
798 spinlock_t lock;
799 atomic_t ring_int[RADEON_NUM_RINGS];
800 bool crtc_vblank_int[RADEON_MAX_CRTCS];
801 atomic_t pflip[RADEON_MAX_CRTCS];
802 wait_queue_head_t vblank_queue;
803 bool hpd[RADEON_MAX_HPD_PINS];
804 bool afmt[RADEON_MAX_AFMT_BLOCKS];
805 union radeon_irq_stat_regs stat_regs;
806 bool dpm_thermal;
807 };
808
809 int radeon_irq_kms_init(struct radeon_device *rdev);
810 void radeon_irq_kms_fini(struct radeon_device *rdev);
811 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
812 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
813 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
814 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
815 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
816 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
817 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
818 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
819 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
820
821 /*
822 * CP & rings.
823 */
824
825 struct radeon_ib {
826 struct radeon_sa_bo *sa_bo;
827 uint32_t length_dw;
828 uint64_t gpu_addr;
829 uint32_t *ptr;
830 int ring;
831 struct radeon_fence *fence;
832 struct radeon_vm *vm;
833 bool is_const_ib;
834 struct radeon_sync sync;
835 };
836
837 struct radeon_ring {
838 struct radeon_bo *ring_obj;
839 volatile uint32_t *ring;
840 unsigned rptr_offs;
841 unsigned rptr_save_reg;
842 u64 next_rptr_gpu_addr;
843 volatile u32 *next_rptr_cpu_addr;
844 unsigned wptr;
845 unsigned wptr_old;
846 unsigned ring_size;
847 unsigned ring_free_dw;
848 int count_dw;
849 atomic_t last_rptr;
850 atomic64_t last_activity;
851 uint64_t gpu_addr;
852 uint32_t align_mask;
853 uint32_t ptr_mask;
854 bool ready;
855 u32 nop;
856 u32 idx;
857 u64 last_semaphore_signal_addr;
858 u64 last_semaphore_wait_addr;
859 /* for CIK queues */
860 u32 me;
861 u32 pipe;
862 u32 queue;
863 struct radeon_bo *mqd_obj;
864 u32 doorbell_index;
865 unsigned wptr_offs;
866 };
867
868 struct radeon_mec {
869 struct radeon_bo *hpd_eop_obj;
870 u64 hpd_eop_gpu_addr;
871 u32 num_pipe;
872 u32 num_mec;
873 u32 num_queue;
874 };
875
876 /*
877 * VM
878 */
879
880 /* maximum number of VMIDs */
881 #define RADEON_NUM_VM 16
882
883 /* number of entries in page table */
884 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
885
886 /* PTBs (Page Table Blocks) need to be aligned to 32K */
887 #define RADEON_VM_PTB_ALIGN_SIZE 32768
888 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
889 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
890
891 #define R600_PTE_VALID (1 << 0)
892 #define R600_PTE_SYSTEM (1 << 1)
893 #define R600_PTE_SNOOPED (1 << 2)
894 #define R600_PTE_READABLE (1 << 5)
895 #define R600_PTE_WRITEABLE (1 << 6)
896
897 /* PTE (Page Table Entry) fragment field for different page sizes */
898 #define R600_PTE_FRAG_4KB (0 << 7)
899 #define R600_PTE_FRAG_64KB (4 << 7)
900 #define R600_PTE_FRAG_256KB (6 << 7)
901
902 /* flags needed to be set so we can copy directly from the GART table */
903 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
904 R600_PTE_SYSTEM | R600_PTE_VALID )
905
906 struct radeon_vm_pt {
907 struct radeon_bo *bo;
908 uint64_t addr;
909 };
910
911 struct radeon_vm_id {
912 unsigned id;
913 uint64_t pd_gpu_addr;
914 /* last flushed PD/PT update */
915 struct radeon_fence *flushed_updates;
916 /* last use of vmid */
917 struct radeon_fence *last_id_use;
918 };
919
920 struct radeon_vm {
921 struct mutex mutex;
922
923 struct rb_root_cached va;
924
925 /* protecting invalidated and freed */
926 spinlock_t status_lock;
927
928 /* BOs moved, but not yet updated in the PT */
929 struct list_head invalidated;
930
931 /* BOs freed, but not yet updated in the PT */
932 struct list_head freed;
933
934 /* BOs cleared in the PT */
935 struct list_head cleared;
936
937 /* contains the page directory */
938 struct radeon_bo *page_directory;
939 unsigned max_pde_used;
940
941 /* array of page tables, one for each page directory entry */
942 struct radeon_vm_pt *page_tables;
943
944 struct radeon_bo_va *ib_bo_va;
945
946 /* for id and flush management per ring */
947 struct radeon_vm_id ids[RADEON_NUM_RINGS];
948 };
949
950 struct radeon_vm_manager {
951 struct radeon_fence *active[RADEON_NUM_VM];
952 uint32_t max_pfn;
953 /* number of VMIDs */
954 unsigned nvm;
955 /* vram base address for page table entry */
956 u64 vram_base_offset;
957 /* is vm enabled? */
958 bool enabled;
959 /* for hw to save the PD addr on suspend/resume */
960 uint32_t saved_table_addr[RADEON_NUM_VM];
961 };
962
963 /*
964 * file private structure
965 */
966 struct radeon_fpriv {
967 struct radeon_vm vm;
968 };
969
970 /*
971 * R6xx+ IH ring
972 */
973 struct r600_ih {
974 struct radeon_bo *ring_obj;
975 volatile uint32_t *ring;
976 unsigned rptr;
977 unsigned ring_size;
978 uint64_t gpu_addr;
979 uint32_t ptr_mask;
980 atomic_t lock;
981 bool enabled;
982 };
983
984 /*
985 * RLC stuff
986 */
987 #include "clearstate_defs.h"
988
989 struct radeon_rlc {
990 /* for power gating */
991 struct radeon_bo *save_restore_obj;
992 uint64_t save_restore_gpu_addr;
993 volatile uint32_t *sr_ptr;
994 const u32 *reg_list;
995 u32 reg_list_size;
996 /* for clear state */
997 struct radeon_bo *clear_state_obj;
998 uint64_t clear_state_gpu_addr;
999 volatile uint32_t *cs_ptr;
1000 const struct cs_section_def *cs_data;
1001 u32 clear_state_size;
1002 /* for cp tables */
1003 struct radeon_bo *cp_table_obj;
1004 uint64_t cp_table_gpu_addr;
1005 volatile uint32_t *cp_table_ptr;
1006 u32 cp_table_size;
1007 };
1008
1009 int radeon_ib_get(struct radeon_device *rdev, int ring,
1010 struct radeon_ib *ib, struct radeon_vm *vm,
1011 unsigned size);
1012 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1013 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1014 struct radeon_ib *const_ib, bool hdp_flush);
1015 int radeon_ib_pool_init(struct radeon_device *rdev);
1016 void radeon_ib_pool_fini(struct radeon_device *rdev);
1017 int radeon_ib_ring_tests(struct radeon_device *rdev);
1018 /* Ring access between begin & end cannot sleep */
1019 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1020 struct radeon_ring *ring);
1021 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1022 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1023 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1024 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1025 bool hdp_flush);
1026 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1027 bool hdp_flush);
1028 void radeon_ring_undo(struct radeon_ring *ring);
1029 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1030 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1031 void radeon_ring_lockup_update(struct radeon_device *rdev,
1032 struct radeon_ring *ring);
1033 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1034 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1035 uint32_t **data);
1036 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1037 unsigned size, uint32_t *data);
1038 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1039 unsigned rptr_offs, u32 nop);
1040 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1041
1042
1043 /* r600 async dma */
1044 void r600_dma_stop(struct radeon_device *rdev);
1045 int r600_dma_resume(struct radeon_device *rdev);
1046 void r600_dma_fini(struct radeon_device *rdev);
1047
1048 void cayman_dma_stop(struct radeon_device *rdev);
1049 int cayman_dma_resume(struct radeon_device *rdev);
1050 void cayman_dma_fini(struct radeon_device *rdev);
1051
1052 /*
1053 * CS.
1054 */
1055 struct radeon_cs_chunk {
1056 uint32_t length_dw;
1057 uint32_t *kdata;
1058 void __user *user_ptr;
1059 };
1060
1061 struct radeon_cs_parser {
1062 struct device *dev;
1063 struct radeon_device *rdev;
1064 struct drm_file *filp;
1065 /* chunks */
1066 unsigned nchunks;
1067 struct radeon_cs_chunk *chunks;
1068 uint64_t *chunks_array;
1069 /* IB */
1070 unsigned idx;
1071 /* relocations */
1072 unsigned nrelocs;
1073 struct radeon_bo_list *relocs;
1074 struct radeon_bo_list *vm_bos;
1075 struct list_head validated;
1076 unsigned dma_reloc_idx;
1077 /* indices of various chunks */
1078 struct radeon_cs_chunk *chunk_ib;
1079 struct radeon_cs_chunk *chunk_relocs;
1080 struct radeon_cs_chunk *chunk_flags;
1081 struct radeon_cs_chunk *chunk_const_ib;
1082 struct radeon_ib ib;
1083 struct radeon_ib const_ib;
1084 void *track;
1085 unsigned family;
1086 int parser_error;
1087 u32 cs_flags;
1088 u32 ring;
1089 s32 priority;
1090 struct ww_acquire_ctx ticket;
1091 };
1092
radeon_get_ib_value(struct radeon_cs_parser * p,int idx)1093 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1094 {
1095 struct radeon_cs_chunk *ibc = p->chunk_ib;
1096
1097 if (ibc->kdata)
1098 return ibc->kdata[idx];
1099 return p->ib.ptr[idx];
1100 }
1101
1102
1103 struct radeon_cs_packet {
1104 unsigned idx;
1105 unsigned type;
1106 unsigned reg;
1107 unsigned opcode;
1108 int count;
1109 unsigned one_reg_wr;
1110 };
1111
1112 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1113 struct radeon_cs_packet *pkt,
1114 unsigned idx, unsigned reg);
1115 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1116 struct radeon_cs_packet *pkt);
1117
1118
1119 /*
1120 * AGP
1121 */
1122 int radeon_agp_init(struct radeon_device *rdev);
1123 void radeon_agp_resume(struct radeon_device *rdev);
1124 void radeon_agp_suspend(struct radeon_device *rdev);
1125 void radeon_agp_fini(struct radeon_device *rdev);
1126
1127
1128 /*
1129 * Writeback
1130 */
1131 struct radeon_wb {
1132 struct radeon_bo *wb_obj;
1133 volatile uint32_t *wb;
1134 uint64_t gpu_addr;
1135 bool enabled;
1136 bool use_event;
1137 };
1138
1139 #define RADEON_WB_SCRATCH_OFFSET 0
1140 #define RADEON_WB_RING0_NEXT_RPTR 256
1141 #define RADEON_WB_CP_RPTR_OFFSET 1024
1142 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1143 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1144 #define R600_WB_DMA_RPTR_OFFSET 1792
1145 #define R600_WB_IH_WPTR_OFFSET 2048
1146 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1147 #define R600_WB_EVENT_OFFSET 3072
1148 #define CIK_WB_CP1_WPTR_OFFSET 3328
1149 #define CIK_WB_CP2_WPTR_OFFSET 3584
1150 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1151 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1152
1153 /**
1154 * struct radeon_pm - power management datas
1155 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1156 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1157 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1158 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1159 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1160 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1161 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1162 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1163 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1164 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1165 * @needed_bandwidth: current bandwidth needs
1166 *
1167 * It keeps track of various data needed to take powermanagement decision.
1168 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1169 * Equation between gpu/memory clock and available bandwidth is hw dependent
1170 * (type of memory, bus size, efficiency, ...)
1171 */
1172
1173 enum radeon_pm_method {
1174 PM_METHOD_PROFILE,
1175 PM_METHOD_DYNPM,
1176 PM_METHOD_DPM,
1177 };
1178
1179 enum radeon_dynpm_state {
1180 DYNPM_STATE_DISABLED,
1181 DYNPM_STATE_MINIMUM,
1182 DYNPM_STATE_PAUSED,
1183 DYNPM_STATE_ACTIVE,
1184 DYNPM_STATE_SUSPENDED,
1185 };
1186 enum radeon_dynpm_action {
1187 DYNPM_ACTION_NONE,
1188 DYNPM_ACTION_MINIMUM,
1189 DYNPM_ACTION_DOWNCLOCK,
1190 DYNPM_ACTION_UPCLOCK,
1191 DYNPM_ACTION_DEFAULT
1192 };
1193
1194 enum radeon_voltage_type {
1195 VOLTAGE_NONE = 0,
1196 VOLTAGE_GPIO,
1197 VOLTAGE_VDDC,
1198 VOLTAGE_SW
1199 };
1200
1201 enum radeon_pm_state_type {
1202 /* not used for dpm */
1203 POWER_STATE_TYPE_DEFAULT,
1204 POWER_STATE_TYPE_POWERSAVE,
1205 /* user selectable states */
1206 POWER_STATE_TYPE_BATTERY,
1207 POWER_STATE_TYPE_BALANCED,
1208 POWER_STATE_TYPE_PERFORMANCE,
1209 /* internal states */
1210 POWER_STATE_TYPE_INTERNAL_UVD,
1211 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1212 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1213 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1214 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1215 POWER_STATE_TYPE_INTERNAL_BOOT,
1216 POWER_STATE_TYPE_INTERNAL_THERMAL,
1217 POWER_STATE_TYPE_INTERNAL_ACPI,
1218 POWER_STATE_TYPE_INTERNAL_ULV,
1219 POWER_STATE_TYPE_INTERNAL_3DPERF,
1220 };
1221
1222 enum radeon_pm_profile_type {
1223 PM_PROFILE_DEFAULT,
1224 PM_PROFILE_AUTO,
1225 PM_PROFILE_LOW,
1226 PM_PROFILE_MID,
1227 PM_PROFILE_HIGH,
1228 };
1229
1230 #define PM_PROFILE_DEFAULT_IDX 0
1231 #define PM_PROFILE_LOW_SH_IDX 1
1232 #define PM_PROFILE_MID_SH_IDX 2
1233 #define PM_PROFILE_HIGH_SH_IDX 3
1234 #define PM_PROFILE_LOW_MH_IDX 4
1235 #define PM_PROFILE_MID_MH_IDX 5
1236 #define PM_PROFILE_HIGH_MH_IDX 6
1237 #define PM_PROFILE_MAX 7
1238
1239 struct radeon_pm_profile {
1240 int dpms_off_ps_idx;
1241 int dpms_on_ps_idx;
1242 int dpms_off_cm_idx;
1243 int dpms_on_cm_idx;
1244 };
1245
1246 enum radeon_int_thermal_type {
1247 THERMAL_TYPE_NONE,
1248 THERMAL_TYPE_EXTERNAL,
1249 THERMAL_TYPE_EXTERNAL_GPIO,
1250 THERMAL_TYPE_RV6XX,
1251 THERMAL_TYPE_RV770,
1252 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1253 THERMAL_TYPE_EVERGREEN,
1254 THERMAL_TYPE_SUMO,
1255 THERMAL_TYPE_NI,
1256 THERMAL_TYPE_SI,
1257 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1258 THERMAL_TYPE_CI,
1259 THERMAL_TYPE_KV,
1260 };
1261
1262 struct radeon_voltage {
1263 enum radeon_voltage_type type;
1264 /* gpio voltage */
1265 struct radeon_gpio_rec gpio;
1266 u32 delay; /* delay in usec from voltage drop to sclk change */
1267 bool active_high; /* voltage drop is active when bit is high */
1268 /* VDDC voltage */
1269 u8 vddc_id; /* index into vddc voltage table */
1270 u8 vddci_id; /* index into vddci voltage table */
1271 bool vddci_enabled;
1272 /* r6xx+ sw */
1273 u16 voltage;
1274 /* evergreen+ vddci */
1275 u16 vddci;
1276 };
1277
1278 /* clock mode flags */
1279 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1280
1281 struct radeon_pm_clock_info {
1282 /* memory clock */
1283 u32 mclk;
1284 /* engine clock */
1285 u32 sclk;
1286 /* voltage info */
1287 struct radeon_voltage voltage;
1288 /* standardized clock flags */
1289 u32 flags;
1290 };
1291
1292 /* state flags */
1293 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1294
1295 struct radeon_power_state {
1296 enum radeon_pm_state_type type;
1297 struct radeon_pm_clock_info *clock_info;
1298 /* number of valid clock modes in this power state */
1299 int num_clock_modes;
1300 struct radeon_pm_clock_info *default_clock_mode;
1301 /* standardized state flags */
1302 u32 flags;
1303 u32 misc; /* vbios specific flags */
1304 u32 misc2; /* vbios specific flags */
1305 int pcie_lanes; /* pcie lanes */
1306 };
1307
1308 /*
1309 * Some modes are overclocked by very low value, accept them
1310 */
1311 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1312
1313 enum radeon_dpm_auto_throttle_src {
1314 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1315 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1316 };
1317
1318 enum radeon_dpm_event_src {
1319 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1320 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1321 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1322 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1323 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1324 };
1325
1326 #define RADEON_MAX_VCE_LEVELS 6
1327
1328 enum radeon_vce_level {
1329 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1330 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1331 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1332 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1333 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1334 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1335 };
1336
1337 struct radeon_ps {
1338 u32 caps; /* vbios flags */
1339 u32 class; /* vbios flags */
1340 u32 class2; /* vbios flags */
1341 /* UVD clocks */
1342 u32 vclk;
1343 u32 dclk;
1344 /* VCE clocks */
1345 u32 evclk;
1346 u32 ecclk;
1347 bool vce_active;
1348 enum radeon_vce_level vce_level;
1349 /* asic priv */
1350 void *ps_priv;
1351 };
1352
1353 struct radeon_dpm_thermal {
1354 /* thermal interrupt work */
1355 struct work_struct work;
1356 /* low temperature threshold */
1357 int min_temp;
1358 /* high temperature threshold */
1359 int max_temp;
1360 /* was interrupt low to high or high to low */
1361 bool high_to_low;
1362 };
1363
1364 enum radeon_clk_action
1365 {
1366 RADEON_SCLK_UP = 1,
1367 RADEON_SCLK_DOWN
1368 };
1369
1370 struct radeon_blacklist_clocks
1371 {
1372 u32 sclk;
1373 u32 mclk;
1374 enum radeon_clk_action action;
1375 };
1376
1377 struct radeon_clock_and_voltage_limits {
1378 u32 sclk;
1379 u32 mclk;
1380 u16 vddc;
1381 u16 vddci;
1382 };
1383
1384 struct radeon_clock_array {
1385 u32 count;
1386 u32 *values;
1387 };
1388
1389 struct radeon_clock_voltage_dependency_entry {
1390 u32 clk;
1391 u16 v;
1392 };
1393
1394 struct radeon_clock_voltage_dependency_table {
1395 u32 count;
1396 struct radeon_clock_voltage_dependency_entry *entries;
1397 };
1398
1399 union radeon_cac_leakage_entry {
1400 struct {
1401 u16 vddc;
1402 u32 leakage;
1403 };
1404 struct {
1405 u16 vddc1;
1406 u16 vddc2;
1407 u16 vddc3;
1408 };
1409 };
1410
1411 struct radeon_cac_leakage_table {
1412 u32 count;
1413 union radeon_cac_leakage_entry *entries;
1414 };
1415
1416 struct radeon_phase_shedding_limits_entry {
1417 u16 voltage;
1418 u32 sclk;
1419 u32 mclk;
1420 };
1421
1422 struct radeon_phase_shedding_limits_table {
1423 u32 count;
1424 struct radeon_phase_shedding_limits_entry *entries;
1425 };
1426
1427 struct radeon_uvd_clock_voltage_dependency_entry {
1428 u32 vclk;
1429 u32 dclk;
1430 u16 v;
1431 };
1432
1433 struct radeon_uvd_clock_voltage_dependency_table {
1434 u8 count;
1435 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1436 };
1437
1438 struct radeon_vce_clock_voltage_dependency_entry {
1439 u32 ecclk;
1440 u32 evclk;
1441 u16 v;
1442 };
1443
1444 struct radeon_vce_clock_voltage_dependency_table {
1445 u8 count;
1446 struct radeon_vce_clock_voltage_dependency_entry *entries;
1447 };
1448
1449 struct radeon_ppm_table {
1450 u8 ppm_design;
1451 u16 cpu_core_number;
1452 u32 platform_tdp;
1453 u32 small_ac_platform_tdp;
1454 u32 platform_tdc;
1455 u32 small_ac_platform_tdc;
1456 u32 apu_tdp;
1457 u32 dgpu_tdp;
1458 u32 dgpu_ulv_power;
1459 u32 tj_max;
1460 };
1461
1462 struct radeon_cac_tdp_table {
1463 u16 tdp;
1464 u16 configurable_tdp;
1465 u16 tdc;
1466 u16 battery_power_limit;
1467 u16 small_power_limit;
1468 u16 low_cac_leakage;
1469 u16 high_cac_leakage;
1470 u16 maximum_power_delivery_limit;
1471 };
1472
1473 struct radeon_dpm_dynamic_state {
1474 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1475 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1476 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1477 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1478 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1479 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1480 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1481 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1482 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1483 struct radeon_clock_array valid_sclk_values;
1484 struct radeon_clock_array valid_mclk_values;
1485 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1486 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1487 u32 mclk_sclk_ratio;
1488 u32 sclk_mclk_delta;
1489 u16 vddc_vddci_delta;
1490 u16 min_vddc_for_pcie_gen2;
1491 struct radeon_cac_leakage_table cac_leakage_table;
1492 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1493 struct radeon_ppm_table *ppm_table;
1494 struct radeon_cac_tdp_table *cac_tdp_table;
1495 };
1496
1497 struct radeon_dpm_fan {
1498 u16 t_min;
1499 u16 t_med;
1500 u16 t_high;
1501 u16 pwm_min;
1502 u16 pwm_med;
1503 u16 pwm_high;
1504 u8 t_hyst;
1505 u32 cycle_delay;
1506 u16 t_max;
1507 u8 control_mode;
1508 u16 default_max_fan_pwm;
1509 u16 default_fan_output_sensitivity;
1510 u16 fan_output_sensitivity;
1511 bool ucode_fan_control;
1512 };
1513
1514 enum radeon_pcie_gen {
1515 RADEON_PCIE_GEN1 = 0,
1516 RADEON_PCIE_GEN2 = 1,
1517 RADEON_PCIE_GEN3 = 2,
1518 RADEON_PCIE_GEN_INVALID = 0xffff
1519 };
1520
1521 enum radeon_dpm_forced_level {
1522 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1523 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1524 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1525 };
1526
1527 struct radeon_vce_state {
1528 /* vce clocks */
1529 u32 evclk;
1530 u32 ecclk;
1531 /* gpu clocks */
1532 u32 sclk;
1533 u32 mclk;
1534 u8 clk_idx;
1535 u8 pstate;
1536 };
1537
1538 struct radeon_dpm {
1539 struct radeon_ps *ps;
1540 /* number of valid power states */
1541 int num_ps;
1542 /* current power state that is active */
1543 struct radeon_ps *current_ps;
1544 /* requested power state */
1545 struct radeon_ps *requested_ps;
1546 /* boot up power state */
1547 struct radeon_ps *boot_ps;
1548 /* default uvd power state */
1549 struct radeon_ps *uvd_ps;
1550 /* vce requirements */
1551 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1552 enum radeon_vce_level vce_level;
1553 enum radeon_pm_state_type state;
1554 enum radeon_pm_state_type user_state;
1555 u32 platform_caps;
1556 u32 voltage_response_time;
1557 u32 backbias_response_time;
1558 void *priv;
1559 u32 new_active_crtcs;
1560 int new_active_crtc_count;
1561 u32 current_active_crtcs;
1562 int current_active_crtc_count;
1563 bool single_display;
1564 struct radeon_dpm_dynamic_state dyn_state;
1565 struct radeon_dpm_fan fan;
1566 u32 tdp_limit;
1567 u32 near_tdp_limit;
1568 u32 near_tdp_limit_adjusted;
1569 u32 sq_ramping_threshold;
1570 u32 cac_leakage;
1571 u16 tdp_od_limit;
1572 u32 tdp_adjustment;
1573 u16 load_line_slope;
1574 bool power_control;
1575 bool ac_power;
1576 /* special states active */
1577 bool thermal_active;
1578 bool uvd_active;
1579 bool vce_active;
1580 /* thermal handling */
1581 struct radeon_dpm_thermal thermal;
1582 /* forced levels */
1583 enum radeon_dpm_forced_level forced_level;
1584 /* track UVD streams */
1585 unsigned sd;
1586 unsigned hd;
1587 };
1588
1589 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1590 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1591
1592 struct radeon_pm {
1593 struct mutex mutex;
1594 /* write locked while reprogramming mclk */
1595 struct rw_semaphore mclk_lock;
1596 u32 active_crtcs;
1597 int active_crtc_count;
1598 int req_vblank;
1599 bool vblank_sync;
1600 fixed20_12 max_bandwidth;
1601 fixed20_12 igp_sideport_mclk;
1602 fixed20_12 igp_system_mclk;
1603 fixed20_12 igp_ht_link_clk;
1604 fixed20_12 igp_ht_link_width;
1605 fixed20_12 k8_bandwidth;
1606 fixed20_12 sideport_bandwidth;
1607 fixed20_12 ht_bandwidth;
1608 fixed20_12 core_bandwidth;
1609 fixed20_12 sclk;
1610 fixed20_12 mclk;
1611 fixed20_12 needed_bandwidth;
1612 struct radeon_power_state *power_state;
1613 /* number of valid power states */
1614 int num_power_states;
1615 int current_power_state_index;
1616 int current_clock_mode_index;
1617 int requested_power_state_index;
1618 int requested_clock_mode_index;
1619 int default_power_state_index;
1620 u32 current_sclk;
1621 u32 current_mclk;
1622 u16 current_vddc;
1623 u16 current_vddci;
1624 u32 default_sclk;
1625 u32 default_mclk;
1626 u16 default_vddc;
1627 u16 default_vddci;
1628 struct radeon_i2c_chan *i2c_bus;
1629 /* selected pm method */
1630 enum radeon_pm_method pm_method;
1631 /* dynpm power management */
1632 struct delayed_work dynpm_idle_work;
1633 enum radeon_dynpm_state dynpm_state;
1634 enum radeon_dynpm_action dynpm_planned_action;
1635 unsigned long dynpm_action_timeout;
1636 bool dynpm_can_upclock;
1637 bool dynpm_can_downclock;
1638 /* profile-based power management */
1639 enum radeon_pm_profile_type profile;
1640 int profile_index;
1641 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1642 /* internal thermal controller on rv6xx+ */
1643 enum radeon_int_thermal_type int_thermal_type;
1644 struct device *int_hwmon_dev;
1645 /* fan control parameters */
1646 bool no_fan;
1647 u8 fan_pulses_per_revolution;
1648 u8 fan_min_rpm;
1649 u8 fan_max_rpm;
1650 /* dpm */
1651 bool dpm_enabled;
1652 bool sysfs_initialized;
1653 struct radeon_dpm dpm;
1654 };
1655
1656 #define RADEON_PCIE_SPEED_25 1
1657 #define RADEON_PCIE_SPEED_50 2
1658 #define RADEON_PCIE_SPEED_80 4
1659
1660 int radeon_pm_get_type_index(struct radeon_device *rdev,
1661 enum radeon_pm_state_type ps_type,
1662 int instance);
1663 /*
1664 * UVD
1665 */
1666 #define RADEON_DEFAULT_UVD_HANDLES 10
1667 #define RADEON_MAX_UVD_HANDLES 30
1668 #define RADEON_UVD_STACK_SIZE (200*1024)
1669 #define RADEON_UVD_HEAP_SIZE (256*1024)
1670 #define RADEON_UVD_SESSION_SIZE (50*1024)
1671
1672 struct radeon_uvd {
1673 bool fw_header_present;
1674 struct radeon_bo *vcpu_bo;
1675 void *cpu_addr;
1676 uint64_t gpu_addr;
1677 unsigned max_handles;
1678 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1679 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1680 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1681 struct delayed_work idle_work;
1682 };
1683
1684 int radeon_uvd_init(struct radeon_device *rdev);
1685 void radeon_uvd_fini(struct radeon_device *rdev);
1686 int radeon_uvd_suspend(struct radeon_device *rdev);
1687 int radeon_uvd_resume(struct radeon_device *rdev);
1688 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1689 uint32_t handle, struct radeon_fence **fence);
1690 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1691 uint32_t handle, struct radeon_fence **fence);
1692 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1693 uint32_t allowed_domains);
1694 void radeon_uvd_free_handles(struct radeon_device *rdev,
1695 struct drm_file *filp);
1696 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1697 void radeon_uvd_note_usage(struct radeon_device *rdev);
1698 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1699 unsigned vclk, unsigned dclk,
1700 unsigned vco_min, unsigned vco_max,
1701 unsigned fb_factor, unsigned fb_mask,
1702 unsigned pd_min, unsigned pd_max,
1703 unsigned pd_even,
1704 unsigned *optimal_fb_div,
1705 unsigned *optimal_vclk_div,
1706 unsigned *optimal_dclk_div);
1707 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1708 unsigned cg_upll_func_cntl);
1709
1710 /*
1711 * VCE
1712 */
1713 #define RADEON_MAX_VCE_HANDLES 16
1714
1715 struct radeon_vce {
1716 struct radeon_bo *vcpu_bo;
1717 uint64_t gpu_addr;
1718 unsigned fw_version;
1719 unsigned fb_version;
1720 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1721 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1722 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1723 struct delayed_work idle_work;
1724 uint32_t keyselect;
1725 };
1726
1727 int radeon_vce_init(struct radeon_device *rdev);
1728 void radeon_vce_fini(struct radeon_device *rdev);
1729 int radeon_vce_suspend(struct radeon_device *rdev);
1730 int radeon_vce_resume(struct radeon_device *rdev);
1731 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1732 uint32_t handle, struct radeon_fence **fence);
1733 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1734 uint32_t handle, struct radeon_fence **fence);
1735 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1736 void radeon_vce_note_usage(struct radeon_device *rdev);
1737 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1738 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1739 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1740 struct radeon_ring *ring,
1741 struct radeon_semaphore *semaphore,
1742 bool emit_wait);
1743 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1744 void radeon_vce_fence_emit(struct radeon_device *rdev,
1745 struct radeon_fence *fence);
1746 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1747 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1748
1749 struct r600_audio_pin {
1750 int channels;
1751 int rate;
1752 int bits_per_sample;
1753 u8 status_bits;
1754 u8 category_code;
1755 u32 offset;
1756 bool connected;
1757 u32 id;
1758 };
1759
1760 struct r600_audio {
1761 bool enabled;
1762 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1763 int num_pins;
1764 struct radeon_audio_funcs *hdmi_funcs;
1765 struct radeon_audio_funcs *dp_funcs;
1766 struct radeon_audio_basic_funcs *funcs;
1767 };
1768
1769 /*
1770 * Benchmarking
1771 */
1772 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1773
1774
1775 /*
1776 * Testing
1777 */
1778 void radeon_test_moves(struct radeon_device *rdev);
1779 void radeon_test_ring_sync(struct radeon_device *rdev,
1780 struct radeon_ring *cpA,
1781 struct radeon_ring *cpB);
1782 void radeon_test_syncing(struct radeon_device *rdev);
1783
1784 /*
1785 * MMU Notifier
1786 */
1787 #if defined(CONFIG_MMU_NOTIFIER)
1788 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1789 void radeon_mn_unregister(struct radeon_bo *bo);
1790 #else
radeon_mn_register(struct radeon_bo * bo,unsigned long addr)1791 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1792 {
1793 return -ENODEV;
1794 }
radeon_mn_unregister(struct radeon_bo * bo)1795 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1796 #endif
1797
1798 /*
1799 * Debugfs
1800 */
1801 struct radeon_debugfs {
1802 struct drm_info_list *files;
1803 unsigned num_files;
1804 };
1805
1806 int radeon_debugfs_add_files(struct radeon_device *rdev,
1807 struct drm_info_list *files,
1808 unsigned nfiles);
1809 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1810
1811 /*
1812 * ASIC ring specific functions.
1813 */
1814 struct radeon_asic_ring {
1815 /* ring read/write ptr handling */
1816 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1817 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1818 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1819
1820 /* validating and patching of IBs */
1821 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1822 int (*cs_parse)(struct radeon_cs_parser *p);
1823
1824 /* command emmit functions */
1825 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1826 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1827 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1828 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1829 struct radeon_semaphore *semaphore, bool emit_wait);
1830 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1831 unsigned vm_id, uint64_t pd_addr);
1832
1833 /* testing functions */
1834 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1835 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1836 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1837
1838 /* deprecated */
1839 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1840 };
1841
1842 /*
1843 * ASIC specific functions.
1844 */
1845 struct radeon_asic {
1846 int (*init)(struct radeon_device *rdev);
1847 void (*fini)(struct radeon_device *rdev);
1848 int (*resume)(struct radeon_device *rdev);
1849 int (*suspend)(struct radeon_device *rdev);
1850 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1851 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1852 /* Flush the HDP cache via MMIO */
1853 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1854 /* check if 3D engine is idle */
1855 bool (*gui_idle)(struct radeon_device *rdev);
1856 /* wait for mc_idle */
1857 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1858 /* get the reference clock */
1859 u32 (*get_xclk)(struct radeon_device *rdev);
1860 /* get the gpu clock counter */
1861 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1862 /* get register for info ioctl */
1863 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1864 /* gart */
1865 struct {
1866 void (*tlb_flush)(struct radeon_device *rdev);
1867 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1868 void (*set_page)(struct radeon_device *rdev, unsigned i,
1869 uint64_t entry);
1870 } gart;
1871 struct {
1872 int (*init)(struct radeon_device *rdev);
1873 void (*fini)(struct radeon_device *rdev);
1874 void (*copy_pages)(struct radeon_device *rdev,
1875 struct radeon_ib *ib,
1876 uint64_t pe, uint64_t src,
1877 unsigned count);
1878 void (*write_pages)(struct radeon_device *rdev,
1879 struct radeon_ib *ib,
1880 uint64_t pe,
1881 uint64_t addr, unsigned count,
1882 uint32_t incr, uint32_t flags);
1883 void (*set_pages)(struct radeon_device *rdev,
1884 struct radeon_ib *ib,
1885 uint64_t pe,
1886 uint64_t addr, unsigned count,
1887 uint32_t incr, uint32_t flags);
1888 void (*pad_ib)(struct radeon_ib *ib);
1889 } vm;
1890 /* ring specific callbacks */
1891 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1892 /* irqs */
1893 struct {
1894 int (*set)(struct radeon_device *rdev);
1895 int (*process)(struct radeon_device *rdev);
1896 } irq;
1897 /* displays */
1898 struct {
1899 /* display watermarks */
1900 void (*bandwidth_update)(struct radeon_device *rdev);
1901 /* get frame count */
1902 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1903 /* wait for vblank */
1904 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1905 /* set backlight level */
1906 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1907 /* get backlight level */
1908 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1909 /* audio callbacks */
1910 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1911 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1912 } display;
1913 /* copy functions for bo handling */
1914 struct {
1915 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1916 uint64_t src_offset,
1917 uint64_t dst_offset,
1918 unsigned num_gpu_pages,
1919 struct reservation_object *resv);
1920 u32 blit_ring_index;
1921 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1922 uint64_t src_offset,
1923 uint64_t dst_offset,
1924 unsigned num_gpu_pages,
1925 struct reservation_object *resv);
1926 u32 dma_ring_index;
1927 /* method used for bo copy */
1928 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1929 uint64_t src_offset,
1930 uint64_t dst_offset,
1931 unsigned num_gpu_pages,
1932 struct reservation_object *resv);
1933 /* ring used for bo copies */
1934 u32 copy_ring_index;
1935 } copy;
1936 /* surfaces */
1937 struct {
1938 int (*set_reg)(struct radeon_device *rdev, int reg,
1939 uint32_t tiling_flags, uint32_t pitch,
1940 uint32_t offset, uint32_t obj_size);
1941 void (*clear_reg)(struct radeon_device *rdev, int reg);
1942 } surface;
1943 /* hotplug detect */
1944 struct {
1945 void (*init)(struct radeon_device *rdev);
1946 void (*fini)(struct radeon_device *rdev);
1947 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1948 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1949 } hpd;
1950 /* static power management */
1951 struct {
1952 void (*misc)(struct radeon_device *rdev);
1953 void (*prepare)(struct radeon_device *rdev);
1954 void (*finish)(struct radeon_device *rdev);
1955 void (*init_profile)(struct radeon_device *rdev);
1956 void (*get_dynpm_state)(struct radeon_device *rdev);
1957 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1958 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1959 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1960 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1961 int (*get_pcie_lanes)(struct radeon_device *rdev);
1962 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1963 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1964 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1965 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1966 int (*get_temperature)(struct radeon_device *rdev);
1967 } pm;
1968 /* dynamic power management */
1969 struct {
1970 int (*init)(struct radeon_device *rdev);
1971 void (*setup_asic)(struct radeon_device *rdev);
1972 int (*enable)(struct radeon_device *rdev);
1973 int (*late_enable)(struct radeon_device *rdev);
1974 void (*disable)(struct radeon_device *rdev);
1975 int (*pre_set_power_state)(struct radeon_device *rdev);
1976 int (*set_power_state)(struct radeon_device *rdev);
1977 void (*post_set_power_state)(struct radeon_device *rdev);
1978 void (*display_configuration_changed)(struct radeon_device *rdev);
1979 void (*fini)(struct radeon_device *rdev);
1980 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1981 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1982 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1983 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1984 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1985 bool (*vblank_too_short)(struct radeon_device *rdev);
1986 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1987 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1988 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1989 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1990 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1991 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1992 u32 (*get_current_sclk)(struct radeon_device *rdev);
1993 u32 (*get_current_mclk)(struct radeon_device *rdev);
1994 } dpm;
1995 /* pageflipping */
1996 struct {
1997 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
1998 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1999 } pflip;
2000 };
2001
2002 /*
2003 * Asic structures
2004 */
2005 struct r100_asic {
2006 const unsigned *reg_safe_bm;
2007 unsigned reg_safe_bm_size;
2008 u32 hdp_cntl;
2009 };
2010
2011 struct r300_asic {
2012 const unsigned *reg_safe_bm;
2013 unsigned reg_safe_bm_size;
2014 u32 resync_scratch;
2015 u32 hdp_cntl;
2016 };
2017
2018 struct r600_asic {
2019 unsigned max_pipes;
2020 unsigned max_tile_pipes;
2021 unsigned max_simds;
2022 unsigned max_backends;
2023 unsigned max_gprs;
2024 unsigned max_threads;
2025 unsigned max_stack_entries;
2026 unsigned max_hw_contexts;
2027 unsigned max_gs_threads;
2028 unsigned sx_max_export_size;
2029 unsigned sx_max_export_pos_size;
2030 unsigned sx_max_export_smx_size;
2031 unsigned sq_num_cf_insts;
2032 unsigned tiling_nbanks;
2033 unsigned tiling_npipes;
2034 unsigned tiling_group_size;
2035 unsigned tile_config;
2036 unsigned backend_map;
2037 unsigned active_simds;
2038 };
2039
2040 struct rv770_asic {
2041 unsigned max_pipes;
2042 unsigned max_tile_pipes;
2043 unsigned max_simds;
2044 unsigned max_backends;
2045 unsigned max_gprs;
2046 unsigned max_threads;
2047 unsigned max_stack_entries;
2048 unsigned max_hw_contexts;
2049 unsigned max_gs_threads;
2050 unsigned sx_max_export_size;
2051 unsigned sx_max_export_pos_size;
2052 unsigned sx_max_export_smx_size;
2053 unsigned sq_num_cf_insts;
2054 unsigned sx_num_of_sets;
2055 unsigned sc_prim_fifo_size;
2056 unsigned sc_hiz_tile_fifo_size;
2057 unsigned sc_earlyz_tile_fifo_fize;
2058 unsigned tiling_nbanks;
2059 unsigned tiling_npipes;
2060 unsigned tiling_group_size;
2061 unsigned tile_config;
2062 unsigned backend_map;
2063 unsigned active_simds;
2064 };
2065
2066 struct evergreen_asic {
2067 unsigned num_ses;
2068 unsigned max_pipes;
2069 unsigned max_tile_pipes;
2070 unsigned max_simds;
2071 unsigned max_backends;
2072 unsigned max_gprs;
2073 unsigned max_threads;
2074 unsigned max_stack_entries;
2075 unsigned max_hw_contexts;
2076 unsigned max_gs_threads;
2077 unsigned sx_max_export_size;
2078 unsigned sx_max_export_pos_size;
2079 unsigned sx_max_export_smx_size;
2080 unsigned sq_num_cf_insts;
2081 unsigned sx_num_of_sets;
2082 unsigned sc_prim_fifo_size;
2083 unsigned sc_hiz_tile_fifo_size;
2084 unsigned sc_earlyz_tile_fifo_size;
2085 unsigned tiling_nbanks;
2086 unsigned tiling_npipes;
2087 unsigned tiling_group_size;
2088 unsigned tile_config;
2089 unsigned backend_map;
2090 unsigned active_simds;
2091 };
2092
2093 struct cayman_asic {
2094 unsigned max_shader_engines;
2095 unsigned max_pipes_per_simd;
2096 unsigned max_tile_pipes;
2097 unsigned max_simds_per_se;
2098 unsigned max_backends_per_se;
2099 unsigned max_texture_channel_caches;
2100 unsigned max_gprs;
2101 unsigned max_threads;
2102 unsigned max_gs_threads;
2103 unsigned max_stack_entries;
2104 unsigned sx_num_of_sets;
2105 unsigned sx_max_export_size;
2106 unsigned sx_max_export_pos_size;
2107 unsigned sx_max_export_smx_size;
2108 unsigned max_hw_contexts;
2109 unsigned sq_num_cf_insts;
2110 unsigned sc_prim_fifo_size;
2111 unsigned sc_hiz_tile_fifo_size;
2112 unsigned sc_earlyz_tile_fifo_size;
2113
2114 unsigned num_shader_engines;
2115 unsigned num_shader_pipes_per_simd;
2116 unsigned num_tile_pipes;
2117 unsigned num_simds_per_se;
2118 unsigned num_backends_per_se;
2119 unsigned backend_disable_mask_per_asic;
2120 unsigned backend_map;
2121 unsigned num_texture_channel_caches;
2122 unsigned mem_max_burst_length_bytes;
2123 unsigned mem_row_size_in_kb;
2124 unsigned shader_engine_tile_size;
2125 unsigned num_gpus;
2126 unsigned multi_gpu_tile_size;
2127
2128 unsigned tile_config;
2129 unsigned active_simds;
2130 };
2131
2132 struct si_asic {
2133 unsigned max_shader_engines;
2134 unsigned max_tile_pipes;
2135 unsigned max_cu_per_sh;
2136 unsigned max_sh_per_se;
2137 unsigned max_backends_per_se;
2138 unsigned max_texture_channel_caches;
2139 unsigned max_gprs;
2140 unsigned max_gs_threads;
2141 unsigned max_hw_contexts;
2142 unsigned sc_prim_fifo_size_frontend;
2143 unsigned sc_prim_fifo_size_backend;
2144 unsigned sc_hiz_tile_fifo_size;
2145 unsigned sc_earlyz_tile_fifo_size;
2146
2147 unsigned num_tile_pipes;
2148 unsigned backend_enable_mask;
2149 unsigned backend_disable_mask_per_asic;
2150 unsigned backend_map;
2151 unsigned num_texture_channel_caches;
2152 unsigned mem_max_burst_length_bytes;
2153 unsigned mem_row_size_in_kb;
2154 unsigned shader_engine_tile_size;
2155 unsigned num_gpus;
2156 unsigned multi_gpu_tile_size;
2157
2158 unsigned tile_config;
2159 uint32_t tile_mode_array[32];
2160 uint32_t active_cus;
2161 };
2162
2163 struct cik_asic {
2164 unsigned max_shader_engines;
2165 unsigned max_tile_pipes;
2166 unsigned max_cu_per_sh;
2167 unsigned max_sh_per_se;
2168 unsigned max_backends_per_se;
2169 unsigned max_texture_channel_caches;
2170 unsigned max_gprs;
2171 unsigned max_gs_threads;
2172 unsigned max_hw_contexts;
2173 unsigned sc_prim_fifo_size_frontend;
2174 unsigned sc_prim_fifo_size_backend;
2175 unsigned sc_hiz_tile_fifo_size;
2176 unsigned sc_earlyz_tile_fifo_size;
2177
2178 unsigned num_tile_pipes;
2179 unsigned backend_enable_mask;
2180 unsigned backend_disable_mask_per_asic;
2181 unsigned backend_map;
2182 unsigned num_texture_channel_caches;
2183 unsigned mem_max_burst_length_bytes;
2184 unsigned mem_row_size_in_kb;
2185 unsigned shader_engine_tile_size;
2186 unsigned num_gpus;
2187 unsigned multi_gpu_tile_size;
2188
2189 unsigned tile_config;
2190 uint32_t tile_mode_array[32];
2191 uint32_t macrotile_mode_array[16];
2192 uint32_t active_cus;
2193 };
2194
2195 union radeon_asic_config {
2196 struct r300_asic r300;
2197 struct r100_asic r100;
2198 struct r600_asic r600;
2199 struct rv770_asic rv770;
2200 struct evergreen_asic evergreen;
2201 struct cayman_asic cayman;
2202 struct si_asic si;
2203 struct cik_asic cik;
2204 };
2205
2206 /*
2207 * asic initizalization from radeon_asic.c
2208 */
2209 void radeon_agp_disable(struct radeon_device *rdev);
2210 int radeon_asic_init(struct radeon_device *rdev);
2211
2212
2213 /*
2214 * IOCTL.
2215 */
2216 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2217 struct drm_file *filp);
2218 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2219 struct drm_file *filp);
2220 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *filp);
2222 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *file_priv);
2224 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *file_priv);
2226 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *file_priv);
2228 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *file_priv);
2230 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *filp);
2232 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *filp);
2234 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2235 struct drm_file *filp);
2236 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *filp);
2238 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *filp);
2240 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2241 struct drm_file *filp);
2242 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2243 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2244 struct drm_file *filp);
2245 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2246 struct drm_file *filp);
2247
2248 /* VRAM scratch page for HDP bug, default vram page */
2249 struct r600_vram_scratch {
2250 struct radeon_bo *robj;
2251 volatile uint32_t *ptr;
2252 u64 gpu_addr;
2253 };
2254
2255 /*
2256 * ACPI
2257 */
2258 struct radeon_atif_notification_cfg {
2259 bool enabled;
2260 int command_code;
2261 };
2262
2263 struct radeon_atif_notifications {
2264 bool display_switch;
2265 bool expansion_mode_change;
2266 bool thermal_state;
2267 bool forced_power_state;
2268 bool system_power_state;
2269 bool display_conf_change;
2270 bool px_gfx_switch;
2271 bool brightness_change;
2272 bool dgpu_display_event;
2273 };
2274
2275 struct radeon_atif_functions {
2276 bool system_params;
2277 bool sbios_requests;
2278 bool select_active_disp;
2279 bool lid_state;
2280 bool get_tv_standard;
2281 bool set_tv_standard;
2282 bool get_panel_expansion_mode;
2283 bool set_panel_expansion_mode;
2284 bool temperature_change;
2285 bool graphics_device_types;
2286 };
2287
2288 struct radeon_atif {
2289 struct radeon_atif_notifications notifications;
2290 struct radeon_atif_functions functions;
2291 struct radeon_atif_notification_cfg notification_cfg;
2292 struct radeon_encoder *encoder_for_bl;
2293 };
2294
2295 struct radeon_atcs_functions {
2296 bool get_ext_state;
2297 bool pcie_perf_req;
2298 bool pcie_dev_rdy;
2299 bool pcie_bus_width;
2300 };
2301
2302 struct radeon_atcs {
2303 struct radeon_atcs_functions functions;
2304 };
2305
2306 /*
2307 * Core structure, functions and helpers.
2308 */
2309 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2310 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2311
2312 struct radeon_device {
2313 struct device *dev;
2314 struct drm_device *ddev;
2315 struct pci_dev *pdev;
2316 struct rw_semaphore exclusive_lock;
2317 /* ASIC */
2318 union radeon_asic_config config;
2319 enum radeon_family family;
2320 unsigned long flags;
2321 int usec_timeout;
2322 enum radeon_pll_errata pll_errata;
2323 int num_gb_pipes;
2324 int num_z_pipes;
2325 int disp_priority;
2326 /* BIOS */
2327 uint8_t *bios;
2328 bool is_atom_bios;
2329 uint16_t bios_header_start;
2330 struct radeon_bo *stolen_vga_memory;
2331 /* Register mmio */
2332 resource_size_t rmmio_base;
2333 resource_size_t rmmio_size;
2334 /* protects concurrent MM_INDEX/DATA based register access */
2335 spinlock_t mmio_idx_lock;
2336 /* protects concurrent SMC based register access */
2337 spinlock_t smc_idx_lock;
2338 /* protects concurrent PLL register access */
2339 spinlock_t pll_idx_lock;
2340 /* protects concurrent MC register access */
2341 spinlock_t mc_idx_lock;
2342 /* protects concurrent PCIE register access */
2343 spinlock_t pcie_idx_lock;
2344 /* protects concurrent PCIE_PORT register access */
2345 spinlock_t pciep_idx_lock;
2346 /* protects concurrent PIF register access */
2347 spinlock_t pif_idx_lock;
2348 /* protects concurrent CG register access */
2349 spinlock_t cg_idx_lock;
2350 /* protects concurrent UVD register access */
2351 spinlock_t uvd_idx_lock;
2352 /* protects concurrent RCU register access */
2353 spinlock_t rcu_idx_lock;
2354 /* protects concurrent DIDT register access */
2355 spinlock_t didt_idx_lock;
2356 /* protects concurrent ENDPOINT (audio) register access */
2357 spinlock_t end_idx_lock;
2358 void __iomem *rmmio;
2359 radeon_rreg_t mc_rreg;
2360 radeon_wreg_t mc_wreg;
2361 radeon_rreg_t pll_rreg;
2362 radeon_wreg_t pll_wreg;
2363 uint32_t pcie_reg_mask;
2364 radeon_rreg_t pciep_rreg;
2365 radeon_wreg_t pciep_wreg;
2366 /* io port */
2367 void __iomem *rio_mem;
2368 resource_size_t rio_mem_size;
2369 struct radeon_clock clock;
2370 struct radeon_mc mc;
2371 struct radeon_gart gart;
2372 struct radeon_mode_info mode_info;
2373 struct radeon_scratch scratch;
2374 struct radeon_doorbell doorbell;
2375 struct radeon_mman mman;
2376 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2377 wait_queue_head_t fence_queue;
2378 u64 fence_context;
2379 struct mutex ring_lock;
2380 struct radeon_ring ring[RADEON_NUM_RINGS];
2381 bool ib_pool_ready;
2382 struct radeon_sa_manager ring_tmp_bo;
2383 struct radeon_irq irq;
2384 struct radeon_asic *asic;
2385 struct radeon_gem gem;
2386 struct radeon_pm pm;
2387 struct radeon_uvd uvd;
2388 struct radeon_vce vce;
2389 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2390 struct radeon_wb wb;
2391 struct radeon_dummy_page dummy_page;
2392 bool shutdown;
2393 bool need_dma32;
2394 bool need_swiotlb;
2395 bool accel_working;
2396 bool fastfb_working; /* IGP feature*/
2397 bool needs_reset, in_reset;
2398 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2399 const struct firmware *me_fw; /* all family ME firmware */
2400 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2401 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2402 const struct firmware *mc_fw; /* NI MC firmware */
2403 const struct firmware *ce_fw; /* SI CE firmware */
2404 const struct firmware *mec_fw; /* CIK MEC firmware */
2405 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2406 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2407 const struct firmware *smc_fw; /* SMC firmware */
2408 const struct firmware *uvd_fw; /* UVD firmware */
2409 const struct firmware *vce_fw; /* VCE firmware */
2410 bool new_fw;
2411 struct r600_vram_scratch vram_scratch;
2412 int msi_enabled; /* msi enabled */
2413 struct r600_ih ih; /* r6/700 interrupt ring */
2414 struct radeon_rlc rlc;
2415 struct radeon_mec mec;
2416 struct delayed_work hotplug_work;
2417 struct work_struct dp_work;
2418 struct work_struct audio_work;
2419 int num_crtc; /* number of crtcs */
2420 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2421 bool has_uvd;
2422 bool has_vce;
2423 struct r600_audio audio; /* audio stuff */
2424 struct notifier_block acpi_nb;
2425 /* only one userspace can use Hyperz features or CMASK at a time */
2426 struct drm_file *hyperz_filp;
2427 struct drm_file *cmask_filp;
2428 /* i2c buses */
2429 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2430 /* debugfs */
2431 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2432 unsigned debugfs_count;
2433 /* virtual memory */
2434 struct radeon_vm_manager vm_manager;
2435 struct mutex gpu_clock_mutex;
2436 /* memory stats */
2437 atomic64_t vram_usage;
2438 atomic64_t gtt_usage;
2439 atomic64_t num_bytes_moved;
2440 atomic_t gpu_reset_counter;
2441 /* ACPI interface */
2442 struct radeon_atif atif;
2443 struct radeon_atcs atcs;
2444 /* srbm instance registers */
2445 struct mutex srbm_mutex;
2446 /* clock, powergating flags */
2447 u32 cg_flags;
2448 u32 pg_flags;
2449
2450 struct dev_pm_domain vga_pm_domain;
2451 bool have_disp_power_ref;
2452 u32 px_quirk_flags;
2453
2454 /* tracking pinned memory */
2455 u64 vram_pin_size;
2456 u64 gart_pin_size;
2457
2458 struct mutex mn_lock;
2459 DECLARE_HASHTABLE(mn_hash, 7);
2460 };
2461
2462 bool radeon_is_px(struct drm_device *dev);
2463 int radeon_device_init(struct radeon_device *rdev,
2464 struct drm_device *ddev,
2465 struct pci_dev *pdev,
2466 uint32_t flags);
2467 void radeon_device_fini(struct radeon_device *rdev);
2468 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2469
2470 #define RADEON_MIN_MMIO_SIZE 0x10000
2471
2472 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2473 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
r100_mm_rreg(struct radeon_device * rdev,uint32_t reg,bool always_indirect)2474 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2475 bool always_indirect)
2476 {
2477 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2478 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2479 return readl(((void __iomem *)rdev->rmmio) + reg);
2480 else
2481 return r100_mm_rreg_slow(rdev, reg);
2482 }
r100_mm_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v,bool always_indirect)2483 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2484 bool always_indirect)
2485 {
2486 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2487 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2488 else
2489 r100_mm_wreg_slow(rdev, reg, v);
2490 }
2491
2492 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2493 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2494
2495 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2496 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2497
2498 /*
2499 * Cast helper
2500 */
2501 extern const struct dma_fence_ops radeon_fence_ops;
2502
to_radeon_fence(struct dma_fence * f)2503 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2504 {
2505 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2506
2507 if (__f->base.ops == &radeon_fence_ops)
2508 return __f;
2509
2510 return NULL;
2511 }
2512
2513 /*
2514 * Registers read & write functions.
2515 */
2516 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2517 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2518 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2519 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2520 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2521 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2522 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2523 r100_mm_rreg(rdev, (reg), false))
2524 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2525 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2526 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2527 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2528 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2529 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2530 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2531 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2532 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2533 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2534 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2535 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2536 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2537 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2538 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2539 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2540 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2541 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2542 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2543 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2544 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2545 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2546 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2547 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2548 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2549 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2550 #define WREG32_P(reg, val, mask) \
2551 do { \
2552 uint32_t tmp_ = RREG32(reg); \
2553 tmp_ &= (mask); \
2554 tmp_ |= ((val) & ~(mask)); \
2555 WREG32(reg, tmp_); \
2556 } while (0)
2557 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2558 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2559 #define WREG32_PLL_P(reg, val, mask) \
2560 do { \
2561 uint32_t tmp_ = RREG32_PLL(reg); \
2562 tmp_ &= (mask); \
2563 tmp_ |= ((val) & ~(mask)); \
2564 WREG32_PLL(reg, tmp_); \
2565 } while (0)
2566 #define WREG32_SMC_P(reg, val, mask) \
2567 do { \
2568 uint32_t tmp_ = RREG32_SMC(reg); \
2569 tmp_ &= (mask); \
2570 tmp_ |= ((val) & ~(mask)); \
2571 WREG32_SMC(reg, tmp_); \
2572 } while (0)
2573 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2574 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2575 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2576
2577 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2578 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2579
2580 /*
2581 * Indirect registers accessors.
2582 * They used to be inlined, but this increases code size by ~65 kbytes.
2583 * Since each performs a pair of MMIO ops
2584 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2585 * the cost of call+ret is almost negligible. MMIO and locking
2586 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2587 */
2588 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2589 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2590 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2591 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2592 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2593 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2594 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2595 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2596 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2597 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2598 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2599 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2600 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2601 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2602 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2603 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2604
2605 void r100_pll_errata_after_index(struct radeon_device *rdev);
2606
2607
2608 /*
2609 * ASICs helpers.
2610 */
2611 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2612 (rdev->pdev->device == 0x5969))
2613 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2614 (rdev->family == CHIP_RV200) || \
2615 (rdev->family == CHIP_RS100) || \
2616 (rdev->family == CHIP_RS200) || \
2617 (rdev->family == CHIP_RV250) || \
2618 (rdev->family == CHIP_RV280) || \
2619 (rdev->family == CHIP_RS300))
2620 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2621 (rdev->family == CHIP_RV350) || \
2622 (rdev->family == CHIP_R350) || \
2623 (rdev->family == CHIP_RV380) || \
2624 (rdev->family == CHIP_R420) || \
2625 (rdev->family == CHIP_R423) || \
2626 (rdev->family == CHIP_RV410) || \
2627 (rdev->family == CHIP_RS400) || \
2628 (rdev->family == CHIP_RS480))
2629 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2630 (rdev->ddev->pdev->device == 0x9443) || \
2631 (rdev->ddev->pdev->device == 0x944B) || \
2632 (rdev->ddev->pdev->device == 0x9506) || \
2633 (rdev->ddev->pdev->device == 0x9509) || \
2634 (rdev->ddev->pdev->device == 0x950F) || \
2635 (rdev->ddev->pdev->device == 0x689C) || \
2636 (rdev->ddev->pdev->device == 0x689D))
2637 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2638 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2639 (rdev->family == CHIP_RS690) || \
2640 (rdev->family == CHIP_RS740) || \
2641 (rdev->family >= CHIP_R600))
2642 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2643 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2644 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2645 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2646 (rdev->flags & RADEON_IS_IGP))
2647 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2648 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2649 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2650 (rdev->flags & RADEON_IS_IGP))
2651 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2652 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2653 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2654 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2655 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2656 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2657 (rdev->family == CHIP_MULLINS))
2658
2659 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2660 (rdev->ddev->pdev->device == 0x6850) || \
2661 (rdev->ddev->pdev->device == 0x6858) || \
2662 (rdev->ddev->pdev->device == 0x6859) || \
2663 (rdev->ddev->pdev->device == 0x6840) || \
2664 (rdev->ddev->pdev->device == 0x6841) || \
2665 (rdev->ddev->pdev->device == 0x6842) || \
2666 (rdev->ddev->pdev->device == 0x6843))
2667
2668 /*
2669 * BIOS helpers.
2670 */
2671 #define RBIOS8(i) (rdev->bios[i])
2672 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2673 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2674
2675 int radeon_combios_init(struct radeon_device *rdev);
2676 void radeon_combios_fini(struct radeon_device *rdev);
2677 int radeon_atombios_init(struct radeon_device *rdev);
2678 void radeon_atombios_fini(struct radeon_device *rdev);
2679
2680
2681 /*
2682 * RING helpers.
2683 */
2684
2685 /**
2686 * radeon_ring_write - write a value to the ring
2687 *
2688 * @ring: radeon_ring structure holding ring information
2689 * @v: dword (dw) value to write
2690 *
2691 * Write a value to the requested ring buffer (all asics).
2692 */
radeon_ring_write(struct radeon_ring * ring,uint32_t v)2693 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2694 {
2695 if (ring->count_dw <= 0)
2696 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2697
2698 ring->ring[ring->wptr++] = v;
2699 ring->wptr &= ring->ptr_mask;
2700 ring->count_dw--;
2701 ring->ring_free_dw--;
2702 }
2703
2704 /*
2705 * ASICs macro.
2706 */
2707 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2708 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2709 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2710 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2711 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2712 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2713 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2714 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2715 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2716 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2717 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2718 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2719 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2720 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2721 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2722 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2723 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2724 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2725 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2726 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2727 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2728 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2729 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2730 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2731 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2732 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2733 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2734 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2735 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2736 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2737 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2738 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2739 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2740 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2741 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2742 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2743 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2744 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2745 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2746 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2747 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2748 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2749 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2750 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2751 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2752 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2753 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2754 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2755 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2756 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2757 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2758 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2759 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2760 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2761 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2762 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2763 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2764 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2765 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2766 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2767 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2768 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2769 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2770 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2771 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2772 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2773 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2774 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2775 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2776 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2777 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2778 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2779 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2780 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2781 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2782 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2783 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2784 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2785 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2786 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2787 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2788 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2789 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2790 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2791 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2792 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2793 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2794 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2795 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2796 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2797 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2798
2799 /* Common functions */
2800 /* AGP */
2801 extern int radeon_gpu_reset(struct radeon_device *rdev);
2802 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2803 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2804 extern void radeon_agp_disable(struct radeon_device *rdev);
2805 extern int radeon_modeset_init(struct radeon_device *rdev);
2806 extern void radeon_modeset_fini(struct radeon_device *rdev);
2807 extern bool radeon_card_posted(struct radeon_device *rdev);
2808 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2809 extern void radeon_update_display_priority(struct radeon_device *rdev);
2810 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2811 extern void radeon_scratch_init(struct radeon_device *rdev);
2812 extern void radeon_wb_fini(struct radeon_device *rdev);
2813 extern int radeon_wb_init(struct radeon_device *rdev);
2814 extern void radeon_wb_disable(struct radeon_device *rdev);
2815 extern void radeon_surface_init(struct radeon_device *rdev);
2816 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2817 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2818 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2819 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2820 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2821 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2822 uint32_t flags);
2823 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2824 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2825 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2826 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2827 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2828 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2829 bool fbcon, bool freeze);
2830 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2831 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2832 const u32 *registers,
2833 const u32 array_size);
2834
2835 /*
2836 * vm
2837 */
2838 int radeon_vm_manager_init(struct radeon_device *rdev);
2839 void radeon_vm_manager_fini(struct radeon_device *rdev);
2840 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2841 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2842 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2843 struct radeon_vm *vm,
2844 struct list_head *head);
2845 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2846 struct radeon_vm *vm, int ring);
2847 void radeon_vm_flush(struct radeon_device *rdev,
2848 struct radeon_vm *vm,
2849 int ring, struct radeon_fence *fence);
2850 void radeon_vm_fence(struct radeon_device *rdev,
2851 struct radeon_vm *vm,
2852 struct radeon_fence *fence);
2853 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2854 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2855 struct radeon_vm *vm);
2856 int radeon_vm_clear_freed(struct radeon_device *rdev,
2857 struct radeon_vm *vm);
2858 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2859 struct radeon_vm *vm);
2860 int radeon_vm_bo_update(struct radeon_device *rdev,
2861 struct radeon_bo_va *bo_va,
2862 struct ttm_mem_reg *mem);
2863 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2864 struct radeon_bo *bo);
2865 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2866 struct radeon_bo *bo);
2867 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2868 struct radeon_vm *vm,
2869 struct radeon_bo *bo);
2870 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2871 struct radeon_bo_va *bo_va,
2872 uint64_t offset,
2873 uint32_t flags);
2874 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2875 struct radeon_bo_va *bo_va);
2876
2877 /* audio */
2878 void r600_audio_update_hdmi(struct work_struct *work);
2879 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2880 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2881 void r600_audio_enable(struct radeon_device *rdev,
2882 struct r600_audio_pin *pin,
2883 u8 enable_mask);
2884 void dce6_audio_enable(struct radeon_device *rdev,
2885 struct r600_audio_pin *pin,
2886 u8 enable_mask);
2887
2888 /*
2889 * R600 vram scratch functions
2890 */
2891 int r600_vram_scratch_init(struct radeon_device *rdev);
2892 void r600_vram_scratch_fini(struct radeon_device *rdev);
2893
2894 /*
2895 * r600 cs checking helper
2896 */
2897 unsigned r600_mip_minify(unsigned size, unsigned level);
2898 bool r600_fmt_is_valid_color(u32 format);
2899 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2900 int r600_fmt_get_blocksize(u32 format);
2901 int r600_fmt_get_nblocksx(u32 format, u32 w);
2902 int r600_fmt_get_nblocksy(u32 format, u32 h);
2903
2904 /*
2905 * r600 functions used by radeon_encoder.c
2906 */
2907 struct radeon_hdmi_acr {
2908 u32 clock;
2909
2910 int n_32khz;
2911 int cts_32khz;
2912
2913 int n_44_1khz;
2914 int cts_44_1khz;
2915
2916 int n_48khz;
2917 int cts_48khz;
2918
2919 };
2920
2921 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2922
2923 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2924 u32 tiling_pipe_num,
2925 u32 max_rb_num,
2926 u32 total_max_rb_num,
2927 u32 enabled_rb_mask);
2928
2929 /*
2930 * evergreen functions used by radeon_encoder.c
2931 */
2932
2933 extern int ni_init_microcode(struct radeon_device *rdev);
2934 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2935
2936 /* radeon_acpi.c */
2937 #if defined(CONFIG_ACPI)
2938 extern int radeon_acpi_init(struct radeon_device *rdev);
2939 extern void radeon_acpi_fini(struct radeon_device *rdev);
2940 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2941 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2942 u8 perf_req, bool advertise);
2943 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2944 #else
radeon_acpi_init(struct radeon_device * rdev)2945 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
radeon_acpi_fini(struct radeon_device * rdev)2946 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2947 #endif
2948
2949 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2950 struct radeon_cs_packet *pkt,
2951 unsigned idx);
2952 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2953 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2954 struct radeon_cs_packet *pkt);
2955 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2956 struct radeon_bo_list **cs_reloc,
2957 int nomm);
2958 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2959 uint32_t *vline_start_end,
2960 uint32_t *vline_status);
2961
2962 /* interrupt control register helpers */
2963 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
2964 u32 reg, u32 mask,
2965 bool enable, const char *name,
2966 unsigned n);
2967
2968 #include "radeon_object.h"
2969
2970 #endif
2971
