1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <drm/drmP.h>
35 #include <drm/radeon_drm.h>
36 #include <drm/drm_cache.h>
37 #include "radeon.h"
38 #include "radeon_trace.h"
39
40
41 int radeon_ttm_init(struct radeon_device *rdev);
42 void radeon_ttm_fini(struct radeon_device *rdev);
43 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
44
45 /*
46 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
47 * function are calling it.
48 */
49
radeon_update_memory_usage(struct radeon_bo * bo,unsigned mem_type,int sign)50 static void radeon_update_memory_usage(struct radeon_bo *bo,
51 unsigned mem_type, int sign)
52 {
53 struct radeon_device *rdev = bo->rdev;
54 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
55
56 switch (mem_type) {
57 case TTM_PL_TT:
58 if (sign > 0)
59 atomic64_add(size, &rdev->gtt_usage);
60 else
61 atomic64_sub(size, &rdev->gtt_usage);
62 break;
63 case TTM_PL_VRAM:
64 if (sign > 0)
65 atomic64_add(size, &rdev->vram_usage);
66 else
67 atomic64_sub(size, &rdev->vram_usage);
68 break;
69 }
70 }
71
radeon_ttm_bo_destroy(struct ttm_buffer_object * tbo)72 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
73 {
74 struct radeon_bo *bo;
75
76 bo = container_of(tbo, struct radeon_bo, tbo);
77
78 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
79
80 mutex_lock(&bo->rdev->gem.mutex);
81 list_del_init(&bo->list);
82 mutex_unlock(&bo->rdev->gem.mutex);
83 radeon_bo_clear_surface_reg(bo);
84 WARN_ON_ONCE(!list_empty(&bo->va));
85 if (bo->gem_base.import_attach)
86 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
87 drm_gem_object_release(&bo->gem_base);
88 kfree(bo);
89 }
90
radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object * bo)91 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
92 {
93 if (bo->destroy == &radeon_ttm_bo_destroy)
94 return true;
95 return false;
96 }
97
radeon_ttm_placement_from_domain(struct radeon_bo * rbo,u32 domain)98 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
99 {
100 u32 c = 0, i;
101
102 rbo->placement.placement = rbo->placements;
103 rbo->placement.busy_placement = rbo->placements;
104 if (domain & RADEON_GEM_DOMAIN_VRAM) {
105 /* Try placing BOs which don't need CPU access outside of the
106 * CPU accessible part of VRAM
107 */
108 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
109 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
110 rbo->placements[c].fpfn =
111 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
112 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
113 TTM_PL_FLAG_UNCACHED |
114 TTM_PL_FLAG_VRAM;
115 }
116
117 rbo->placements[c].fpfn = 0;
118 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
119 TTM_PL_FLAG_UNCACHED |
120 TTM_PL_FLAG_VRAM;
121 }
122
123 if (domain & RADEON_GEM_DOMAIN_GTT) {
124 if (rbo->flags & RADEON_GEM_GTT_UC) {
125 rbo->placements[c].fpfn = 0;
126 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
127 TTM_PL_FLAG_TT;
128
129 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
130 (rbo->rdev->flags & RADEON_IS_AGP)) {
131 rbo->placements[c].fpfn = 0;
132 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
133 TTM_PL_FLAG_UNCACHED |
134 TTM_PL_FLAG_TT;
135 } else {
136 rbo->placements[c].fpfn = 0;
137 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
138 TTM_PL_FLAG_TT;
139 }
140 }
141
142 if (domain & RADEON_GEM_DOMAIN_CPU) {
143 if (rbo->flags & RADEON_GEM_GTT_UC) {
144 rbo->placements[c].fpfn = 0;
145 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
146 TTM_PL_FLAG_SYSTEM;
147
148 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
149 rbo->rdev->flags & RADEON_IS_AGP) {
150 rbo->placements[c].fpfn = 0;
151 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
152 TTM_PL_FLAG_UNCACHED |
153 TTM_PL_FLAG_SYSTEM;
154 } else {
155 rbo->placements[c].fpfn = 0;
156 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
157 TTM_PL_FLAG_SYSTEM;
158 }
159 }
160 if (!c) {
161 rbo->placements[c].fpfn = 0;
162 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
163 TTM_PL_FLAG_SYSTEM;
164 }
165
166 rbo->placement.num_placement = c;
167 rbo->placement.num_busy_placement = c;
168
169 for (i = 0; i < c; ++i) {
170 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
171 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
172 !rbo->placements[i].fpfn)
173 rbo->placements[i].lpfn =
174 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
175 else
176 rbo->placements[i].lpfn = 0;
177 }
178 }
179
radeon_bo_create(struct radeon_device * rdev,unsigned long size,int byte_align,bool kernel,u32 domain,u32 flags,struct sg_table * sg,struct reservation_object * resv,struct radeon_bo ** bo_ptr)180 int radeon_bo_create(struct radeon_device *rdev,
181 unsigned long size, int byte_align, bool kernel,
182 u32 domain, u32 flags, struct sg_table *sg,
183 struct reservation_object *resv,
184 struct radeon_bo **bo_ptr)
185 {
186 struct radeon_bo *bo;
187 enum ttm_bo_type type;
188 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
189 size_t acc_size;
190 int r;
191
192 size = ALIGN(size, PAGE_SIZE);
193
194 if (kernel) {
195 type = ttm_bo_type_kernel;
196 } else if (sg) {
197 type = ttm_bo_type_sg;
198 } else {
199 type = ttm_bo_type_device;
200 }
201 *bo_ptr = NULL;
202
203 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
204 sizeof(struct radeon_bo));
205
206 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
207 if (bo == NULL)
208 return -ENOMEM;
209 drm_gem_private_object_init(rdev->ddev, &bo->gem_base, size);
210 bo->rdev = rdev;
211 bo->surface_reg = -1;
212 INIT_LIST_HEAD(&bo->list);
213 INIT_LIST_HEAD(&bo->va);
214 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
215 RADEON_GEM_DOMAIN_GTT |
216 RADEON_GEM_DOMAIN_CPU);
217
218 bo->flags = flags;
219 /* PCI GART is always snooped */
220 if (!(rdev->flags & RADEON_IS_PCIE))
221 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
222
223 /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx
224 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268
225 */
226 if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635)
227 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
228
229 #ifdef CONFIG_X86_32
230 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
231 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
232 */
233 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
234 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
235 /* Don't try to enable write-combining when it can't work, or things
236 * may be slow
237 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
238 */
239 #ifndef CONFIG_COMPILE_TEST
240 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
241 thanks to write-combining
242 #endif
243
244 if (bo->flags & RADEON_GEM_GTT_WC)
245 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
246 "better performance thanks to write-combining\n");
247 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
248 #else
249 /* For architectures that don't support WC memory,
250 * mask out the WC flag from the BO
251 */
252 if (!drm_arch_can_wc_memory())
253 bo->flags &= ~RADEON_GEM_GTT_WC;
254 #endif
255
256 radeon_ttm_placement_from_domain(bo, domain);
257 /* Kernel allocation are uninterruptible */
258 down_read(&rdev->pm.mclk_lock);
259 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
260 &bo->placement, page_align, !kernel, acc_size,
261 sg, resv, &radeon_ttm_bo_destroy);
262 up_read(&rdev->pm.mclk_lock);
263 if (unlikely(r != 0)) {
264 return r;
265 }
266 *bo_ptr = bo;
267
268 trace_radeon_bo_create(bo);
269
270 return 0;
271 }
272
radeon_bo_kmap(struct radeon_bo * bo,void ** ptr)273 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
274 {
275 bool is_iomem;
276 int r;
277
278 if (bo->kptr) {
279 if (ptr) {
280 *ptr = bo->kptr;
281 }
282 return 0;
283 }
284 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
285 if (r) {
286 return r;
287 }
288 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
289 if (ptr) {
290 *ptr = bo->kptr;
291 }
292 radeon_bo_check_tiling(bo, 0, 0);
293 return 0;
294 }
295
radeon_bo_kunmap(struct radeon_bo * bo)296 void radeon_bo_kunmap(struct radeon_bo *bo)
297 {
298 if (bo->kptr == NULL)
299 return;
300 bo->kptr = NULL;
301 radeon_bo_check_tiling(bo, 0, 0);
302 ttm_bo_kunmap(&bo->kmap);
303 }
304
radeon_bo_ref(struct radeon_bo * bo)305 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
306 {
307 if (bo == NULL)
308 return NULL;
309
310 ttm_bo_get(&bo->tbo);
311 return bo;
312 }
313
radeon_bo_unref(struct radeon_bo ** bo)314 void radeon_bo_unref(struct radeon_bo **bo)
315 {
316 struct ttm_buffer_object *tbo;
317 struct radeon_device *rdev;
318
319 if ((*bo) == NULL)
320 return;
321 rdev = (*bo)->rdev;
322 tbo = &((*bo)->tbo);
323 ttm_bo_put(tbo);
324 *bo = NULL;
325 }
326
radeon_bo_pin_restricted(struct radeon_bo * bo,u32 domain,u64 max_offset,u64 * gpu_addr)327 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
328 u64 *gpu_addr)
329 {
330 struct ttm_operation_ctx ctx = { false, false };
331 int r, i;
332
333 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
334 return -EPERM;
335
336 if (bo->pin_count) {
337 bo->pin_count++;
338 if (gpu_addr)
339 *gpu_addr = radeon_bo_gpu_offset(bo);
340
341 if (max_offset != 0) {
342 u64 domain_start;
343
344 if (domain == RADEON_GEM_DOMAIN_VRAM)
345 domain_start = bo->rdev->mc.vram_start;
346 else
347 domain_start = bo->rdev->mc.gtt_start;
348 WARN_ON_ONCE(max_offset <
349 (radeon_bo_gpu_offset(bo) - domain_start));
350 }
351
352 return 0;
353 }
354 if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) {
355 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */
356 return -EINVAL;
357 }
358
359 radeon_ttm_placement_from_domain(bo, domain);
360 for (i = 0; i < bo->placement.num_placement; i++) {
361 /* force to pin into visible video ram */
362 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
363 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
364 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
365 bo->placements[i].lpfn =
366 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
367 else
368 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
369
370 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
371 }
372
373 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
374 if (likely(r == 0)) {
375 bo->pin_count = 1;
376 if (gpu_addr != NULL)
377 *gpu_addr = radeon_bo_gpu_offset(bo);
378 if (domain == RADEON_GEM_DOMAIN_VRAM)
379 bo->rdev->vram_pin_size += radeon_bo_size(bo);
380 else
381 bo->rdev->gart_pin_size += radeon_bo_size(bo);
382 } else {
383 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
384 }
385 return r;
386 }
387
radeon_bo_pin(struct radeon_bo * bo,u32 domain,u64 * gpu_addr)388 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
389 {
390 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
391 }
392
radeon_bo_unpin(struct radeon_bo * bo)393 int radeon_bo_unpin(struct radeon_bo *bo)
394 {
395 struct ttm_operation_ctx ctx = { false, false };
396 int r, i;
397
398 if (!bo->pin_count) {
399 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
400 return 0;
401 }
402 bo->pin_count--;
403 if (bo->pin_count)
404 return 0;
405 for (i = 0; i < bo->placement.num_placement; i++) {
406 bo->placements[i].lpfn = 0;
407 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
408 }
409 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
410 if (likely(r == 0)) {
411 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
412 bo->rdev->vram_pin_size -= radeon_bo_size(bo);
413 else
414 bo->rdev->gart_pin_size -= radeon_bo_size(bo);
415 } else {
416 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
417 }
418 return r;
419 }
420
radeon_bo_evict_vram(struct radeon_device * rdev)421 int radeon_bo_evict_vram(struct radeon_device *rdev)
422 {
423 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
424 if (0 && (rdev->flags & RADEON_IS_IGP)) {
425 if (rdev->mc.igp_sideport_enabled == false)
426 /* Useless to evict on IGP chips */
427 return 0;
428 }
429 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
430 }
431
radeon_bo_force_delete(struct radeon_device * rdev)432 void radeon_bo_force_delete(struct radeon_device *rdev)
433 {
434 struct radeon_bo *bo, *n;
435
436 if (list_empty(&rdev->gem.objects)) {
437 return;
438 }
439 dev_err(rdev->dev, "Userspace still has active objects !\n");
440 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
441 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
442 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
443 *((unsigned long *)&bo->gem_base.refcount));
444 mutex_lock(&bo->rdev->gem.mutex);
445 list_del_init(&bo->list);
446 mutex_unlock(&bo->rdev->gem.mutex);
447 /* this should unref the ttm bo */
448 drm_gem_object_put_unlocked(&bo->gem_base);
449 }
450 }
451
radeon_bo_init(struct radeon_device * rdev)452 int radeon_bo_init(struct radeon_device *rdev)
453 {
454 /* reserve PAT memory space to WC for VRAM */
455 arch_io_reserve_memtype_wc(rdev->mc.aper_base,
456 rdev->mc.aper_size);
457
458 /* Add an MTRR for the VRAM */
459 if (!rdev->fastfb_working) {
460 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
461 rdev->mc.aper_size);
462 }
463 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
464 rdev->mc.mc_vram_size >> 20,
465 (unsigned long long)rdev->mc.aper_size >> 20);
466 DRM_INFO("RAM width %dbits %cDR\n",
467 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
468 return radeon_ttm_init(rdev);
469 }
470
radeon_bo_fini(struct radeon_device * rdev)471 void radeon_bo_fini(struct radeon_device *rdev)
472 {
473 radeon_ttm_fini(rdev);
474 arch_phys_wc_del(rdev->mc.vram_mtrr);
475 arch_io_free_memtype_wc(rdev->mc.aper_base, rdev->mc.aper_size);
476 }
477
478 /* Returns how many bytes TTM can move per IB.
479 */
radeon_bo_get_threshold_for_moves(struct radeon_device * rdev)480 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
481 {
482 u64 real_vram_size = rdev->mc.real_vram_size;
483 u64 vram_usage = atomic64_read(&rdev->vram_usage);
484
485 /* This function is based on the current VRAM usage.
486 *
487 * - If all of VRAM is free, allow relocating the number of bytes that
488 * is equal to 1/4 of the size of VRAM for this IB.
489
490 * - If more than one half of VRAM is occupied, only allow relocating
491 * 1 MB of data for this IB.
492 *
493 * - From 0 to one half of used VRAM, the threshold decreases
494 * linearly.
495 * __________________
496 * 1/4 of -|\ |
497 * VRAM | \ |
498 * | \ |
499 * | \ |
500 * | \ |
501 * | \ |
502 * | \ |
503 * | \________|1 MB
504 * |----------------|
505 * VRAM 0 % 100 %
506 * used used
507 *
508 * Note: It's a threshold, not a limit. The threshold must be crossed
509 * for buffer relocations to stop, so any buffer of an arbitrary size
510 * can be moved as long as the threshold isn't crossed before
511 * the relocation takes place. We don't want to disable buffer
512 * relocations completely.
513 *
514 * The idea is that buffers should be placed in VRAM at creation time
515 * and TTM should only do a minimum number of relocations during
516 * command submission. In practice, you need to submit at least
517 * a dozen IBs to move all buffers to VRAM if they are in GTT.
518 *
519 * Also, things can get pretty crazy under memory pressure and actual
520 * VRAM usage can change a lot, so playing safe even at 50% does
521 * consistently increase performance.
522 */
523
524 u64 half_vram = real_vram_size >> 1;
525 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
526 u64 bytes_moved_threshold = half_free_vram >> 1;
527 return max(bytes_moved_threshold, 1024*1024ull);
528 }
529
radeon_bo_list_validate(struct radeon_device * rdev,struct ww_acquire_ctx * ticket,struct list_head * head,int ring)530 int radeon_bo_list_validate(struct radeon_device *rdev,
531 struct ww_acquire_ctx *ticket,
532 struct list_head *head, int ring)
533 {
534 struct ttm_operation_ctx ctx = { true, false };
535 struct radeon_bo_list *lobj;
536 struct list_head duplicates;
537 int r;
538 u64 bytes_moved = 0, initial_bytes_moved;
539 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
540
541 INIT_LIST_HEAD(&duplicates);
542 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates);
543 if (unlikely(r != 0)) {
544 return r;
545 }
546
547 list_for_each_entry(lobj, head, tv.head) {
548 struct radeon_bo *bo = lobj->robj;
549 if (!bo->pin_count) {
550 u32 domain = lobj->preferred_domains;
551 u32 allowed = lobj->allowed_domains;
552 u32 current_domain =
553 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
554
555 /* Check if this buffer will be moved and don't move it
556 * if we have moved too many buffers for this IB already.
557 *
558 * Note that this allows moving at least one buffer of
559 * any size, because it doesn't take the current "bo"
560 * into account. We don't want to disallow buffer moves
561 * completely.
562 */
563 if ((allowed & current_domain) != 0 &&
564 (domain & current_domain) == 0 && /* will be moved */
565 bytes_moved > bytes_moved_threshold) {
566 /* don't move it */
567 domain = current_domain;
568 }
569
570 retry:
571 radeon_ttm_placement_from_domain(bo, domain);
572 if (ring == R600_RING_TYPE_UVD_INDEX)
573 radeon_uvd_force_into_uvd_segment(bo, allowed);
574
575 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
576 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
577 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
578 initial_bytes_moved;
579
580 if (unlikely(r)) {
581 if (r != -ERESTARTSYS &&
582 domain != lobj->allowed_domains) {
583 domain = lobj->allowed_domains;
584 goto retry;
585 }
586 ttm_eu_backoff_reservation(ticket, head);
587 return r;
588 }
589 }
590 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
591 lobj->tiling_flags = bo->tiling_flags;
592 }
593
594 list_for_each_entry(lobj, &duplicates, tv.head) {
595 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj);
596 lobj->tiling_flags = lobj->robj->tiling_flags;
597 }
598
599 return 0;
600 }
601
radeon_bo_get_surface_reg(struct radeon_bo * bo)602 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
603 {
604 struct radeon_device *rdev = bo->rdev;
605 struct radeon_surface_reg *reg;
606 struct radeon_bo *old_object;
607 int steal;
608 int i;
609
610 lockdep_assert_held(&bo->tbo.resv->lock.base);
611
612 if (!bo->tiling_flags)
613 return 0;
614
615 if (bo->surface_reg >= 0) {
616 reg = &rdev->surface_regs[bo->surface_reg];
617 i = bo->surface_reg;
618 goto out;
619 }
620
621 steal = -1;
622 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
623
624 reg = &rdev->surface_regs[i];
625 if (!reg->bo)
626 break;
627
628 old_object = reg->bo;
629 if (old_object->pin_count == 0)
630 steal = i;
631 }
632
633 /* if we are all out */
634 if (i == RADEON_GEM_MAX_SURFACES) {
635 if (steal == -1)
636 return -ENOMEM;
637 /* find someone with a surface reg and nuke their BO */
638 reg = &rdev->surface_regs[steal];
639 old_object = reg->bo;
640 /* blow away the mapping */
641 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
642 ttm_bo_unmap_virtual(&old_object->tbo);
643 old_object->surface_reg = -1;
644 i = steal;
645 }
646
647 bo->surface_reg = i;
648 reg->bo = bo;
649
650 out:
651 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
652 bo->tbo.mem.start << PAGE_SHIFT,
653 bo->tbo.num_pages << PAGE_SHIFT);
654 return 0;
655 }
656
radeon_bo_clear_surface_reg(struct radeon_bo * bo)657 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
658 {
659 struct radeon_device *rdev = bo->rdev;
660 struct radeon_surface_reg *reg;
661
662 if (bo->surface_reg == -1)
663 return;
664
665 reg = &rdev->surface_regs[bo->surface_reg];
666 radeon_clear_surface_reg(rdev, bo->surface_reg);
667
668 reg->bo = NULL;
669 bo->surface_reg = -1;
670 }
671
radeon_bo_set_tiling_flags(struct radeon_bo * bo,uint32_t tiling_flags,uint32_t pitch)672 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
673 uint32_t tiling_flags, uint32_t pitch)
674 {
675 struct radeon_device *rdev = bo->rdev;
676 int r;
677
678 if (rdev->family >= CHIP_CEDAR) {
679 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
680
681 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
682 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
683 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
684 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
685 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
686 switch (bankw) {
687 case 0:
688 case 1:
689 case 2:
690 case 4:
691 case 8:
692 break;
693 default:
694 return -EINVAL;
695 }
696 switch (bankh) {
697 case 0:
698 case 1:
699 case 2:
700 case 4:
701 case 8:
702 break;
703 default:
704 return -EINVAL;
705 }
706 switch (mtaspect) {
707 case 0:
708 case 1:
709 case 2:
710 case 4:
711 case 8:
712 break;
713 default:
714 return -EINVAL;
715 }
716 if (tilesplit > 6) {
717 return -EINVAL;
718 }
719 if (stilesplit > 6) {
720 return -EINVAL;
721 }
722 }
723 r = radeon_bo_reserve(bo, false);
724 if (unlikely(r != 0))
725 return r;
726 bo->tiling_flags = tiling_flags;
727 bo->pitch = pitch;
728 radeon_bo_unreserve(bo);
729 return 0;
730 }
731
radeon_bo_get_tiling_flags(struct radeon_bo * bo,uint32_t * tiling_flags,uint32_t * pitch)732 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
733 uint32_t *tiling_flags,
734 uint32_t *pitch)
735 {
736 lockdep_assert_held(&bo->tbo.resv->lock.base);
737
738 if (tiling_flags)
739 *tiling_flags = bo->tiling_flags;
740 if (pitch)
741 *pitch = bo->pitch;
742 }
743
radeon_bo_check_tiling(struct radeon_bo * bo,bool has_moved,bool force_drop)744 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
745 bool force_drop)
746 {
747 if (!force_drop)
748 lockdep_assert_held(&bo->tbo.resv->lock.base);
749
750 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
751 return 0;
752
753 if (force_drop) {
754 radeon_bo_clear_surface_reg(bo);
755 return 0;
756 }
757
758 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
759 if (!has_moved)
760 return 0;
761
762 if (bo->surface_reg >= 0)
763 radeon_bo_clear_surface_reg(bo);
764 return 0;
765 }
766
767 if ((bo->surface_reg >= 0) && !has_moved)
768 return 0;
769
770 return radeon_bo_get_surface_reg(bo);
771 }
772
radeon_bo_move_notify(struct ttm_buffer_object * bo,bool evict,struct ttm_mem_reg * new_mem)773 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
774 bool evict,
775 struct ttm_mem_reg *new_mem)
776 {
777 struct radeon_bo *rbo;
778
779 if (!radeon_ttm_bo_is_radeon_bo(bo))
780 return;
781
782 rbo = container_of(bo, struct radeon_bo, tbo);
783 radeon_bo_check_tiling(rbo, 0, 1);
784 radeon_vm_bo_invalidate(rbo->rdev, rbo);
785
786 /* update statistics */
787 if (!new_mem)
788 return;
789
790 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
791 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
792 }
793
radeon_bo_fault_reserve_notify(struct ttm_buffer_object * bo)794 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
795 {
796 struct ttm_operation_ctx ctx = { false, false };
797 struct radeon_device *rdev;
798 struct radeon_bo *rbo;
799 unsigned long offset, size, lpfn;
800 int i, r;
801
802 if (!radeon_ttm_bo_is_radeon_bo(bo))
803 return 0;
804 rbo = container_of(bo, struct radeon_bo, tbo);
805 radeon_bo_check_tiling(rbo, 0, 0);
806 rdev = rbo->rdev;
807 if (bo->mem.mem_type != TTM_PL_VRAM)
808 return 0;
809
810 size = bo->mem.num_pages << PAGE_SHIFT;
811 offset = bo->mem.start << PAGE_SHIFT;
812 if ((offset + size) <= rdev->mc.visible_vram_size)
813 return 0;
814
815 /* Can't move a pinned BO to visible VRAM */
816 if (rbo->pin_count > 0)
817 return -EINVAL;
818
819 /* hurrah the memory is not visible ! */
820 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
821 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
822 for (i = 0; i < rbo->placement.num_placement; i++) {
823 /* Force into visible VRAM */
824 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
825 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
826 rbo->placements[i].lpfn = lpfn;
827 }
828 r = ttm_bo_validate(bo, &rbo->placement, &ctx);
829 if (unlikely(r == -ENOMEM)) {
830 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
831 return ttm_bo_validate(bo, &rbo->placement, &ctx);
832 } else if (unlikely(r != 0)) {
833 return r;
834 }
835
836 offset = bo->mem.start << PAGE_SHIFT;
837 /* this should never happen */
838 if ((offset + size) > rdev->mc.visible_vram_size)
839 return -EINVAL;
840
841 return 0;
842 }
843
radeon_bo_wait(struct radeon_bo * bo,u32 * mem_type,bool no_wait)844 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
845 {
846 int r;
847
848 r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL);
849 if (unlikely(r != 0))
850 return r;
851 if (mem_type)
852 *mem_type = bo->tbo.mem.mem_type;
853
854 r = ttm_bo_wait(&bo->tbo, true, no_wait);
855 ttm_bo_unreserve(&bo->tbo);
856 return r;
857 }
858
859 /**
860 * radeon_bo_fence - add fence to buffer object
861 *
862 * @bo: buffer object in question
863 * @fence: fence to add
864 * @shared: true if fence should be added shared
865 *
866 */
radeon_bo_fence(struct radeon_bo * bo,struct radeon_fence * fence,bool shared)867 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
868 bool shared)
869 {
870 struct reservation_object *resv = bo->tbo.resv;
871
872 if (shared)
873 reservation_object_add_shared_fence(resv, &fence->base);
874 else
875 reservation_object_add_excl_fence(resv, &fence->base);
876 }
877
