1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Microchip Image Sensor Controller (ISC) driver header file 4 * 5 * Copyright (C) 2016-2019 Microchip Technology, Inc. 6 * 7 * Author: Songjun Wu 8 * Author: Eugen Hristev <eugen.hristev@microchip.com> 9 * 10 */ 11 #ifndef _ATMEL_ISC_H_ 12 13 #define ISC_CLK_MAX_DIV 255 14 15 enum isc_clk_id { 16 ISC_ISPCK = 0, 17 ISC_MCK = 1, 18 }; 19 20 struct isc_clk { 21 struct clk_hw hw; 22 struct clk *clk; 23 struct regmap *regmap; 24 spinlock_t lock; /* serialize access to clock registers */ 25 u8 id; 26 u8 parent_id; 27 u32 div; 28 struct device *dev; 29 }; 30 31 #define to_isc_clk(v) container_of(v, struct isc_clk, hw) 32 33 struct isc_buffer { 34 struct vb2_v4l2_buffer vb; 35 struct list_head list; 36 }; 37 38 struct isc_subdev_entity { 39 struct v4l2_subdev *sd; 40 struct v4l2_async_subdev *asd; 41 struct device_node *epn; 42 struct v4l2_async_notifier notifier; 43 44 u32 pfe_cfg0; 45 46 struct list_head list; 47 }; 48 49 /* 50 * struct isc_format - ISC media bus format information 51 This structure represents the interface between the ISC 52 and the sensor. It's the input format received by 53 the ISC. 54 * @fourcc: Fourcc code for this format 55 * @mbus_code: V4L2 media bus format code. 56 * @cfa_baycfg: If this format is RAW BAYER, indicate the type of bayer. 57 this is either BGBG, RGRG, etc. 58 * @pfe_cfg0_bps: Number of hardware data lines connected to the ISC 59 */ 60 61 struct isc_format { 62 u32 fourcc; 63 u32 mbus_code; 64 u32 cfa_baycfg; 65 66 bool sd_support; 67 u32 pfe_cfg0_bps; 68 }; 69 70 /* Pipeline bitmap */ 71 #define DPC_DPCENABLE BIT(0) 72 #define DPC_GDCENABLE BIT(1) 73 #define DPC_BLCENABLE BIT(2) 74 #define WB_ENABLE BIT(3) 75 #define CFA_ENABLE BIT(4) 76 #define CC_ENABLE BIT(5) 77 #define GAM_ENABLE BIT(6) 78 #define GAM_BENABLE BIT(7) 79 #define GAM_GENABLE BIT(8) 80 #define GAM_RENABLE BIT(9) 81 #define VHXS_ENABLE BIT(10) 82 #define CSC_ENABLE BIT(11) 83 #define CBC_ENABLE BIT(12) 84 #define SUB422_ENABLE BIT(13) 85 #define SUB420_ENABLE BIT(14) 86 87 #define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE) 88 89 /* 90 * struct fmt_config - ISC format configuration and internal pipeline 91 This structure represents the internal configuration 92 of the ISC. 93 It also holds the format that ISC will present to v4l2. 94 * @sd_format: Pointer to an isc_format struct that holds the sensor 95 configuration. 96 * @fourcc: Fourcc code for this format. 97 * @bpp: Bytes per pixel in the current format. 98 * @rlp_cfg_mode: Configuration of the RLP (rounding, limiting packaging) 99 * @dcfg_imode: Configuration of the input of the DMA module 100 * @dctrl_dview: Configuration of the output of the DMA module 101 * @bits_pipeline: Configuration of the pipeline, which modules are enabled 102 */ 103 struct fmt_config { 104 struct isc_format *sd_format; 105 106 u32 fourcc; 107 u8 bpp; 108 109 u32 rlp_cfg_mode; 110 u32 dcfg_imode; 111 u32 dctrl_dview; 112 113 u32 bits_pipeline; 114 }; 115 116 #define HIST_ENTRIES 512 117 #define HIST_BAYER (ISC_HIS_CFG_MODE_B + 1) 118 119 enum{ 120 HIST_INIT = 0, 121 HIST_ENABLED, 122 HIST_DISABLED, 123 }; 124 125 struct isc_ctrls { 126 struct v4l2_ctrl_handler handler; 127 128 u32 brightness; 129 u32 contrast; 130 u8 gamma_index; 131 #define ISC_WB_NONE 0 132 #define ISC_WB_AUTO 1 133 #define ISC_WB_ONETIME 2 134 u8 awb; 135 136 /* one for each component : GR, R, GB, B */ 137 u32 gain[HIST_BAYER]; 138 s32 offset[HIST_BAYER]; 139 140 u32 hist_entry[HIST_ENTRIES]; 141 u32 hist_count[HIST_BAYER]; 142 u8 hist_id; 143 u8 hist_stat; 144 #define HIST_MIN_INDEX 0 145 #define HIST_MAX_INDEX 1 146 u32 hist_minmax[HIST_BAYER][2]; 147 }; 148 149 #define ISC_PIPE_LINE_NODE_NUM 15 150 151 /* 152 * struct isc_reg_offsets - ISC device register offsets 153 * @csc: Offset for the CSC register 154 * @cbc: Offset for the CBC register 155 * @sub422: Offset for the SUB422 register 156 * @sub420: Offset for the SUB420 register 157 * @rlp: Offset for the RLP register 158 * @his: Offset for the HIS related registers 159 * @dma: Offset for the DMA related registers 160 * @version: Offset for the version register 161 * @his_entry: Offset for the HIS entries registers 162 */ 163 struct isc_reg_offsets { 164 u32 csc; 165 u32 cbc; 166 u32 sub422; 167 u32 sub420; 168 u32 rlp; 169 u32 his; 170 u32 dma; 171 u32 version; 172 u32 his_entry; 173 }; 174 175 /* 176 * struct isc_device - ISC device driver data/config struct 177 * @regmap: Register map 178 * @hclock: Hclock clock input (refer datasheet) 179 * @ispck: iscpck clock (refer datasheet) 180 * @isc_clks: ISC clocks 181 * @dcfg: DMA master configuration, architecture dependent 182 * 183 * @dev: Registered device driver 184 * @v4l2_dev: v4l2 registered device 185 * @video_dev: registered video device 186 * 187 * @vb2_vidq: video buffer 2 video queue 188 * @dma_queue_lock: lock to serialize the dma buffer queue 189 * @dma_queue: the queue for dma buffers 190 * @cur_frm: current isc frame/buffer 191 * @sequence: current frame number 192 * @stop: true if isc is not streaming, false if streaming 193 * @comp: completion reference that signals frame completion 194 * 195 * @fmt: current v42l format 196 * @user_formats: list of formats that are supported and agreed with sd 197 * @num_user_formats: how many formats are in user_formats 198 * 199 * @config: current ISC format configuration 200 * @try_config: the current ISC try format , not yet activated 201 * 202 * @ctrls: holds information about ISC controls 203 * @do_wb_ctrl: control regarding the DO_WHITE_BALANCE button 204 * @awb_work: workqueue reference for autowhitebalance histogram 205 * analysis 206 * 207 * @lock: lock for serializing userspace file operations 208 * with ISC operations 209 * @awb_lock: lock for serializing awb work queue operations 210 * with DMA/buffer operations 211 * 212 * @pipeline: configuration of the ISC pipeline 213 * 214 * @current_subdev: current subdevice: the sensor 215 * @subdev_entities: list of subdevice entitites 216 * 217 * @gamma_table: pointer to the table with gamma values, has 218 * gamma_max sets of GAMMA_ENTRIES entries each 219 * @gamma_max: maximum number of sets of inside the gamma_table 220 * 221 * @max_width: maximum frame width, dependent on the internal RAM 222 * @max_height: maximum frame height, dependent on the internal RAM 223 * 224 * @config_dpc: pointer to a function that initializes product 225 * specific DPC module 226 * @config_csc: pointer to a function that initializes product 227 * specific CSC module 228 * @config_cbc: pointer to a function that initializes product 229 * specific CBC module 230 * @config_cc: pointer to a function that initializes product 231 * specific CC module 232 * @config_gam: pointer to a function that initializes product 233 * specific GAMMA module 234 * @config_rlp: pointer to a function that initializes product 235 * specific RLP module 236 * @config_ctrls: pointer to a functoin that initializes product 237 * specific v4l2 controls. 238 * 239 * @adapt_pipeline: pointer to a function that adapts the pipeline bits 240 * to the product specific pipeline 241 * 242 * @offsets: struct holding the product specific register offsets 243 * @controller_formats: pointer to the array of possible formats that the 244 * controller can output 245 * @formats_list: pointer to the array of possible formats that can 246 * be used as an input to the controller 247 * @controller_formats_size: size of controller_formats array 248 * @formats_list_size: size of formats_list array 249 */ 250 struct isc_device { 251 struct regmap *regmap; 252 struct clk *hclock; 253 struct clk *ispck; 254 struct isc_clk isc_clks[2]; 255 u32 dcfg; 256 257 struct device *dev; 258 struct v4l2_device v4l2_dev; 259 struct video_device video_dev; 260 261 struct vb2_queue vb2_vidq; 262 spinlock_t dma_queue_lock; /* serialize access to dma queue */ 263 struct list_head dma_queue; 264 struct isc_buffer *cur_frm; 265 unsigned int sequence; 266 bool stop; 267 struct completion comp; 268 269 struct v4l2_format fmt; 270 struct isc_format **user_formats; 271 unsigned int num_user_formats; 272 273 struct fmt_config config; 274 struct fmt_config try_config; 275 276 struct isc_ctrls ctrls; 277 struct work_struct awb_work; 278 279 struct mutex lock; /* serialize access to file operations */ 280 spinlock_t awb_lock; /* serialize access to DMA buffers from awb work queue */ 281 282 struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM]; 283 284 struct isc_subdev_entity *current_subdev; 285 struct list_head subdev_entities; 286 287 struct { 288 #define ISC_CTRL_DO_WB 1 289 #define ISC_CTRL_R_GAIN 2 290 #define ISC_CTRL_B_GAIN 3 291 #define ISC_CTRL_GR_GAIN 4 292 #define ISC_CTRL_GB_GAIN 5 293 #define ISC_CTRL_R_OFF 6 294 #define ISC_CTRL_B_OFF 7 295 #define ISC_CTRL_GR_OFF 8 296 #define ISC_CTRL_GB_OFF 9 297 struct v4l2_ctrl *awb_ctrl; 298 struct v4l2_ctrl *do_wb_ctrl; 299 struct v4l2_ctrl *r_gain_ctrl; 300 struct v4l2_ctrl *b_gain_ctrl; 301 struct v4l2_ctrl *gr_gain_ctrl; 302 struct v4l2_ctrl *gb_gain_ctrl; 303 struct v4l2_ctrl *r_off_ctrl; 304 struct v4l2_ctrl *b_off_ctrl; 305 struct v4l2_ctrl *gr_off_ctrl; 306 struct v4l2_ctrl *gb_off_ctrl; 307 }; 308 309 #define GAMMA_ENTRIES 64 310 /* pointer to the defined gamma table */ 311 const u32 (*gamma_table)[GAMMA_ENTRIES]; 312 u32 gamma_max; 313 314 u32 max_width; 315 u32 max_height; 316 317 struct { 318 void (*config_dpc)(struct isc_device *isc); 319 void (*config_csc)(struct isc_device *isc); 320 void (*config_cbc)(struct isc_device *isc); 321 void (*config_cc)(struct isc_device *isc); 322 void (*config_gam)(struct isc_device *isc); 323 void (*config_rlp)(struct isc_device *isc); 324 325 void (*config_ctrls)(struct isc_device *isc, 326 const struct v4l2_ctrl_ops *ops); 327 328 void (*adapt_pipeline)(struct isc_device *isc); 329 }; 330 331 struct isc_reg_offsets offsets; 332 const struct isc_format *controller_formats; 333 struct isc_format *formats_list; 334 u32 controller_formats_size; 335 u32 formats_list_size; 336 }; 337 338 extern const struct regmap_config isc_regmap_config; 339 extern const struct v4l2_async_notifier_operations isc_async_ops; 340 341 irqreturn_t isc_interrupt(int irq, void *dev_id); 342 int isc_pipeline_init(struct isc_device *isc); 343 int isc_clk_init(struct isc_device *isc); 344 void isc_subdev_cleanup(struct isc_device *isc); 345 void isc_clk_cleanup(struct isc_device *isc); 346 347 #endif 348
