1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77980 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15 #include <linux/errno.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18
19 #include "core.h"
20 #include "sh_pfc.h"
21
22 #define CPU_ALL_GP(fn, sfx) \
23 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
24 PORT_GP_28(1, fn, sfx), \
25 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_25(4, fn, sfx), \
28 PORT_GP_15(5, fn, sfx)
29
30 /*
31 * F_() : just information
32 * FM() : macro for FN_xxx / xxx_MARK
33 */
34
35 /* GPSR0 */
36 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
37 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
38 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
39 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
40 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
41 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
42 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
43 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
44 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
45 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
46 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
47 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
48 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
49 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
50 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
51 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
52 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
53 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
54 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
55 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
56 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
57 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
58
59 /* GPSR1 */
60 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
61 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
62 #define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
63 #define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
64 #define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
65 #define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
66 #define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
67 #define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
68 #define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
69 #define GPSR1_18 FM(AVB_LINK)
70 #define GPSR1_17 FM(AVB_PHY_INT)
71 #define GPSR1_16 FM(AVB_MAGIC)
72 #define GPSR1_15 FM(AVB_MDC)
73 #define GPSR1_14 FM(AVB_MDIO)
74 #define GPSR1_13 FM(AVB_TXCREFCLK)
75 #define GPSR1_12 FM(AVB_TD3)
76 #define GPSR1_11 FM(AVB_TD2)
77 #define GPSR1_10 FM(AVB_TD1)
78 #define GPSR1_9 FM(AVB_TD0)
79 #define GPSR1_8 FM(AVB_TXC)
80 #define GPSR1_7 FM(AVB_TX_CTL)
81 #define GPSR1_6 FM(AVB_RD3)
82 #define GPSR1_5 FM(AVB_RD2)
83 #define GPSR1_4 FM(AVB_RD1)
84 #define GPSR1_3 FM(AVB_RD0)
85 #define GPSR1_2 FM(AVB_RXC)
86 #define GPSR1_1 FM(AVB_RX_CTL)
87 #define GPSR1_0 F_(IRQ0, IP2_27_24)
88
89 /* GPSR2 */
90 #define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
91 #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
92 #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
93 #define GPSR2_26 F_(SDA3, IP10_7_4)
94 #define GPSR2_25 F_(SCL3, IP10_3_0)
95 #define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
96 #define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
97 #define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
98 #define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
99 #define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
100 #define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
101 #define GPSR2_18 F_(IRQ5, IP9_7_4)
102 #define GPSR2_17 F_(IRQ4, IP9_3_0)
103 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
104 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
105 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
106 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
107 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
108 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
109 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
110 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
111 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
112 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
113 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
114 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
115 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
116 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
117 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
118 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
119 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
120
121 /* GPSR3 */
122 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
123 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
124 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
125 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
126 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
127 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
128 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
129 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
130 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
131 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
132 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
133 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
134 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
135 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
136 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
137 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
138 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
139
140 /* GPSR4 */
141 #define GPSR4_24 FM(GETHER_LINK_A)
142 #define GPSR4_23 FM(GETHER_PHY_INT_A)
143 #define GPSR4_22 FM(GETHER_MAGIC)
144 #define GPSR4_21 FM(GETHER_MDC_A)
145 #define GPSR4_20 FM(GETHER_MDIO_A)
146 #define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
147 #define GPSR4_18 FM(GETHER_TXCREFCLK)
148 #define GPSR4_17 FM(GETHER_TD3)
149 #define GPSR4_16 FM(GETHER_TD2)
150 #define GPSR4_15 FM(GETHER_TD1)
151 #define GPSR4_14 FM(GETHER_TD0)
152 #define GPSR4_13 FM(GETHER_TXC)
153 #define GPSR4_12 FM(GETHER_TX_CTL)
154 #define GPSR4_11 FM(GETHER_RD3)
155 #define GPSR4_10 FM(GETHER_RD2)
156 #define GPSR4_9 FM(GETHER_RD1)
157 #define GPSR4_8 FM(GETHER_RD0)
158 #define GPSR4_7 FM(GETHER_RXC)
159 #define GPSR4_6 FM(GETHER_RX_CTL)
160 #define GPSR4_5 F_(SDA2, IP7_27_24)
161 #define GPSR4_4 F_(SCL2, IP7_23_20)
162 #define GPSR4_3 F_(SDA1, IP7_19_16)
163 #define GPSR4_2 F_(SCL1, IP7_15_12)
164 #define GPSR4_1 F_(SDA0, IP7_11_8)
165 #define GPSR4_0 F_(SCL0, IP7_7_4)
166
167 /* GPSR5 */
168 #define GPSR5_14 FM(RPC_INT_N)
169 #define GPSR5_13 FM(RPC_WP_N)
170 #define GPSR5_12 FM(RPC_RESET_N)
171 #define GPSR5_11 FM(QSPI1_SSL)
172 #define GPSR5_10 FM(QSPI1_IO3)
173 #define GPSR5_9 FM(QSPI1_IO2)
174 #define GPSR5_8 FM(QSPI1_MISO_IO1)
175 #define GPSR5_7 FM(QSPI1_MOSI_IO0)
176 #define GPSR5_6 FM(QSPI1_SPCLK)
177 #define GPSR5_5 FM(QSPI0_SSL)
178 #define GPSR5_4 FM(QSPI0_IO3)
179 #define GPSR5_3 FM(QSPI0_IO2)
180 #define GPSR5_2 FM(QSPI0_MISO_IO1)
181 #define GPSR5_1 FM(QSPI0_MOSI_IO0)
182 #define GPSR5_0 FM(QSPI0_SPCLK)
183
184
185 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
186 #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187 #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188 #define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189 #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275 #define PINMUX_GPSR \
276 \
277 GPSR2_29 \
278 GPSR2_28 \
279 GPSR1_27 GPSR2_27 \
280 GPSR1_26 GPSR2_26 \
281 GPSR1_25 GPSR2_25 \
282 GPSR1_24 GPSR2_24 GPSR4_24 \
283 GPSR1_23 GPSR2_23 GPSR4_23 \
284 GPSR1_22 GPSR2_22 GPSR4_22 \
285 GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
286 GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
287 GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
288 GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
289 GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
290 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
291 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
292 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
293 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
294 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
295 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
296 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
297 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
298 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
299 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
300 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
301 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
302 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
303 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
304 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
305 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
306 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
307
308 #define PINMUX_IPSR \
309 \
310 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
311 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
312 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
313 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
314 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
315 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
316 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
317 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
318 \
319 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
320 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
321 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
322 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
323 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
324 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
325 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
326 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
327 \
328 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
329 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
330 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
331 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
332 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
333 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \
334 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \
335 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28
336
337 /* MOD_SEL0 */ /* 0 */ /* 1 */
338 #define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
339 #define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
340 #define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
341 #define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
342 #define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
343 #define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
344 #define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
345 #define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
346 #define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
347 #define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
348 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
349
350 #define PINMUX_MOD_SELS \
351 \
352 MOD_SEL0_11 \
353 MOD_SEL0_10 \
354 MOD_SEL0_9 \
355 MOD_SEL0_8 \
356 MOD_SEL0_7 \
357 MOD_SEL0_6 \
358 MOD_SEL0_5 \
359 MOD_SEL0_4 \
360 MOD_SEL0_2 \
361 MOD_SEL0_1 \
362 MOD_SEL0_0
363
364 enum {
365 PINMUX_RESERVED = 0,
366
367 PINMUX_DATA_BEGIN,
368 GP_ALL(DATA),
369 PINMUX_DATA_END,
370
371 #define F_(x, y)
372 #define FM(x) FN_##x,
373 PINMUX_FUNCTION_BEGIN,
374 GP_ALL(FN),
375 PINMUX_GPSR
376 PINMUX_IPSR
377 PINMUX_MOD_SELS
378 PINMUX_FUNCTION_END,
379 #undef F_
380 #undef FM
381
382 #define F_(x, y)
383 #define FM(x) x##_MARK,
384 PINMUX_MARK_BEGIN,
385 PINMUX_GPSR
386 PINMUX_IPSR
387 PINMUX_MOD_SELS
388 PINMUX_MARK_END,
389 #undef F_
390 #undef FM
391 };
392
393 static const u16 pinmux_data[] = {
394 PINMUX_DATA_GP_ALL(),
395
396 PINMUX_SINGLE(AVB_RX_CTL),
397 PINMUX_SINGLE(AVB_RXC),
398 PINMUX_SINGLE(AVB_RD0),
399 PINMUX_SINGLE(AVB_RD1),
400 PINMUX_SINGLE(AVB_RD2),
401 PINMUX_SINGLE(AVB_RD3),
402 PINMUX_SINGLE(AVB_TX_CTL),
403 PINMUX_SINGLE(AVB_TXC),
404 PINMUX_SINGLE(AVB_TD0),
405 PINMUX_SINGLE(AVB_TD1),
406 PINMUX_SINGLE(AVB_TD2),
407 PINMUX_SINGLE(AVB_TD3),
408 PINMUX_SINGLE(AVB_TXCREFCLK),
409 PINMUX_SINGLE(AVB_MDIO),
410 PINMUX_SINGLE(AVB_MDC),
411 PINMUX_SINGLE(AVB_MAGIC),
412 PINMUX_SINGLE(AVB_PHY_INT),
413 PINMUX_SINGLE(AVB_LINK),
414
415 PINMUX_SINGLE(GETHER_RX_CTL),
416 PINMUX_SINGLE(GETHER_RXC),
417 PINMUX_SINGLE(GETHER_RD0),
418 PINMUX_SINGLE(GETHER_RD1),
419 PINMUX_SINGLE(GETHER_RD2),
420 PINMUX_SINGLE(GETHER_RD3),
421 PINMUX_SINGLE(GETHER_TX_CTL),
422 PINMUX_SINGLE(GETHER_TXC),
423 PINMUX_SINGLE(GETHER_TD0),
424 PINMUX_SINGLE(GETHER_TD1),
425 PINMUX_SINGLE(GETHER_TD2),
426 PINMUX_SINGLE(GETHER_TD3),
427 PINMUX_SINGLE(GETHER_TXCREFCLK),
428 PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
429 PINMUX_SINGLE(GETHER_MDIO_A),
430 PINMUX_SINGLE(GETHER_MDC_A),
431 PINMUX_SINGLE(GETHER_MAGIC),
432 PINMUX_SINGLE(GETHER_PHY_INT_A),
433 PINMUX_SINGLE(GETHER_LINK_A),
434
435 PINMUX_SINGLE(QSPI0_SPCLK),
436 PINMUX_SINGLE(QSPI0_MOSI_IO0),
437 PINMUX_SINGLE(QSPI0_MISO_IO1),
438 PINMUX_SINGLE(QSPI0_IO2),
439 PINMUX_SINGLE(QSPI0_IO3),
440 PINMUX_SINGLE(QSPI0_SSL),
441 PINMUX_SINGLE(QSPI1_SPCLK),
442 PINMUX_SINGLE(QSPI1_MOSI_IO0),
443 PINMUX_SINGLE(QSPI1_MISO_IO1),
444 PINMUX_SINGLE(QSPI1_IO2),
445 PINMUX_SINGLE(QSPI1_IO3),
446 PINMUX_SINGLE(QSPI1_SSL),
447 PINMUX_SINGLE(RPC_RESET_N),
448 PINMUX_SINGLE(RPC_WP_N),
449 PINMUX_SINGLE(RPC_INT_N),
450
451 /* IPSR0 */
452 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
453 PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
454 PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
455 PINMUX_IPSR_GPSR(IP0_3_0, A0),
456
457 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
458 PINMUX_IPSR_GPSR(IP0_7_4, RX4),
459 PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
460 PINMUX_IPSR_GPSR(IP0_7_4, A1),
461
462 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
463 PINMUX_IPSR_GPSR(IP0_11_8, TX4),
464 PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
465 PINMUX_IPSR_GPSR(IP0_11_8, A2),
466
467 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
468 PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
469 PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
470 PINMUX_IPSR_GPSR(IP0_15_12, A3),
471
472 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
473 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
474 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
475 PINMUX_IPSR_GPSR(IP0_19_16, A4),
476
477 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
478 PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
479 PINMUX_IPSR_GPSR(IP0_23_20, A5),
480
481 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
482 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
483 PINMUX_IPSR_GPSR(IP0_27_24, A6),
484
485 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
486 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
487 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
488 PINMUX_IPSR_GPSR(IP0_31_28, A7),
489 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
490
491 /* IPSR1 */
492 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
493 PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
494 PINMUX_IPSR_GPSR(IP1_3_0, A8),
495
496 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
497 PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
498 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
499 PINMUX_IPSR_GPSR(IP1_7_4, A9),
500
501 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
502 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
503 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
504 PINMUX_IPSR_GPSR(IP1_11_8, A10),
505
506 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
507 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
508 PINMUX_IPSR_GPSR(IP1_15_12, A11),
509
510 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
511 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
512 PINMUX_IPSR_GPSR(IP1_19_16, A12),
513 PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
514
515 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
516 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
517 PINMUX_IPSR_GPSR(IP1_23_20, A13),
518 PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
519
520 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
521 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
522 PINMUX_IPSR_GPSR(IP1_27_24, A14),
523 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
524
525 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
526 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
527 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
528 PINMUX_IPSR_GPSR(IP1_31_28, A15),
529
530 /* IPSR2 */
531 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
532 PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
533 PINMUX_IPSR_GPSR(IP2_3_0, A16),
534
535 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
536 PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
537 PINMUX_IPSR_GPSR(IP2_7_4, A17),
538
539 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
540 PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
541 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
542 PINMUX_IPSR_GPSR(IP2_11_8, A18),
543
544 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
545 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
546 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
547 PINMUX_IPSR_GPSR(IP2_15_12, A19),
548 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
549
550 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
551 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
552 PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
553
554 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
555 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
556
557 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
558
559 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
560 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
561 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
562 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
563
564 /* IPSR3 */
565 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
566 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
567 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
568 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
569 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
570
571 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
572 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
573 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
574 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
575
576 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
577 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
578 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
579 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
580
581 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
582 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
583 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
584 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
585
586 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
587 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
588 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
589 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
590
591 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
592 PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
593
594 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
595 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
596
597 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
598 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
599 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
600
601 /* IPSR4 */
602 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
603 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
604 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
605
606 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
607 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
608 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
609
610 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
611 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
612 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
613
614 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
615 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
616
617 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
618 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
619 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
620
621 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
622 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
623 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
624
625 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
626 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
627 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
628
629 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
630 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
631 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
632 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
633
634 /* IPSR5 */
635 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
636 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
637 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
638
639 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
640 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
641 PINMUX_IPSR_GPSR(IP5_7_4, D0),
642
643 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
644 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
645 PINMUX_IPSR_GPSR(IP5_11_8, D1),
646
647 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
648 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
649 PINMUX_IPSR_GPSR(IP5_15_12, D2),
650
651 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
652 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
653 PINMUX_IPSR_GPSR(IP5_19_16, D3),
654 PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
655
656 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
657 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
658 PINMUX_IPSR_GPSR(IP5_23_20, D4),
659 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
660
661 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
662 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
663 PINMUX_IPSR_GPSR(IP5_27_24, D5),
664 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
665
666 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
667 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
668 PINMUX_IPSR_GPSR(IP5_31_28, D6),
669 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
670
671 /* IPSR6 */
672 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
673 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
674 PINMUX_IPSR_GPSR(IP6_3_0, D7),
675 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
676
677 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
678 PINMUX_IPSR_GPSR(IP6_7_4, D8),
679 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
680
681 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
682 PINMUX_IPSR_GPSR(IP6_11_8, D9),
683 PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
684
685 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
686 PINMUX_IPSR_GPSR(IP6_15_12, D10),
687 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
688
689 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
690 PINMUX_IPSR_GPSR(IP6_19_16, D11),
691 PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
692
693 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
694 PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
695 PINMUX_IPSR_GPSR(IP6_23_20, D12),
696 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
697
698 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
699 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
700 PINMUX_IPSR_GPSR(IP6_27_24, D13),
701 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
702
703 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
704 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
705 PINMUX_IPSR_GPSR(IP6_31_28, D14),
706 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
707
708 /* IPSR7 */
709 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
710 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
711 PINMUX_IPSR_GPSR(IP7_3_0, D15),
712 PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
713
714 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
715 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
716
717 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
718 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
719 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
720 PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
721
722 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
723 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
724 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
725 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
726 PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
727
728 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
729 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
730 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
731 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
732 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
733
734 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
735 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
736 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
737 PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
738
739 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
740 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
741 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
742 PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
743
744 PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
745 PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
746
747 /* IPSR8 */
748 PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
749 PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
750
751 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
752 PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
753 PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
754 PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
755
756 PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
757 PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
758 PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
759 PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
760
761 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
762 PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
763 PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
764 PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
765 PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
766
767 PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
768 PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
769 PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
770 PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
771 PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
772
773 PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
774 PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
775 PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
776 PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
777 PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
778
779 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
780 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
781
782 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
783 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
784
785 /* IPSR9 */
786 PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
787 PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
788
789 PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
790 PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
791
792 PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
793 PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
794 PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
795
796 PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
797 PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
798 PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
799
800 PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
801 PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
802 PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
803
804 PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
805 PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
806 PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
807
808 PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
809 PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
810 PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
811 PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
812
813 PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
814 PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
815 PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
816 PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
817
818 /* IPSR10 */
819 PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
820 PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
821
822 PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
823 PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
824
825 PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
826 PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
827
828 PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
829 PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
830
831 PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
832 };
833
834 static const struct sh_pfc_pin pinmux_pins[] = {
835 PINMUX_GPIO_GP_ALL(),
836 };
837
838 /* - AVB -------------------------------------------------------------------- */
839 static const unsigned int avb_link_pins[] = {
840 /* AVB_LINK */
841 RCAR_GP_PIN(1, 18),
842 };
843 static const unsigned int avb_link_mux[] = {
844 AVB_LINK_MARK,
845 };
846 static const unsigned int avb_magic_pins[] = {
847 /* AVB_MAGIC */
848 RCAR_GP_PIN(1, 16),
849 };
850 static const unsigned int avb_magic_mux[] = {
851 AVB_MAGIC_MARK,
852 };
853 static const unsigned int avb_phy_int_pins[] = {
854 /* AVB_PHY_INT */
855 RCAR_GP_PIN(1, 17),
856 };
857 static const unsigned int avb_phy_int_mux[] = {
858 AVB_PHY_INT_MARK,
859 };
860 static const unsigned int avb_mdio_pins[] = {
861 /* AVB_MDC, AVB_MDIO */
862 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
863 };
864 static const unsigned int avb_mdio_mux[] = {
865 AVB_MDC_MARK, AVB_MDIO_MARK,
866 };
867 static const unsigned int avb_rgmii_pins[] = {
868 /*
869 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
870 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
871 */
872 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
873 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
874 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
875 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
876 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
877 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
878 };
879 static const unsigned int avb_rgmii_mux[] = {
880 AVB_TX_CTL_MARK, AVB_TXC_MARK,
881 AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
882 AVB_RX_CTL_MARK, AVB_RXC_MARK,
883 AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
884 };
885 static const unsigned int avb_txcrefclk_pins[] = {
886 /* AVB_TXCREFCLK */
887 RCAR_GP_PIN(1, 13),
888 };
889 static const unsigned int avb_txcrefclk_mux[] = {
890 AVB_TXCREFCLK_MARK,
891 };
892 static const unsigned int avb_avtp_pps_pins[] = {
893 /* AVB_AVTP_PPS */
894 RCAR_GP_PIN(2, 6),
895 };
896 static const unsigned int avb_avtp_pps_mux[] = {
897 AVB_AVTP_PPS_MARK,
898 };
899 static const unsigned int avb_avtp_capture_pins[] = {
900 /* AVB_AVTP_CAPTURE */
901 RCAR_GP_PIN(1, 20),
902 };
903 static const unsigned int avb_avtp_capture_mux[] = {
904 AVB_AVTP_CAPTURE_MARK,
905 };
906 static const unsigned int avb_avtp_match_pins[] = {
907 /* AVB_AVTP_MATCH */
908 RCAR_GP_PIN(1, 19),
909 };
910 static const unsigned int avb_avtp_match_mux[] = {
911 AVB_AVTP_MATCH_MARK,
912 };
913
914 /* - CANFD0 ----------------------------------------------------------------- */
915 static const unsigned int canfd0_data_a_pins[] = {
916 /* CANFD0_TX, CANFD0_RX */
917 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
918 };
919 static const unsigned int canfd0_data_a_mux[] = {
920 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
921 };
922 static const unsigned int canfd0_data_b_pins[] = {
923 /* CANFD0_TX, CANFD0_RX */
924 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
925 };
926 static const unsigned int canfd0_data_b_mux[] = {
927 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
928 };
929
930 /* - CANFD1 ----------------------------------------------------------------- */
931 static const unsigned int canfd1_data_pins[] = {
932 /* CANFD1_TX, CANFD1_RX */
933 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
934 };
935 static const unsigned int canfd1_data_mux[] = {
936 CANFD1_TX_MARK, CANFD1_RX_MARK,
937 };
938
939 /* - CANFD Clock ------------------------------------------------------------ */
940 static const unsigned int canfd_clk_a_pins[] = {
941 /* CANFD_CLK */
942 RCAR_GP_PIN(1, 25),
943 };
944 static const unsigned int canfd_clk_a_mux[] = {
945 CANFD_CLK_A_MARK,
946 };
947 static const unsigned int canfd_clk_b_pins[] = {
948 /* CANFD_CLK */
949 RCAR_GP_PIN(3, 8),
950 };
951 static const unsigned int canfd_clk_b_mux[] = {
952 CANFD_CLK_B_MARK,
953 };
954
955 /* - DU --------------------------------------------------------------------- */
956 static const unsigned int du_rgb666_pins[] = {
957 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
958 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
959 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
960 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
961 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
962 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
963 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
964 };
965 static const unsigned int du_rgb666_mux[] = {
966 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
967 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
968 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
969 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
970 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
971 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
972 };
973 static const unsigned int du_rgb888_pins[] = {
974 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
975 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
976 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
977 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
978 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
979 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
980 RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
981 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
982 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
983 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
984 };
985 static const unsigned int du_rgb888_mux[] = {
986 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
987 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
988 DU_DR1_MARK, DU_DR0_MARK,
989 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
990 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
991 DU_DG1_MARK, DU_DG0_MARK,
992 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
993 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
994 DU_DB1_MARK, DU_DB0_MARK,
995 };
996 static const unsigned int du_clk_out_pins[] = {
997 /* DU_DOTCLKOUT */
998 RCAR_GP_PIN(0, 18),
999 };
1000 static const unsigned int du_clk_out_mux[] = {
1001 DU_DOTCLKOUT_MARK,
1002 };
1003 static const unsigned int du_sync_pins[] = {
1004 /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
1005 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1006 };
1007 static const unsigned int du_sync_mux[] = {
1008 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1009 };
1010 static const unsigned int du_oddf_pins[] = {
1011 /* DU_EXODDF/DU_ODDF/DISP/CDE */
1012 RCAR_GP_PIN(0, 21),
1013 };
1014 static const unsigned int du_oddf_mux[] = {
1015 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1016 };
1017 static const unsigned int du_cde_pins[] = {
1018 /* DU_CDE */
1019 RCAR_GP_PIN(1, 22),
1020 };
1021 static const unsigned int du_cde_mux[] = {
1022 DU_CDE_MARK,
1023 };
1024 static const unsigned int du_disp_pins[] = {
1025 /* DU_DISP */
1026 RCAR_GP_PIN(1, 21),
1027 };
1028 static const unsigned int du_disp_mux[] = {
1029 DU_DISP_MARK,
1030 };
1031
1032 /* - GETHER ----------------------------------------------------------------- */
1033 static const unsigned int gether_link_a_pins[] = {
1034 /* GETHER_LINK */
1035 RCAR_GP_PIN(4, 24),
1036 };
1037 static const unsigned int gether_link_a_mux[] = {
1038 GETHER_LINK_A_MARK,
1039 };
1040 static const unsigned int gether_phy_int_a_pins[] = {
1041 /* GETHER_PHY_INT */
1042 RCAR_GP_PIN(4, 23),
1043 };
1044 static const unsigned int gether_phy_int_a_mux[] = {
1045 GETHER_PHY_INT_A_MARK,
1046 };
1047 static const unsigned int gether_mdio_a_pins[] = {
1048 /* GETHER_MDC, GETHER_MDIO */
1049 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1050 };
1051 static const unsigned int gether_mdio_a_mux[] = {
1052 GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
1053 };
1054 static const unsigned int gether_link_b_pins[] = {
1055 /* GETHER_LINK */
1056 RCAR_GP_PIN(0, 18),
1057 };
1058 static const unsigned int gether_link_b_mux[] = {
1059 GETHER_LINK_B_MARK,
1060 };
1061 static const unsigned int gether_phy_int_b_pins[] = {
1062 /* GETHER_PHY_INT */
1063 RCAR_GP_PIN(0, 19),
1064 };
1065 static const unsigned int gether_phy_int_b_mux[] = {
1066 GETHER_PHY_INT_B_MARK,
1067 };
1068 static const unsigned int gether_mdio_b_mux[] = {
1069 GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
1070 };
1071 static const unsigned int gether_mdio_b_pins[] = {
1072 /* GETHER_MDC, GETHER_MDIO */
1073 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1074 };
1075 static const unsigned int gether_magic_pins[] = {
1076 /* GETHER_MAGIC */
1077 RCAR_GP_PIN(4, 22),
1078 };
1079 static const unsigned int gether_magic_mux[] = {
1080 GETHER_MAGIC_MARK,
1081 };
1082 static const unsigned int gether_rgmii_pins[] = {
1083 /*
1084 * GETHER_TX_CTL, GETHER_TXC,
1085 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
1086 * GETHER_RX_CTL, GETHER_RXC,
1087 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
1088 */
1089 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1090 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1091 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1092 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1093 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1094 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1095 };
1096 static const unsigned int gether_rgmii_mux[] = {
1097 GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
1098 GETHER_TD0_MARK, GETHER_TD1_MARK,
1099 GETHER_TD2_MARK, GETHER_TD3_MARK,
1100 GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
1101 GETHER_RD0_MARK, AVB_RD1_MARK,
1102 GETHER_RD2_MARK, AVB_RD3_MARK,
1103 };
1104 static const unsigned int gether_txcrefclk_pins[] = {
1105 /* GETHER_TXCREFCLK */
1106 RCAR_GP_PIN(4, 18),
1107 };
1108 static const unsigned int gether_txcrefclk_mux[] = {
1109 GETHER_TXCREFCLK_MARK,
1110 };
1111 static const unsigned int gether_txcrefclk_mega_pins[] = {
1112 /* GETHER_TXCREFCLK_MEGA */
1113 RCAR_GP_PIN(4, 19),
1114 };
1115 static const unsigned int gether_txcrefclk_mega_mux[] = {
1116 GETHER_TXCREFCLK_MEGA_MARK,
1117 };
1118 static const unsigned int gether_rmii_pins[] = {
1119 /*
1120 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
1121 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
1122 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
1123 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
1124 */
1125 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1126 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1127 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1128 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
1129 };
1130 static const unsigned int gether_rmii_mux[] = {
1131 GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
1132 GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
1133 GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
1134 GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
1135 };
1136
1137 /* - HSCIF0 ----------------------------------------------------------------- */
1138 static const unsigned int hscif0_data_a_pins[] = {
1139 /* HRX0, HTX0 */
1140 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
1141 };
1142 static const unsigned int hscif0_data_a_mux[] = {
1143 HRX0_A_MARK, HTX0_A_MARK,
1144 };
1145 static const unsigned int hscif0_clk_a_pins[] = {
1146 /* HSCK0 */
1147 RCAR_GP_PIN(0, 12),
1148 };
1149 static const unsigned int hscif0_clk_a_mux[] = {
1150 HSCK0_A_MARK,
1151 };
1152 static const unsigned int hscif0_ctrl_a_pins[] = {
1153 /* HRTS0#, HCTS0# */
1154 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1155 };
1156 static const unsigned int hscif0_ctrl_a_mux[] = {
1157 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1158 };
1159 static const unsigned int hscif0_data_b_pins[] = {
1160 /* HRX0, HTX0 */
1161 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1162 };
1163 static const unsigned int hscif0_data_b_mux[] = {
1164 HRX0_B_MARK, HTX0_B_MARK,
1165 };
1166 static const unsigned int hscif0_clk_b_pins[] = {
1167 /* HSCK0 */
1168 RCAR_GP_PIN(4, 1),
1169 };
1170 static const unsigned int hscif0_clk_b_mux[] = {
1171 HSCK0_B_MARK,
1172 };
1173 static const unsigned int hscif0_ctrl_b_pins[] = {
1174 /* HRTS0#, HCTS0# */
1175 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1176 };
1177 static const unsigned int hscif0_ctrl_b_mux[] = {
1178 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1179 };
1180
1181 /* - HSCIF1 ----------------------------------------------------------------- */
1182 static const unsigned int hscif1_data_pins[] = {
1183 /* HRX1, HTX1 */
1184 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1185 };
1186 static const unsigned int hscif1_data_mux[] = {
1187 HRX1_MARK, HTX1_MARK,
1188 };
1189 static const unsigned int hscif1_clk_pins[] = {
1190 /* HSCK1 */
1191 RCAR_GP_PIN(2, 7),
1192 };
1193 static const unsigned int hscif1_clk_mux[] = {
1194 HSCK1_MARK,
1195 };
1196 static const unsigned int hscif1_ctrl_pins[] = {
1197 /* HRTS1#, HCTS1# */
1198 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1199 };
1200 static const unsigned int hscif1_ctrl_mux[] = {
1201 HRTS1_N_MARK, HCTS1_N_MARK,
1202 };
1203
1204 /* - HSCIF2 ----------------------------------------------------------------- */
1205 static const unsigned int hscif2_data_pins[] = {
1206 /* HRX2, HTX2 */
1207 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1208 };
1209 static const unsigned int hscif2_data_mux[] = {
1210 HRX2_MARK, HTX2_MARK,
1211 };
1212 static const unsigned int hscif2_clk_pins[] = {
1213 /* HSCK2 */
1214 RCAR_GP_PIN(2, 12),
1215 };
1216 static const unsigned int hscif2_clk_mux[] = {
1217 HSCK2_MARK,
1218 };
1219 static const unsigned int hscif2_ctrl_pins[] = {
1220 /* HRTS2#, HCTS2# */
1221 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1222 };
1223 static const unsigned int hscif2_ctrl_mux[] = {
1224 HRTS2_N_MARK, HCTS2_N_MARK,
1225 };
1226
1227 /* - HSCIF3 ----------------------------------------------------------------- */
1228 static const unsigned int hscif3_data_pins[] = {
1229 /* HRX3, HTX3 */
1230 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1231 };
1232 static const unsigned int hscif3_data_mux[] = {
1233 HRX3_MARK, HTX3_MARK,
1234 };
1235 static const unsigned int hscif3_clk_pins[] = {
1236 /* HSCK3 */
1237 RCAR_GP_PIN(2, 0),
1238 };
1239 static const unsigned int hscif3_clk_mux[] = {
1240 HSCK3_MARK,
1241 };
1242 static const unsigned int hscif3_ctrl_pins[] = {
1243 /* HRTS3#, HCTS3# */
1244 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1245 };
1246 static const unsigned int hscif3_ctrl_mux[] = {
1247 HRTS3_N_MARK, HCTS3_N_MARK,
1248 };
1249
1250 /* - I2C0 ------------------------------------------------------------------- */
1251 static const unsigned int i2c0_pins[] = {
1252 /* SDA0, SCL0 */
1253 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1254 };
1255 static const unsigned int i2c0_mux[] = {
1256 SDA0_MARK, SCL0_MARK,
1257 };
1258
1259 /* - I2C1 ------------------------------------------------------------------- */
1260 static const unsigned int i2c1_pins[] = {
1261 /* SDA1, SCL1 */
1262 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1263 };
1264 static const unsigned int i2c1_mux[] = {
1265 SDA1_MARK, SCL1_MARK,
1266 };
1267
1268 /* - I2C2 ------------------------------------------------------------------- */
1269 static const unsigned int i2c2_pins[] = {
1270 /* SDA2, SCL2 */
1271 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1272 };
1273 static const unsigned int i2c2_mux[] = {
1274 SDA2_MARK, SCL2_MARK,
1275 };
1276
1277 /* - I2C3 ------------------------------------------------------------------- */
1278 static const unsigned int i2c3_pins[] = {
1279 /* SDA3, SCL3 */
1280 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1281 };
1282 static const unsigned int i2c3_mux[] = {
1283 SDA3_MARK, SCL3_MARK,
1284 };
1285
1286 /* - I2C4 ------------------------------------------------------------------- */
1287 static const unsigned int i2c4_pins[] = {
1288 /* SDA4, SCL4 */
1289 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1290 };
1291 static const unsigned int i2c4_mux[] = {
1292 SDA4_MARK, SCL4_MARK,
1293 };
1294
1295 /* - I2C5 ------------------------------------------------------------------- */
1296 static const unsigned int i2c5_pins[] = {
1297 /* SDA5, SCL5 */
1298 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1299 };
1300 static const unsigned int i2c5_mux[] = {
1301 SDA5_MARK, SCL5_MARK,
1302 };
1303
1304 /* - INTC-EX ---------------------------------------------------------------- */
1305 static const unsigned int intc_ex_irq0_pins[] = {
1306 /* IRQ0 */
1307 RCAR_GP_PIN(1, 0),
1308 };
1309 static const unsigned int intc_ex_irq0_mux[] = {
1310 IRQ0_MARK,
1311 };
1312 static const unsigned int intc_ex_irq1_pins[] = {
1313 /* IRQ1 */
1314 RCAR_GP_PIN(0, 12),
1315 };
1316 static const unsigned int intc_ex_irq1_mux[] = {
1317 IRQ1_MARK,
1318 };
1319 static const unsigned int intc_ex_irq2_pins[] = {
1320 /* IRQ2 */
1321 RCAR_GP_PIN(0, 13),
1322 };
1323 static const unsigned int intc_ex_irq2_mux[] = {
1324 IRQ2_MARK,
1325 };
1326 static const unsigned int intc_ex_irq3_pins[] = {
1327 /* IRQ3 */
1328 RCAR_GP_PIN(0, 14),
1329 };
1330 static const unsigned int intc_ex_irq3_mux[] = {
1331 IRQ3_MARK,
1332 };
1333 static const unsigned int intc_ex_irq4_pins[] = {
1334 /* IRQ4 */
1335 RCAR_GP_PIN(2, 17),
1336 };
1337 static const unsigned int intc_ex_irq4_mux[] = {
1338 IRQ4_MARK,
1339 };
1340 static const unsigned int intc_ex_irq5_pins[] = {
1341 /* IRQ5 */
1342 RCAR_GP_PIN(2, 18),
1343 };
1344 static const unsigned int intc_ex_irq5_mux[] = {
1345 IRQ5_MARK,
1346 };
1347
1348 /* - MMC -------------------------------------------------------------------- */
1349 static const unsigned int mmc_data1_pins[] = {
1350 /* MMC_D0 */
1351 RCAR_GP_PIN(3, 8),
1352 };
1353 static const unsigned int mmc_data1_mux[] = {
1354 MMC_D0_MARK,
1355 };
1356 static const unsigned int mmc_data4_pins[] = {
1357 /* MMC_D[0:3] */
1358 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1359 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1360 };
1361 static const unsigned int mmc_data4_mux[] = {
1362 MMC_D0_MARK, MMC_D1_MARK,
1363 MMC_D2_MARK, MMC_D3_MARK,
1364 };
1365 static const unsigned int mmc_data8_pins[] = {
1366 /* MMC_D[0:7] */
1367 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1368 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1369 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1370 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1371 };
1372 static const unsigned int mmc_data8_mux[] = {
1373 MMC_D0_MARK, MMC_D1_MARK,
1374 MMC_D2_MARK, MMC_D3_MARK,
1375 MMC_D4_MARK, MMC_D5_MARK,
1376 MMC_D6_MARK, MMC_D7_MARK,
1377 };
1378 static const unsigned int mmc_ctrl_pins[] = {
1379 /* MMC_CLK, MMC_CMD */
1380 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
1381 };
1382 static const unsigned int mmc_ctrl_mux[] = {
1383 MMC_CLK_MARK, MMC_CMD_MARK,
1384 };
1385 static const unsigned int mmc_cd_pins[] = {
1386 /* MMC_CD */
1387 RCAR_GP_PIN(3, 5),
1388 };
1389 static const unsigned int mmc_cd_mux[] = {
1390 MMC_CD_MARK,
1391 };
1392 static const unsigned int mmc_wp_pins[] = {
1393 /* MMC_WP */
1394 RCAR_GP_PIN(3, 4),
1395 };
1396 static const unsigned int mmc_wp_mux[] = {
1397 MMC_WP_MARK,
1398 };
1399 static const unsigned int mmc_ds_pins[] = {
1400 /* MMC_DS */
1401 RCAR_GP_PIN(3, 6),
1402 };
1403 static const unsigned int mmc_ds_mux[] = {
1404 MMC_DS_MARK,
1405 };
1406
1407 /* - MSIOF0 ----------------------------------------------------------------- */
1408 static const unsigned int msiof0_clk_pins[] = {
1409 /* MSIOF0_SCK */
1410 RCAR_GP_PIN(2, 21),
1411 };
1412 static const unsigned int msiof0_clk_mux[] = {
1413 MSIOF0_SCK_MARK,
1414 };
1415 static const unsigned int msiof0_sync_pins[] = {
1416 /* MSIOF0_SYNC */
1417 RCAR_GP_PIN(2, 22),
1418 };
1419 static const unsigned int msiof0_sync_mux[] = {
1420 MSIOF0_SYNC_MARK,
1421 };
1422 static const unsigned int msiof0_ss1_pins[] = {
1423 /* MSIOF0_SS1 */
1424 RCAR_GP_PIN(2, 23),
1425 };
1426 static const unsigned int msiof0_ss1_mux[] = {
1427 MSIOF0_SS1_MARK,
1428 };
1429 static const unsigned int msiof0_ss2_pins[] = {
1430 /* MSIOF0_SS2 */
1431 RCAR_GP_PIN(2, 24),
1432 };
1433 static const unsigned int msiof0_ss2_mux[] = {
1434 MSIOF0_SS2_MARK,
1435 };
1436 static const unsigned int msiof0_txd_pins[] = {
1437 /* MSIOF0_TXD */
1438 RCAR_GP_PIN(2, 20),
1439 };
1440 static const unsigned int msiof0_txd_mux[] = {
1441 MSIOF0_TXD_MARK,
1442 };
1443 static const unsigned int msiof0_rxd_pins[] = {
1444 /* MSIOF0_RXD */
1445 RCAR_GP_PIN(2, 19),
1446 };
1447 static const unsigned int msiof0_rxd_mux[] = {
1448 MSIOF0_RXD_MARK,
1449 };
1450
1451 /* - MSIOF1 ----------------------------------------------------------------- */
1452 static const unsigned int msiof1_clk_pins[] = {
1453 /* MSIOF1_SCK */
1454 RCAR_GP_PIN(3, 2),
1455 };
1456 static const unsigned int msiof1_clk_mux[] = {
1457 MSIOF1_SCK_MARK,
1458 };
1459 static const unsigned int msiof1_sync_pins[] = {
1460 /* MSIOF1_SYNC */
1461 RCAR_GP_PIN(3, 3),
1462 };
1463 static const unsigned int msiof1_sync_mux[] = {
1464 MSIOF1_SYNC_MARK,
1465 };
1466 static const unsigned int msiof1_ss1_pins[] = {
1467 /* MSIOF1_SS1 */
1468 RCAR_GP_PIN(3, 4),
1469 };
1470 static const unsigned int msiof1_ss1_mux[] = {
1471 MSIOF1_SS1_MARK,
1472 };
1473 static const unsigned int msiof1_ss2_pins[] = {
1474 /* MSIOF1_SS2 */
1475 RCAR_GP_PIN(3, 5),
1476 };
1477 static const unsigned int msiof1_ss2_mux[] = {
1478 MSIOF1_SS2_MARK,
1479 };
1480 static const unsigned int msiof1_txd_pins[] = {
1481 /* MSIOF1_TXD */
1482 RCAR_GP_PIN(3, 1),
1483 };
1484 static const unsigned int msiof1_txd_mux[] = {
1485 MSIOF1_TXD_MARK,
1486 };
1487 static const unsigned int msiof1_rxd_pins[] = {
1488 /* MSIOF1_RXD */
1489 RCAR_GP_PIN(3, 0),
1490 };
1491 static const unsigned int msiof1_rxd_mux[] = {
1492 MSIOF1_RXD_MARK,
1493 };
1494
1495 /* - MSIOF2 ----------------------------------------------------------------- */
1496 static const unsigned int msiof2_clk_pins[] = {
1497 /* MSIOF2_SCK */
1498 RCAR_GP_PIN(2, 0),
1499 };
1500 static const unsigned int msiof2_clk_mux[] = {
1501 MSIOF2_SCK_MARK,
1502 };
1503 static const unsigned int msiof2_sync_pins[] = {
1504 /* MSIOF2_SYNC */
1505 RCAR_GP_PIN(2, 3),
1506 };
1507 static const unsigned int msiof2_sync_mux[] = {
1508 MSIOF2_SYNC_MARK,
1509 };
1510 static const unsigned int msiof2_ss1_pins[] = {
1511 /* MSIOF2_SS1 */
1512 RCAR_GP_PIN(2, 4),
1513 };
1514 static const unsigned int msiof2_ss1_mux[] = {
1515 MSIOF2_SS1_MARK,
1516 };
1517 static const unsigned int msiof2_ss2_pins[] = {
1518 /* MSIOF2_SS2 */
1519 RCAR_GP_PIN(2, 5),
1520 };
1521 static const unsigned int msiof2_ss2_mux[] = {
1522 MSIOF2_SS2_MARK,
1523 };
1524 static const unsigned int msiof2_txd_pins[] = {
1525 /* MSIOF2_TXD */
1526 RCAR_GP_PIN(2, 2),
1527 };
1528 static const unsigned int msiof2_txd_mux[] = {
1529 MSIOF2_TXD_MARK,
1530 };
1531 static const unsigned int msiof2_rxd_pins[] = {
1532 /* MSIOF2_RXD */
1533 RCAR_GP_PIN(2, 1),
1534 };
1535 static const unsigned int msiof2_rxd_mux[] = {
1536 MSIOF2_RXD_MARK,
1537 };
1538
1539 /* - MSIOF3 ----------------------------------------------------------------- */
1540 static const unsigned int msiof3_clk_pins[] = {
1541 /* MSIOF3_SCK */
1542 RCAR_GP_PIN(0, 20),
1543 };
1544 static const unsigned int msiof3_clk_mux[] = {
1545 MSIOF3_SCK_MARK,
1546 };
1547 static const unsigned int msiof3_sync_pins[] = {
1548 /* MSIOF3_SYNC */
1549 RCAR_GP_PIN(0, 21),
1550 };
1551 static const unsigned int msiof3_sync_mux[] = {
1552 MSIOF3_SYNC_MARK,
1553 };
1554 static const unsigned int msiof3_ss1_pins[] = {
1555 /* MSIOF3_SS1 */
1556 RCAR_GP_PIN(0, 18),
1557 };
1558 static const unsigned int msiof3_ss1_mux[] = {
1559 MSIOF3_SS1_MARK,
1560 };
1561 static const unsigned int msiof3_ss2_pins[] = {
1562 /* MSIOF3_SS2 */
1563 RCAR_GP_PIN(0, 19),
1564 };
1565 static const unsigned int msiof3_ss2_mux[] = {
1566 MSIOF3_SS2_MARK,
1567 };
1568 static const unsigned int msiof3_txd_pins[] = {
1569 /* MSIOF3_TXD */
1570 RCAR_GP_PIN(0, 17),
1571 };
1572 static const unsigned int msiof3_txd_mux[] = {
1573 MSIOF3_TXD_MARK,
1574 };
1575 static const unsigned int msiof3_rxd_pins[] = {
1576 /* MSIOF3_RXD */
1577 RCAR_GP_PIN(0, 16),
1578 };
1579 static const unsigned int msiof3_rxd_mux[] = {
1580 MSIOF3_RXD_MARK,
1581 };
1582
1583 /* - PWM0 ------------------------------------------------------------------- */
1584 static const unsigned int pwm0_a_pins[] = {
1585 /* PWM0 */
1586 RCAR_GP_PIN(0, 15),
1587 };
1588 static const unsigned int pwm0_a_mux[] = {
1589 PWM0_A_MARK,
1590 };
1591 static const unsigned int pwm0_b_pins[] = {
1592 /* PWM0 */
1593 RCAR_GP_PIN(1, 21),
1594 };
1595 static const unsigned int pwm0_b_mux[] = {
1596 PWM0_B_MARK,
1597 };
1598
1599 /* - PWM1 ------------------------------------------------------------------- */
1600 static const unsigned int pwm1_a_pins[] = {
1601 /* PWM1 */
1602 RCAR_GP_PIN(2, 13),
1603 };
1604 static const unsigned int pwm1_a_mux[] = {
1605 PWM1_A_MARK,
1606 };
1607 static const unsigned int pwm1_b_pins[] = {
1608 /* PWM1 */
1609 RCAR_GP_PIN(1, 22),
1610 };
1611 static const unsigned int pwm1_b_mux[] = {
1612 PWM1_B_MARK,
1613 };
1614
1615 /* - PWM2 ------------------------------------------------------------------- */
1616 static const unsigned int pwm2_a_pins[] = {
1617 /* PWM2 */
1618 RCAR_GP_PIN(2, 14),
1619 };
1620 static const unsigned int pwm2_a_mux[] = {
1621 PWM2_A_MARK,
1622 };
1623 static const unsigned int pwm2_b_pins[] = {
1624 /* PWM2 */
1625 RCAR_GP_PIN(1, 23),
1626 };
1627 static const unsigned int pwm2_b_mux[] = {
1628 PWM2_B_MARK,
1629 };
1630
1631 /* - PWM3 ------------------------------------------------------------------- */
1632 static const unsigned int pwm3_a_pins[] = {
1633 /* PWM3 */
1634 RCAR_GP_PIN(2, 15),
1635 };
1636 static const unsigned int pwm3_a_mux[] = {
1637 PWM3_A_MARK,
1638 };
1639 static const unsigned int pwm3_b_pins[] = {
1640 /* PWM3 */
1641 RCAR_GP_PIN(1, 24),
1642 };
1643 static const unsigned int pwm3_b_mux[] = {
1644 PWM3_B_MARK,
1645 };
1646
1647 /* - PWM4 ------------------------------------------------------------------- */
1648 static const unsigned int pwm4_a_pins[] = {
1649 /* PWM4 */
1650 RCAR_GP_PIN(2, 16),
1651 };
1652 static const unsigned int pwm4_a_mux[] = {
1653 PWM4_A_MARK,
1654 };
1655 static const unsigned int pwm4_b_pins[] = {
1656 /* PWM4 */
1657 RCAR_GP_PIN(1, 25),
1658 };
1659 static const unsigned int pwm4_b_mux[] = {
1660 PWM4_B_MARK,
1661 };
1662
1663 /* - QSPI0 ------------------------------------------------------------------ */
1664 static const unsigned int qspi0_ctrl_pins[] = {
1665 /* SPCLK, SSL */
1666 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1667 };
1668 static const unsigned int qspi0_ctrl_mux[] = {
1669 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1670 };
1671 static const unsigned int qspi0_data2_pins[] = {
1672 /* MOSI_IO0, MISO_IO1 */
1673 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1674 };
1675 static const unsigned int qspi0_data2_mux[] = {
1676 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1677 };
1678 static const unsigned int qspi0_data4_pins[] = {
1679 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1680 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1681 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1682 };
1683 static const unsigned int qspi0_data4_mux[] = {
1684 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1685 QSPI0_IO2_MARK, QSPI0_IO3_MARK
1686 };
1687
1688 /* - QSPI1 ------------------------------------------------------------------ */
1689 static const unsigned int qspi1_ctrl_pins[] = {
1690 /* SPCLK, SSL */
1691 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1692 };
1693 static const unsigned int qspi1_ctrl_mux[] = {
1694 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1695 };
1696 static const unsigned int qspi1_data2_pins[] = {
1697 /* MOSI_IO0, MISO_IO1 */
1698 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1699 };
1700 static const unsigned int qspi1_data2_mux[] = {
1701 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1702 };
1703 static const unsigned int qspi1_data4_pins[] = {
1704 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1705 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1706 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1707 };
1708 static const unsigned int qspi1_data4_mux[] = {
1709 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1710 QSPI1_IO2_MARK, QSPI1_IO3_MARK
1711 };
1712
1713 /* - SCIF0 ------------------------------------------------------------------ */
1714 static const unsigned int scif0_data_pins[] = {
1715 /* RX0, TX0 */
1716 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1717 };
1718 static const unsigned int scif0_data_mux[] = {
1719 RX0_MARK, TX0_MARK,
1720 };
1721 static const unsigned int scif0_clk_pins[] = {
1722 /* SCK0 */
1723 RCAR_GP_PIN(4, 1),
1724 };
1725 static const unsigned int scif0_clk_mux[] = {
1726 SCK0_MARK,
1727 };
1728 static const unsigned int scif0_ctrl_pins[] = {
1729 /* RTS0#, CTS0# */
1730 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1731 };
1732 static const unsigned int scif0_ctrl_mux[] = {
1733 RTS0_N_MARK, CTS0_N_MARK,
1734 };
1735
1736 /* - SCIF1 ------------------------------------------------------------------ */
1737 static const unsigned int scif1_data_a_pins[] = {
1738 /* RX1, TX1 */
1739 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1740 };
1741 static const unsigned int scif1_data_a_mux[] = {
1742 RX1_A_MARK, TX1_A_MARK,
1743 };
1744 static const unsigned int scif1_clk_pins[] = {
1745 /* SCK1 */
1746 RCAR_GP_PIN(2, 5),
1747 };
1748 static const unsigned int scif1_clk_mux[] = {
1749 SCK1_MARK,
1750 };
1751 static const unsigned int scif1_ctrl_pins[] = {
1752 /* RTS1#, CTS1# */
1753 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1754 };
1755 static const unsigned int scif1_ctrl_mux[] = {
1756 RTS1_N_MARK, CTS1_N_MARK,
1757 };
1758 static const unsigned int scif1_data_b_pins[] = {
1759 /* RX1, TX1 */
1760 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1761 };
1762 static const unsigned int scif1_data_b_mux[] = {
1763 RX1_B_MARK, TX1_B_MARK,
1764 };
1765
1766 /* - SCIF3 ------------------------------------------------------------------ */
1767 static const unsigned int scif3_data_pins[] = {
1768 /* RX3, TX3 */
1769 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1770 };
1771 static const unsigned int scif3_data_mux[] = {
1772 RX3_MARK, TX3_MARK,
1773 };
1774 static const unsigned int scif3_clk_pins[] = {
1775 /* SCK3 */
1776 RCAR_GP_PIN(2, 0),
1777 };
1778 static const unsigned int scif3_clk_mux[] = {
1779 SCK3_MARK,
1780 };
1781 static const unsigned int scif3_ctrl_pins[] = {
1782 /* RTS3#, CTS3# */
1783 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1784 };
1785 static const unsigned int scif3_ctrl_mux[] = {
1786 RTS3_N_MARK, CTS3_N_MARK,
1787 };
1788
1789 /* - SCIF4 ------------------------------------------------------------------ */
1790 static const unsigned int scif4_data_pins[] = {
1791 /* RX4, TX4 */
1792 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1793 };
1794 static const unsigned int scif4_data_mux[] = {
1795 RX4_MARK, TX4_MARK,
1796 };
1797 static const unsigned int scif4_clk_pins[] = {
1798 /* SCK4 */
1799 RCAR_GP_PIN(0, 0),
1800 };
1801 static const unsigned int scif4_clk_mux[] = {
1802 SCK4_MARK,
1803 };
1804 static const unsigned int scif4_ctrl_pins[] = {
1805 /* RTS4#, CTS4# */
1806 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1807 };
1808 static const unsigned int scif4_ctrl_mux[] = {
1809 RTS4_N_MARK, CTS4_N_MARK,
1810 };
1811
1812 /* - SCIF Clock ------------------------------------------------------------- */
1813 static const unsigned int scif_clk_a_pins[] = {
1814 /* SCIF_CLK */
1815 RCAR_GP_PIN(0, 10),
1816 };
1817 static const unsigned int scif_clk_a_mux[] = {
1818 SCIF_CLK_A_MARK,
1819 };
1820 static const unsigned int scif_clk_b_pins[] = {
1821 /* SCIF_CLK */
1822 RCAR_GP_PIN(1, 25),
1823 };
1824 static const unsigned int scif_clk_b_mux[] = {
1825 SCIF_CLK_B_MARK,
1826 };
1827
1828 /* - TMU -------------------------------------------------------------------- */
1829 static const unsigned int tmu_tclk1_a_pins[] = {
1830 /* TCLK1 */
1831 RCAR_GP_PIN(3, 13),
1832 };
1833 static const unsigned int tmu_tclk1_a_mux[] = {
1834 TCLK1_A_MARK,
1835 };
1836 static const unsigned int tmu_tclk1_b_pins[] = {
1837 /* TCLK1 */
1838 RCAR_GP_PIN(1, 23),
1839 };
1840 static const unsigned int tmu_tclk1_b_mux[] = {
1841 TCLK1_B_MARK,
1842 };
1843 static const unsigned int tmu_tclk2_a_pins[] = {
1844 /* TCLK2 */
1845 RCAR_GP_PIN(3, 14),
1846 };
1847 static const unsigned int tmu_tclk2_a_mux[] = {
1848 TCLK2_A_MARK,
1849 };
1850 static const unsigned int tmu_tclk2_b_pins[] = {
1851 /* TCLK2 */
1852 RCAR_GP_PIN(1, 24),
1853 };
1854 static const unsigned int tmu_tclk2_b_mux[] = {
1855 TCLK2_B_MARK,
1856 };
1857
1858 /* - TPU ------------------------------------------------------------------- */
1859 static const unsigned int tpu_to0_pins[] = {
1860 /* TPU0TO0 */
1861 RCAR_GP_PIN(1, 19),
1862 };
1863 static const unsigned int tpu_to0_mux[] = {
1864 TPU0TO0_MARK,
1865 };
1866 static const unsigned int tpu_to1_pins[] = {
1867 /* TPU0TO1 */
1868 RCAR_GP_PIN(1, 20),
1869 };
1870 static const unsigned int tpu_to1_mux[] = {
1871 TPU0TO1_MARK,
1872 };
1873 static const unsigned int tpu_to2_pins[] = {
1874 /* TPU0TO2 */
1875 RCAR_GP_PIN(4, 2),
1876 };
1877 static const unsigned int tpu_to2_mux[] = {
1878 TPU0TO2_MARK,
1879 };
1880 static const unsigned int tpu_to3_pins[] = {
1881 /* TPU0TO3 */
1882 RCAR_GP_PIN(4, 3),
1883 };
1884 static const unsigned int tpu_to3_mux[] = {
1885 TPU0TO3_MARK,
1886 };
1887
1888 /* - VIN0 ------------------------------------------------------------------- */
1889 static const union vin_data vin0_data_pins = {
1890 .data24 = {
1891 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1892 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1893 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1894 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1895 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1896 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1897 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1898 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1899 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1900 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1901 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1902 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1903 },
1904 };
1905 static const union vin_data vin0_data_mux = {
1906 .data24 = {
1907 VI0_DATA0_MARK, VI0_DATA1_MARK,
1908 VI0_DATA2_MARK, VI0_DATA3_MARK,
1909 VI0_DATA4_MARK, VI0_DATA5_MARK,
1910 VI0_DATA6_MARK, VI0_DATA7_MARK,
1911 VI0_DATA8_MARK, VI0_DATA9_MARK,
1912 VI0_DATA10_MARK, VI0_DATA11_MARK,
1913 VI0_DATA12_MARK, VI0_DATA13_MARK,
1914 VI0_DATA14_MARK, VI0_DATA15_MARK,
1915 VI0_DATA16_MARK, VI0_DATA17_MARK,
1916 VI0_DATA18_MARK, VI0_DATA19_MARK,
1917 VI0_DATA20_MARK, VI0_DATA21_MARK,
1918 VI0_DATA22_MARK, VI0_DATA23_MARK,
1919 },
1920 };
1921 static const unsigned int vin0_data18_pins[] = {
1922 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1923 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1924 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1925 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1926 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1927 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1928 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1929 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1930 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1931 };
1932 static const unsigned int vin0_data18_mux[] = {
1933 VI0_DATA2_MARK, VI0_DATA3_MARK,
1934 VI0_DATA4_MARK, VI0_DATA5_MARK,
1935 VI0_DATA6_MARK, VI0_DATA7_MARK,
1936 VI0_DATA10_MARK, VI0_DATA11_MARK,
1937 VI0_DATA12_MARK, VI0_DATA13_MARK,
1938 VI0_DATA14_MARK, VI0_DATA15_MARK,
1939 VI0_DATA18_MARK, VI0_DATA19_MARK,
1940 VI0_DATA20_MARK, VI0_DATA21_MARK,
1941 VI0_DATA22_MARK, VI0_DATA23_MARK,
1942 };
1943 static const unsigned int vin0_sync_pins[] = {
1944 /* VI0_VSYNC#, VI0_HSYNC# */
1945 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1946 };
1947 static const unsigned int vin0_sync_mux[] = {
1948 VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
1949 };
1950 static const unsigned int vin0_field_pins[] = {
1951 /* VI0_FIELD */
1952 RCAR_GP_PIN(2, 16),
1953 };
1954 static const unsigned int vin0_field_mux[] = {
1955 VI0_FIELD_MARK,
1956 };
1957 static const unsigned int vin0_clkenb_pins[] = {
1958 /* VI0_CLKENB */
1959 RCAR_GP_PIN(2, 1),
1960 };
1961 static const unsigned int vin0_clkenb_mux[] = {
1962 VI0_CLKENB_MARK,
1963 };
1964 static const unsigned int vin0_clk_pins[] = {
1965 /* VI0_CLK */
1966 RCAR_GP_PIN(2, 0),
1967 };
1968 static const unsigned int vin0_clk_mux[] = {
1969 VI0_CLK_MARK,
1970 };
1971
1972 /* - VIN1 ------------------------------------------------------------------- */
1973 static const union vin_data12 vin1_data_pins = {
1974 .data12 = {
1975 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1976 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1977 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1978 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1979 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1980 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1981 },
1982 };
1983 static const union vin_data12 vin1_data_mux = {
1984 .data12 = {
1985 VI1_DATA0_MARK, VI1_DATA1_MARK,
1986 VI1_DATA2_MARK, VI1_DATA3_MARK,
1987 VI1_DATA4_MARK, VI1_DATA5_MARK,
1988 VI1_DATA6_MARK, VI1_DATA7_MARK,
1989 VI1_DATA8_MARK, VI1_DATA9_MARK,
1990 VI1_DATA10_MARK, VI1_DATA11_MARK,
1991 },
1992 };
1993 static const unsigned int vin1_sync_pins[] = {
1994 /* VI1_VSYNC#, VI1_HSYNC# */
1995 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1996 };
1997 static const unsigned int vin1_sync_mux[] = {
1998 VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
1999 };
2000 static const unsigned int vin1_field_pins[] = {
2001 /* VI1_FIELD */
2002 RCAR_GP_PIN(3, 16),
2003 };
2004 static const unsigned int vin1_field_mux[] = {
2005 VI1_FIELD_MARK,
2006 };
2007 static const unsigned int vin1_clkenb_pins[] = {
2008 /* VI1_CLKENB */
2009 RCAR_GP_PIN(3, 1),
2010 };
2011 static const unsigned int vin1_clkenb_mux[] = {
2012 VI1_CLKENB_MARK,
2013 };
2014 static const unsigned int vin1_clk_pins[] = {
2015 /* VI1_CLK */
2016 RCAR_GP_PIN(3, 0),
2017 };
2018 static const unsigned int vin1_clk_mux[] = {
2019 VI1_CLK_MARK,
2020 };
2021
2022 static const struct sh_pfc_pin_group pinmux_groups[] = {
2023 SH_PFC_PIN_GROUP(avb_link),
2024 SH_PFC_PIN_GROUP(avb_magic),
2025 SH_PFC_PIN_GROUP(avb_phy_int),
2026 SH_PFC_PIN_GROUP(avb_mdio),
2027 SH_PFC_PIN_GROUP(avb_rgmii),
2028 SH_PFC_PIN_GROUP(avb_txcrefclk),
2029 SH_PFC_PIN_GROUP(avb_avtp_pps),
2030 SH_PFC_PIN_GROUP(avb_avtp_capture),
2031 SH_PFC_PIN_GROUP(avb_avtp_match),
2032 SH_PFC_PIN_GROUP(canfd0_data_a),
2033 SH_PFC_PIN_GROUP(canfd0_data_b),
2034 SH_PFC_PIN_GROUP(canfd1_data),
2035 SH_PFC_PIN_GROUP(canfd_clk_a),
2036 SH_PFC_PIN_GROUP(canfd_clk_b),
2037 SH_PFC_PIN_GROUP(du_rgb666),
2038 SH_PFC_PIN_GROUP(du_rgb888),
2039 SH_PFC_PIN_GROUP(du_clk_out),
2040 SH_PFC_PIN_GROUP(du_sync),
2041 SH_PFC_PIN_GROUP(du_oddf),
2042 SH_PFC_PIN_GROUP(du_cde),
2043 SH_PFC_PIN_GROUP(du_disp),
2044 SH_PFC_PIN_GROUP(gether_link_a),
2045 SH_PFC_PIN_GROUP(gether_phy_int_a),
2046 SH_PFC_PIN_GROUP(gether_mdio_a),
2047 SH_PFC_PIN_GROUP(gether_link_b),
2048 SH_PFC_PIN_GROUP(gether_phy_int_b),
2049 SH_PFC_PIN_GROUP(gether_mdio_b),
2050 SH_PFC_PIN_GROUP(gether_magic),
2051 SH_PFC_PIN_GROUP(gether_rgmii),
2052 SH_PFC_PIN_GROUP(gether_txcrefclk),
2053 SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
2054 SH_PFC_PIN_GROUP(gether_rmii),
2055 SH_PFC_PIN_GROUP(hscif0_data_a),
2056 SH_PFC_PIN_GROUP(hscif0_clk_a),
2057 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
2058 SH_PFC_PIN_GROUP(hscif0_data_b),
2059 SH_PFC_PIN_GROUP(hscif0_clk_b),
2060 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2061 SH_PFC_PIN_GROUP(hscif1_data),
2062 SH_PFC_PIN_GROUP(hscif1_clk),
2063 SH_PFC_PIN_GROUP(hscif1_ctrl),
2064 SH_PFC_PIN_GROUP(hscif2_data),
2065 SH_PFC_PIN_GROUP(hscif2_clk),
2066 SH_PFC_PIN_GROUP(hscif2_ctrl),
2067 SH_PFC_PIN_GROUP(hscif3_data),
2068 SH_PFC_PIN_GROUP(hscif3_clk),
2069 SH_PFC_PIN_GROUP(hscif3_ctrl),
2070 SH_PFC_PIN_GROUP(i2c0),
2071 SH_PFC_PIN_GROUP(i2c1),
2072 SH_PFC_PIN_GROUP(i2c2),
2073 SH_PFC_PIN_GROUP(i2c3),
2074 SH_PFC_PIN_GROUP(i2c4),
2075 SH_PFC_PIN_GROUP(i2c5),
2076 SH_PFC_PIN_GROUP(intc_ex_irq0),
2077 SH_PFC_PIN_GROUP(intc_ex_irq1),
2078 SH_PFC_PIN_GROUP(intc_ex_irq2),
2079 SH_PFC_PIN_GROUP(intc_ex_irq3),
2080 SH_PFC_PIN_GROUP(intc_ex_irq4),
2081 SH_PFC_PIN_GROUP(intc_ex_irq5),
2082 SH_PFC_PIN_GROUP(mmc_data1),
2083 SH_PFC_PIN_GROUP(mmc_data4),
2084 SH_PFC_PIN_GROUP(mmc_data8),
2085 SH_PFC_PIN_GROUP(mmc_ctrl),
2086 SH_PFC_PIN_GROUP(mmc_cd),
2087 SH_PFC_PIN_GROUP(mmc_wp),
2088 SH_PFC_PIN_GROUP(mmc_ds),
2089 SH_PFC_PIN_GROUP(msiof0_clk),
2090 SH_PFC_PIN_GROUP(msiof0_sync),
2091 SH_PFC_PIN_GROUP(msiof0_ss1),
2092 SH_PFC_PIN_GROUP(msiof0_ss2),
2093 SH_PFC_PIN_GROUP(msiof0_txd),
2094 SH_PFC_PIN_GROUP(msiof0_rxd),
2095 SH_PFC_PIN_GROUP(msiof1_clk),
2096 SH_PFC_PIN_GROUP(msiof1_sync),
2097 SH_PFC_PIN_GROUP(msiof1_ss1),
2098 SH_PFC_PIN_GROUP(msiof1_ss2),
2099 SH_PFC_PIN_GROUP(msiof1_txd),
2100 SH_PFC_PIN_GROUP(msiof1_rxd),
2101 SH_PFC_PIN_GROUP(msiof2_clk),
2102 SH_PFC_PIN_GROUP(msiof2_sync),
2103 SH_PFC_PIN_GROUP(msiof2_ss1),
2104 SH_PFC_PIN_GROUP(msiof2_ss2),
2105 SH_PFC_PIN_GROUP(msiof2_txd),
2106 SH_PFC_PIN_GROUP(msiof2_rxd),
2107 SH_PFC_PIN_GROUP(msiof3_clk),
2108 SH_PFC_PIN_GROUP(msiof3_sync),
2109 SH_PFC_PIN_GROUP(msiof3_ss1),
2110 SH_PFC_PIN_GROUP(msiof3_ss2),
2111 SH_PFC_PIN_GROUP(msiof3_txd),
2112 SH_PFC_PIN_GROUP(msiof3_rxd),
2113 SH_PFC_PIN_GROUP(pwm0_a),
2114 SH_PFC_PIN_GROUP(pwm0_b),
2115 SH_PFC_PIN_GROUP(pwm1_a),
2116 SH_PFC_PIN_GROUP(pwm1_b),
2117 SH_PFC_PIN_GROUP(pwm2_a),
2118 SH_PFC_PIN_GROUP(pwm2_b),
2119 SH_PFC_PIN_GROUP(pwm3_a),
2120 SH_PFC_PIN_GROUP(pwm3_b),
2121 SH_PFC_PIN_GROUP(pwm4_a),
2122 SH_PFC_PIN_GROUP(pwm4_b),
2123 SH_PFC_PIN_GROUP(qspi0_ctrl),
2124 SH_PFC_PIN_GROUP(qspi0_data2),
2125 SH_PFC_PIN_GROUP(qspi0_data4),
2126 SH_PFC_PIN_GROUP(qspi1_ctrl),
2127 SH_PFC_PIN_GROUP(qspi1_data2),
2128 SH_PFC_PIN_GROUP(qspi1_data4),
2129 SH_PFC_PIN_GROUP(scif0_data),
2130 SH_PFC_PIN_GROUP(scif0_clk),
2131 SH_PFC_PIN_GROUP(scif0_ctrl),
2132 SH_PFC_PIN_GROUP(scif1_data_a),
2133 SH_PFC_PIN_GROUP(scif1_clk),
2134 SH_PFC_PIN_GROUP(scif1_ctrl),
2135 SH_PFC_PIN_GROUP(scif1_data_b),
2136 SH_PFC_PIN_GROUP(scif3_data),
2137 SH_PFC_PIN_GROUP(scif3_clk),
2138 SH_PFC_PIN_GROUP(scif3_ctrl),
2139 SH_PFC_PIN_GROUP(scif4_data),
2140 SH_PFC_PIN_GROUP(scif4_clk),
2141 SH_PFC_PIN_GROUP(scif4_ctrl),
2142 SH_PFC_PIN_GROUP(scif_clk_a),
2143 SH_PFC_PIN_GROUP(scif_clk_b),
2144 SH_PFC_PIN_GROUP(tmu_tclk1_a),
2145 SH_PFC_PIN_GROUP(tmu_tclk1_b),
2146 SH_PFC_PIN_GROUP(tmu_tclk2_a),
2147 SH_PFC_PIN_GROUP(tmu_tclk2_b),
2148 SH_PFC_PIN_GROUP(tpu_to0),
2149 SH_PFC_PIN_GROUP(tpu_to1),
2150 SH_PFC_PIN_GROUP(tpu_to2),
2151 SH_PFC_PIN_GROUP(tpu_to3),
2152 VIN_DATA_PIN_GROUP(vin0_data, 8),
2153 VIN_DATA_PIN_GROUP(vin0_data, 10),
2154 VIN_DATA_PIN_GROUP(vin0_data, 12),
2155 VIN_DATA_PIN_GROUP(vin0_data, 16),
2156 SH_PFC_PIN_GROUP(vin0_data18),
2157 VIN_DATA_PIN_GROUP(vin0_data, 20),
2158 VIN_DATA_PIN_GROUP(vin0_data, 24),
2159 SH_PFC_PIN_GROUP(vin0_sync),
2160 SH_PFC_PIN_GROUP(vin0_field),
2161 SH_PFC_PIN_GROUP(vin0_clkenb),
2162 SH_PFC_PIN_GROUP(vin0_clk),
2163 VIN_DATA_PIN_GROUP(vin1_data, 8),
2164 VIN_DATA_PIN_GROUP(vin1_data, 10),
2165 VIN_DATA_PIN_GROUP(vin1_data, 12),
2166 SH_PFC_PIN_GROUP(vin1_sync),
2167 SH_PFC_PIN_GROUP(vin1_field),
2168 SH_PFC_PIN_GROUP(vin1_clkenb),
2169 SH_PFC_PIN_GROUP(vin1_clk),
2170 };
2171
2172 static const char * const avb_groups[] = {
2173 "avb_link",
2174 "avb_magic",
2175 "avb_phy_int",
2176 "avb_mdio",
2177 "avb_rgmii",
2178 "avb_txcrefclk",
2179 "avb_avtp_pps",
2180 "avb_avtp_capture",
2181 "avb_avtp_match",
2182 };
2183
2184 static const char * const canfd0_groups[] = {
2185 "canfd0_data_a",
2186 "canfd0_data_b",
2187 };
2188
2189 static const char * const canfd1_groups[] = {
2190 "canfd1_data",
2191 };
2192
2193 static const char * const canfd_clk_groups[] = {
2194 "canfd_clk_a",
2195 "canfd_clk_b",
2196 };
2197
2198 static const char * const du_groups[] = {
2199 "du_rgb666",
2200 "du_rgb888",
2201 "du_clk_out",
2202 "du_sync",
2203 "du_oddf",
2204 "du_cde",
2205 "du_disp",
2206 };
2207
2208 static const char * const gether_groups[] = {
2209 "gether_link_a",
2210 "gether_phy_int_a",
2211 "gether_mdio_a",
2212 "gether_link_b",
2213 "gether_phy_int_b",
2214 "gether_mdio_b",
2215 "gether_magic",
2216 "gether_rgmii",
2217 "gether_txcrefclk",
2218 "gether_txcrefclk_mega",
2219 "gether_rmii",
2220 };
2221
2222 static const char * const hscif0_groups[] = {
2223 "hscif0_data_a",
2224 "hscif0_clk_a",
2225 "hscif0_ctrl_a",
2226 "hscif0_data_b",
2227 "hscif0_clk_b",
2228 "hscif0_ctrl_b",
2229 };
2230
2231 static const char * const hscif1_groups[] = {
2232 "hscif1_data",
2233 "hscif1_clk",
2234 "hscif1_ctrl",
2235 };
2236
2237 static const char * const hscif2_groups[] = {
2238 "hscif2_data",
2239 "hscif2_clk",
2240 "hscif2_ctrl",
2241 };
2242
2243 static const char * const hscif3_groups[] = {
2244 "hscif3_data",
2245 "hscif3_clk",
2246 "hscif3_ctrl",
2247 };
2248
2249 static const char * const i2c0_groups[] = {
2250 "i2c0",
2251 };
2252
2253 static const char * const i2c1_groups[] = {
2254 "i2c1",
2255 };
2256
2257 static const char * const i2c2_groups[] = {
2258 "i2c2",
2259 };
2260
2261 static const char * const i2c3_groups[] = {
2262 "i2c3",
2263 };
2264
2265 static const char * const i2c4_groups[] = {
2266 "i2c4",
2267 };
2268
2269 static const char * const i2c5_groups[] = {
2270 "i2c5",
2271 };
2272
2273 static const char * const intc_ex_groups[] = {
2274 "intc_ex_irq0",
2275 "intc_ex_irq1",
2276 "intc_ex_irq2",
2277 "intc_ex_irq3",
2278 "intc_ex_irq4",
2279 "intc_ex_irq5",
2280 };
2281
2282 static const char * const mmc_groups[] = {
2283 "mmc_data1",
2284 "mmc_data4",
2285 "mmc_data8",
2286 "mmc_ctrl",
2287 "mmc_cd",
2288 "mmc_wp",
2289 "mmc_ds",
2290 };
2291
2292 static const char * const msiof0_groups[] = {
2293 "msiof0_clk",
2294 "msiof0_sync",
2295 "msiof0_ss1",
2296 "msiof0_ss2",
2297 "msiof0_txd",
2298 "msiof0_rxd",
2299 };
2300
2301 static const char * const msiof1_groups[] = {
2302 "msiof1_clk",
2303 "msiof1_sync",
2304 "msiof1_ss1",
2305 "msiof1_ss2",
2306 "msiof1_txd",
2307 "msiof1_rxd",
2308 };
2309
2310 static const char * const msiof2_groups[] = {
2311 "msiof2_clk",
2312 "msiof2_sync",
2313 "msiof2_ss1",
2314 "msiof2_ss2",
2315 "msiof2_txd",
2316 "msiof2_rxd",
2317 };
2318
2319 static const char * const msiof3_groups[] = {
2320 "msiof3_clk",
2321 "msiof3_sync",
2322 "msiof3_ss1",
2323 "msiof3_ss2",
2324 "msiof3_txd",
2325 "msiof3_rxd",
2326 };
2327
2328 static const char * const pwm0_groups[] = {
2329 "pwm0_a",
2330 "pwm0_b",
2331 };
2332
2333 static const char * const pwm1_groups[] = {
2334 "pwm1_a",
2335 "pwm1_b",
2336 };
2337
2338 static const char * const pwm2_groups[] = {
2339 "pwm2_a",
2340 "pwm2_b",
2341 };
2342
2343 static const char * const pwm3_groups[] = {
2344 "pwm3_a",
2345 "pwm3_b",
2346 };
2347
2348 static const char * const pwm4_groups[] = {
2349 "pwm4_a",
2350 "pwm4_b",
2351 };
2352
2353 static const char * const qspi0_groups[] = {
2354 "qspi0_ctrl",
2355 "qspi0_data2",
2356 "qspi0_data4",
2357 };
2358
2359 static const char * const qspi1_groups[] = {
2360 "qspi1_ctrl",
2361 "qspi1_data2",
2362 "qspi1_data4",
2363 };
2364
2365 static const char * const scif0_groups[] = {
2366 "scif0_data",
2367 "scif0_clk",
2368 "scif0_ctrl",
2369 };
2370
2371 static const char * const scif1_groups[] = {
2372 "scif1_data_a",
2373 "scif1_clk",
2374 "scif1_ctrl",
2375 "scif1_data_b",
2376 };
2377
2378 static const char * const scif3_groups[] = {
2379 "scif3_data",
2380 "scif3_clk",
2381 "scif3_ctrl",
2382 };
2383
2384 static const char * const scif4_groups[] = {
2385 "scif4_data",
2386 "scif4_clk",
2387 "scif4_ctrl",
2388 };
2389
2390 static const char * const scif_clk_groups[] = {
2391 "scif_clk_a",
2392 "scif_clk_b",
2393 };
2394
2395 static const char * const tmu_groups[] = {
2396 "tmu_tclk1_a",
2397 "tmu_tclk1_b",
2398 "tmu_tclk2_a",
2399 "tmu_tclk2_b",
2400 };
2401
2402 static const char * const tpu_groups[] = {
2403 "tpu_to0",
2404 "tpu_to1",
2405 "tpu_to2",
2406 "tpu_to3",
2407 };
2408
2409 static const char * const vin0_groups[] = {
2410 "vin0_data8",
2411 "vin0_data10",
2412 "vin0_data12",
2413 "vin0_data16",
2414 "vin0_data18",
2415 "vin0_data20",
2416 "vin0_data24",
2417 "vin0_sync",
2418 "vin0_field",
2419 "vin0_clkenb",
2420 "vin0_clk",
2421 };
2422
2423 static const char * const vin1_groups[] = {
2424 "vin1_data8",
2425 "vin1_data10",
2426 "vin1_data12",
2427 "vin1_sync",
2428 "vin1_field",
2429 "vin1_clkenb",
2430 "vin1_clk",
2431 };
2432
2433 static const struct sh_pfc_function pinmux_functions[] = {
2434 SH_PFC_FUNCTION(avb),
2435 SH_PFC_FUNCTION(canfd0),
2436 SH_PFC_FUNCTION(canfd1),
2437 SH_PFC_FUNCTION(canfd_clk),
2438 SH_PFC_FUNCTION(du),
2439 SH_PFC_FUNCTION(gether),
2440 SH_PFC_FUNCTION(hscif0),
2441 SH_PFC_FUNCTION(hscif1),
2442 SH_PFC_FUNCTION(hscif2),
2443 SH_PFC_FUNCTION(hscif3),
2444 SH_PFC_FUNCTION(i2c0),
2445 SH_PFC_FUNCTION(i2c1),
2446 SH_PFC_FUNCTION(i2c2),
2447 SH_PFC_FUNCTION(i2c3),
2448 SH_PFC_FUNCTION(i2c4),
2449 SH_PFC_FUNCTION(i2c5),
2450 SH_PFC_FUNCTION(intc_ex),
2451 SH_PFC_FUNCTION(mmc),
2452 SH_PFC_FUNCTION(msiof0),
2453 SH_PFC_FUNCTION(msiof1),
2454 SH_PFC_FUNCTION(msiof2),
2455 SH_PFC_FUNCTION(msiof3),
2456 SH_PFC_FUNCTION(pwm0),
2457 SH_PFC_FUNCTION(pwm1),
2458 SH_PFC_FUNCTION(pwm2),
2459 SH_PFC_FUNCTION(pwm3),
2460 SH_PFC_FUNCTION(pwm4),
2461 SH_PFC_FUNCTION(qspi0),
2462 SH_PFC_FUNCTION(qspi1),
2463 SH_PFC_FUNCTION(scif0),
2464 SH_PFC_FUNCTION(scif1),
2465 SH_PFC_FUNCTION(scif3),
2466 SH_PFC_FUNCTION(scif4),
2467 SH_PFC_FUNCTION(scif_clk),
2468 SH_PFC_FUNCTION(tmu),
2469 SH_PFC_FUNCTION(tpu),
2470 SH_PFC_FUNCTION(vin0),
2471 SH_PFC_FUNCTION(vin1),
2472 };
2473
2474 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2475 #define F_(x, y) FN_##y
2476 #define FM(x) FN_##x
2477 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2478 0, 0,
2479 0, 0,
2480 0, 0,
2481 0, 0,
2482 0, 0,
2483 0, 0,
2484 0, 0,
2485 0, 0,
2486 0, 0,
2487 0, 0,
2488 GP_0_21_FN, GPSR0_21,
2489 GP_0_20_FN, GPSR0_20,
2490 GP_0_19_FN, GPSR0_19,
2491 GP_0_18_FN, GPSR0_18,
2492 GP_0_17_FN, GPSR0_17,
2493 GP_0_16_FN, GPSR0_16,
2494 GP_0_15_FN, GPSR0_15,
2495 GP_0_14_FN, GPSR0_14,
2496 GP_0_13_FN, GPSR0_13,
2497 GP_0_12_FN, GPSR0_12,
2498 GP_0_11_FN, GPSR0_11,
2499 GP_0_10_FN, GPSR0_10,
2500 GP_0_9_FN, GPSR0_9,
2501 GP_0_8_FN, GPSR0_8,
2502 GP_0_7_FN, GPSR0_7,
2503 GP_0_6_FN, GPSR0_6,
2504 GP_0_5_FN, GPSR0_5,
2505 GP_0_4_FN, GPSR0_4,
2506 GP_0_3_FN, GPSR0_3,
2507 GP_0_2_FN, GPSR0_2,
2508 GP_0_1_FN, GPSR0_1,
2509 GP_0_0_FN, GPSR0_0, ))
2510 },
2511 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2512 0, 0,
2513 0, 0,
2514 0, 0,
2515 0, 0,
2516 GP_1_27_FN, GPSR1_27,
2517 GP_1_26_FN, GPSR1_26,
2518 GP_1_25_FN, GPSR1_25,
2519 GP_1_24_FN, GPSR1_24,
2520 GP_1_23_FN, GPSR1_23,
2521 GP_1_22_FN, GPSR1_22,
2522 GP_1_21_FN, GPSR1_21,
2523 GP_1_20_FN, GPSR1_20,
2524 GP_1_19_FN, GPSR1_19,
2525 GP_1_18_FN, GPSR1_18,
2526 GP_1_17_FN, GPSR1_17,
2527 GP_1_16_FN, GPSR1_16,
2528 GP_1_15_FN, GPSR1_15,
2529 GP_1_14_FN, GPSR1_14,
2530 GP_1_13_FN, GPSR1_13,
2531 GP_1_12_FN, GPSR1_12,
2532 GP_1_11_FN, GPSR1_11,
2533 GP_1_10_FN, GPSR1_10,
2534 GP_1_9_FN, GPSR1_9,
2535 GP_1_8_FN, GPSR1_8,
2536 GP_1_7_FN, GPSR1_7,
2537 GP_1_6_FN, GPSR1_6,
2538 GP_1_5_FN, GPSR1_5,
2539 GP_1_4_FN, GPSR1_4,
2540 GP_1_3_FN, GPSR1_3,
2541 GP_1_2_FN, GPSR1_2,
2542 GP_1_1_FN, GPSR1_1,
2543 GP_1_0_FN, GPSR1_0, ))
2544 },
2545 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2546 0, 0,
2547 0, 0,
2548 GP_2_29_FN, GPSR2_29,
2549 GP_2_28_FN, GPSR2_28,
2550 GP_2_27_FN, GPSR2_27,
2551 GP_2_26_FN, GPSR2_26,
2552 GP_2_25_FN, GPSR2_25,
2553 GP_2_24_FN, GPSR2_24,
2554 GP_2_23_FN, GPSR2_23,
2555 GP_2_22_FN, GPSR2_22,
2556 GP_2_21_FN, GPSR2_21,
2557 GP_2_20_FN, GPSR2_20,
2558 GP_2_19_FN, GPSR2_19,
2559 GP_2_18_FN, GPSR2_18,
2560 GP_2_17_FN, GPSR2_17,
2561 GP_2_16_FN, GPSR2_16,
2562 GP_2_15_FN, GPSR2_15,
2563 GP_2_14_FN, GPSR2_14,
2564 GP_2_13_FN, GPSR2_13,
2565 GP_2_12_FN, GPSR2_12,
2566 GP_2_11_FN, GPSR2_11,
2567 GP_2_10_FN, GPSR2_10,
2568 GP_2_9_FN, GPSR2_9,
2569 GP_2_8_FN, GPSR2_8,
2570 GP_2_7_FN, GPSR2_7,
2571 GP_2_6_FN, GPSR2_6,
2572 GP_2_5_FN, GPSR2_5,
2573 GP_2_4_FN, GPSR2_4,
2574 GP_2_3_FN, GPSR2_3,
2575 GP_2_2_FN, GPSR2_2,
2576 GP_2_1_FN, GPSR2_1,
2577 GP_2_0_FN, GPSR2_0, ))
2578 },
2579 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2580 0, 0,
2581 0, 0,
2582 0, 0,
2583 0, 0,
2584 0, 0,
2585 0, 0,
2586 0, 0,
2587 0, 0,
2588 0, 0,
2589 0, 0,
2590 0, 0,
2591 0, 0,
2592 0, 0,
2593 0, 0,
2594 0, 0,
2595 GP_3_16_FN, GPSR3_16,
2596 GP_3_15_FN, GPSR3_15,
2597 GP_3_14_FN, GPSR3_14,
2598 GP_3_13_FN, GPSR3_13,
2599 GP_3_12_FN, GPSR3_12,
2600 GP_3_11_FN, GPSR3_11,
2601 GP_3_10_FN, GPSR3_10,
2602 GP_3_9_FN, GPSR3_9,
2603 GP_3_8_FN, GPSR3_8,
2604 GP_3_7_FN, GPSR3_7,
2605 GP_3_6_FN, GPSR3_6,
2606 GP_3_5_FN, GPSR3_5,
2607 GP_3_4_FN, GPSR3_4,
2608 GP_3_3_FN, GPSR3_3,
2609 GP_3_2_FN, GPSR3_2,
2610 GP_3_1_FN, GPSR3_1,
2611 GP_3_0_FN, GPSR3_0, ))
2612 },
2613 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2614 0, 0,
2615 0, 0,
2616 0, 0,
2617 0, 0,
2618 0, 0,
2619 0, 0,
2620 0, 0,
2621 GP_4_24_FN, GPSR4_24,
2622 GP_4_23_FN, GPSR4_23,
2623 GP_4_22_FN, GPSR4_22,
2624 GP_4_21_FN, GPSR4_21,
2625 GP_4_20_FN, GPSR4_20,
2626 GP_4_19_FN, GPSR4_19,
2627 GP_4_18_FN, GPSR4_18,
2628 GP_4_17_FN, GPSR4_17,
2629 GP_4_16_FN, GPSR4_16,
2630 GP_4_15_FN, GPSR4_15,
2631 GP_4_14_FN, GPSR4_14,
2632 GP_4_13_FN, GPSR4_13,
2633 GP_4_12_FN, GPSR4_12,
2634 GP_4_11_FN, GPSR4_11,
2635 GP_4_10_FN, GPSR4_10,
2636 GP_4_9_FN, GPSR4_9,
2637 GP_4_8_FN, GPSR4_8,
2638 GP_4_7_FN, GPSR4_7,
2639 GP_4_6_FN, GPSR4_6,
2640 GP_4_5_FN, GPSR4_5,
2641 GP_4_4_FN, GPSR4_4,
2642 GP_4_3_FN, GPSR4_3,
2643 GP_4_2_FN, GPSR4_2,
2644 GP_4_1_FN, GPSR4_1,
2645 GP_4_0_FN, GPSR4_0, ))
2646 },
2647 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2648 0, 0,
2649 0, 0,
2650 0, 0,
2651 0, 0,
2652 0, 0,
2653 0, 0,
2654 0, 0,
2655 0, 0,
2656 0, 0,
2657 0, 0,
2658 0, 0,
2659 0, 0,
2660 0, 0,
2661 0, 0,
2662 0, 0,
2663 0, 0,
2664 0, 0,
2665 GP_5_14_FN, GPSR5_14,
2666 GP_5_13_FN, GPSR5_13,
2667 GP_5_12_FN, GPSR5_12,
2668 GP_5_11_FN, GPSR5_11,
2669 GP_5_10_FN, GPSR5_10,
2670 GP_5_9_FN, GPSR5_9,
2671 GP_5_8_FN, GPSR5_8,
2672 GP_5_7_FN, GPSR5_7,
2673 GP_5_6_FN, GPSR5_6,
2674 GP_5_5_FN, GPSR5_5,
2675 GP_5_4_FN, GPSR5_4,
2676 GP_5_3_FN, GPSR5_3,
2677 GP_5_2_FN, GPSR5_2,
2678 GP_5_1_FN, GPSR5_1,
2679 GP_5_0_FN, GPSR5_0, ))
2680 },
2681 #undef F_
2682 #undef FM
2683
2684 #define F_(x, y) x,
2685 #define FM(x) FN_##x,
2686 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2687 IP0_31_28
2688 IP0_27_24
2689 IP0_23_20
2690 IP0_19_16
2691 IP0_15_12
2692 IP0_11_8
2693 IP0_7_4
2694 IP0_3_0 ))
2695 },
2696 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2697 IP1_31_28
2698 IP1_27_24
2699 IP1_23_20
2700 IP1_19_16
2701 IP1_15_12
2702 IP1_11_8
2703 IP1_7_4
2704 IP1_3_0 ))
2705 },
2706 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2707 IP2_31_28
2708 IP2_27_24
2709 IP2_23_20
2710 IP2_19_16
2711 IP2_15_12
2712 IP2_11_8
2713 IP2_7_4
2714 IP2_3_0 ))
2715 },
2716 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2717 IP3_31_28
2718 IP3_27_24
2719 IP3_23_20
2720 IP3_19_16
2721 IP3_15_12
2722 IP3_11_8
2723 IP3_7_4
2724 IP3_3_0 ))
2725 },
2726 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2727 IP4_31_28
2728 IP4_27_24
2729 IP4_23_20
2730 IP4_19_16
2731 IP4_15_12
2732 IP4_11_8
2733 IP4_7_4
2734 IP4_3_0 ))
2735 },
2736 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2737 IP5_31_28
2738 IP5_27_24
2739 IP5_23_20
2740 IP5_19_16
2741 IP5_15_12
2742 IP5_11_8
2743 IP5_7_4
2744 IP5_3_0 ))
2745 },
2746 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2747 IP6_31_28
2748 IP6_27_24
2749 IP6_23_20
2750 IP6_19_16
2751 IP6_15_12
2752 IP6_11_8
2753 IP6_7_4
2754 IP6_3_0 ))
2755 },
2756 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2757 IP7_31_28
2758 IP7_27_24
2759 IP7_23_20
2760 IP7_19_16
2761 IP7_15_12
2762 IP7_11_8
2763 IP7_7_4
2764 IP7_3_0 ))
2765 },
2766 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2767 IP8_31_28
2768 IP8_27_24
2769 IP8_23_20
2770 IP8_19_16
2771 IP8_15_12
2772 IP8_11_8
2773 IP8_7_4
2774 IP8_3_0 ))
2775 },
2776 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2777 IP9_31_28
2778 IP9_27_24
2779 IP9_23_20
2780 IP9_19_16
2781 IP9_15_12
2782 IP9_11_8
2783 IP9_7_4
2784 IP9_3_0 ))
2785 },
2786 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
2787 IP10_31_28
2788 IP10_27_24
2789 IP10_23_20
2790 IP10_19_16
2791 IP10_15_12
2792 IP10_11_8
2793 IP10_7_4
2794 IP10_3_0 ))
2795 },
2796 #undef F_
2797 #undef FM
2798
2799 #define F_(x, y) x,
2800 #define FM(x) FN_##x,
2801 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2802 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
2803 1, 1, 1, 1, 1),
2804 GROUP(
2805 /* RESERVED 31, 30, 29, 28 */
2806 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2807 /* RESERVED 27, 26, 25, 24 */
2808 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2809 /* RESERVED 23, 22, 21, 20 */
2810 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2811 /* RESERVED 19, 18, 17, 16 */
2812 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2813 /* RESERVED 15, 14, 13, 12 */
2814 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2815 MOD_SEL0_11
2816 MOD_SEL0_10
2817 MOD_SEL0_9
2818 MOD_SEL0_8
2819 MOD_SEL0_7
2820 MOD_SEL0_6
2821 MOD_SEL0_5
2822 MOD_SEL0_4
2823 0, 0,
2824 MOD_SEL0_2
2825 MOD_SEL0_1
2826 MOD_SEL0_0 ))
2827 },
2828 { },
2829 };
2830
2831 enum ioctrl_regs {
2832 POCCTRL0,
2833 POCCTRL1,
2834 POCCTRL2,
2835 POCCTRL3,
2836 TDSELCTRL,
2837 };
2838
2839 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2840 [POCCTRL0] = { 0xe6060380, },
2841 [POCCTRL1] = { 0xe6060384, },
2842 [POCCTRL2] = { 0xe6060388, },
2843 [POCCTRL3] = { 0xe606038c, },
2844 [TDSELCTRL] = { 0xe60603c0, },
2845 { /* sentinel */ },
2846 };
2847
r8a77980_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)2848 static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2849 u32 *pocctrl)
2850 {
2851 int bit = pin & 0x1f;
2852
2853 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2854 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2855 return bit;
2856 else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2857 return bit + 22;
2858
2859 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2860 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2861 return bit - 10;
2862 if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
2863 (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
2864 return bit + 7;
2865
2866 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
2867 if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
2868 return pin - 25;
2869
2870 return -EINVAL;
2871 }
2872
2873 static const struct sh_pfc_soc_operations pinmux_ops = {
2874 .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
2875 };
2876
2877 const struct sh_pfc_soc_info r8a77980_pinmux_info = {
2878 .name = "r8a77980_pfc",
2879 .ops = &pinmux_ops,
2880 .unlock_reg = 0xe6060000, /* PMMR */
2881
2882 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2883
2884 .pins = pinmux_pins,
2885 .nr_pins = ARRAY_SIZE(pinmux_pins),
2886 .groups = pinmux_groups,
2887 .nr_groups = ARRAY_SIZE(pinmux_groups),
2888 .functions = pinmux_functions,
2889 .nr_functions = ARRAY_SIZE(pinmux_functions),
2890
2891 .cfg_regs = pinmux_config_regs,
2892 .ioctrl_regs = pinmux_ioctrl_regs,
2893
2894 .pinmux_data = pinmux_data,
2895 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2896 };
2897
