1 /*
2 * R8A7795 ES2.0+ processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015-2017 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/sys_soc.h>
13
14 #include "core.h"
15 #include "sh_pfc.h"
16
17 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
21 #define CPU_ALL_PORT(fn, sfx) \
22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
34 /*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39 /* GPSR0 */
40 #define GPSR0_15 F_(D15, IP7_11_8)
41 #define GPSR0_14 F_(D14, IP7_7_4)
42 #define GPSR0_13 F_(D13, IP7_3_0)
43 #define GPSR0_12 F_(D12, IP6_31_28)
44 #define GPSR0_11 F_(D11, IP6_27_24)
45 #define GPSR0_10 F_(D10, IP6_23_20)
46 #define GPSR0_9 F_(D9, IP6_19_16)
47 #define GPSR0_8 F_(D8, IP6_15_12)
48 #define GPSR0_7 F_(D7, IP6_11_8)
49 #define GPSR0_6 F_(D6, IP6_7_4)
50 #define GPSR0_5 F_(D5, IP6_3_0)
51 #define GPSR0_4 F_(D4, IP5_31_28)
52 #define GPSR0_3 F_(D3, IP5_27_24)
53 #define GPSR0_2 F_(D2, IP5_23_20)
54 #define GPSR0_1 F_(D1, IP5_19_16)
55 #define GPSR0_0 F_(D0, IP5_15_12)
56
57 /* GPSR1 */
58 #define GPSR1_28 FM(CLKOUT)
59 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
60 #define GPSR1_26 F_(WE1_N, IP5_7_4)
61 #define GPSR1_25 F_(WE0_N, IP5_3_0)
62 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
63 #define GPSR1_23 F_(RD_N, IP4_27_24)
64 #define GPSR1_22 F_(BS_N, IP4_23_20)
65 #define GPSR1_21 F_(CS1_N, IP4_19_16)
66 #define GPSR1_20 F_(CS0_N, IP4_15_12)
67 #define GPSR1_19 F_(A19, IP4_11_8)
68 #define GPSR1_18 F_(A18, IP4_7_4)
69 #define GPSR1_17 F_(A17, IP4_3_0)
70 #define GPSR1_16 F_(A16, IP3_31_28)
71 #define GPSR1_15 F_(A15, IP3_27_24)
72 #define GPSR1_14 F_(A14, IP3_23_20)
73 #define GPSR1_13 F_(A13, IP3_19_16)
74 #define GPSR1_12 F_(A12, IP3_15_12)
75 #define GPSR1_11 F_(A11, IP3_11_8)
76 #define GPSR1_10 F_(A10, IP3_7_4)
77 #define GPSR1_9 F_(A9, IP3_3_0)
78 #define GPSR1_8 F_(A8, IP2_31_28)
79 #define GPSR1_7 F_(A7, IP2_27_24)
80 #define GPSR1_6 F_(A6, IP2_23_20)
81 #define GPSR1_5 F_(A5, IP2_19_16)
82 #define GPSR1_4 F_(A4, IP2_15_12)
83 #define GPSR1_3 F_(A3, IP2_11_8)
84 #define GPSR1_2 F_(A2, IP2_7_4)
85 #define GPSR1_1 F_(A1, IP2_3_0)
86 #define GPSR1_0 F_(A0, IP1_31_28)
87
88 /* GPSR2 */
89 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
90 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
91 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
92 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
93 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
94 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
95 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
96 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
97 #define GPSR2_6 F_(PWM0, IP1_19_16)
98 #define GPSR2_5 F_(IRQ5, IP1_15_12)
99 #define GPSR2_4 F_(IRQ4, IP1_11_8)
100 #define GPSR2_3 F_(IRQ3, IP1_7_4)
101 #define GPSR2_2 F_(IRQ2, IP1_3_0)
102 #define GPSR2_1 F_(IRQ1, IP0_31_28)
103 #define GPSR2_0 F_(IRQ0, IP0_27_24)
104
105 /* GPSR3 */
106 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
107 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
108 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
109 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
110 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
111 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
112 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
113 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
114 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
115 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
116 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
117 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
118 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
119 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
120 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
121 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
122
123 /* GPSR4 */
124 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
125 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
126 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
127 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
128 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
129 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
130 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
131 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
132 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
133 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
134 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
135 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
136 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
137 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
138 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
139 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
140 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
141 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
142
143 /* GPSR5 */
144 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
145 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
146 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
147 #define GPSR5_22 FM(MSIOF0_RXD)
148 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
149 #define GPSR5_20 FM(MSIOF0_TXD)
150 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
151 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
152 #define GPSR5_17 FM(MSIOF0_SCK)
153 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
154 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
155 #define GPSR5_14 F_(HTX0, IP13_19_16)
156 #define GPSR5_13 F_(HRX0, IP13_15_12)
157 #define GPSR5_12 F_(HSCK0, IP13_11_8)
158 #define GPSR5_11 F_(RX2_A, IP13_7_4)
159 #define GPSR5_10 F_(TX2_A, IP13_3_0)
160 #define GPSR5_9 F_(SCK2, IP12_31_28)
161 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
162 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
163 #define GPSR5_6 F_(TX1_A, IP12_19_16)
164 #define GPSR5_5 F_(RX1_A, IP12_15_12)
165 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
166 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
167 #define GPSR5_2 F_(TX0, IP12_3_0)
168 #define GPSR5_1 F_(RX0, IP11_31_28)
169 #define GPSR5_0 F_(SCK0, IP11_27_24)
170
171 /* GPSR6 */
172 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
173 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
174 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
175 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
176 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
177 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
178 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
179 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
180 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
181 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
182 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
183 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
184 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
185 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
186 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
187 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
188 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
189 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
190 #define GPSR6_13 FM(SSI_SDATA5)
191 #define GPSR6_12 FM(SSI_WS5)
192 #define GPSR6_11 FM(SSI_SCK5)
193 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
194 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
195 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
196 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
197 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
198 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
199 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
200 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
201 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
202 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
203 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
204
205 /* GPSR7 */
206 #define GPSR7_3 FM(HDMI1_CEC)
207 #define GPSR7_2 FM(HDMI0_CEC)
208 #define GPSR7_1 FM(AVS2)
209 #define GPSR7_0 FM(AVS1)
210
211
212 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
213 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232
233 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
234 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275
276 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
277 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307
308 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
309 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
330 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337
338 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
339 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
359 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
360 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
361 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
362 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
363 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
365 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
366
367 #define PINMUX_GPSR \
368 \
369 GPSR6_31 \
370 GPSR6_30 \
371 GPSR6_29 \
372 GPSR1_28 GPSR6_28 \
373 GPSR1_27 GPSR6_27 \
374 GPSR1_26 GPSR6_26 \
375 GPSR1_25 GPSR5_25 GPSR6_25 \
376 GPSR1_24 GPSR5_24 GPSR6_24 \
377 GPSR1_23 GPSR5_23 GPSR6_23 \
378 GPSR1_22 GPSR5_22 GPSR6_22 \
379 GPSR1_21 GPSR5_21 GPSR6_21 \
380 GPSR1_20 GPSR5_20 GPSR6_20 \
381 GPSR1_19 GPSR5_19 GPSR6_19 \
382 GPSR1_18 GPSR5_18 GPSR6_18 \
383 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
384 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
385 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
386 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
387 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
388 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
389 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
390 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
391 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
392 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
393 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
394 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
395 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
396 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
397 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
398 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
399 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
400 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
401
402 #define PINMUX_IPSR \
403 \
404 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
405 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
406 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
407 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
408 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
409 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
410 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
411 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
412 \
413 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
414 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
415 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
416 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
417 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
418 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
419 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
420 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
421 \
422 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
423 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
424 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
425 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
426 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
427 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
428 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
429 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
430 \
431 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
432 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
433 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
434 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
435 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
436 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
437 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
438 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
439 \
440 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
441 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
442 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
443 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
444 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
445 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
446 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
447 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
448
449 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
450 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
451 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
452 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
453 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
454 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
455 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
456 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
457 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
458 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
459 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
460 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
461 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
462 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
463 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
464 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
465 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
466 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
467 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
468
469 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
470 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
473 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
476 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
477 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
478 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
479 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
480 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
483 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
484 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
487 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
488 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
489 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
490 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
491 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
492
493 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
494 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
495 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
496 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
497 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
501 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
502 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
503 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
504 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
505 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
506
507 #define PINMUX_MOD_SELS \
508 \
509 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
510 MOD_SEL2_30 \
511 MOD_SEL1_29_28_27 MOD_SEL2_29 \
512 MOD_SEL0_28_27 MOD_SEL2_28_27 \
513 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
514 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
515 MOD_SEL0_23 MOD_SEL1_23_22_21 \
516 MOD_SEL0_22 \
517 MOD_SEL0_21 MOD_SEL2_21 \
518 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
519 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
520 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
521 MOD_SEL2_17 \
522 MOD_SEL0_16 MOD_SEL1_16 \
523 MOD_SEL1_15_14 \
524 MOD_SEL0_14_13 \
525 MOD_SEL1_13 \
526 MOD_SEL0_12 MOD_SEL1_12 \
527 MOD_SEL0_11 MOD_SEL1_11 \
528 MOD_SEL0_10 MOD_SEL1_10 \
529 MOD_SEL0_9_8 MOD_SEL1_9 \
530 MOD_SEL0_7_6 \
531 MOD_SEL1_6 \
532 MOD_SEL0_5 MOD_SEL1_5 \
533 MOD_SEL0_4_3 MOD_SEL1_4 \
534 MOD_SEL1_3 \
535 MOD_SEL1_2 \
536 MOD_SEL1_1 \
537 MOD_SEL1_0 MOD_SEL2_0
538
539 /*
540 * These pins are not able to be muxed but have other properties
541 * that can be set, such as drive-strength or pull-up/pull-down enable.
542 */
543 #define PINMUX_STATIC \
544 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
545 FM(QSPI0_IO2) FM(QSPI0_IO3) \
546 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
547 FM(QSPI1_IO2) FM(QSPI1_IO3) \
548 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
549 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
550 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
551 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
552 FM(PRESETOUT) \
553 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
554 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
555
556 enum {
557 PINMUX_RESERVED = 0,
558
559 PINMUX_DATA_BEGIN,
560 GP_ALL(DATA),
561 PINMUX_DATA_END,
562
563 #define F_(x, y)
564 #define FM(x) FN_##x,
565 PINMUX_FUNCTION_BEGIN,
566 GP_ALL(FN),
567 PINMUX_GPSR
568 PINMUX_IPSR
569 PINMUX_MOD_SELS
570 PINMUX_FUNCTION_END,
571 #undef F_
572 #undef FM
573
574 #define F_(x, y)
575 #define FM(x) x##_MARK,
576 PINMUX_MARK_BEGIN,
577 PINMUX_GPSR
578 PINMUX_IPSR
579 PINMUX_MOD_SELS
580 PINMUX_STATIC
581 PINMUX_MARK_END,
582 #undef F_
583 #undef FM
584 };
585
586 static const u16 pinmux_data[] = {
587 PINMUX_DATA_GP_ALL(),
588
589 PINMUX_SINGLE(AVS1),
590 PINMUX_SINGLE(AVS2),
591 PINMUX_SINGLE(CLKOUT),
592 PINMUX_SINGLE(HDMI0_CEC),
593 PINMUX_SINGLE(HDMI1_CEC),
594 PINMUX_SINGLE(I2C_SEL_0_1),
595 PINMUX_SINGLE(I2C_SEL_3_1),
596 PINMUX_SINGLE(I2C_SEL_5_1),
597 PINMUX_SINGLE(MSIOF0_RXD),
598 PINMUX_SINGLE(MSIOF0_SCK),
599 PINMUX_SINGLE(MSIOF0_TXD),
600 PINMUX_SINGLE(SSI_SCK5),
601 PINMUX_SINGLE(SSI_SDATA5),
602 PINMUX_SINGLE(SSI_WS5),
603
604 /* IPSR0 */
605 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
606 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
607
608 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
609 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
611
612 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
613 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
615
616 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
617 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
619
620 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
621 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
623 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
624
625 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
626 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
627 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
628
629 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
630 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
631 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
632 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
636
637 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
638 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
639 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
640 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
644
645 /* IPSR1 */
646 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
647 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
648 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
649 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
651 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
652
653 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
654 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
655 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
656 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
657 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
659
660 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
661 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
662 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
663 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
665 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
666
667 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
668 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
669 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
670 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
671 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
672 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
673 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
674
675 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
676 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
677 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
678 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
679
680 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
681 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
682 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
683 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
684
685 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
686 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
687 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
688
689 PINMUX_IPSR_GPSR(IP1_31_28, A0),
690 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
691 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
692 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
693 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
694 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
695
696 /* IPSR2 */
697 PINMUX_IPSR_GPSR(IP2_3_0, A1),
698 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
699 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
700 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
701 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
702 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
703
704 PINMUX_IPSR_GPSR(IP2_7_4, A2),
705 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
706 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
707 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
708 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
709 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
710
711 PINMUX_IPSR_GPSR(IP2_11_8, A3),
712 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
713 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
714 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
715 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
716 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
717
718 PINMUX_IPSR_GPSR(IP2_15_12, A4),
719 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
720 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
721 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
722 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
723 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
724
725 PINMUX_IPSR_GPSR(IP2_19_16, A5),
726 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
727 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
728 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
729 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
730 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
731 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
732
733 PINMUX_IPSR_GPSR(IP2_23_20, A6),
734 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
735 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
736 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
737 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
738 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
739 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
740
741 PINMUX_IPSR_GPSR(IP2_27_24, A7),
742 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
743 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
744 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
745 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
746 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
747 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
748
749 PINMUX_IPSR_GPSR(IP2_31_28, A8),
750 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
751 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
752 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
753 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
754 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
756
757 /* IPSR3 */
758 PINMUX_IPSR_GPSR(IP3_3_0, A9),
759 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
760 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
761 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
762
763 PINMUX_IPSR_GPSR(IP3_7_4, A10),
764 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
765 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
766 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
767
768 PINMUX_IPSR_GPSR(IP3_11_8, A11),
769 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
770 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
771 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
772 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
773 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
774 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
775 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
776 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
777
778 PINMUX_IPSR_GPSR(IP3_15_12, A12),
779 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
780 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
781 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
782 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
783 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
784
785 PINMUX_IPSR_GPSR(IP3_19_16, A13),
786 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
787 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
788 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
789 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
790 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
791
792 PINMUX_IPSR_GPSR(IP3_23_20, A14),
793 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
794 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
795 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
796 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
797 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
798
799 PINMUX_IPSR_GPSR(IP3_27_24, A15),
800 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
801 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
802 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
803 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
804 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
805
806 PINMUX_IPSR_GPSR(IP3_31_28, A16),
807 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
808 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
809 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
810
811 /* IPSR4 */
812 PINMUX_IPSR_GPSR(IP4_3_0, A17),
813 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
814 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
815 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
816
817 PINMUX_IPSR_GPSR(IP4_7_4, A18),
818 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
819 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
820 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
821
822 PINMUX_IPSR_GPSR(IP4_11_8, A19),
823 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
824 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
825 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
826
827 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
828 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
829
830 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
831 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
832 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
833
834 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
835 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
836 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
837 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
838 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
839 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
840 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
841 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
842
843 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
844 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
845 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
846 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
847 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
848 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
849
850 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
851 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
852 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
855 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
856
857 /* IPSR5 */
858 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
859 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
860 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
861 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
862 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
863 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
864 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
865
866 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
867 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
868 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
869 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
870 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
871 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
872 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
873 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
874
875 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
876 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
877 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
878 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
879
880 PINMUX_IPSR_GPSR(IP5_15_12, D0),
881 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
882 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
883 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
884 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
885
886 PINMUX_IPSR_GPSR(IP5_19_16, D1),
887 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
888 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
889 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
890 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
891
892 PINMUX_IPSR_GPSR(IP5_23_20, D2),
893 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
894 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
895 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
896
897 PINMUX_IPSR_GPSR(IP5_27_24, D3),
898 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
899 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
900 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
901
902 PINMUX_IPSR_GPSR(IP5_31_28, D4),
903 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
904 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
905 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
906
907 /* IPSR6 */
908 PINMUX_IPSR_GPSR(IP6_3_0, D5),
909 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
910 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
911 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
912
913 PINMUX_IPSR_GPSR(IP6_7_4, D6),
914 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
915 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
916 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
917
918 PINMUX_IPSR_GPSR(IP6_11_8, D7),
919 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
920 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
921 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
922
923 PINMUX_IPSR_GPSR(IP6_15_12, D8),
924 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
925 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
926 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
927 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
928 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
929
930 PINMUX_IPSR_GPSR(IP6_19_16, D9),
931 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
932 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
933 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
934 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
935
936 PINMUX_IPSR_GPSR(IP6_23_20, D10),
937 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
938 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
939 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
940 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
941 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
942 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
943
944 PINMUX_IPSR_GPSR(IP6_27_24, D11),
945 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
946 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
947 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
948 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
949 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
950 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
951
952 PINMUX_IPSR_GPSR(IP6_31_28, D12),
953 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
954 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
955 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
956 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
957 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
958
959 /* IPSR7 */
960 PINMUX_IPSR_GPSR(IP7_3_0, D13),
961 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
962 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
963 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
964 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
965 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
966
967 PINMUX_IPSR_GPSR(IP7_7_4, D14),
968 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
969 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
970 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
971 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
972 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
973 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
974
975 PINMUX_IPSR_GPSR(IP7_11_8, D15),
976 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
977 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
978 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
979 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
980 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
981 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
982
983 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
984 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
985 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
986
987 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
988 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
989 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
990
991 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
992 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
994 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
995
996 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
997 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
998 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
999 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1000
1001 /* IPSR8 */
1002 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1003 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1004 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1005 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1006
1007 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1008 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1009 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1010 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1011
1012 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1013 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1014 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1015
1016 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1017 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1019 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1020 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1021
1022 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1023 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1024 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1025 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1026 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1027 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1028
1029 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1030 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1031 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1032 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1033 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1034 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1035
1036 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1037 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1038 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1039 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1040 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1041 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1042
1043 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1044 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1045 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1046 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1047 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1048 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1049
1050 /* IPSR9 */
1051 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1052 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1053
1054 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1055 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1056
1057 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1058 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1059
1060 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1061 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1062
1063 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1064 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1065
1066 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1067 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1068
1069 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1070 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1071 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1072
1073 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1074 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1075
1076 /* IPSR10 */
1077 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1078 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1079
1080 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1081 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1082
1083 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1084 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1085
1086 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1087 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1088
1089 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1090 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1091
1092 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1093 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1094 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1095
1096 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1097 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1099
1100 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1101 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1102 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1103
1104 /* IPSR11 */
1105 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1106 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1107 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1108
1109 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1110 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1111
1112 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1113 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1114 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1115
1116 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1117 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1118
1119 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1120 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1121
1122 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1123 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1124
1125 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1126 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1127 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1128 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1129 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1132 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1133 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1135
1136 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1137 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1138 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1139 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1140 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1141
1142 /* IPSR12 */
1143 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1144 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1145 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1146 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1147 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1148
1149 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1150 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1151 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1152 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1153 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1154 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1155 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1156 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1157
1158 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1159 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1160 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1161 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1162 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1163 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1164 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1165 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1166
1167 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1168 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1169 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1170 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1171 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1172
1173 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1175 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1176 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1177 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1178
1179 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1180 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1181 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1182 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1183 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1184 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1185 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1186
1187 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1188 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1189 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1190 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1191 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1192 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1193 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1194
1195 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1196 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1197 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1198 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1199 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1200 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1201 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1202
1203 /* IPSR13 */
1204 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1205 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1206 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1207 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1208 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1209 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1210
1211 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1212 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1213 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1214 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1215 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1216 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1217
1218 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1219 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1220 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1221 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1222 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1223 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1225 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1226
1227 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1228 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1229 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1230 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1231 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1232 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1233
1234 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1235 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1236 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1237 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1238 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1239 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1240
1241 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1242 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1243 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1244 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1245 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1246 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1247 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1248 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1249
1250 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1251 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1252 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1253 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1254 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1255 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1256 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1257
1258 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1259 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1260 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1261 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1262
1263 /* IPSR14 */
1264 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1265 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1266 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
1267 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1268 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1269 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1270 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1271 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1272
1273 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1274 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1275 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1276 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1277 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1278 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1279 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1280 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1281
1282 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1283 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1284 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1285
1286 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1287 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1288 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1289 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1290
1291 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1292 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1293 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1294
1295 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1296 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1297
1298 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1299 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1300
1301 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1302 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1303
1304 /* IPSR15 */
1305 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1306
1307 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1308 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1309
1310 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1311 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1312 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1313
1314 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1315 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1316 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1317 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1318
1319 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1320 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1321 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1322 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1323 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1324 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1326
1327 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1328 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1329 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1330 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1332 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1334
1335 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1336 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1337 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1338 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1340 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1342
1343 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1344 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1345 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1346 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1348 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1350
1351 /* IPSR16 */
1352 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1353 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1354 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1355
1356 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1357 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1358 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1361 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1362 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1363
1364 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1365 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1366 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1367 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1368 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1369 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1370 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1371
1372 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1373 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1374 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1375 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1377 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1378 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1379
1380 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1381 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1382 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1383 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1385 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1386 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1387 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1388
1389 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1390 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1391 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1392 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1393 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1394 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1395 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1396
1397 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1398 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1399 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1400 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1401 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1402 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1403 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1404 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1405
1406 /* IPSR17 */
1407 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1408 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1409
1410 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1411 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1412 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1413 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1414 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1415
1416 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1417 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1418 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1419 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1420 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1421 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1422 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1423
1424 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1425 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1426 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1427 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1428 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1429 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1430
1431 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1432 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1433 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1434 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1435 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1436 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1437 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1438 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1439 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1440
1441 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1442 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1443 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1444 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1445 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1446 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1447 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1448 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1449 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1450
1451 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1452 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1453 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1454 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1455 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1456 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1457 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1458 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1459 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1460 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1461 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1462
1463 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1464 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1465 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1466 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1467 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1468 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1469 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1470 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1471 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1472
1473 /* IPSR18 */
1474 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1475 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1476 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1477 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1478 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1479 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1480 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1481 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1482 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1483
1484 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1485 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1486 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1487 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1488 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1489 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1490 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1491 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1492 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1493
1494 /*
1495 * Static pins can not be muxed between different functions but
1496 * still need mark entries in the pinmux list. Add each static
1497 * pin to the list without an associated function. The sh-pfc
1498 * core will do the right thing and skip trying to mux the pin
1499 * while still applying configuration to it.
1500 */
1501 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1502 PINMUX_STATIC
1503 #undef FM
1504 };
1505
1506 /*
1507 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1508 * Physical layout rows: A - AW, cols: 1 - 39.
1509 */
1510 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1511 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1512 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1513 #define PIN_NONE U16_MAX
1514
1515 static const struct sh_pfc_pin pinmux_pins[] = {
1516 PINMUX_GPIO_GP_ALL(),
1517
1518 /*
1519 * Pins not associated with a GPIO port.
1520 *
1521 * The pin positions are different between different r8a7795
1522 * packages, all that is needed for the pfc driver is a unique
1523 * number for each pin. To this end use the pin layout from
1524 * R-Car H3SiP to calculate a unique number for each pin.
1525 */
1526 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1527 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1528 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1529 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1530 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1569 };
1570
1571 /* - AUDIO CLOCK ------------------------------------------------------------ */
1572 static const unsigned int audio_clk_a_a_pins[] = {
1573 /* CLK A */
1574 RCAR_GP_PIN(6, 22),
1575 };
1576 static const unsigned int audio_clk_a_a_mux[] = {
1577 AUDIO_CLKA_A_MARK,
1578 };
1579 static const unsigned int audio_clk_a_b_pins[] = {
1580 /* CLK A */
1581 RCAR_GP_PIN(5, 4),
1582 };
1583 static const unsigned int audio_clk_a_b_mux[] = {
1584 AUDIO_CLKA_B_MARK,
1585 };
1586 static const unsigned int audio_clk_a_c_pins[] = {
1587 /* CLK A */
1588 RCAR_GP_PIN(5, 19),
1589 };
1590 static const unsigned int audio_clk_a_c_mux[] = {
1591 AUDIO_CLKA_C_MARK,
1592 };
1593 static const unsigned int audio_clk_b_a_pins[] = {
1594 /* CLK B */
1595 RCAR_GP_PIN(5, 12),
1596 };
1597 static const unsigned int audio_clk_b_a_mux[] = {
1598 AUDIO_CLKB_A_MARK,
1599 };
1600 static const unsigned int audio_clk_b_b_pins[] = {
1601 /* CLK B */
1602 RCAR_GP_PIN(6, 23),
1603 };
1604 static const unsigned int audio_clk_b_b_mux[] = {
1605 AUDIO_CLKB_B_MARK,
1606 };
1607 static const unsigned int audio_clk_c_a_pins[] = {
1608 /* CLK C */
1609 RCAR_GP_PIN(5, 21),
1610 };
1611 static const unsigned int audio_clk_c_a_mux[] = {
1612 AUDIO_CLKC_A_MARK,
1613 };
1614 static const unsigned int audio_clk_c_b_pins[] = {
1615 /* CLK C */
1616 RCAR_GP_PIN(5, 0),
1617 };
1618 static const unsigned int audio_clk_c_b_mux[] = {
1619 AUDIO_CLKC_B_MARK,
1620 };
1621 static const unsigned int audio_clkout_a_pins[] = {
1622 /* CLKOUT */
1623 RCAR_GP_PIN(5, 18),
1624 };
1625 static const unsigned int audio_clkout_a_mux[] = {
1626 AUDIO_CLKOUT_A_MARK,
1627 };
1628 static const unsigned int audio_clkout_b_pins[] = {
1629 /* CLKOUT */
1630 RCAR_GP_PIN(6, 28),
1631 };
1632 static const unsigned int audio_clkout_b_mux[] = {
1633 AUDIO_CLKOUT_B_MARK,
1634 };
1635 static const unsigned int audio_clkout_c_pins[] = {
1636 /* CLKOUT */
1637 RCAR_GP_PIN(5, 3),
1638 };
1639 static const unsigned int audio_clkout_c_mux[] = {
1640 AUDIO_CLKOUT_C_MARK,
1641 };
1642 static const unsigned int audio_clkout_d_pins[] = {
1643 /* CLKOUT */
1644 RCAR_GP_PIN(5, 21),
1645 };
1646 static const unsigned int audio_clkout_d_mux[] = {
1647 AUDIO_CLKOUT_D_MARK,
1648 };
1649 static const unsigned int audio_clkout1_a_pins[] = {
1650 /* CLKOUT1 */
1651 RCAR_GP_PIN(5, 15),
1652 };
1653 static const unsigned int audio_clkout1_a_mux[] = {
1654 AUDIO_CLKOUT1_A_MARK,
1655 };
1656 static const unsigned int audio_clkout1_b_pins[] = {
1657 /* CLKOUT1 */
1658 RCAR_GP_PIN(6, 29),
1659 };
1660 static const unsigned int audio_clkout1_b_mux[] = {
1661 AUDIO_CLKOUT1_B_MARK,
1662 };
1663 static const unsigned int audio_clkout2_a_pins[] = {
1664 /* CLKOUT2 */
1665 RCAR_GP_PIN(5, 16),
1666 };
1667 static const unsigned int audio_clkout2_a_mux[] = {
1668 AUDIO_CLKOUT2_A_MARK,
1669 };
1670 static const unsigned int audio_clkout2_b_pins[] = {
1671 /* CLKOUT2 */
1672 RCAR_GP_PIN(6, 30),
1673 };
1674 static const unsigned int audio_clkout2_b_mux[] = {
1675 AUDIO_CLKOUT2_B_MARK,
1676 };
1677 static const unsigned int audio_clkout3_a_pins[] = {
1678 /* CLKOUT3 */
1679 RCAR_GP_PIN(5, 19),
1680 };
1681 static const unsigned int audio_clkout3_a_mux[] = {
1682 AUDIO_CLKOUT3_A_MARK,
1683 };
1684 static const unsigned int audio_clkout3_b_pins[] = {
1685 /* CLKOUT3 */
1686 RCAR_GP_PIN(6, 31),
1687 };
1688 static const unsigned int audio_clkout3_b_mux[] = {
1689 AUDIO_CLKOUT3_B_MARK,
1690 };
1691
1692 /* - EtherAVB --------------------------------------------------------------- */
1693 static const unsigned int avb_link_pins[] = {
1694 /* AVB_LINK */
1695 RCAR_GP_PIN(2, 12),
1696 };
1697 static const unsigned int avb_link_mux[] = {
1698 AVB_LINK_MARK,
1699 };
1700 static const unsigned int avb_magic_pins[] = {
1701 /* AVB_MAGIC_ */
1702 RCAR_GP_PIN(2, 10),
1703 };
1704 static const unsigned int avb_magic_mux[] = {
1705 AVB_MAGIC_MARK,
1706 };
1707 static const unsigned int avb_phy_int_pins[] = {
1708 /* AVB_PHY_INT */
1709 RCAR_GP_PIN(2, 11),
1710 };
1711 static const unsigned int avb_phy_int_mux[] = {
1712 AVB_PHY_INT_MARK,
1713 };
1714 static const unsigned int avb_mdio_pins[] = {
1715 /* AVB_MDC, AVB_MDIO */
1716 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1717 };
1718 static const unsigned int avb_mdio_mux[] = {
1719 AVB_MDC_MARK, AVB_MDIO_MARK,
1720 };
1721 static const unsigned int avb_mii_pins[] = {
1722 /*
1723 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1724 * AVB_TD1, AVB_TD2, AVB_TD3,
1725 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1726 * AVB_RD1, AVB_RD2, AVB_RD3,
1727 * AVB_TXCREFCLK
1728 */
1729 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1730 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1731 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1732 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1733 PIN_NUMBER('A', 12),
1734
1735 };
1736 static const unsigned int avb_mii_mux[] = {
1737 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1738 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1739 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1740 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1741 AVB_TXCREFCLK_MARK,
1742 };
1743 static const unsigned int avb_avtp_pps_pins[] = {
1744 /* AVB_AVTP_PPS */
1745 RCAR_GP_PIN(2, 6),
1746 };
1747 static const unsigned int avb_avtp_pps_mux[] = {
1748 AVB_AVTP_PPS_MARK,
1749 };
1750 static const unsigned int avb_avtp_match_a_pins[] = {
1751 /* AVB_AVTP_MATCH_A */
1752 RCAR_GP_PIN(2, 13),
1753 };
1754 static const unsigned int avb_avtp_match_a_mux[] = {
1755 AVB_AVTP_MATCH_A_MARK,
1756 };
1757 static const unsigned int avb_avtp_capture_a_pins[] = {
1758 /* AVB_AVTP_CAPTURE_A */
1759 RCAR_GP_PIN(2, 14),
1760 };
1761 static const unsigned int avb_avtp_capture_a_mux[] = {
1762 AVB_AVTP_CAPTURE_A_MARK,
1763 };
1764 static const unsigned int avb_avtp_match_b_pins[] = {
1765 /* AVB_AVTP_MATCH_B */
1766 RCAR_GP_PIN(1, 8),
1767 };
1768 static const unsigned int avb_avtp_match_b_mux[] = {
1769 AVB_AVTP_MATCH_B_MARK,
1770 };
1771 static const unsigned int avb_avtp_capture_b_pins[] = {
1772 /* AVB_AVTP_CAPTURE_B */
1773 RCAR_GP_PIN(1, 11),
1774 };
1775 static const unsigned int avb_avtp_capture_b_mux[] = {
1776 AVB_AVTP_CAPTURE_B_MARK,
1777 };
1778
1779 /* - CAN ------------------------------------------------------------------ */
1780 static const unsigned int can0_data_a_pins[] = {
1781 /* TX, RX */
1782 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1783 };
1784 static const unsigned int can0_data_a_mux[] = {
1785 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1786 };
1787 static const unsigned int can0_data_b_pins[] = {
1788 /* TX, RX */
1789 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1790 };
1791 static const unsigned int can0_data_b_mux[] = {
1792 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1793 };
1794 static const unsigned int can1_data_pins[] = {
1795 /* TX, RX */
1796 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1797 };
1798 static const unsigned int can1_data_mux[] = {
1799 CAN1_TX_MARK, CAN1_RX_MARK,
1800 };
1801
1802 /* - CAN Clock -------------------------------------------------------------- */
1803 static const unsigned int can_clk_pins[] = {
1804 /* CLK */
1805 RCAR_GP_PIN(1, 25),
1806 };
1807 static const unsigned int can_clk_mux[] = {
1808 CAN_CLK_MARK,
1809 };
1810
1811 /* - CAN FD --------------------------------------------------------------- */
1812 static const unsigned int canfd0_data_a_pins[] = {
1813 /* TX, RX */
1814 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1815 };
1816 static const unsigned int canfd0_data_a_mux[] = {
1817 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1818 };
1819 static const unsigned int canfd0_data_b_pins[] = {
1820 /* TX, RX */
1821 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1822 };
1823 static const unsigned int canfd0_data_b_mux[] = {
1824 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1825 };
1826 static const unsigned int canfd1_data_pins[] = {
1827 /* TX, RX */
1828 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1829 };
1830 static const unsigned int canfd1_data_mux[] = {
1831 CANFD1_TX_MARK, CANFD1_RX_MARK,
1832 };
1833
1834 /* - DRIF0 --------------------------------------------------------------- */
1835 static const unsigned int drif0_ctrl_a_pins[] = {
1836 /* CLK, SYNC */
1837 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1838 };
1839 static const unsigned int drif0_ctrl_a_mux[] = {
1840 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1841 };
1842 static const unsigned int drif0_data0_a_pins[] = {
1843 /* D0 */
1844 RCAR_GP_PIN(6, 10),
1845 };
1846 static const unsigned int drif0_data0_a_mux[] = {
1847 RIF0_D0_A_MARK,
1848 };
1849 static const unsigned int drif0_data1_a_pins[] = {
1850 /* D1 */
1851 RCAR_GP_PIN(6, 7),
1852 };
1853 static const unsigned int drif0_data1_a_mux[] = {
1854 RIF0_D1_A_MARK,
1855 };
1856 static const unsigned int drif0_ctrl_b_pins[] = {
1857 /* CLK, SYNC */
1858 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1859 };
1860 static const unsigned int drif0_ctrl_b_mux[] = {
1861 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1862 };
1863 static const unsigned int drif0_data0_b_pins[] = {
1864 /* D0 */
1865 RCAR_GP_PIN(5, 1),
1866 };
1867 static const unsigned int drif0_data0_b_mux[] = {
1868 RIF0_D0_B_MARK,
1869 };
1870 static const unsigned int drif0_data1_b_pins[] = {
1871 /* D1 */
1872 RCAR_GP_PIN(5, 2),
1873 };
1874 static const unsigned int drif0_data1_b_mux[] = {
1875 RIF0_D1_B_MARK,
1876 };
1877 static const unsigned int drif0_ctrl_c_pins[] = {
1878 /* CLK, SYNC */
1879 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1880 };
1881 static const unsigned int drif0_ctrl_c_mux[] = {
1882 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1883 };
1884 static const unsigned int drif0_data0_c_pins[] = {
1885 /* D0 */
1886 RCAR_GP_PIN(5, 13),
1887 };
1888 static const unsigned int drif0_data0_c_mux[] = {
1889 RIF0_D0_C_MARK,
1890 };
1891 static const unsigned int drif0_data1_c_pins[] = {
1892 /* D1 */
1893 RCAR_GP_PIN(5, 14),
1894 };
1895 static const unsigned int drif0_data1_c_mux[] = {
1896 RIF0_D1_C_MARK,
1897 };
1898 /* - DRIF1 --------------------------------------------------------------- */
1899 static const unsigned int drif1_ctrl_a_pins[] = {
1900 /* CLK, SYNC */
1901 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1902 };
1903 static const unsigned int drif1_ctrl_a_mux[] = {
1904 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1905 };
1906 static const unsigned int drif1_data0_a_pins[] = {
1907 /* D0 */
1908 RCAR_GP_PIN(6, 19),
1909 };
1910 static const unsigned int drif1_data0_a_mux[] = {
1911 RIF1_D0_A_MARK,
1912 };
1913 static const unsigned int drif1_data1_a_pins[] = {
1914 /* D1 */
1915 RCAR_GP_PIN(6, 20),
1916 };
1917 static const unsigned int drif1_data1_a_mux[] = {
1918 RIF1_D1_A_MARK,
1919 };
1920 static const unsigned int drif1_ctrl_b_pins[] = {
1921 /* CLK, SYNC */
1922 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1923 };
1924 static const unsigned int drif1_ctrl_b_mux[] = {
1925 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1926 };
1927 static const unsigned int drif1_data0_b_pins[] = {
1928 /* D0 */
1929 RCAR_GP_PIN(5, 7),
1930 };
1931 static const unsigned int drif1_data0_b_mux[] = {
1932 RIF1_D0_B_MARK,
1933 };
1934 static const unsigned int drif1_data1_b_pins[] = {
1935 /* D1 */
1936 RCAR_GP_PIN(5, 8),
1937 };
1938 static const unsigned int drif1_data1_b_mux[] = {
1939 RIF1_D1_B_MARK,
1940 };
1941 static const unsigned int drif1_ctrl_c_pins[] = {
1942 /* CLK, SYNC */
1943 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1944 };
1945 static const unsigned int drif1_ctrl_c_mux[] = {
1946 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1947 };
1948 static const unsigned int drif1_data0_c_pins[] = {
1949 /* D0 */
1950 RCAR_GP_PIN(5, 6),
1951 };
1952 static const unsigned int drif1_data0_c_mux[] = {
1953 RIF1_D0_C_MARK,
1954 };
1955 static const unsigned int drif1_data1_c_pins[] = {
1956 /* D1 */
1957 RCAR_GP_PIN(5, 10),
1958 };
1959 static const unsigned int drif1_data1_c_mux[] = {
1960 RIF1_D1_C_MARK,
1961 };
1962 /* - DRIF2 --------------------------------------------------------------- */
1963 static const unsigned int drif2_ctrl_a_pins[] = {
1964 /* CLK, SYNC */
1965 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1966 };
1967 static const unsigned int drif2_ctrl_a_mux[] = {
1968 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1969 };
1970 static const unsigned int drif2_data0_a_pins[] = {
1971 /* D0 */
1972 RCAR_GP_PIN(6, 7),
1973 };
1974 static const unsigned int drif2_data0_a_mux[] = {
1975 RIF2_D0_A_MARK,
1976 };
1977 static const unsigned int drif2_data1_a_pins[] = {
1978 /* D1 */
1979 RCAR_GP_PIN(6, 10),
1980 };
1981 static const unsigned int drif2_data1_a_mux[] = {
1982 RIF2_D1_A_MARK,
1983 };
1984 static const unsigned int drif2_ctrl_b_pins[] = {
1985 /* CLK, SYNC */
1986 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1987 };
1988 static const unsigned int drif2_ctrl_b_mux[] = {
1989 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1990 };
1991 static const unsigned int drif2_data0_b_pins[] = {
1992 /* D0 */
1993 RCAR_GP_PIN(6, 30),
1994 };
1995 static const unsigned int drif2_data0_b_mux[] = {
1996 RIF2_D0_B_MARK,
1997 };
1998 static const unsigned int drif2_data1_b_pins[] = {
1999 /* D1 */
2000 RCAR_GP_PIN(6, 31),
2001 };
2002 static const unsigned int drif2_data1_b_mux[] = {
2003 RIF2_D1_B_MARK,
2004 };
2005 /* - DRIF3 --------------------------------------------------------------- */
2006 static const unsigned int drif3_ctrl_a_pins[] = {
2007 /* CLK, SYNC */
2008 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2009 };
2010 static const unsigned int drif3_ctrl_a_mux[] = {
2011 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2012 };
2013 static const unsigned int drif3_data0_a_pins[] = {
2014 /* D0 */
2015 RCAR_GP_PIN(6, 19),
2016 };
2017 static const unsigned int drif3_data0_a_mux[] = {
2018 RIF3_D0_A_MARK,
2019 };
2020 static const unsigned int drif3_data1_a_pins[] = {
2021 /* D1 */
2022 RCAR_GP_PIN(6, 20),
2023 };
2024 static const unsigned int drif3_data1_a_mux[] = {
2025 RIF3_D1_A_MARK,
2026 };
2027 static const unsigned int drif3_ctrl_b_pins[] = {
2028 /* CLK, SYNC */
2029 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2030 };
2031 static const unsigned int drif3_ctrl_b_mux[] = {
2032 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2033 };
2034 static const unsigned int drif3_data0_b_pins[] = {
2035 /* D0 */
2036 RCAR_GP_PIN(6, 28),
2037 };
2038 static const unsigned int drif3_data0_b_mux[] = {
2039 RIF3_D0_B_MARK,
2040 };
2041 static const unsigned int drif3_data1_b_pins[] = {
2042 /* D1 */
2043 RCAR_GP_PIN(6, 29),
2044 };
2045 static const unsigned int drif3_data1_b_mux[] = {
2046 RIF3_D1_B_MARK,
2047 };
2048
2049 /* - DU --------------------------------------------------------------------- */
2050 static const unsigned int du_rgb666_pins[] = {
2051 /* R[7:2], G[7:2], B[7:2] */
2052 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2053 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2054 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2055 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2056 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2057 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2058 };
2059 static const unsigned int du_rgb666_mux[] = {
2060 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2061 DU_DR3_MARK, DU_DR2_MARK,
2062 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2063 DU_DG3_MARK, DU_DG2_MARK,
2064 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2065 DU_DB3_MARK, DU_DB2_MARK,
2066 };
2067 static const unsigned int du_rgb888_pins[] = {
2068 /* R[7:0], G[7:0], B[7:0] */
2069 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2070 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2071 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2072 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2073 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2074 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2075 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2076 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2077 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2078 };
2079 static const unsigned int du_rgb888_mux[] = {
2080 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2081 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2082 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2083 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2084 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2085 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2086 };
2087 static const unsigned int du_clk_out_0_pins[] = {
2088 /* CLKOUT */
2089 RCAR_GP_PIN(1, 27),
2090 };
2091 static const unsigned int du_clk_out_0_mux[] = {
2092 DU_DOTCLKOUT0_MARK
2093 };
2094 static const unsigned int du_clk_out_1_pins[] = {
2095 /* CLKOUT */
2096 RCAR_GP_PIN(2, 3),
2097 };
2098 static const unsigned int du_clk_out_1_mux[] = {
2099 DU_DOTCLKOUT1_MARK
2100 };
2101 static const unsigned int du_sync_pins[] = {
2102 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2103 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2104 };
2105 static const unsigned int du_sync_mux[] = {
2106 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2107 };
2108 static const unsigned int du_oddf_pins[] = {
2109 /* EXDISP/EXODDF/EXCDE */
2110 RCAR_GP_PIN(2, 2),
2111 };
2112 static const unsigned int du_oddf_mux[] = {
2113 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2114 };
2115 static const unsigned int du_cde_pins[] = {
2116 /* CDE */
2117 RCAR_GP_PIN(2, 0),
2118 };
2119 static const unsigned int du_cde_mux[] = {
2120 DU_CDE_MARK,
2121 };
2122 static const unsigned int du_disp_pins[] = {
2123 /* DISP */
2124 RCAR_GP_PIN(2, 1),
2125 };
2126 static const unsigned int du_disp_mux[] = {
2127 DU_DISP_MARK,
2128 };
2129
2130 /* - HDMI ------------------------------------------------------------------- */
2131 static const unsigned int hdmi0_cec_pins[] = {
2132 /* HDMI0_CEC */
2133 RCAR_GP_PIN(7, 2),
2134 };
2135 static const unsigned int hdmi0_cec_mux[] = {
2136 HDMI0_CEC_MARK,
2137 };
2138 static const unsigned int hdmi1_cec_pins[] = {
2139 /* HDMI1_CEC */
2140 RCAR_GP_PIN(7, 3),
2141 };
2142 static const unsigned int hdmi1_cec_mux[] = {
2143 HDMI1_CEC_MARK,
2144 };
2145
2146 /* - HSCIF0 ----------------------------------------------------------------- */
2147 static const unsigned int hscif0_data_pins[] = {
2148 /* RX, TX */
2149 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2150 };
2151 static const unsigned int hscif0_data_mux[] = {
2152 HRX0_MARK, HTX0_MARK,
2153 };
2154 static const unsigned int hscif0_clk_pins[] = {
2155 /* SCK */
2156 RCAR_GP_PIN(5, 12),
2157 };
2158 static const unsigned int hscif0_clk_mux[] = {
2159 HSCK0_MARK,
2160 };
2161 static const unsigned int hscif0_ctrl_pins[] = {
2162 /* RTS, CTS */
2163 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2164 };
2165 static const unsigned int hscif0_ctrl_mux[] = {
2166 HRTS0_N_MARK, HCTS0_N_MARK,
2167 };
2168 /* - HSCIF1 ----------------------------------------------------------------- */
2169 static const unsigned int hscif1_data_a_pins[] = {
2170 /* RX, TX */
2171 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2172 };
2173 static const unsigned int hscif1_data_a_mux[] = {
2174 HRX1_A_MARK, HTX1_A_MARK,
2175 };
2176 static const unsigned int hscif1_clk_a_pins[] = {
2177 /* SCK */
2178 RCAR_GP_PIN(6, 21),
2179 };
2180 static const unsigned int hscif1_clk_a_mux[] = {
2181 HSCK1_A_MARK,
2182 };
2183 static const unsigned int hscif1_ctrl_a_pins[] = {
2184 /* RTS, CTS */
2185 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2186 };
2187 static const unsigned int hscif1_ctrl_a_mux[] = {
2188 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2189 };
2190
2191 static const unsigned int hscif1_data_b_pins[] = {
2192 /* RX, TX */
2193 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2194 };
2195 static const unsigned int hscif1_data_b_mux[] = {
2196 HRX1_B_MARK, HTX1_B_MARK,
2197 };
2198 static const unsigned int hscif1_clk_b_pins[] = {
2199 /* SCK */
2200 RCAR_GP_PIN(5, 0),
2201 };
2202 static const unsigned int hscif1_clk_b_mux[] = {
2203 HSCK1_B_MARK,
2204 };
2205 static const unsigned int hscif1_ctrl_b_pins[] = {
2206 /* RTS, CTS */
2207 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2208 };
2209 static const unsigned int hscif1_ctrl_b_mux[] = {
2210 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2211 };
2212 /* - HSCIF2 ----------------------------------------------------------------- */
2213 static const unsigned int hscif2_data_a_pins[] = {
2214 /* RX, TX */
2215 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2216 };
2217 static const unsigned int hscif2_data_a_mux[] = {
2218 HRX2_A_MARK, HTX2_A_MARK,
2219 };
2220 static const unsigned int hscif2_clk_a_pins[] = {
2221 /* SCK */
2222 RCAR_GP_PIN(6, 10),
2223 };
2224 static const unsigned int hscif2_clk_a_mux[] = {
2225 HSCK2_A_MARK,
2226 };
2227 static const unsigned int hscif2_ctrl_a_pins[] = {
2228 /* RTS, CTS */
2229 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2230 };
2231 static const unsigned int hscif2_ctrl_a_mux[] = {
2232 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2233 };
2234
2235 static const unsigned int hscif2_data_b_pins[] = {
2236 /* RX, TX */
2237 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2238 };
2239 static const unsigned int hscif2_data_b_mux[] = {
2240 HRX2_B_MARK, HTX2_B_MARK,
2241 };
2242 static const unsigned int hscif2_clk_b_pins[] = {
2243 /* SCK */
2244 RCAR_GP_PIN(6, 21),
2245 };
2246 static const unsigned int hscif2_clk_b_mux[] = {
2247 HSCK2_B_MARK,
2248 };
2249 static const unsigned int hscif2_ctrl_b_pins[] = {
2250 /* RTS, CTS */
2251 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2252 };
2253 static const unsigned int hscif2_ctrl_b_mux[] = {
2254 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2255 };
2256
2257 static const unsigned int hscif2_data_c_pins[] = {
2258 /* RX, TX */
2259 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2260 };
2261 static const unsigned int hscif2_data_c_mux[] = {
2262 HRX2_C_MARK, HTX2_C_MARK,
2263 };
2264 static const unsigned int hscif2_clk_c_pins[] = {
2265 /* SCK */
2266 RCAR_GP_PIN(6, 24),
2267 };
2268 static const unsigned int hscif2_clk_c_mux[] = {
2269 HSCK2_C_MARK,
2270 };
2271 static const unsigned int hscif2_ctrl_c_pins[] = {
2272 /* RTS, CTS */
2273 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2274 };
2275 static const unsigned int hscif2_ctrl_c_mux[] = {
2276 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2277 };
2278 /* - HSCIF3 ----------------------------------------------------------------- */
2279 static const unsigned int hscif3_data_a_pins[] = {
2280 /* RX, TX */
2281 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2282 };
2283 static const unsigned int hscif3_data_a_mux[] = {
2284 HRX3_A_MARK, HTX3_A_MARK,
2285 };
2286 static const unsigned int hscif3_clk_pins[] = {
2287 /* SCK */
2288 RCAR_GP_PIN(1, 22),
2289 };
2290 static const unsigned int hscif3_clk_mux[] = {
2291 HSCK3_MARK,
2292 };
2293 static const unsigned int hscif3_ctrl_pins[] = {
2294 /* RTS, CTS */
2295 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2296 };
2297 static const unsigned int hscif3_ctrl_mux[] = {
2298 HRTS3_N_MARK, HCTS3_N_MARK,
2299 };
2300
2301 static const unsigned int hscif3_data_b_pins[] = {
2302 /* RX, TX */
2303 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2304 };
2305 static const unsigned int hscif3_data_b_mux[] = {
2306 HRX3_B_MARK, HTX3_B_MARK,
2307 };
2308 static const unsigned int hscif3_data_c_pins[] = {
2309 /* RX, TX */
2310 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2311 };
2312 static const unsigned int hscif3_data_c_mux[] = {
2313 HRX3_C_MARK, HTX3_C_MARK,
2314 };
2315 static const unsigned int hscif3_data_d_pins[] = {
2316 /* RX, TX */
2317 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2318 };
2319 static const unsigned int hscif3_data_d_mux[] = {
2320 HRX3_D_MARK, HTX3_D_MARK,
2321 };
2322 /* - HSCIF4 ----------------------------------------------------------------- */
2323 static const unsigned int hscif4_data_a_pins[] = {
2324 /* RX, TX */
2325 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2326 };
2327 static const unsigned int hscif4_data_a_mux[] = {
2328 HRX4_A_MARK, HTX4_A_MARK,
2329 };
2330 static const unsigned int hscif4_clk_pins[] = {
2331 /* SCK */
2332 RCAR_GP_PIN(1, 11),
2333 };
2334 static const unsigned int hscif4_clk_mux[] = {
2335 HSCK4_MARK,
2336 };
2337 static const unsigned int hscif4_ctrl_pins[] = {
2338 /* RTS, CTS */
2339 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2340 };
2341 static const unsigned int hscif4_ctrl_mux[] = {
2342 HRTS4_N_MARK, HCTS4_N_MARK,
2343 };
2344
2345 static const unsigned int hscif4_data_b_pins[] = {
2346 /* RX, TX */
2347 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2348 };
2349 static const unsigned int hscif4_data_b_mux[] = {
2350 HRX4_B_MARK, HTX4_B_MARK,
2351 };
2352
2353 /* - I2C -------------------------------------------------------------------- */
2354 static const unsigned int i2c1_a_pins[] = {
2355 /* SDA, SCL */
2356 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2357 };
2358 static const unsigned int i2c1_a_mux[] = {
2359 SDA1_A_MARK, SCL1_A_MARK,
2360 };
2361 static const unsigned int i2c1_b_pins[] = {
2362 /* SDA, SCL */
2363 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2364 };
2365 static const unsigned int i2c1_b_mux[] = {
2366 SDA1_B_MARK, SCL1_B_MARK,
2367 };
2368 static const unsigned int i2c2_a_pins[] = {
2369 /* SDA, SCL */
2370 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2371 };
2372 static const unsigned int i2c2_a_mux[] = {
2373 SDA2_A_MARK, SCL2_A_MARK,
2374 };
2375 static const unsigned int i2c2_b_pins[] = {
2376 /* SDA, SCL */
2377 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2378 };
2379 static const unsigned int i2c2_b_mux[] = {
2380 SDA2_B_MARK, SCL2_B_MARK,
2381 };
2382 static const unsigned int i2c6_a_pins[] = {
2383 /* SDA, SCL */
2384 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2385 };
2386 static const unsigned int i2c6_a_mux[] = {
2387 SDA6_A_MARK, SCL6_A_MARK,
2388 };
2389 static const unsigned int i2c6_b_pins[] = {
2390 /* SDA, SCL */
2391 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2392 };
2393 static const unsigned int i2c6_b_mux[] = {
2394 SDA6_B_MARK, SCL6_B_MARK,
2395 };
2396 static const unsigned int i2c6_c_pins[] = {
2397 /* SDA, SCL */
2398 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2399 };
2400 static const unsigned int i2c6_c_mux[] = {
2401 SDA6_C_MARK, SCL6_C_MARK,
2402 };
2403
2404 /* - INTC-EX ---------------------------------------------------------------- */
2405 static const unsigned int intc_ex_irq0_pins[] = {
2406 /* IRQ0 */
2407 RCAR_GP_PIN(2, 0),
2408 };
2409 static const unsigned int intc_ex_irq0_mux[] = {
2410 IRQ0_MARK,
2411 };
2412 static const unsigned int intc_ex_irq1_pins[] = {
2413 /* IRQ1 */
2414 RCAR_GP_PIN(2, 1),
2415 };
2416 static const unsigned int intc_ex_irq1_mux[] = {
2417 IRQ1_MARK,
2418 };
2419 static const unsigned int intc_ex_irq2_pins[] = {
2420 /* IRQ2 */
2421 RCAR_GP_PIN(2, 2),
2422 };
2423 static const unsigned int intc_ex_irq2_mux[] = {
2424 IRQ2_MARK,
2425 };
2426 static const unsigned int intc_ex_irq3_pins[] = {
2427 /* IRQ3 */
2428 RCAR_GP_PIN(2, 3),
2429 };
2430 static const unsigned int intc_ex_irq3_mux[] = {
2431 IRQ3_MARK,
2432 };
2433 static const unsigned int intc_ex_irq4_pins[] = {
2434 /* IRQ4 */
2435 RCAR_GP_PIN(2, 4),
2436 };
2437 static const unsigned int intc_ex_irq4_mux[] = {
2438 IRQ4_MARK,
2439 };
2440 static const unsigned int intc_ex_irq5_pins[] = {
2441 /* IRQ5 */
2442 RCAR_GP_PIN(2, 5),
2443 };
2444 static const unsigned int intc_ex_irq5_mux[] = {
2445 IRQ5_MARK,
2446 };
2447
2448 /* - MSIOF0 ----------------------------------------------------------------- */
2449 static const unsigned int msiof0_clk_pins[] = {
2450 /* SCK */
2451 RCAR_GP_PIN(5, 17),
2452 };
2453 static const unsigned int msiof0_clk_mux[] = {
2454 MSIOF0_SCK_MARK,
2455 };
2456 static const unsigned int msiof0_sync_pins[] = {
2457 /* SYNC */
2458 RCAR_GP_PIN(5, 18),
2459 };
2460 static const unsigned int msiof0_sync_mux[] = {
2461 MSIOF0_SYNC_MARK,
2462 };
2463 static const unsigned int msiof0_ss1_pins[] = {
2464 /* SS1 */
2465 RCAR_GP_PIN(5, 19),
2466 };
2467 static const unsigned int msiof0_ss1_mux[] = {
2468 MSIOF0_SS1_MARK,
2469 };
2470 static const unsigned int msiof0_ss2_pins[] = {
2471 /* SS2 */
2472 RCAR_GP_PIN(5, 21),
2473 };
2474 static const unsigned int msiof0_ss2_mux[] = {
2475 MSIOF0_SS2_MARK,
2476 };
2477 static const unsigned int msiof0_txd_pins[] = {
2478 /* TXD */
2479 RCAR_GP_PIN(5, 20),
2480 };
2481 static const unsigned int msiof0_txd_mux[] = {
2482 MSIOF0_TXD_MARK,
2483 };
2484 static const unsigned int msiof0_rxd_pins[] = {
2485 /* RXD */
2486 RCAR_GP_PIN(5, 22),
2487 };
2488 static const unsigned int msiof0_rxd_mux[] = {
2489 MSIOF0_RXD_MARK,
2490 };
2491 /* - MSIOF1 ----------------------------------------------------------------- */
2492 static const unsigned int msiof1_clk_a_pins[] = {
2493 /* SCK */
2494 RCAR_GP_PIN(6, 8),
2495 };
2496 static const unsigned int msiof1_clk_a_mux[] = {
2497 MSIOF1_SCK_A_MARK,
2498 };
2499 static const unsigned int msiof1_sync_a_pins[] = {
2500 /* SYNC */
2501 RCAR_GP_PIN(6, 9),
2502 };
2503 static const unsigned int msiof1_sync_a_mux[] = {
2504 MSIOF1_SYNC_A_MARK,
2505 };
2506 static const unsigned int msiof1_ss1_a_pins[] = {
2507 /* SS1 */
2508 RCAR_GP_PIN(6, 5),
2509 };
2510 static const unsigned int msiof1_ss1_a_mux[] = {
2511 MSIOF1_SS1_A_MARK,
2512 };
2513 static const unsigned int msiof1_ss2_a_pins[] = {
2514 /* SS2 */
2515 RCAR_GP_PIN(6, 6),
2516 };
2517 static const unsigned int msiof1_ss2_a_mux[] = {
2518 MSIOF1_SS2_A_MARK,
2519 };
2520 static const unsigned int msiof1_txd_a_pins[] = {
2521 /* TXD */
2522 RCAR_GP_PIN(6, 7),
2523 };
2524 static const unsigned int msiof1_txd_a_mux[] = {
2525 MSIOF1_TXD_A_MARK,
2526 };
2527 static const unsigned int msiof1_rxd_a_pins[] = {
2528 /* RXD */
2529 RCAR_GP_PIN(6, 10),
2530 };
2531 static const unsigned int msiof1_rxd_a_mux[] = {
2532 MSIOF1_RXD_A_MARK,
2533 };
2534 static const unsigned int msiof1_clk_b_pins[] = {
2535 /* SCK */
2536 RCAR_GP_PIN(5, 9),
2537 };
2538 static const unsigned int msiof1_clk_b_mux[] = {
2539 MSIOF1_SCK_B_MARK,
2540 };
2541 static const unsigned int msiof1_sync_b_pins[] = {
2542 /* SYNC */
2543 RCAR_GP_PIN(5, 3),
2544 };
2545 static const unsigned int msiof1_sync_b_mux[] = {
2546 MSIOF1_SYNC_B_MARK,
2547 };
2548 static const unsigned int msiof1_ss1_b_pins[] = {
2549 /* SS1 */
2550 RCAR_GP_PIN(5, 4),
2551 };
2552 static const unsigned int msiof1_ss1_b_mux[] = {
2553 MSIOF1_SS1_B_MARK,
2554 };
2555 static const unsigned int msiof1_ss2_b_pins[] = {
2556 /* SS2 */
2557 RCAR_GP_PIN(5, 0),
2558 };
2559 static const unsigned int msiof1_ss2_b_mux[] = {
2560 MSIOF1_SS2_B_MARK,
2561 };
2562 static const unsigned int msiof1_txd_b_pins[] = {
2563 /* TXD */
2564 RCAR_GP_PIN(5, 8),
2565 };
2566 static const unsigned int msiof1_txd_b_mux[] = {
2567 MSIOF1_TXD_B_MARK,
2568 };
2569 static const unsigned int msiof1_rxd_b_pins[] = {
2570 /* RXD */
2571 RCAR_GP_PIN(5, 7),
2572 };
2573 static const unsigned int msiof1_rxd_b_mux[] = {
2574 MSIOF1_RXD_B_MARK,
2575 };
2576 static const unsigned int msiof1_clk_c_pins[] = {
2577 /* SCK */
2578 RCAR_GP_PIN(6, 17),
2579 };
2580 static const unsigned int msiof1_clk_c_mux[] = {
2581 MSIOF1_SCK_C_MARK,
2582 };
2583 static const unsigned int msiof1_sync_c_pins[] = {
2584 /* SYNC */
2585 RCAR_GP_PIN(6, 18),
2586 };
2587 static const unsigned int msiof1_sync_c_mux[] = {
2588 MSIOF1_SYNC_C_MARK,
2589 };
2590 static const unsigned int msiof1_ss1_c_pins[] = {
2591 /* SS1 */
2592 RCAR_GP_PIN(6, 21),
2593 };
2594 static const unsigned int msiof1_ss1_c_mux[] = {
2595 MSIOF1_SS1_C_MARK,
2596 };
2597 static const unsigned int msiof1_ss2_c_pins[] = {
2598 /* SS2 */
2599 RCAR_GP_PIN(6, 27),
2600 };
2601 static const unsigned int msiof1_ss2_c_mux[] = {
2602 MSIOF1_SS2_C_MARK,
2603 };
2604 static const unsigned int msiof1_txd_c_pins[] = {
2605 /* TXD */
2606 RCAR_GP_PIN(6, 20),
2607 };
2608 static const unsigned int msiof1_txd_c_mux[] = {
2609 MSIOF1_TXD_C_MARK,
2610 };
2611 static const unsigned int msiof1_rxd_c_pins[] = {
2612 /* RXD */
2613 RCAR_GP_PIN(6, 19),
2614 };
2615 static const unsigned int msiof1_rxd_c_mux[] = {
2616 MSIOF1_RXD_C_MARK,
2617 };
2618 static const unsigned int msiof1_clk_d_pins[] = {
2619 /* SCK */
2620 RCAR_GP_PIN(5, 12),
2621 };
2622 static const unsigned int msiof1_clk_d_mux[] = {
2623 MSIOF1_SCK_D_MARK,
2624 };
2625 static const unsigned int msiof1_sync_d_pins[] = {
2626 /* SYNC */
2627 RCAR_GP_PIN(5, 15),
2628 };
2629 static const unsigned int msiof1_sync_d_mux[] = {
2630 MSIOF1_SYNC_D_MARK,
2631 };
2632 static const unsigned int msiof1_ss1_d_pins[] = {
2633 /* SS1 */
2634 RCAR_GP_PIN(5, 16),
2635 };
2636 static const unsigned int msiof1_ss1_d_mux[] = {
2637 MSIOF1_SS1_D_MARK,
2638 };
2639 static const unsigned int msiof1_ss2_d_pins[] = {
2640 /* SS2 */
2641 RCAR_GP_PIN(5, 21),
2642 };
2643 static const unsigned int msiof1_ss2_d_mux[] = {
2644 MSIOF1_SS2_D_MARK,
2645 };
2646 static const unsigned int msiof1_txd_d_pins[] = {
2647 /* TXD */
2648 RCAR_GP_PIN(5, 14),
2649 };
2650 static const unsigned int msiof1_txd_d_mux[] = {
2651 MSIOF1_TXD_D_MARK,
2652 };
2653 static const unsigned int msiof1_rxd_d_pins[] = {
2654 /* RXD */
2655 RCAR_GP_PIN(5, 13),
2656 };
2657 static const unsigned int msiof1_rxd_d_mux[] = {
2658 MSIOF1_RXD_D_MARK,
2659 };
2660 static const unsigned int msiof1_clk_e_pins[] = {
2661 /* SCK */
2662 RCAR_GP_PIN(3, 0),
2663 };
2664 static const unsigned int msiof1_clk_e_mux[] = {
2665 MSIOF1_SCK_E_MARK,
2666 };
2667 static const unsigned int msiof1_sync_e_pins[] = {
2668 /* SYNC */
2669 RCAR_GP_PIN(3, 1),
2670 };
2671 static const unsigned int msiof1_sync_e_mux[] = {
2672 MSIOF1_SYNC_E_MARK,
2673 };
2674 static const unsigned int msiof1_ss1_e_pins[] = {
2675 /* SS1 */
2676 RCAR_GP_PIN(3, 4),
2677 };
2678 static const unsigned int msiof1_ss1_e_mux[] = {
2679 MSIOF1_SS1_E_MARK,
2680 };
2681 static const unsigned int msiof1_ss2_e_pins[] = {
2682 /* SS2 */
2683 RCAR_GP_PIN(3, 5),
2684 };
2685 static const unsigned int msiof1_ss2_e_mux[] = {
2686 MSIOF1_SS2_E_MARK,
2687 };
2688 static const unsigned int msiof1_txd_e_pins[] = {
2689 /* TXD */
2690 RCAR_GP_PIN(3, 3),
2691 };
2692 static const unsigned int msiof1_txd_e_mux[] = {
2693 MSIOF1_TXD_E_MARK,
2694 };
2695 static const unsigned int msiof1_rxd_e_pins[] = {
2696 /* RXD */
2697 RCAR_GP_PIN(3, 2),
2698 };
2699 static const unsigned int msiof1_rxd_e_mux[] = {
2700 MSIOF1_RXD_E_MARK,
2701 };
2702 static const unsigned int msiof1_clk_f_pins[] = {
2703 /* SCK */
2704 RCAR_GP_PIN(5, 23),
2705 };
2706 static const unsigned int msiof1_clk_f_mux[] = {
2707 MSIOF1_SCK_F_MARK,
2708 };
2709 static const unsigned int msiof1_sync_f_pins[] = {
2710 /* SYNC */
2711 RCAR_GP_PIN(5, 24),
2712 };
2713 static const unsigned int msiof1_sync_f_mux[] = {
2714 MSIOF1_SYNC_F_MARK,
2715 };
2716 static const unsigned int msiof1_ss1_f_pins[] = {
2717 /* SS1 */
2718 RCAR_GP_PIN(6, 1),
2719 };
2720 static const unsigned int msiof1_ss1_f_mux[] = {
2721 MSIOF1_SS1_F_MARK,
2722 };
2723 static const unsigned int msiof1_ss2_f_pins[] = {
2724 /* SS2 */
2725 RCAR_GP_PIN(6, 2),
2726 };
2727 static const unsigned int msiof1_ss2_f_mux[] = {
2728 MSIOF1_SS2_F_MARK,
2729 };
2730 static const unsigned int msiof1_txd_f_pins[] = {
2731 /* TXD */
2732 RCAR_GP_PIN(6, 0),
2733 };
2734 static const unsigned int msiof1_txd_f_mux[] = {
2735 MSIOF1_TXD_F_MARK,
2736 };
2737 static const unsigned int msiof1_rxd_f_pins[] = {
2738 /* RXD */
2739 RCAR_GP_PIN(5, 25),
2740 };
2741 static const unsigned int msiof1_rxd_f_mux[] = {
2742 MSIOF1_RXD_F_MARK,
2743 };
2744 static const unsigned int msiof1_clk_g_pins[] = {
2745 /* SCK */
2746 RCAR_GP_PIN(3, 6),
2747 };
2748 static const unsigned int msiof1_clk_g_mux[] = {
2749 MSIOF1_SCK_G_MARK,
2750 };
2751 static const unsigned int msiof1_sync_g_pins[] = {
2752 /* SYNC */
2753 RCAR_GP_PIN(3, 7),
2754 };
2755 static const unsigned int msiof1_sync_g_mux[] = {
2756 MSIOF1_SYNC_G_MARK,
2757 };
2758 static const unsigned int msiof1_ss1_g_pins[] = {
2759 /* SS1 */
2760 RCAR_GP_PIN(3, 10),
2761 };
2762 static const unsigned int msiof1_ss1_g_mux[] = {
2763 MSIOF1_SS1_G_MARK,
2764 };
2765 static const unsigned int msiof1_ss2_g_pins[] = {
2766 /* SS2 */
2767 RCAR_GP_PIN(3, 11),
2768 };
2769 static const unsigned int msiof1_ss2_g_mux[] = {
2770 MSIOF1_SS2_G_MARK,
2771 };
2772 static const unsigned int msiof1_txd_g_pins[] = {
2773 /* TXD */
2774 RCAR_GP_PIN(3, 9),
2775 };
2776 static const unsigned int msiof1_txd_g_mux[] = {
2777 MSIOF1_TXD_G_MARK,
2778 };
2779 static const unsigned int msiof1_rxd_g_pins[] = {
2780 /* RXD */
2781 RCAR_GP_PIN(3, 8),
2782 };
2783 static const unsigned int msiof1_rxd_g_mux[] = {
2784 MSIOF1_RXD_G_MARK,
2785 };
2786 /* - MSIOF2 ----------------------------------------------------------------- */
2787 static const unsigned int msiof2_clk_a_pins[] = {
2788 /* SCK */
2789 RCAR_GP_PIN(1, 9),
2790 };
2791 static const unsigned int msiof2_clk_a_mux[] = {
2792 MSIOF2_SCK_A_MARK,
2793 };
2794 static const unsigned int msiof2_sync_a_pins[] = {
2795 /* SYNC */
2796 RCAR_GP_PIN(1, 8),
2797 };
2798 static const unsigned int msiof2_sync_a_mux[] = {
2799 MSIOF2_SYNC_A_MARK,
2800 };
2801 static const unsigned int msiof2_ss1_a_pins[] = {
2802 /* SS1 */
2803 RCAR_GP_PIN(1, 6),
2804 };
2805 static const unsigned int msiof2_ss1_a_mux[] = {
2806 MSIOF2_SS1_A_MARK,
2807 };
2808 static const unsigned int msiof2_ss2_a_pins[] = {
2809 /* SS2 */
2810 RCAR_GP_PIN(1, 7),
2811 };
2812 static const unsigned int msiof2_ss2_a_mux[] = {
2813 MSIOF2_SS2_A_MARK,
2814 };
2815 static const unsigned int msiof2_txd_a_pins[] = {
2816 /* TXD */
2817 RCAR_GP_PIN(1, 11),
2818 };
2819 static const unsigned int msiof2_txd_a_mux[] = {
2820 MSIOF2_TXD_A_MARK,
2821 };
2822 static const unsigned int msiof2_rxd_a_pins[] = {
2823 /* RXD */
2824 RCAR_GP_PIN(1, 10),
2825 };
2826 static const unsigned int msiof2_rxd_a_mux[] = {
2827 MSIOF2_RXD_A_MARK,
2828 };
2829 static const unsigned int msiof2_clk_b_pins[] = {
2830 /* SCK */
2831 RCAR_GP_PIN(0, 4),
2832 };
2833 static const unsigned int msiof2_clk_b_mux[] = {
2834 MSIOF2_SCK_B_MARK,
2835 };
2836 static const unsigned int msiof2_sync_b_pins[] = {
2837 /* SYNC */
2838 RCAR_GP_PIN(0, 5),
2839 };
2840 static const unsigned int msiof2_sync_b_mux[] = {
2841 MSIOF2_SYNC_B_MARK,
2842 };
2843 static const unsigned int msiof2_ss1_b_pins[] = {
2844 /* SS1 */
2845 RCAR_GP_PIN(0, 0),
2846 };
2847 static const unsigned int msiof2_ss1_b_mux[] = {
2848 MSIOF2_SS1_B_MARK,
2849 };
2850 static const unsigned int msiof2_ss2_b_pins[] = {
2851 /* SS2 */
2852 RCAR_GP_PIN(0, 1),
2853 };
2854 static const unsigned int msiof2_ss2_b_mux[] = {
2855 MSIOF2_SS2_B_MARK,
2856 };
2857 static const unsigned int msiof2_txd_b_pins[] = {
2858 /* TXD */
2859 RCAR_GP_PIN(0, 7),
2860 };
2861 static const unsigned int msiof2_txd_b_mux[] = {
2862 MSIOF2_TXD_B_MARK,
2863 };
2864 static const unsigned int msiof2_rxd_b_pins[] = {
2865 /* RXD */
2866 RCAR_GP_PIN(0, 6),
2867 };
2868 static const unsigned int msiof2_rxd_b_mux[] = {
2869 MSIOF2_RXD_B_MARK,
2870 };
2871 static const unsigned int msiof2_clk_c_pins[] = {
2872 /* SCK */
2873 RCAR_GP_PIN(2, 12),
2874 };
2875 static const unsigned int msiof2_clk_c_mux[] = {
2876 MSIOF2_SCK_C_MARK,
2877 };
2878 static const unsigned int msiof2_sync_c_pins[] = {
2879 /* SYNC */
2880 RCAR_GP_PIN(2, 11),
2881 };
2882 static const unsigned int msiof2_sync_c_mux[] = {
2883 MSIOF2_SYNC_C_MARK,
2884 };
2885 static const unsigned int msiof2_ss1_c_pins[] = {
2886 /* SS1 */
2887 RCAR_GP_PIN(2, 10),
2888 };
2889 static const unsigned int msiof2_ss1_c_mux[] = {
2890 MSIOF2_SS1_C_MARK,
2891 };
2892 static const unsigned int msiof2_ss2_c_pins[] = {
2893 /* SS2 */
2894 RCAR_GP_PIN(2, 9),
2895 };
2896 static const unsigned int msiof2_ss2_c_mux[] = {
2897 MSIOF2_SS2_C_MARK,
2898 };
2899 static const unsigned int msiof2_txd_c_pins[] = {
2900 /* TXD */
2901 RCAR_GP_PIN(2, 14),
2902 };
2903 static const unsigned int msiof2_txd_c_mux[] = {
2904 MSIOF2_TXD_C_MARK,
2905 };
2906 static const unsigned int msiof2_rxd_c_pins[] = {
2907 /* RXD */
2908 RCAR_GP_PIN(2, 13),
2909 };
2910 static const unsigned int msiof2_rxd_c_mux[] = {
2911 MSIOF2_RXD_C_MARK,
2912 };
2913 static const unsigned int msiof2_clk_d_pins[] = {
2914 /* SCK */
2915 RCAR_GP_PIN(0, 8),
2916 };
2917 static const unsigned int msiof2_clk_d_mux[] = {
2918 MSIOF2_SCK_D_MARK,
2919 };
2920 static const unsigned int msiof2_sync_d_pins[] = {
2921 /* SYNC */
2922 RCAR_GP_PIN(0, 9),
2923 };
2924 static const unsigned int msiof2_sync_d_mux[] = {
2925 MSIOF2_SYNC_D_MARK,
2926 };
2927 static const unsigned int msiof2_ss1_d_pins[] = {
2928 /* SS1 */
2929 RCAR_GP_PIN(0, 12),
2930 };
2931 static const unsigned int msiof2_ss1_d_mux[] = {
2932 MSIOF2_SS1_D_MARK,
2933 };
2934 static const unsigned int msiof2_ss2_d_pins[] = {
2935 /* SS2 */
2936 RCAR_GP_PIN(0, 13),
2937 };
2938 static const unsigned int msiof2_ss2_d_mux[] = {
2939 MSIOF2_SS2_D_MARK,
2940 };
2941 static const unsigned int msiof2_txd_d_pins[] = {
2942 /* TXD */
2943 RCAR_GP_PIN(0, 11),
2944 };
2945 static const unsigned int msiof2_txd_d_mux[] = {
2946 MSIOF2_TXD_D_MARK,
2947 };
2948 static const unsigned int msiof2_rxd_d_pins[] = {
2949 /* RXD */
2950 RCAR_GP_PIN(0, 10),
2951 };
2952 static const unsigned int msiof2_rxd_d_mux[] = {
2953 MSIOF2_RXD_D_MARK,
2954 };
2955 /* - MSIOF3 ----------------------------------------------------------------- */
2956 static const unsigned int msiof3_clk_a_pins[] = {
2957 /* SCK */
2958 RCAR_GP_PIN(0, 0),
2959 };
2960 static const unsigned int msiof3_clk_a_mux[] = {
2961 MSIOF3_SCK_A_MARK,
2962 };
2963 static const unsigned int msiof3_sync_a_pins[] = {
2964 /* SYNC */
2965 RCAR_GP_PIN(0, 1),
2966 };
2967 static const unsigned int msiof3_sync_a_mux[] = {
2968 MSIOF3_SYNC_A_MARK,
2969 };
2970 static const unsigned int msiof3_ss1_a_pins[] = {
2971 /* SS1 */
2972 RCAR_GP_PIN(0, 14),
2973 };
2974 static const unsigned int msiof3_ss1_a_mux[] = {
2975 MSIOF3_SS1_A_MARK,
2976 };
2977 static const unsigned int msiof3_ss2_a_pins[] = {
2978 /* SS2 */
2979 RCAR_GP_PIN(0, 15),
2980 };
2981 static const unsigned int msiof3_ss2_a_mux[] = {
2982 MSIOF3_SS2_A_MARK,
2983 };
2984 static const unsigned int msiof3_txd_a_pins[] = {
2985 /* TXD */
2986 RCAR_GP_PIN(0, 3),
2987 };
2988 static const unsigned int msiof3_txd_a_mux[] = {
2989 MSIOF3_TXD_A_MARK,
2990 };
2991 static const unsigned int msiof3_rxd_a_pins[] = {
2992 /* RXD */
2993 RCAR_GP_PIN(0, 2),
2994 };
2995 static const unsigned int msiof3_rxd_a_mux[] = {
2996 MSIOF3_RXD_A_MARK,
2997 };
2998 static const unsigned int msiof3_clk_b_pins[] = {
2999 /* SCK */
3000 RCAR_GP_PIN(1, 2),
3001 };
3002 static const unsigned int msiof3_clk_b_mux[] = {
3003 MSIOF3_SCK_B_MARK,
3004 };
3005 static const unsigned int msiof3_sync_b_pins[] = {
3006 /* SYNC */
3007 RCAR_GP_PIN(1, 0),
3008 };
3009 static const unsigned int msiof3_sync_b_mux[] = {
3010 MSIOF3_SYNC_B_MARK,
3011 };
3012 static const unsigned int msiof3_ss1_b_pins[] = {
3013 /* SS1 */
3014 RCAR_GP_PIN(1, 4),
3015 };
3016 static const unsigned int msiof3_ss1_b_mux[] = {
3017 MSIOF3_SS1_B_MARK,
3018 };
3019 static const unsigned int msiof3_ss2_b_pins[] = {
3020 /* SS2 */
3021 RCAR_GP_PIN(1, 5),
3022 };
3023 static const unsigned int msiof3_ss2_b_mux[] = {
3024 MSIOF3_SS2_B_MARK,
3025 };
3026 static const unsigned int msiof3_txd_b_pins[] = {
3027 /* TXD */
3028 RCAR_GP_PIN(1, 1),
3029 };
3030 static const unsigned int msiof3_txd_b_mux[] = {
3031 MSIOF3_TXD_B_MARK,
3032 };
3033 static const unsigned int msiof3_rxd_b_pins[] = {
3034 /* RXD */
3035 RCAR_GP_PIN(1, 3),
3036 };
3037 static const unsigned int msiof3_rxd_b_mux[] = {
3038 MSIOF3_RXD_B_MARK,
3039 };
3040 static const unsigned int msiof3_clk_c_pins[] = {
3041 /* SCK */
3042 RCAR_GP_PIN(1, 12),
3043 };
3044 static const unsigned int msiof3_clk_c_mux[] = {
3045 MSIOF3_SCK_C_MARK,
3046 };
3047 static const unsigned int msiof3_sync_c_pins[] = {
3048 /* SYNC */
3049 RCAR_GP_PIN(1, 13),
3050 };
3051 static const unsigned int msiof3_sync_c_mux[] = {
3052 MSIOF3_SYNC_C_MARK,
3053 };
3054 static const unsigned int msiof3_txd_c_pins[] = {
3055 /* TXD */
3056 RCAR_GP_PIN(1, 15),
3057 };
3058 static const unsigned int msiof3_txd_c_mux[] = {
3059 MSIOF3_TXD_C_MARK,
3060 };
3061 static const unsigned int msiof3_rxd_c_pins[] = {
3062 /* RXD */
3063 RCAR_GP_PIN(1, 14),
3064 };
3065 static const unsigned int msiof3_rxd_c_mux[] = {
3066 MSIOF3_RXD_C_MARK,
3067 };
3068 static const unsigned int msiof3_clk_d_pins[] = {
3069 /* SCK */
3070 RCAR_GP_PIN(1, 22),
3071 };
3072 static const unsigned int msiof3_clk_d_mux[] = {
3073 MSIOF3_SCK_D_MARK,
3074 };
3075 static const unsigned int msiof3_sync_d_pins[] = {
3076 /* SYNC */
3077 RCAR_GP_PIN(1, 23),
3078 };
3079 static const unsigned int msiof3_sync_d_mux[] = {
3080 MSIOF3_SYNC_D_MARK,
3081 };
3082 static const unsigned int msiof3_ss1_d_pins[] = {
3083 /* SS1 */
3084 RCAR_GP_PIN(1, 26),
3085 };
3086 static const unsigned int msiof3_ss1_d_mux[] = {
3087 MSIOF3_SS1_D_MARK,
3088 };
3089 static const unsigned int msiof3_txd_d_pins[] = {
3090 /* TXD */
3091 RCAR_GP_PIN(1, 25),
3092 };
3093 static const unsigned int msiof3_txd_d_mux[] = {
3094 MSIOF3_TXD_D_MARK,
3095 };
3096 static const unsigned int msiof3_rxd_d_pins[] = {
3097 /* RXD */
3098 RCAR_GP_PIN(1, 24),
3099 };
3100 static const unsigned int msiof3_rxd_d_mux[] = {
3101 MSIOF3_RXD_D_MARK,
3102 };
3103 static const unsigned int msiof3_clk_e_pins[] = {
3104 /* SCK */
3105 RCAR_GP_PIN(2, 3),
3106 };
3107 static const unsigned int msiof3_clk_e_mux[] = {
3108 MSIOF3_SCK_E_MARK,
3109 };
3110 static const unsigned int msiof3_sync_e_pins[] = {
3111 /* SYNC */
3112 RCAR_GP_PIN(2, 2),
3113 };
3114 static const unsigned int msiof3_sync_e_mux[] = {
3115 MSIOF3_SYNC_E_MARK,
3116 };
3117 static const unsigned int msiof3_ss1_e_pins[] = {
3118 /* SS1 */
3119 RCAR_GP_PIN(2, 1),
3120 };
3121 static const unsigned int msiof3_ss1_e_mux[] = {
3122 MSIOF3_SS1_E_MARK,
3123 };
3124 static const unsigned int msiof3_ss2_e_pins[] = {
3125 /* SS2 */
3126 RCAR_GP_PIN(2, 0),
3127 };
3128 static const unsigned int msiof3_ss2_e_mux[] = {
3129 MSIOF3_SS2_E_MARK,
3130 };
3131 static const unsigned int msiof3_txd_e_pins[] = {
3132 /* TXD */
3133 RCAR_GP_PIN(2, 5),
3134 };
3135 static const unsigned int msiof3_txd_e_mux[] = {
3136 MSIOF3_TXD_E_MARK,
3137 };
3138 static const unsigned int msiof3_rxd_e_pins[] = {
3139 /* RXD */
3140 RCAR_GP_PIN(2, 4),
3141 };
3142 static const unsigned int msiof3_rxd_e_mux[] = {
3143 MSIOF3_RXD_E_MARK,
3144 };
3145
3146 /* - PWM0 --------------------------------------------------------------------*/
3147 static const unsigned int pwm0_pins[] = {
3148 /* PWM */
3149 RCAR_GP_PIN(2, 6),
3150 };
3151 static const unsigned int pwm0_mux[] = {
3152 PWM0_MARK,
3153 };
3154 /* - PWM1 --------------------------------------------------------------------*/
3155 static const unsigned int pwm1_a_pins[] = {
3156 /* PWM */
3157 RCAR_GP_PIN(2, 7),
3158 };
3159 static const unsigned int pwm1_a_mux[] = {
3160 PWM1_A_MARK,
3161 };
3162 static const unsigned int pwm1_b_pins[] = {
3163 /* PWM */
3164 RCAR_GP_PIN(1, 8),
3165 };
3166 static const unsigned int pwm1_b_mux[] = {
3167 PWM1_B_MARK,
3168 };
3169 /* - PWM2 --------------------------------------------------------------------*/
3170 static const unsigned int pwm2_a_pins[] = {
3171 /* PWM */
3172 RCAR_GP_PIN(2, 8),
3173 };
3174 static const unsigned int pwm2_a_mux[] = {
3175 PWM2_A_MARK,
3176 };
3177 static const unsigned int pwm2_b_pins[] = {
3178 /* PWM */
3179 RCAR_GP_PIN(1, 11),
3180 };
3181 static const unsigned int pwm2_b_mux[] = {
3182 PWM2_B_MARK,
3183 };
3184 /* - PWM3 --------------------------------------------------------------------*/
3185 static const unsigned int pwm3_a_pins[] = {
3186 /* PWM */
3187 RCAR_GP_PIN(1, 0),
3188 };
3189 static const unsigned int pwm3_a_mux[] = {
3190 PWM3_A_MARK,
3191 };
3192 static const unsigned int pwm3_b_pins[] = {
3193 /* PWM */
3194 RCAR_GP_PIN(2, 2),
3195 };
3196 static const unsigned int pwm3_b_mux[] = {
3197 PWM3_B_MARK,
3198 };
3199 /* - PWM4 --------------------------------------------------------------------*/
3200 static const unsigned int pwm4_a_pins[] = {
3201 /* PWM */
3202 RCAR_GP_PIN(1, 1),
3203 };
3204 static const unsigned int pwm4_a_mux[] = {
3205 PWM4_A_MARK,
3206 };
3207 static const unsigned int pwm4_b_pins[] = {
3208 /* PWM */
3209 RCAR_GP_PIN(2, 3),
3210 };
3211 static const unsigned int pwm4_b_mux[] = {
3212 PWM4_B_MARK,
3213 };
3214 /* - PWM5 --------------------------------------------------------------------*/
3215 static const unsigned int pwm5_a_pins[] = {
3216 /* PWM */
3217 RCAR_GP_PIN(1, 2),
3218 };
3219 static const unsigned int pwm5_a_mux[] = {
3220 PWM5_A_MARK,
3221 };
3222 static const unsigned int pwm5_b_pins[] = {
3223 /* PWM */
3224 RCAR_GP_PIN(2, 4),
3225 };
3226 static const unsigned int pwm5_b_mux[] = {
3227 PWM5_B_MARK,
3228 };
3229 /* - PWM6 --------------------------------------------------------------------*/
3230 static const unsigned int pwm6_a_pins[] = {
3231 /* PWM */
3232 RCAR_GP_PIN(1, 3),
3233 };
3234 static const unsigned int pwm6_a_mux[] = {
3235 PWM6_A_MARK,
3236 };
3237 static const unsigned int pwm6_b_pins[] = {
3238 /* PWM */
3239 RCAR_GP_PIN(2, 5),
3240 };
3241 static const unsigned int pwm6_b_mux[] = {
3242 PWM6_B_MARK,
3243 };
3244
3245 /* - SATA --------------------------------------------------------------------*/
3246 static const unsigned int sata0_devslp_a_pins[] = {
3247 /* DEVSLP */
3248 RCAR_GP_PIN(6, 16),
3249 };
3250 static const unsigned int sata0_devslp_a_mux[] = {
3251 SATA_DEVSLP_A_MARK,
3252 };
3253 static const unsigned int sata0_devslp_b_pins[] = {
3254 /* DEVSLP */
3255 RCAR_GP_PIN(4, 6),
3256 };
3257 static const unsigned int sata0_devslp_b_mux[] = {
3258 SATA_DEVSLP_B_MARK,
3259 };
3260
3261 /* - SCIF0 ------------------------------------------------------------------ */
3262 static const unsigned int scif0_data_pins[] = {
3263 /* RX, TX */
3264 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3265 };
3266 static const unsigned int scif0_data_mux[] = {
3267 RX0_MARK, TX0_MARK,
3268 };
3269 static const unsigned int scif0_clk_pins[] = {
3270 /* SCK */
3271 RCAR_GP_PIN(5, 0),
3272 };
3273 static const unsigned int scif0_clk_mux[] = {
3274 SCK0_MARK,
3275 };
3276 static const unsigned int scif0_ctrl_pins[] = {
3277 /* RTS, CTS */
3278 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3279 };
3280 static const unsigned int scif0_ctrl_mux[] = {
3281 RTS0_N_MARK, CTS0_N_MARK,
3282 };
3283 /* - SCIF1 ------------------------------------------------------------------ */
3284 static const unsigned int scif1_data_a_pins[] = {
3285 /* RX, TX */
3286 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3287 };
3288 static const unsigned int scif1_data_a_mux[] = {
3289 RX1_A_MARK, TX1_A_MARK,
3290 };
3291 static const unsigned int scif1_clk_pins[] = {
3292 /* SCK */
3293 RCAR_GP_PIN(6, 21),
3294 };
3295 static const unsigned int scif1_clk_mux[] = {
3296 SCK1_MARK,
3297 };
3298 static const unsigned int scif1_ctrl_pins[] = {
3299 /* RTS, CTS */
3300 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3301 };
3302 static const unsigned int scif1_ctrl_mux[] = {
3303 RTS1_N_MARK, CTS1_N_MARK,
3304 };
3305
3306 static const unsigned int scif1_data_b_pins[] = {
3307 /* RX, TX */
3308 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3309 };
3310 static const unsigned int scif1_data_b_mux[] = {
3311 RX1_B_MARK, TX1_B_MARK,
3312 };
3313 /* - SCIF2 ------------------------------------------------------------------ */
3314 static const unsigned int scif2_data_a_pins[] = {
3315 /* RX, TX */
3316 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3317 };
3318 static const unsigned int scif2_data_a_mux[] = {
3319 RX2_A_MARK, TX2_A_MARK,
3320 };
3321 static const unsigned int scif2_clk_pins[] = {
3322 /* SCK */
3323 RCAR_GP_PIN(5, 9),
3324 };
3325 static const unsigned int scif2_clk_mux[] = {
3326 SCK2_MARK,
3327 };
3328 static const unsigned int scif2_data_b_pins[] = {
3329 /* RX, TX */
3330 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3331 };
3332 static const unsigned int scif2_data_b_mux[] = {
3333 RX2_B_MARK, TX2_B_MARK,
3334 };
3335 /* - SCIF3 ------------------------------------------------------------------ */
3336 static const unsigned int scif3_data_a_pins[] = {
3337 /* RX, TX */
3338 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3339 };
3340 static const unsigned int scif3_data_a_mux[] = {
3341 RX3_A_MARK, TX3_A_MARK,
3342 };
3343 static const unsigned int scif3_clk_pins[] = {
3344 /* SCK */
3345 RCAR_GP_PIN(1, 22),
3346 };
3347 static const unsigned int scif3_clk_mux[] = {
3348 SCK3_MARK,
3349 };
3350 static const unsigned int scif3_ctrl_pins[] = {
3351 /* RTS, CTS */
3352 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3353 };
3354 static const unsigned int scif3_ctrl_mux[] = {
3355 RTS3_N_MARK, CTS3_N_MARK,
3356 };
3357 static const unsigned int scif3_data_b_pins[] = {
3358 /* RX, TX */
3359 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3360 };
3361 static const unsigned int scif3_data_b_mux[] = {
3362 RX3_B_MARK, TX3_B_MARK,
3363 };
3364 /* - SCIF4 ------------------------------------------------------------------ */
3365 static const unsigned int scif4_data_a_pins[] = {
3366 /* RX, TX */
3367 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3368 };
3369 static const unsigned int scif4_data_a_mux[] = {
3370 RX4_A_MARK, TX4_A_MARK,
3371 };
3372 static const unsigned int scif4_clk_a_pins[] = {
3373 /* SCK */
3374 RCAR_GP_PIN(2, 10),
3375 };
3376 static const unsigned int scif4_clk_a_mux[] = {
3377 SCK4_A_MARK,
3378 };
3379 static const unsigned int scif4_ctrl_a_pins[] = {
3380 /* RTS, CTS */
3381 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3382 };
3383 static const unsigned int scif4_ctrl_a_mux[] = {
3384 RTS4_N_A_MARK, CTS4_N_A_MARK,
3385 };
3386 static const unsigned int scif4_data_b_pins[] = {
3387 /* RX, TX */
3388 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3389 };
3390 static const unsigned int scif4_data_b_mux[] = {
3391 RX4_B_MARK, TX4_B_MARK,
3392 };
3393 static const unsigned int scif4_clk_b_pins[] = {
3394 /* SCK */
3395 RCAR_GP_PIN(1, 5),
3396 };
3397 static const unsigned int scif4_clk_b_mux[] = {
3398 SCK4_B_MARK,
3399 };
3400 static const unsigned int scif4_ctrl_b_pins[] = {
3401 /* RTS, CTS */
3402 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3403 };
3404 static const unsigned int scif4_ctrl_b_mux[] = {
3405 RTS4_N_B_MARK, CTS4_N_B_MARK,
3406 };
3407 static const unsigned int scif4_data_c_pins[] = {
3408 /* RX, TX */
3409 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3410 };
3411 static const unsigned int scif4_data_c_mux[] = {
3412 RX4_C_MARK, TX4_C_MARK,
3413 };
3414 static const unsigned int scif4_clk_c_pins[] = {
3415 /* SCK */
3416 RCAR_GP_PIN(0, 8),
3417 };
3418 static const unsigned int scif4_clk_c_mux[] = {
3419 SCK4_C_MARK,
3420 };
3421 static const unsigned int scif4_ctrl_c_pins[] = {
3422 /* RTS, CTS */
3423 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3424 };
3425 static const unsigned int scif4_ctrl_c_mux[] = {
3426 RTS4_N_C_MARK, CTS4_N_C_MARK,
3427 };
3428 /* - SCIF5 ------------------------------------------------------------------ */
3429 static const unsigned int scif5_data_a_pins[] = {
3430 /* RX, TX */
3431 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3432 };
3433 static const unsigned int scif5_data_a_mux[] = {
3434 RX5_A_MARK, TX5_A_MARK,
3435 };
3436 static const unsigned int scif5_clk_a_pins[] = {
3437 /* SCK */
3438 RCAR_GP_PIN(6, 21),
3439 };
3440 static const unsigned int scif5_clk_a_mux[] = {
3441 SCK5_A_MARK,
3442 };
3443 static const unsigned int scif5_data_b_pins[] = {
3444 /* RX, TX */
3445 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3446 };
3447 static const unsigned int scif5_data_b_mux[] = {
3448 RX5_B_MARK, TX5_B_MARK,
3449 };
3450 static const unsigned int scif5_clk_b_pins[] = {
3451 /* SCK */
3452 RCAR_GP_PIN(5, 0),
3453 };
3454 static const unsigned int scif5_clk_b_mux[] = {
3455 SCK5_B_MARK,
3456 };
3457
3458 /* - SCIF Clock ------------------------------------------------------------- */
3459 static const unsigned int scif_clk_a_pins[] = {
3460 /* SCIF_CLK */
3461 RCAR_GP_PIN(6, 23),
3462 };
3463 static const unsigned int scif_clk_a_mux[] = {
3464 SCIF_CLK_A_MARK,
3465 };
3466 static const unsigned int scif_clk_b_pins[] = {
3467 /* SCIF_CLK */
3468 RCAR_GP_PIN(5, 9),
3469 };
3470 static const unsigned int scif_clk_b_mux[] = {
3471 SCIF_CLK_B_MARK,
3472 };
3473
3474 /* - SDHI0 ------------------------------------------------------------------ */
3475 static const unsigned int sdhi0_data1_pins[] = {
3476 /* D0 */
3477 RCAR_GP_PIN(3, 2),
3478 };
3479 static const unsigned int sdhi0_data1_mux[] = {
3480 SD0_DAT0_MARK,
3481 };
3482 static const unsigned int sdhi0_data4_pins[] = {
3483 /* D[0:3] */
3484 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3485 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3486 };
3487 static const unsigned int sdhi0_data4_mux[] = {
3488 SD0_DAT0_MARK, SD0_DAT1_MARK,
3489 SD0_DAT2_MARK, SD0_DAT3_MARK,
3490 };
3491 static const unsigned int sdhi0_ctrl_pins[] = {
3492 /* CLK, CMD */
3493 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3494 };
3495 static const unsigned int sdhi0_ctrl_mux[] = {
3496 SD0_CLK_MARK, SD0_CMD_MARK,
3497 };
3498 static const unsigned int sdhi0_cd_pins[] = {
3499 /* CD */
3500 RCAR_GP_PIN(3, 12),
3501 };
3502 static const unsigned int sdhi0_cd_mux[] = {
3503 SD0_CD_MARK,
3504 };
3505 static const unsigned int sdhi0_wp_pins[] = {
3506 /* WP */
3507 RCAR_GP_PIN(3, 13),
3508 };
3509 static const unsigned int sdhi0_wp_mux[] = {
3510 SD0_WP_MARK,
3511 };
3512 /* - SDHI1 ------------------------------------------------------------------ */
3513 static const unsigned int sdhi1_data1_pins[] = {
3514 /* D0 */
3515 RCAR_GP_PIN(3, 8),
3516 };
3517 static const unsigned int sdhi1_data1_mux[] = {
3518 SD1_DAT0_MARK,
3519 };
3520 static const unsigned int sdhi1_data4_pins[] = {
3521 /* D[0:3] */
3522 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3523 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3524 };
3525 static const unsigned int sdhi1_data4_mux[] = {
3526 SD1_DAT0_MARK, SD1_DAT1_MARK,
3527 SD1_DAT2_MARK, SD1_DAT3_MARK,
3528 };
3529 static const unsigned int sdhi1_ctrl_pins[] = {
3530 /* CLK, CMD */
3531 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3532 };
3533 static const unsigned int sdhi1_ctrl_mux[] = {
3534 SD1_CLK_MARK, SD1_CMD_MARK,
3535 };
3536 static const unsigned int sdhi1_cd_pins[] = {
3537 /* CD */
3538 RCAR_GP_PIN(3, 14),
3539 };
3540 static const unsigned int sdhi1_cd_mux[] = {
3541 SD1_CD_MARK,
3542 };
3543 static const unsigned int sdhi1_wp_pins[] = {
3544 /* WP */
3545 RCAR_GP_PIN(3, 15),
3546 };
3547 static const unsigned int sdhi1_wp_mux[] = {
3548 SD1_WP_MARK,
3549 };
3550 /* - SDHI2 ------------------------------------------------------------------ */
3551 static const unsigned int sdhi2_data1_pins[] = {
3552 /* D0 */
3553 RCAR_GP_PIN(4, 2),
3554 };
3555 static const unsigned int sdhi2_data1_mux[] = {
3556 SD2_DAT0_MARK,
3557 };
3558 static const unsigned int sdhi2_data4_pins[] = {
3559 /* D[0:3] */
3560 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3561 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3562 };
3563 static const unsigned int sdhi2_data4_mux[] = {
3564 SD2_DAT0_MARK, SD2_DAT1_MARK,
3565 SD2_DAT2_MARK, SD2_DAT3_MARK,
3566 };
3567 static const unsigned int sdhi2_data8_pins[] = {
3568 /* D[0:7] */
3569 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3570 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3571 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3572 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3573 };
3574 static const unsigned int sdhi2_data8_mux[] = {
3575 SD2_DAT0_MARK, SD2_DAT1_MARK,
3576 SD2_DAT2_MARK, SD2_DAT3_MARK,
3577 SD2_DAT4_MARK, SD2_DAT5_MARK,
3578 SD2_DAT6_MARK, SD2_DAT7_MARK,
3579 };
3580 static const unsigned int sdhi2_ctrl_pins[] = {
3581 /* CLK, CMD */
3582 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3583 };
3584 static const unsigned int sdhi2_ctrl_mux[] = {
3585 SD2_CLK_MARK, SD2_CMD_MARK,
3586 };
3587 static const unsigned int sdhi2_cd_a_pins[] = {
3588 /* CD */
3589 RCAR_GP_PIN(4, 13),
3590 };
3591 static const unsigned int sdhi2_cd_a_mux[] = {
3592 SD2_CD_A_MARK,
3593 };
3594 static const unsigned int sdhi2_cd_b_pins[] = {
3595 /* CD */
3596 RCAR_GP_PIN(5, 10),
3597 };
3598 static const unsigned int sdhi2_cd_b_mux[] = {
3599 SD2_CD_B_MARK,
3600 };
3601 static const unsigned int sdhi2_wp_a_pins[] = {
3602 /* WP */
3603 RCAR_GP_PIN(4, 14),
3604 };
3605 static const unsigned int sdhi2_wp_a_mux[] = {
3606 SD2_WP_A_MARK,
3607 };
3608 static const unsigned int sdhi2_wp_b_pins[] = {
3609 /* WP */
3610 RCAR_GP_PIN(5, 11),
3611 };
3612 static const unsigned int sdhi2_wp_b_mux[] = {
3613 SD2_WP_B_MARK,
3614 };
3615 static const unsigned int sdhi2_ds_pins[] = {
3616 /* DS */
3617 RCAR_GP_PIN(4, 6),
3618 };
3619 static const unsigned int sdhi2_ds_mux[] = {
3620 SD2_DS_MARK,
3621 };
3622 /* - SDHI3 ------------------------------------------------------------------ */
3623 static const unsigned int sdhi3_data1_pins[] = {
3624 /* D0 */
3625 RCAR_GP_PIN(4, 9),
3626 };
3627 static const unsigned int sdhi3_data1_mux[] = {
3628 SD3_DAT0_MARK,
3629 };
3630 static const unsigned int sdhi3_data4_pins[] = {
3631 /* D[0:3] */
3632 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3633 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3634 };
3635 static const unsigned int sdhi3_data4_mux[] = {
3636 SD3_DAT0_MARK, SD3_DAT1_MARK,
3637 SD3_DAT2_MARK, SD3_DAT3_MARK,
3638 };
3639 static const unsigned int sdhi3_data8_pins[] = {
3640 /* D[0:7] */
3641 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3642 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3643 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3644 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3645 };
3646 static const unsigned int sdhi3_data8_mux[] = {
3647 SD3_DAT0_MARK, SD3_DAT1_MARK,
3648 SD3_DAT2_MARK, SD3_DAT3_MARK,
3649 SD3_DAT4_MARK, SD3_DAT5_MARK,
3650 SD3_DAT6_MARK, SD3_DAT7_MARK,
3651 };
3652 static const unsigned int sdhi3_ctrl_pins[] = {
3653 /* CLK, CMD */
3654 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3655 };
3656 static const unsigned int sdhi3_ctrl_mux[] = {
3657 SD3_CLK_MARK, SD3_CMD_MARK,
3658 };
3659 static const unsigned int sdhi3_cd_pins[] = {
3660 /* CD */
3661 RCAR_GP_PIN(4, 15),
3662 };
3663 static const unsigned int sdhi3_cd_mux[] = {
3664 SD3_CD_MARK,
3665 };
3666 static const unsigned int sdhi3_wp_pins[] = {
3667 /* WP */
3668 RCAR_GP_PIN(4, 16),
3669 };
3670 static const unsigned int sdhi3_wp_mux[] = {
3671 SD3_WP_MARK,
3672 };
3673 static const unsigned int sdhi3_ds_pins[] = {
3674 /* DS */
3675 RCAR_GP_PIN(4, 17),
3676 };
3677 static const unsigned int sdhi3_ds_mux[] = {
3678 SD3_DS_MARK,
3679 };
3680
3681 /* - SSI -------------------------------------------------------------------- */
3682 static const unsigned int ssi0_data_pins[] = {
3683 /* SDATA */
3684 RCAR_GP_PIN(6, 2),
3685 };
3686 static const unsigned int ssi0_data_mux[] = {
3687 SSI_SDATA0_MARK,
3688 };
3689 static const unsigned int ssi01239_ctrl_pins[] = {
3690 /* SCK, WS */
3691 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3692 };
3693 static const unsigned int ssi01239_ctrl_mux[] = {
3694 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3695 };
3696 static const unsigned int ssi1_data_a_pins[] = {
3697 /* SDATA */
3698 RCAR_GP_PIN(6, 3),
3699 };
3700 static const unsigned int ssi1_data_a_mux[] = {
3701 SSI_SDATA1_A_MARK,
3702 };
3703 static const unsigned int ssi1_data_b_pins[] = {
3704 /* SDATA */
3705 RCAR_GP_PIN(5, 12),
3706 };
3707 static const unsigned int ssi1_data_b_mux[] = {
3708 SSI_SDATA1_B_MARK,
3709 };
3710 static const unsigned int ssi1_ctrl_a_pins[] = {
3711 /* SCK, WS */
3712 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3713 };
3714 static const unsigned int ssi1_ctrl_a_mux[] = {
3715 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3716 };
3717 static const unsigned int ssi1_ctrl_b_pins[] = {
3718 /* SCK, WS */
3719 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3720 };
3721 static const unsigned int ssi1_ctrl_b_mux[] = {
3722 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3723 };
3724 static const unsigned int ssi2_data_a_pins[] = {
3725 /* SDATA */
3726 RCAR_GP_PIN(6, 4),
3727 };
3728 static const unsigned int ssi2_data_a_mux[] = {
3729 SSI_SDATA2_A_MARK,
3730 };
3731 static const unsigned int ssi2_data_b_pins[] = {
3732 /* SDATA */
3733 RCAR_GP_PIN(5, 13),
3734 };
3735 static const unsigned int ssi2_data_b_mux[] = {
3736 SSI_SDATA2_B_MARK,
3737 };
3738 static const unsigned int ssi2_ctrl_a_pins[] = {
3739 /* SCK, WS */
3740 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3741 };
3742 static const unsigned int ssi2_ctrl_a_mux[] = {
3743 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3744 };
3745 static const unsigned int ssi2_ctrl_b_pins[] = {
3746 /* SCK, WS */
3747 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3748 };
3749 static const unsigned int ssi2_ctrl_b_mux[] = {
3750 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3751 };
3752 static const unsigned int ssi3_data_pins[] = {
3753 /* SDATA */
3754 RCAR_GP_PIN(6, 7),
3755 };
3756 static const unsigned int ssi3_data_mux[] = {
3757 SSI_SDATA3_MARK,
3758 };
3759 static const unsigned int ssi349_ctrl_pins[] = {
3760 /* SCK, WS */
3761 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3762 };
3763 static const unsigned int ssi349_ctrl_mux[] = {
3764 SSI_SCK349_MARK, SSI_WS349_MARK,
3765 };
3766 static const unsigned int ssi4_data_pins[] = {
3767 /* SDATA */
3768 RCAR_GP_PIN(6, 10),
3769 };
3770 static const unsigned int ssi4_data_mux[] = {
3771 SSI_SDATA4_MARK,
3772 };
3773 static const unsigned int ssi4_ctrl_pins[] = {
3774 /* SCK, WS */
3775 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3776 };
3777 static const unsigned int ssi4_ctrl_mux[] = {
3778 SSI_SCK4_MARK, SSI_WS4_MARK,
3779 };
3780 static const unsigned int ssi5_data_pins[] = {
3781 /* SDATA */
3782 RCAR_GP_PIN(6, 13),
3783 };
3784 static const unsigned int ssi5_data_mux[] = {
3785 SSI_SDATA5_MARK,
3786 };
3787 static const unsigned int ssi5_ctrl_pins[] = {
3788 /* SCK, WS */
3789 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3790 };
3791 static const unsigned int ssi5_ctrl_mux[] = {
3792 SSI_SCK5_MARK, SSI_WS5_MARK,
3793 };
3794 static const unsigned int ssi6_data_pins[] = {
3795 /* SDATA */
3796 RCAR_GP_PIN(6, 16),
3797 };
3798 static const unsigned int ssi6_data_mux[] = {
3799 SSI_SDATA6_MARK,
3800 };
3801 static const unsigned int ssi6_ctrl_pins[] = {
3802 /* SCK, WS */
3803 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3804 };
3805 static const unsigned int ssi6_ctrl_mux[] = {
3806 SSI_SCK6_MARK, SSI_WS6_MARK,
3807 };
3808 static const unsigned int ssi7_data_pins[] = {
3809 /* SDATA */
3810 RCAR_GP_PIN(6, 19),
3811 };
3812 static const unsigned int ssi7_data_mux[] = {
3813 SSI_SDATA7_MARK,
3814 };
3815 static const unsigned int ssi78_ctrl_pins[] = {
3816 /* SCK, WS */
3817 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3818 };
3819 static const unsigned int ssi78_ctrl_mux[] = {
3820 SSI_SCK78_MARK, SSI_WS78_MARK,
3821 };
3822 static const unsigned int ssi8_data_pins[] = {
3823 /* SDATA */
3824 RCAR_GP_PIN(6, 20),
3825 };
3826 static const unsigned int ssi8_data_mux[] = {
3827 SSI_SDATA8_MARK,
3828 };
3829 static const unsigned int ssi9_data_a_pins[] = {
3830 /* SDATA */
3831 RCAR_GP_PIN(6, 21),
3832 };
3833 static const unsigned int ssi9_data_a_mux[] = {
3834 SSI_SDATA9_A_MARK,
3835 };
3836 static const unsigned int ssi9_data_b_pins[] = {
3837 /* SDATA */
3838 RCAR_GP_PIN(5, 14),
3839 };
3840 static const unsigned int ssi9_data_b_mux[] = {
3841 SSI_SDATA9_B_MARK,
3842 };
3843 static const unsigned int ssi9_ctrl_a_pins[] = {
3844 /* SCK, WS */
3845 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3846 };
3847 static const unsigned int ssi9_ctrl_a_mux[] = {
3848 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3849 };
3850 static const unsigned int ssi9_ctrl_b_pins[] = {
3851 /* SCK, WS */
3852 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3853 };
3854 static const unsigned int ssi9_ctrl_b_mux[] = {
3855 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3856 };
3857
3858 /* - TMU -------------------------------------------------------------------- */
3859 static const unsigned int tmu_tclk1_a_pins[] = {
3860 /* TCLK */
3861 RCAR_GP_PIN(6, 23),
3862 };
3863 static const unsigned int tmu_tclk1_a_mux[] = {
3864 TCLK1_A_MARK,
3865 };
3866 static const unsigned int tmu_tclk1_b_pins[] = {
3867 /* TCLK */
3868 RCAR_GP_PIN(5, 19),
3869 };
3870 static const unsigned int tmu_tclk1_b_mux[] = {
3871 TCLK1_B_MARK,
3872 };
3873 static const unsigned int tmu_tclk2_a_pins[] = {
3874 /* TCLK */
3875 RCAR_GP_PIN(6, 19),
3876 };
3877 static const unsigned int tmu_tclk2_a_mux[] = {
3878 TCLK2_A_MARK,
3879 };
3880 static const unsigned int tmu_tclk2_b_pins[] = {
3881 /* TCLK */
3882 RCAR_GP_PIN(6, 28),
3883 };
3884 static const unsigned int tmu_tclk2_b_mux[] = {
3885 TCLK2_B_MARK,
3886 };
3887
3888 /* - USB0 ------------------------------------------------------------------- */
3889 static const unsigned int usb0_pins[] = {
3890 /* PWEN, OVC */
3891 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3892 };
3893 static const unsigned int usb0_mux[] = {
3894 USB0_PWEN_MARK, USB0_OVC_MARK,
3895 };
3896 /* - USB1 ------------------------------------------------------------------- */
3897 static const unsigned int usb1_pins[] = {
3898 /* PWEN, OVC */
3899 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3900 };
3901 static const unsigned int usb1_mux[] = {
3902 USB1_PWEN_MARK, USB1_OVC_MARK,
3903 };
3904 /* - USB2 ------------------------------------------------------------------- */
3905 static const unsigned int usb2_pins[] = {
3906 /* PWEN, OVC */
3907 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3908 };
3909 static const unsigned int usb2_mux[] = {
3910 USB2_PWEN_MARK, USB2_OVC_MARK,
3911 };
3912 /* - USB2_CH3 --------------------------------------------------------------- */
3913 static const unsigned int usb2_ch3_pins[] = {
3914 /* PWEN, OVC */
3915 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3916 };
3917 static const unsigned int usb2_ch3_mux[] = {
3918 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3919 };
3920
3921 /* - USB30 ------------------------------------------------------------------ */
3922 static const unsigned int usb30_pins[] = {
3923 /* PWEN, OVC */
3924 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3925 };
3926 static const unsigned int usb30_mux[] = {
3927 USB30_PWEN_MARK, USB30_OVC_MARK,
3928 };
3929
3930 /* - VIN4 ------------------------------------------------------------------- */
3931 static const unsigned int vin4_data18_a_pins[] = {
3932 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3933 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3934 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3935 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3936 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3937 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3938 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3939 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3940 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3941 };
3942 static const unsigned int vin4_data18_a_mux[] = {
3943 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3944 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3945 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3946 VI4_DATA10_MARK, VI4_DATA11_MARK,
3947 VI4_DATA12_MARK, VI4_DATA13_MARK,
3948 VI4_DATA14_MARK, VI4_DATA15_MARK,
3949 VI4_DATA18_MARK, VI4_DATA19_MARK,
3950 VI4_DATA20_MARK, VI4_DATA21_MARK,
3951 VI4_DATA22_MARK, VI4_DATA23_MARK,
3952 };
3953 static const unsigned int vin4_data18_b_pins[] = {
3954 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3955 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3956 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3957 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3958 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3959 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3960 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3961 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3962 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3963 };
3964 static const unsigned int vin4_data18_b_mux[] = {
3965 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3966 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3967 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3968 VI4_DATA10_MARK, VI4_DATA11_MARK,
3969 VI4_DATA12_MARK, VI4_DATA13_MARK,
3970 VI4_DATA14_MARK, VI4_DATA15_MARK,
3971 VI4_DATA18_MARK, VI4_DATA19_MARK,
3972 VI4_DATA20_MARK, VI4_DATA21_MARK,
3973 VI4_DATA22_MARK, VI4_DATA23_MARK,
3974 };
3975 static const union vin_data vin4_data_a_pins = {
3976 .data24 = {
3977 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3978 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3979 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3980 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3981 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3982 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3983 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3984 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3985 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3986 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3987 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3988 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3989 },
3990 };
3991 static const union vin_data vin4_data_a_mux = {
3992 .data24 = {
3993 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3994 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3995 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3996 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3997 VI4_DATA8_MARK, VI4_DATA9_MARK,
3998 VI4_DATA10_MARK, VI4_DATA11_MARK,
3999 VI4_DATA12_MARK, VI4_DATA13_MARK,
4000 VI4_DATA14_MARK, VI4_DATA15_MARK,
4001 VI4_DATA16_MARK, VI4_DATA17_MARK,
4002 VI4_DATA18_MARK, VI4_DATA19_MARK,
4003 VI4_DATA20_MARK, VI4_DATA21_MARK,
4004 VI4_DATA22_MARK, VI4_DATA23_MARK,
4005 },
4006 };
4007 static const union vin_data vin4_data_b_pins = {
4008 .data24 = {
4009 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4010 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4011 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4012 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4013 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4014 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4015 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4016 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4017 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4018 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4019 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4020 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4021 },
4022 };
4023 static const union vin_data vin4_data_b_mux = {
4024 .data24 = {
4025 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4026 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4027 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4028 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4029 VI4_DATA8_MARK, VI4_DATA9_MARK,
4030 VI4_DATA10_MARK, VI4_DATA11_MARK,
4031 VI4_DATA12_MARK, VI4_DATA13_MARK,
4032 VI4_DATA14_MARK, VI4_DATA15_MARK,
4033 VI4_DATA16_MARK, VI4_DATA17_MARK,
4034 VI4_DATA18_MARK, VI4_DATA19_MARK,
4035 VI4_DATA20_MARK, VI4_DATA21_MARK,
4036 VI4_DATA22_MARK, VI4_DATA23_MARK,
4037 },
4038 };
4039 static const unsigned int vin4_sync_pins[] = {
4040 /* HSYNC#, VSYNC# */
4041 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4042 };
4043 static const unsigned int vin4_sync_mux[] = {
4044 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4045 };
4046 static const unsigned int vin4_field_pins[] = {
4047 /* FIELD */
4048 RCAR_GP_PIN(1, 16),
4049 };
4050 static const unsigned int vin4_field_mux[] = {
4051 VI4_FIELD_MARK,
4052 };
4053 static const unsigned int vin4_clkenb_pins[] = {
4054 /* CLKENB */
4055 RCAR_GP_PIN(1, 19),
4056 };
4057 static const unsigned int vin4_clkenb_mux[] = {
4058 VI4_CLKENB_MARK,
4059 };
4060 static const unsigned int vin4_clk_pins[] = {
4061 /* CLK */
4062 RCAR_GP_PIN(1, 27),
4063 };
4064 static const unsigned int vin4_clk_mux[] = {
4065 VI4_CLK_MARK,
4066 };
4067
4068 /* - VIN5 ------------------------------------------------------------------- */
4069 static const unsigned int vin5_data8_pins[] = {
4070 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4071 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4072 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4073 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4074 };
4075 static const unsigned int vin5_data8_mux[] = {
4076 VI5_DATA0_MARK, VI5_DATA1_MARK,
4077 VI5_DATA2_MARK, VI5_DATA3_MARK,
4078 VI5_DATA4_MARK, VI5_DATA5_MARK,
4079 VI5_DATA6_MARK, VI5_DATA7_MARK,
4080 };
4081 static const unsigned int vin5_data10_pins[] = {
4082 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4083 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4084 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4085 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4086 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4087 };
4088 static const unsigned int vin5_data10_mux[] = {
4089 VI5_DATA0_MARK, VI5_DATA1_MARK,
4090 VI5_DATA2_MARK, VI5_DATA3_MARK,
4091 VI5_DATA4_MARK, VI5_DATA5_MARK,
4092 VI5_DATA6_MARK, VI5_DATA7_MARK,
4093 VI5_DATA8_MARK, VI5_DATA9_MARK,
4094 };
4095 static const unsigned int vin5_data12_pins[] = {
4096 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4097 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4098 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4099 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4100 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4101 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4102 };
4103 static const unsigned int vin5_data12_mux[] = {
4104 VI5_DATA0_MARK, VI5_DATA1_MARK,
4105 VI5_DATA2_MARK, VI5_DATA3_MARK,
4106 VI5_DATA4_MARK, VI5_DATA5_MARK,
4107 VI5_DATA6_MARK, VI5_DATA7_MARK,
4108 VI5_DATA8_MARK, VI5_DATA9_MARK,
4109 VI5_DATA10_MARK, VI5_DATA11_MARK,
4110 };
4111 static const unsigned int vin5_data16_pins[] = {
4112 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4113 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4114 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4115 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4116 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4117 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4118 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4119 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4120 };
4121 static const unsigned int vin5_data16_mux[] = {
4122 VI5_DATA0_MARK, VI5_DATA1_MARK,
4123 VI5_DATA2_MARK, VI5_DATA3_MARK,
4124 VI5_DATA4_MARK, VI5_DATA5_MARK,
4125 VI5_DATA6_MARK, VI5_DATA7_MARK,
4126 VI5_DATA8_MARK, VI5_DATA9_MARK,
4127 VI5_DATA10_MARK, VI5_DATA11_MARK,
4128 VI5_DATA12_MARK, VI5_DATA13_MARK,
4129 VI5_DATA14_MARK, VI5_DATA15_MARK,
4130 };
4131 static const unsigned int vin5_sync_pins[] = {
4132 /* HSYNC#, VSYNC# */
4133 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4134 };
4135 static const unsigned int vin5_sync_mux[] = {
4136 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4137 };
4138 static const unsigned int vin5_field_pins[] = {
4139 RCAR_GP_PIN(1, 11),
4140 };
4141 static const unsigned int vin5_field_mux[] = {
4142 /* FIELD */
4143 VI5_FIELD_MARK,
4144 };
4145 static const unsigned int vin5_clkenb_pins[] = {
4146 RCAR_GP_PIN(1, 20),
4147 };
4148 static const unsigned int vin5_clkenb_mux[] = {
4149 /* CLKENB */
4150 VI5_CLKENB_MARK,
4151 };
4152 static const unsigned int vin5_clk_pins[] = {
4153 RCAR_GP_PIN(1, 21),
4154 };
4155 static const unsigned int vin5_clk_mux[] = {
4156 /* CLK */
4157 VI5_CLK_MARK,
4158 };
4159
4160 static const struct sh_pfc_pin_group pinmux_groups[] = {
4161 SH_PFC_PIN_GROUP(audio_clk_a_a),
4162 SH_PFC_PIN_GROUP(audio_clk_a_b),
4163 SH_PFC_PIN_GROUP(audio_clk_a_c),
4164 SH_PFC_PIN_GROUP(audio_clk_b_a),
4165 SH_PFC_PIN_GROUP(audio_clk_b_b),
4166 SH_PFC_PIN_GROUP(audio_clk_c_a),
4167 SH_PFC_PIN_GROUP(audio_clk_c_b),
4168 SH_PFC_PIN_GROUP(audio_clkout_a),
4169 SH_PFC_PIN_GROUP(audio_clkout_b),
4170 SH_PFC_PIN_GROUP(audio_clkout_c),
4171 SH_PFC_PIN_GROUP(audio_clkout_d),
4172 SH_PFC_PIN_GROUP(audio_clkout1_a),
4173 SH_PFC_PIN_GROUP(audio_clkout1_b),
4174 SH_PFC_PIN_GROUP(audio_clkout2_a),
4175 SH_PFC_PIN_GROUP(audio_clkout2_b),
4176 SH_PFC_PIN_GROUP(audio_clkout3_a),
4177 SH_PFC_PIN_GROUP(audio_clkout3_b),
4178 SH_PFC_PIN_GROUP(avb_link),
4179 SH_PFC_PIN_GROUP(avb_magic),
4180 SH_PFC_PIN_GROUP(avb_phy_int),
4181 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4182 SH_PFC_PIN_GROUP(avb_mdio),
4183 SH_PFC_PIN_GROUP(avb_mii),
4184 SH_PFC_PIN_GROUP(avb_avtp_pps),
4185 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4186 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4187 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4188 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4189 SH_PFC_PIN_GROUP(can0_data_a),
4190 SH_PFC_PIN_GROUP(can0_data_b),
4191 SH_PFC_PIN_GROUP(can1_data),
4192 SH_PFC_PIN_GROUP(can_clk),
4193 SH_PFC_PIN_GROUP(canfd0_data_a),
4194 SH_PFC_PIN_GROUP(canfd0_data_b),
4195 SH_PFC_PIN_GROUP(canfd1_data),
4196 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4197 SH_PFC_PIN_GROUP(drif0_data0_a),
4198 SH_PFC_PIN_GROUP(drif0_data1_a),
4199 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4200 SH_PFC_PIN_GROUP(drif0_data0_b),
4201 SH_PFC_PIN_GROUP(drif0_data1_b),
4202 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4203 SH_PFC_PIN_GROUP(drif0_data0_c),
4204 SH_PFC_PIN_GROUP(drif0_data1_c),
4205 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4206 SH_PFC_PIN_GROUP(drif1_data0_a),
4207 SH_PFC_PIN_GROUP(drif1_data1_a),
4208 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4209 SH_PFC_PIN_GROUP(drif1_data0_b),
4210 SH_PFC_PIN_GROUP(drif1_data1_b),
4211 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4212 SH_PFC_PIN_GROUP(drif1_data0_c),
4213 SH_PFC_PIN_GROUP(drif1_data1_c),
4214 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4215 SH_PFC_PIN_GROUP(drif2_data0_a),
4216 SH_PFC_PIN_GROUP(drif2_data1_a),
4217 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4218 SH_PFC_PIN_GROUP(drif2_data0_b),
4219 SH_PFC_PIN_GROUP(drif2_data1_b),
4220 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4221 SH_PFC_PIN_GROUP(drif3_data0_a),
4222 SH_PFC_PIN_GROUP(drif3_data1_a),
4223 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4224 SH_PFC_PIN_GROUP(drif3_data0_b),
4225 SH_PFC_PIN_GROUP(drif3_data1_b),
4226 SH_PFC_PIN_GROUP(du_rgb666),
4227 SH_PFC_PIN_GROUP(du_rgb888),
4228 SH_PFC_PIN_GROUP(du_clk_out_0),
4229 SH_PFC_PIN_GROUP(du_clk_out_1),
4230 SH_PFC_PIN_GROUP(du_sync),
4231 SH_PFC_PIN_GROUP(du_oddf),
4232 SH_PFC_PIN_GROUP(du_cde),
4233 SH_PFC_PIN_GROUP(du_disp),
4234 SH_PFC_PIN_GROUP(hdmi0_cec),
4235 SH_PFC_PIN_GROUP(hdmi1_cec),
4236 SH_PFC_PIN_GROUP(hscif0_data),
4237 SH_PFC_PIN_GROUP(hscif0_clk),
4238 SH_PFC_PIN_GROUP(hscif0_ctrl),
4239 SH_PFC_PIN_GROUP(hscif1_data_a),
4240 SH_PFC_PIN_GROUP(hscif1_clk_a),
4241 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4242 SH_PFC_PIN_GROUP(hscif1_data_b),
4243 SH_PFC_PIN_GROUP(hscif1_clk_b),
4244 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4245 SH_PFC_PIN_GROUP(hscif2_data_a),
4246 SH_PFC_PIN_GROUP(hscif2_clk_a),
4247 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4248 SH_PFC_PIN_GROUP(hscif2_data_b),
4249 SH_PFC_PIN_GROUP(hscif2_clk_b),
4250 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4251 SH_PFC_PIN_GROUP(hscif2_data_c),
4252 SH_PFC_PIN_GROUP(hscif2_clk_c),
4253 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4254 SH_PFC_PIN_GROUP(hscif3_data_a),
4255 SH_PFC_PIN_GROUP(hscif3_clk),
4256 SH_PFC_PIN_GROUP(hscif3_ctrl),
4257 SH_PFC_PIN_GROUP(hscif3_data_b),
4258 SH_PFC_PIN_GROUP(hscif3_data_c),
4259 SH_PFC_PIN_GROUP(hscif3_data_d),
4260 SH_PFC_PIN_GROUP(hscif4_data_a),
4261 SH_PFC_PIN_GROUP(hscif4_clk),
4262 SH_PFC_PIN_GROUP(hscif4_ctrl),
4263 SH_PFC_PIN_GROUP(hscif4_data_b),
4264 SH_PFC_PIN_GROUP(i2c1_a),
4265 SH_PFC_PIN_GROUP(i2c1_b),
4266 SH_PFC_PIN_GROUP(i2c2_a),
4267 SH_PFC_PIN_GROUP(i2c2_b),
4268 SH_PFC_PIN_GROUP(i2c6_a),
4269 SH_PFC_PIN_GROUP(i2c6_b),
4270 SH_PFC_PIN_GROUP(i2c6_c),
4271 SH_PFC_PIN_GROUP(intc_ex_irq0),
4272 SH_PFC_PIN_GROUP(intc_ex_irq1),
4273 SH_PFC_PIN_GROUP(intc_ex_irq2),
4274 SH_PFC_PIN_GROUP(intc_ex_irq3),
4275 SH_PFC_PIN_GROUP(intc_ex_irq4),
4276 SH_PFC_PIN_GROUP(intc_ex_irq5),
4277 SH_PFC_PIN_GROUP(msiof0_clk),
4278 SH_PFC_PIN_GROUP(msiof0_sync),
4279 SH_PFC_PIN_GROUP(msiof0_ss1),
4280 SH_PFC_PIN_GROUP(msiof0_ss2),
4281 SH_PFC_PIN_GROUP(msiof0_txd),
4282 SH_PFC_PIN_GROUP(msiof0_rxd),
4283 SH_PFC_PIN_GROUP(msiof1_clk_a),
4284 SH_PFC_PIN_GROUP(msiof1_sync_a),
4285 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4286 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4287 SH_PFC_PIN_GROUP(msiof1_txd_a),
4288 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4289 SH_PFC_PIN_GROUP(msiof1_clk_b),
4290 SH_PFC_PIN_GROUP(msiof1_sync_b),
4291 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4292 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4293 SH_PFC_PIN_GROUP(msiof1_txd_b),
4294 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4295 SH_PFC_PIN_GROUP(msiof1_clk_c),
4296 SH_PFC_PIN_GROUP(msiof1_sync_c),
4297 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4298 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4299 SH_PFC_PIN_GROUP(msiof1_txd_c),
4300 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4301 SH_PFC_PIN_GROUP(msiof1_clk_d),
4302 SH_PFC_PIN_GROUP(msiof1_sync_d),
4303 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4304 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4305 SH_PFC_PIN_GROUP(msiof1_txd_d),
4306 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4307 SH_PFC_PIN_GROUP(msiof1_clk_e),
4308 SH_PFC_PIN_GROUP(msiof1_sync_e),
4309 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4310 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4311 SH_PFC_PIN_GROUP(msiof1_txd_e),
4312 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4313 SH_PFC_PIN_GROUP(msiof1_clk_f),
4314 SH_PFC_PIN_GROUP(msiof1_sync_f),
4315 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4316 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4317 SH_PFC_PIN_GROUP(msiof1_txd_f),
4318 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4319 SH_PFC_PIN_GROUP(msiof1_clk_g),
4320 SH_PFC_PIN_GROUP(msiof1_sync_g),
4321 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4322 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4323 SH_PFC_PIN_GROUP(msiof1_txd_g),
4324 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4325 SH_PFC_PIN_GROUP(msiof2_clk_a),
4326 SH_PFC_PIN_GROUP(msiof2_sync_a),
4327 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4328 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4329 SH_PFC_PIN_GROUP(msiof2_txd_a),
4330 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4331 SH_PFC_PIN_GROUP(msiof2_clk_b),
4332 SH_PFC_PIN_GROUP(msiof2_sync_b),
4333 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4334 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4335 SH_PFC_PIN_GROUP(msiof2_txd_b),
4336 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4337 SH_PFC_PIN_GROUP(msiof2_clk_c),
4338 SH_PFC_PIN_GROUP(msiof2_sync_c),
4339 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4340 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4341 SH_PFC_PIN_GROUP(msiof2_txd_c),
4342 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4343 SH_PFC_PIN_GROUP(msiof2_clk_d),
4344 SH_PFC_PIN_GROUP(msiof2_sync_d),
4345 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4346 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4347 SH_PFC_PIN_GROUP(msiof2_txd_d),
4348 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4349 SH_PFC_PIN_GROUP(msiof3_clk_a),
4350 SH_PFC_PIN_GROUP(msiof3_sync_a),
4351 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4352 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4353 SH_PFC_PIN_GROUP(msiof3_txd_a),
4354 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4355 SH_PFC_PIN_GROUP(msiof3_clk_b),
4356 SH_PFC_PIN_GROUP(msiof3_sync_b),
4357 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4358 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4359 SH_PFC_PIN_GROUP(msiof3_txd_b),
4360 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4361 SH_PFC_PIN_GROUP(msiof3_clk_c),
4362 SH_PFC_PIN_GROUP(msiof3_sync_c),
4363 SH_PFC_PIN_GROUP(msiof3_txd_c),
4364 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4365 SH_PFC_PIN_GROUP(msiof3_clk_d),
4366 SH_PFC_PIN_GROUP(msiof3_sync_d),
4367 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4368 SH_PFC_PIN_GROUP(msiof3_txd_d),
4369 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4370 SH_PFC_PIN_GROUP(msiof3_clk_e),
4371 SH_PFC_PIN_GROUP(msiof3_sync_e),
4372 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4373 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4374 SH_PFC_PIN_GROUP(msiof3_txd_e),
4375 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4376 SH_PFC_PIN_GROUP(pwm0),
4377 SH_PFC_PIN_GROUP(pwm1_a),
4378 SH_PFC_PIN_GROUP(pwm1_b),
4379 SH_PFC_PIN_GROUP(pwm2_a),
4380 SH_PFC_PIN_GROUP(pwm2_b),
4381 SH_PFC_PIN_GROUP(pwm3_a),
4382 SH_PFC_PIN_GROUP(pwm3_b),
4383 SH_PFC_PIN_GROUP(pwm4_a),
4384 SH_PFC_PIN_GROUP(pwm4_b),
4385 SH_PFC_PIN_GROUP(pwm5_a),
4386 SH_PFC_PIN_GROUP(pwm5_b),
4387 SH_PFC_PIN_GROUP(pwm6_a),
4388 SH_PFC_PIN_GROUP(pwm6_b),
4389 SH_PFC_PIN_GROUP(sata0_devslp_a),
4390 SH_PFC_PIN_GROUP(sata0_devslp_b),
4391 SH_PFC_PIN_GROUP(scif0_data),
4392 SH_PFC_PIN_GROUP(scif0_clk),
4393 SH_PFC_PIN_GROUP(scif0_ctrl),
4394 SH_PFC_PIN_GROUP(scif1_data_a),
4395 SH_PFC_PIN_GROUP(scif1_clk),
4396 SH_PFC_PIN_GROUP(scif1_ctrl),
4397 SH_PFC_PIN_GROUP(scif1_data_b),
4398 SH_PFC_PIN_GROUP(scif2_data_a),
4399 SH_PFC_PIN_GROUP(scif2_clk),
4400 SH_PFC_PIN_GROUP(scif2_data_b),
4401 SH_PFC_PIN_GROUP(scif3_data_a),
4402 SH_PFC_PIN_GROUP(scif3_clk),
4403 SH_PFC_PIN_GROUP(scif3_ctrl),
4404 SH_PFC_PIN_GROUP(scif3_data_b),
4405 SH_PFC_PIN_GROUP(scif4_data_a),
4406 SH_PFC_PIN_GROUP(scif4_clk_a),
4407 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4408 SH_PFC_PIN_GROUP(scif4_data_b),
4409 SH_PFC_PIN_GROUP(scif4_clk_b),
4410 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4411 SH_PFC_PIN_GROUP(scif4_data_c),
4412 SH_PFC_PIN_GROUP(scif4_clk_c),
4413 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4414 SH_PFC_PIN_GROUP(scif5_data_a),
4415 SH_PFC_PIN_GROUP(scif5_clk_a),
4416 SH_PFC_PIN_GROUP(scif5_data_b),
4417 SH_PFC_PIN_GROUP(scif5_clk_b),
4418 SH_PFC_PIN_GROUP(scif_clk_a),
4419 SH_PFC_PIN_GROUP(scif_clk_b),
4420 SH_PFC_PIN_GROUP(sdhi0_data1),
4421 SH_PFC_PIN_GROUP(sdhi0_data4),
4422 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4423 SH_PFC_PIN_GROUP(sdhi0_cd),
4424 SH_PFC_PIN_GROUP(sdhi0_wp),
4425 SH_PFC_PIN_GROUP(sdhi1_data1),
4426 SH_PFC_PIN_GROUP(sdhi1_data4),
4427 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4428 SH_PFC_PIN_GROUP(sdhi1_cd),
4429 SH_PFC_PIN_GROUP(sdhi1_wp),
4430 SH_PFC_PIN_GROUP(sdhi2_data1),
4431 SH_PFC_PIN_GROUP(sdhi2_data4),
4432 SH_PFC_PIN_GROUP(sdhi2_data8),
4433 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4434 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4435 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4436 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4437 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4438 SH_PFC_PIN_GROUP(sdhi2_ds),
4439 SH_PFC_PIN_GROUP(sdhi3_data1),
4440 SH_PFC_PIN_GROUP(sdhi3_data4),
4441 SH_PFC_PIN_GROUP(sdhi3_data8),
4442 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4443 SH_PFC_PIN_GROUP(sdhi3_cd),
4444 SH_PFC_PIN_GROUP(sdhi3_wp),
4445 SH_PFC_PIN_GROUP(sdhi3_ds),
4446 SH_PFC_PIN_GROUP(ssi0_data),
4447 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4448 SH_PFC_PIN_GROUP(ssi1_data_a),
4449 SH_PFC_PIN_GROUP(ssi1_data_b),
4450 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4451 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4452 SH_PFC_PIN_GROUP(ssi2_data_a),
4453 SH_PFC_PIN_GROUP(ssi2_data_b),
4454 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4455 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4456 SH_PFC_PIN_GROUP(ssi3_data),
4457 SH_PFC_PIN_GROUP(ssi349_ctrl),
4458 SH_PFC_PIN_GROUP(ssi4_data),
4459 SH_PFC_PIN_GROUP(ssi4_ctrl),
4460 SH_PFC_PIN_GROUP(ssi5_data),
4461 SH_PFC_PIN_GROUP(ssi5_ctrl),
4462 SH_PFC_PIN_GROUP(ssi6_data),
4463 SH_PFC_PIN_GROUP(ssi6_ctrl),
4464 SH_PFC_PIN_GROUP(ssi7_data),
4465 SH_PFC_PIN_GROUP(ssi78_ctrl),
4466 SH_PFC_PIN_GROUP(ssi8_data),
4467 SH_PFC_PIN_GROUP(ssi9_data_a),
4468 SH_PFC_PIN_GROUP(ssi9_data_b),
4469 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4470 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4471 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4472 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4473 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4474 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4475 SH_PFC_PIN_GROUP(usb0),
4476 SH_PFC_PIN_GROUP(usb1),
4477 SH_PFC_PIN_GROUP(usb2),
4478 SH_PFC_PIN_GROUP(usb2_ch3),
4479 SH_PFC_PIN_GROUP(usb30),
4480 VIN_DATA_PIN_GROUP(vin4_data_a, 8),
4481 VIN_DATA_PIN_GROUP(vin4_data_a, 10),
4482 VIN_DATA_PIN_GROUP(vin4_data_a, 12),
4483 VIN_DATA_PIN_GROUP(vin4_data_a, 16),
4484 SH_PFC_PIN_GROUP(vin4_data18_a),
4485 VIN_DATA_PIN_GROUP(vin4_data_a, 20),
4486 VIN_DATA_PIN_GROUP(vin4_data_a, 24),
4487 VIN_DATA_PIN_GROUP(vin4_data_b, 8),
4488 VIN_DATA_PIN_GROUP(vin4_data_b, 10),
4489 VIN_DATA_PIN_GROUP(vin4_data_b, 12),
4490 VIN_DATA_PIN_GROUP(vin4_data_b, 16),
4491 SH_PFC_PIN_GROUP(vin4_data18_b),
4492 VIN_DATA_PIN_GROUP(vin4_data_b, 20),
4493 VIN_DATA_PIN_GROUP(vin4_data_b, 24),
4494 SH_PFC_PIN_GROUP(vin4_sync),
4495 SH_PFC_PIN_GROUP(vin4_field),
4496 SH_PFC_PIN_GROUP(vin4_clkenb),
4497 SH_PFC_PIN_GROUP(vin4_clk),
4498 SH_PFC_PIN_GROUP(vin5_data8),
4499 SH_PFC_PIN_GROUP(vin5_data10),
4500 SH_PFC_PIN_GROUP(vin5_data12),
4501 SH_PFC_PIN_GROUP(vin5_data16),
4502 SH_PFC_PIN_GROUP(vin5_sync),
4503 SH_PFC_PIN_GROUP(vin5_field),
4504 SH_PFC_PIN_GROUP(vin5_clkenb),
4505 SH_PFC_PIN_GROUP(vin5_clk),
4506 };
4507
4508 static const char * const audio_clk_groups[] = {
4509 "audio_clk_a_a",
4510 "audio_clk_a_b",
4511 "audio_clk_a_c",
4512 "audio_clk_b_a",
4513 "audio_clk_b_b",
4514 "audio_clk_c_a",
4515 "audio_clk_c_b",
4516 "audio_clkout_a",
4517 "audio_clkout_b",
4518 "audio_clkout_c",
4519 "audio_clkout_d",
4520 "audio_clkout1_a",
4521 "audio_clkout1_b",
4522 "audio_clkout2_a",
4523 "audio_clkout2_b",
4524 "audio_clkout3_a",
4525 "audio_clkout3_b",
4526 };
4527
4528 static const char * const avb_groups[] = {
4529 "avb_link",
4530 "avb_magic",
4531 "avb_phy_int",
4532 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4533 "avb_mdio",
4534 "avb_mii",
4535 "avb_avtp_pps",
4536 "avb_avtp_match_a",
4537 "avb_avtp_capture_a",
4538 "avb_avtp_match_b",
4539 "avb_avtp_capture_b",
4540 };
4541
4542 static const char * const can0_groups[] = {
4543 "can0_data_a",
4544 "can0_data_b",
4545 };
4546
4547 static const char * const can1_groups[] = {
4548 "can1_data",
4549 };
4550
4551 static const char * const can_clk_groups[] = {
4552 "can_clk",
4553 };
4554
4555 static const char * const canfd0_groups[] = {
4556 "canfd0_data_a",
4557 "canfd0_data_b",
4558 };
4559
4560 static const char * const canfd1_groups[] = {
4561 "canfd1_data",
4562 };
4563
4564 static const char * const drif0_groups[] = {
4565 "drif0_ctrl_a",
4566 "drif0_data0_a",
4567 "drif0_data1_a",
4568 "drif0_ctrl_b",
4569 "drif0_data0_b",
4570 "drif0_data1_b",
4571 "drif0_ctrl_c",
4572 "drif0_data0_c",
4573 "drif0_data1_c",
4574 };
4575
4576 static const char * const drif1_groups[] = {
4577 "drif1_ctrl_a",
4578 "drif1_data0_a",
4579 "drif1_data1_a",
4580 "drif1_ctrl_b",
4581 "drif1_data0_b",
4582 "drif1_data1_b",
4583 "drif1_ctrl_c",
4584 "drif1_data0_c",
4585 "drif1_data1_c",
4586 };
4587
4588 static const char * const drif2_groups[] = {
4589 "drif2_ctrl_a",
4590 "drif2_data0_a",
4591 "drif2_data1_a",
4592 "drif2_ctrl_b",
4593 "drif2_data0_b",
4594 "drif2_data1_b",
4595 };
4596
4597 static const char * const drif3_groups[] = {
4598 "drif3_ctrl_a",
4599 "drif3_data0_a",
4600 "drif3_data1_a",
4601 "drif3_ctrl_b",
4602 "drif3_data0_b",
4603 "drif3_data1_b",
4604 };
4605
4606 static const char * const du_groups[] = {
4607 "du_rgb666",
4608 "du_rgb888",
4609 "du_clk_out_0",
4610 "du_clk_out_1",
4611 "du_sync",
4612 "du_oddf",
4613 "du_cde",
4614 "du_disp",
4615 };
4616
4617 static const char * const hdmi0_groups[] = {
4618 "hdmi0_cec",
4619 };
4620
4621 static const char * const hdmi1_groups[] = {
4622 "hdmi1_cec",
4623 };
4624
4625 static const char * const hscif0_groups[] = {
4626 "hscif0_data",
4627 "hscif0_clk",
4628 "hscif0_ctrl",
4629 };
4630
4631 static const char * const hscif1_groups[] = {
4632 "hscif1_data_a",
4633 "hscif1_clk_a",
4634 "hscif1_ctrl_a",
4635 "hscif1_data_b",
4636 "hscif1_clk_b",
4637 "hscif1_ctrl_b",
4638 };
4639
4640 static const char * const hscif2_groups[] = {
4641 "hscif2_data_a",
4642 "hscif2_clk_a",
4643 "hscif2_ctrl_a",
4644 "hscif2_data_b",
4645 "hscif2_clk_b",
4646 "hscif2_ctrl_b",
4647 "hscif2_data_c",
4648 "hscif2_clk_c",
4649 "hscif2_ctrl_c",
4650 };
4651
4652 static const char * const hscif3_groups[] = {
4653 "hscif3_data_a",
4654 "hscif3_clk",
4655 "hscif3_ctrl",
4656 "hscif3_data_b",
4657 "hscif3_data_c",
4658 "hscif3_data_d",
4659 };
4660
4661 static const char * const hscif4_groups[] = {
4662 "hscif4_data_a",
4663 "hscif4_clk",
4664 "hscif4_ctrl",
4665 "hscif4_data_b",
4666 };
4667
4668 static const char * const i2c1_groups[] = {
4669 "i2c1_a",
4670 "i2c1_b",
4671 };
4672
4673 static const char * const i2c2_groups[] = {
4674 "i2c2_a",
4675 "i2c2_b",
4676 };
4677
4678 static const char * const i2c6_groups[] = {
4679 "i2c6_a",
4680 "i2c6_b",
4681 "i2c6_c",
4682 };
4683
4684 static const char * const intc_ex_groups[] = {
4685 "intc_ex_irq0",
4686 "intc_ex_irq1",
4687 "intc_ex_irq2",
4688 "intc_ex_irq3",
4689 "intc_ex_irq4",
4690 "intc_ex_irq5",
4691 };
4692
4693 static const char * const msiof0_groups[] = {
4694 "msiof0_clk",
4695 "msiof0_sync",
4696 "msiof0_ss1",
4697 "msiof0_ss2",
4698 "msiof0_txd",
4699 "msiof0_rxd",
4700 };
4701
4702 static const char * const msiof1_groups[] = {
4703 "msiof1_clk_a",
4704 "msiof1_sync_a",
4705 "msiof1_ss1_a",
4706 "msiof1_ss2_a",
4707 "msiof1_txd_a",
4708 "msiof1_rxd_a",
4709 "msiof1_clk_b",
4710 "msiof1_sync_b",
4711 "msiof1_ss1_b",
4712 "msiof1_ss2_b",
4713 "msiof1_txd_b",
4714 "msiof1_rxd_b",
4715 "msiof1_clk_c",
4716 "msiof1_sync_c",
4717 "msiof1_ss1_c",
4718 "msiof1_ss2_c",
4719 "msiof1_txd_c",
4720 "msiof1_rxd_c",
4721 "msiof1_clk_d",
4722 "msiof1_sync_d",
4723 "msiof1_ss1_d",
4724 "msiof1_ss2_d",
4725 "msiof1_txd_d",
4726 "msiof1_rxd_d",
4727 "msiof1_clk_e",
4728 "msiof1_sync_e",
4729 "msiof1_ss1_e",
4730 "msiof1_ss2_e",
4731 "msiof1_txd_e",
4732 "msiof1_rxd_e",
4733 "msiof1_clk_f",
4734 "msiof1_sync_f",
4735 "msiof1_ss1_f",
4736 "msiof1_ss2_f",
4737 "msiof1_txd_f",
4738 "msiof1_rxd_f",
4739 "msiof1_clk_g",
4740 "msiof1_sync_g",
4741 "msiof1_ss1_g",
4742 "msiof1_ss2_g",
4743 "msiof1_txd_g",
4744 "msiof1_rxd_g",
4745 };
4746
4747 static const char * const msiof2_groups[] = {
4748 "msiof2_clk_a",
4749 "msiof2_sync_a",
4750 "msiof2_ss1_a",
4751 "msiof2_ss2_a",
4752 "msiof2_txd_a",
4753 "msiof2_rxd_a",
4754 "msiof2_clk_b",
4755 "msiof2_sync_b",
4756 "msiof2_ss1_b",
4757 "msiof2_ss2_b",
4758 "msiof2_txd_b",
4759 "msiof2_rxd_b",
4760 "msiof2_clk_c",
4761 "msiof2_sync_c",
4762 "msiof2_ss1_c",
4763 "msiof2_ss2_c",
4764 "msiof2_txd_c",
4765 "msiof2_rxd_c",
4766 "msiof2_clk_d",
4767 "msiof2_sync_d",
4768 "msiof2_ss1_d",
4769 "msiof2_ss2_d",
4770 "msiof2_txd_d",
4771 "msiof2_rxd_d",
4772 };
4773
4774 static const char * const msiof3_groups[] = {
4775 "msiof3_clk_a",
4776 "msiof3_sync_a",
4777 "msiof3_ss1_a",
4778 "msiof3_ss2_a",
4779 "msiof3_txd_a",
4780 "msiof3_rxd_a",
4781 "msiof3_clk_b",
4782 "msiof3_sync_b",
4783 "msiof3_ss1_b",
4784 "msiof3_ss2_b",
4785 "msiof3_txd_b",
4786 "msiof3_rxd_b",
4787 "msiof3_clk_c",
4788 "msiof3_sync_c",
4789 "msiof3_txd_c",
4790 "msiof3_rxd_c",
4791 "msiof3_clk_d",
4792 "msiof3_sync_d",
4793 "msiof3_ss1_d",
4794 "msiof3_txd_d",
4795 "msiof3_rxd_d",
4796 "msiof3_clk_e",
4797 "msiof3_sync_e",
4798 "msiof3_ss1_e",
4799 "msiof3_ss2_e",
4800 "msiof3_txd_e",
4801 "msiof3_rxd_e",
4802 };
4803
4804 static const char * const pwm0_groups[] = {
4805 "pwm0",
4806 };
4807
4808 static const char * const pwm1_groups[] = {
4809 "pwm1_a",
4810 "pwm1_b",
4811 };
4812
4813 static const char * const pwm2_groups[] = {
4814 "pwm2_a",
4815 "pwm2_b",
4816 };
4817
4818 static const char * const pwm3_groups[] = {
4819 "pwm3_a",
4820 "pwm3_b",
4821 };
4822
4823 static const char * const pwm4_groups[] = {
4824 "pwm4_a",
4825 "pwm4_b",
4826 };
4827
4828 static const char * const pwm5_groups[] = {
4829 "pwm5_a",
4830 "pwm5_b",
4831 };
4832
4833 static const char * const pwm6_groups[] = {
4834 "pwm6_a",
4835 "pwm6_b",
4836 };
4837
4838 static const char * const sata0_groups[] = {
4839 "sata0_devslp_a",
4840 "sata0_devslp_b",
4841 };
4842
4843 static const char * const scif0_groups[] = {
4844 "scif0_data",
4845 "scif0_clk",
4846 "scif0_ctrl",
4847 };
4848
4849 static const char * const scif1_groups[] = {
4850 "scif1_data_a",
4851 "scif1_clk",
4852 "scif1_ctrl",
4853 "scif1_data_b",
4854 };
4855
4856 static const char * const scif2_groups[] = {
4857 "scif2_data_a",
4858 "scif2_clk",
4859 "scif2_data_b",
4860 };
4861
4862 static const char * const scif3_groups[] = {
4863 "scif3_data_a",
4864 "scif3_clk",
4865 "scif3_ctrl",
4866 "scif3_data_b",
4867 };
4868
4869 static const char * const scif4_groups[] = {
4870 "scif4_data_a",
4871 "scif4_clk_a",
4872 "scif4_ctrl_a",
4873 "scif4_data_b",
4874 "scif4_clk_b",
4875 "scif4_ctrl_b",
4876 "scif4_data_c",
4877 "scif4_clk_c",
4878 "scif4_ctrl_c",
4879 };
4880
4881 static const char * const scif5_groups[] = {
4882 "scif5_data_a",
4883 "scif5_clk_a",
4884 "scif5_data_b",
4885 "scif5_clk_b",
4886 };
4887
4888 static const char * const scif_clk_groups[] = {
4889 "scif_clk_a",
4890 "scif_clk_b",
4891 };
4892
4893 static const char * const sdhi0_groups[] = {
4894 "sdhi0_data1",
4895 "sdhi0_data4",
4896 "sdhi0_ctrl",
4897 "sdhi0_cd",
4898 "sdhi0_wp",
4899 };
4900
4901 static const char * const sdhi1_groups[] = {
4902 "sdhi1_data1",
4903 "sdhi1_data4",
4904 "sdhi1_ctrl",
4905 "sdhi1_cd",
4906 "sdhi1_wp",
4907 };
4908
4909 static const char * const sdhi2_groups[] = {
4910 "sdhi2_data1",
4911 "sdhi2_data4",
4912 "sdhi2_data8",
4913 "sdhi2_ctrl",
4914 "sdhi2_cd_a",
4915 "sdhi2_wp_a",
4916 "sdhi2_cd_b",
4917 "sdhi2_wp_b",
4918 "sdhi2_ds",
4919 };
4920
4921 static const char * const sdhi3_groups[] = {
4922 "sdhi3_data1",
4923 "sdhi3_data4",
4924 "sdhi3_data8",
4925 "sdhi3_ctrl",
4926 "sdhi3_cd",
4927 "sdhi3_wp",
4928 "sdhi3_ds",
4929 };
4930
4931 static const char * const ssi_groups[] = {
4932 "ssi0_data",
4933 "ssi01239_ctrl",
4934 "ssi1_data_a",
4935 "ssi1_data_b",
4936 "ssi1_ctrl_a",
4937 "ssi1_ctrl_b",
4938 "ssi2_data_a",
4939 "ssi2_data_b",
4940 "ssi2_ctrl_a",
4941 "ssi2_ctrl_b",
4942 "ssi3_data",
4943 "ssi349_ctrl",
4944 "ssi4_data",
4945 "ssi4_ctrl",
4946 "ssi5_data",
4947 "ssi5_ctrl",
4948 "ssi6_data",
4949 "ssi6_ctrl",
4950 "ssi7_data",
4951 "ssi78_ctrl",
4952 "ssi8_data",
4953 "ssi9_data_a",
4954 "ssi9_data_b",
4955 "ssi9_ctrl_a",
4956 "ssi9_ctrl_b",
4957 };
4958
4959 static const char * const tmu_groups[] = {
4960 "tmu_tclk1_a",
4961 "tmu_tclk1_b",
4962 "tmu_tclk2_a",
4963 "tmu_tclk2_b",
4964 };
4965
4966 static const char * const usb0_groups[] = {
4967 "usb0",
4968 };
4969
4970 static const char * const usb1_groups[] = {
4971 "usb1",
4972 };
4973
4974 static const char * const usb2_groups[] = {
4975 "usb2",
4976 };
4977
4978 static const char * const usb2_ch3_groups[] = {
4979 "usb2_ch3",
4980 };
4981
4982 static const char * const usb30_groups[] = {
4983 "usb30",
4984 };
4985
4986 static const char * const vin4_groups[] = {
4987 "vin4_data8_a",
4988 "vin4_data10_a",
4989 "vin4_data12_a",
4990 "vin4_data16_a",
4991 "vin4_data18_a",
4992 "vin4_data20_a",
4993 "vin4_data24_a",
4994 "vin4_data8_b",
4995 "vin4_data10_b",
4996 "vin4_data12_b",
4997 "vin4_data16_b",
4998 "vin4_data18_b",
4999 "vin4_data20_b",
5000 "vin4_data24_b",
5001 "vin4_sync",
5002 "vin4_field",
5003 "vin4_clkenb",
5004 "vin4_clk",
5005 };
5006
5007 static const char * const vin5_groups[] = {
5008 "vin5_data8",
5009 "vin5_data10",
5010 "vin5_data12",
5011 "vin5_data16",
5012 "vin5_sync",
5013 "vin5_field",
5014 "vin5_clkenb",
5015 "vin5_clk",
5016 };
5017
5018 static const struct sh_pfc_function pinmux_functions[] = {
5019 SH_PFC_FUNCTION(audio_clk),
5020 SH_PFC_FUNCTION(avb),
5021 SH_PFC_FUNCTION(can0),
5022 SH_PFC_FUNCTION(can1),
5023 SH_PFC_FUNCTION(can_clk),
5024 SH_PFC_FUNCTION(canfd0),
5025 SH_PFC_FUNCTION(canfd1),
5026 SH_PFC_FUNCTION(drif0),
5027 SH_PFC_FUNCTION(drif1),
5028 SH_PFC_FUNCTION(drif2),
5029 SH_PFC_FUNCTION(drif3),
5030 SH_PFC_FUNCTION(du),
5031 SH_PFC_FUNCTION(hdmi0),
5032 SH_PFC_FUNCTION(hdmi1),
5033 SH_PFC_FUNCTION(hscif0),
5034 SH_PFC_FUNCTION(hscif1),
5035 SH_PFC_FUNCTION(hscif2),
5036 SH_PFC_FUNCTION(hscif3),
5037 SH_PFC_FUNCTION(hscif4),
5038 SH_PFC_FUNCTION(i2c1),
5039 SH_PFC_FUNCTION(i2c2),
5040 SH_PFC_FUNCTION(i2c6),
5041 SH_PFC_FUNCTION(intc_ex),
5042 SH_PFC_FUNCTION(msiof0),
5043 SH_PFC_FUNCTION(msiof1),
5044 SH_PFC_FUNCTION(msiof2),
5045 SH_PFC_FUNCTION(msiof3),
5046 SH_PFC_FUNCTION(pwm0),
5047 SH_PFC_FUNCTION(pwm1),
5048 SH_PFC_FUNCTION(pwm2),
5049 SH_PFC_FUNCTION(pwm3),
5050 SH_PFC_FUNCTION(pwm4),
5051 SH_PFC_FUNCTION(pwm5),
5052 SH_PFC_FUNCTION(pwm6),
5053 SH_PFC_FUNCTION(sata0),
5054 SH_PFC_FUNCTION(scif0),
5055 SH_PFC_FUNCTION(scif1),
5056 SH_PFC_FUNCTION(scif2),
5057 SH_PFC_FUNCTION(scif3),
5058 SH_PFC_FUNCTION(scif4),
5059 SH_PFC_FUNCTION(scif5),
5060 SH_PFC_FUNCTION(scif_clk),
5061 SH_PFC_FUNCTION(sdhi0),
5062 SH_PFC_FUNCTION(sdhi1),
5063 SH_PFC_FUNCTION(sdhi2),
5064 SH_PFC_FUNCTION(sdhi3),
5065 SH_PFC_FUNCTION(ssi),
5066 SH_PFC_FUNCTION(tmu),
5067 SH_PFC_FUNCTION(usb0),
5068 SH_PFC_FUNCTION(usb1),
5069 SH_PFC_FUNCTION(usb2),
5070 SH_PFC_FUNCTION(usb2_ch3),
5071 SH_PFC_FUNCTION(usb30),
5072 SH_PFC_FUNCTION(vin4),
5073 SH_PFC_FUNCTION(vin5),
5074 };
5075
5076 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5077 #define F_(x, y) FN_##y
5078 #define FM(x) FN_##x
5079 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5080 0, 0,
5081 0, 0,
5082 0, 0,
5083 0, 0,
5084 0, 0,
5085 0, 0,
5086 0, 0,
5087 0, 0,
5088 0, 0,
5089 0, 0,
5090 0, 0,
5091 0, 0,
5092 0, 0,
5093 0, 0,
5094 0, 0,
5095 0, 0,
5096 GP_0_15_FN, GPSR0_15,
5097 GP_0_14_FN, GPSR0_14,
5098 GP_0_13_FN, GPSR0_13,
5099 GP_0_12_FN, GPSR0_12,
5100 GP_0_11_FN, GPSR0_11,
5101 GP_0_10_FN, GPSR0_10,
5102 GP_0_9_FN, GPSR0_9,
5103 GP_0_8_FN, GPSR0_8,
5104 GP_0_7_FN, GPSR0_7,
5105 GP_0_6_FN, GPSR0_6,
5106 GP_0_5_FN, GPSR0_5,
5107 GP_0_4_FN, GPSR0_4,
5108 GP_0_3_FN, GPSR0_3,
5109 GP_0_2_FN, GPSR0_2,
5110 GP_0_1_FN, GPSR0_1,
5111 GP_0_0_FN, GPSR0_0, }
5112 },
5113 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5114 0, 0,
5115 0, 0,
5116 0, 0,
5117 GP_1_28_FN, GPSR1_28,
5118 GP_1_27_FN, GPSR1_27,
5119 GP_1_26_FN, GPSR1_26,
5120 GP_1_25_FN, GPSR1_25,
5121 GP_1_24_FN, GPSR1_24,
5122 GP_1_23_FN, GPSR1_23,
5123 GP_1_22_FN, GPSR1_22,
5124 GP_1_21_FN, GPSR1_21,
5125 GP_1_20_FN, GPSR1_20,
5126 GP_1_19_FN, GPSR1_19,
5127 GP_1_18_FN, GPSR1_18,
5128 GP_1_17_FN, GPSR1_17,
5129 GP_1_16_FN, GPSR1_16,
5130 GP_1_15_FN, GPSR1_15,
5131 GP_1_14_FN, GPSR1_14,
5132 GP_1_13_FN, GPSR1_13,
5133 GP_1_12_FN, GPSR1_12,
5134 GP_1_11_FN, GPSR1_11,
5135 GP_1_10_FN, GPSR1_10,
5136 GP_1_9_FN, GPSR1_9,
5137 GP_1_8_FN, GPSR1_8,
5138 GP_1_7_FN, GPSR1_7,
5139 GP_1_6_FN, GPSR1_6,
5140 GP_1_5_FN, GPSR1_5,
5141 GP_1_4_FN, GPSR1_4,
5142 GP_1_3_FN, GPSR1_3,
5143 GP_1_2_FN, GPSR1_2,
5144 GP_1_1_FN, GPSR1_1,
5145 GP_1_0_FN, GPSR1_0, }
5146 },
5147 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5148 0, 0,
5149 0, 0,
5150 0, 0,
5151 0, 0,
5152 0, 0,
5153 0, 0,
5154 0, 0,
5155 0, 0,
5156 0, 0,
5157 0, 0,
5158 0, 0,
5159 0, 0,
5160 0, 0,
5161 0, 0,
5162 0, 0,
5163 0, 0,
5164 0, 0,
5165 GP_2_14_FN, GPSR2_14,
5166 GP_2_13_FN, GPSR2_13,
5167 GP_2_12_FN, GPSR2_12,
5168 GP_2_11_FN, GPSR2_11,
5169 GP_2_10_FN, GPSR2_10,
5170 GP_2_9_FN, GPSR2_9,
5171 GP_2_8_FN, GPSR2_8,
5172 GP_2_7_FN, GPSR2_7,
5173 GP_2_6_FN, GPSR2_6,
5174 GP_2_5_FN, GPSR2_5,
5175 GP_2_4_FN, GPSR2_4,
5176 GP_2_3_FN, GPSR2_3,
5177 GP_2_2_FN, GPSR2_2,
5178 GP_2_1_FN, GPSR2_1,
5179 GP_2_0_FN, GPSR2_0, }
5180 },
5181 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5182 0, 0,
5183 0, 0,
5184 0, 0,
5185 0, 0,
5186 0, 0,
5187 0, 0,
5188 0, 0,
5189 0, 0,
5190 0, 0,
5191 0, 0,
5192 0, 0,
5193 0, 0,
5194 0, 0,
5195 0, 0,
5196 0, 0,
5197 0, 0,
5198 GP_3_15_FN, GPSR3_15,
5199 GP_3_14_FN, GPSR3_14,
5200 GP_3_13_FN, GPSR3_13,
5201 GP_3_12_FN, GPSR3_12,
5202 GP_3_11_FN, GPSR3_11,
5203 GP_3_10_FN, GPSR3_10,
5204 GP_3_9_FN, GPSR3_9,
5205 GP_3_8_FN, GPSR3_8,
5206 GP_3_7_FN, GPSR3_7,
5207 GP_3_6_FN, GPSR3_6,
5208 GP_3_5_FN, GPSR3_5,
5209 GP_3_4_FN, GPSR3_4,
5210 GP_3_3_FN, GPSR3_3,
5211 GP_3_2_FN, GPSR3_2,
5212 GP_3_1_FN, GPSR3_1,
5213 GP_3_0_FN, GPSR3_0, }
5214 },
5215 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5216 0, 0,
5217 0, 0,
5218 0, 0,
5219 0, 0,
5220 0, 0,
5221 0, 0,
5222 0, 0,
5223 0, 0,
5224 0, 0,
5225 0, 0,
5226 0, 0,
5227 0, 0,
5228 0, 0,
5229 0, 0,
5230 GP_4_17_FN, GPSR4_17,
5231 GP_4_16_FN, GPSR4_16,
5232 GP_4_15_FN, GPSR4_15,
5233 GP_4_14_FN, GPSR4_14,
5234 GP_4_13_FN, GPSR4_13,
5235 GP_4_12_FN, GPSR4_12,
5236 GP_4_11_FN, GPSR4_11,
5237 GP_4_10_FN, GPSR4_10,
5238 GP_4_9_FN, GPSR4_9,
5239 GP_4_8_FN, GPSR4_8,
5240 GP_4_7_FN, GPSR4_7,
5241 GP_4_6_FN, GPSR4_6,
5242 GP_4_5_FN, GPSR4_5,
5243 GP_4_4_FN, GPSR4_4,
5244 GP_4_3_FN, GPSR4_3,
5245 GP_4_2_FN, GPSR4_2,
5246 GP_4_1_FN, GPSR4_1,
5247 GP_4_0_FN, GPSR4_0, }
5248 },
5249 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5250 0, 0,
5251 0, 0,
5252 0, 0,
5253 0, 0,
5254 0, 0,
5255 0, 0,
5256 GP_5_25_FN, GPSR5_25,
5257 GP_5_24_FN, GPSR5_24,
5258 GP_5_23_FN, GPSR5_23,
5259 GP_5_22_FN, GPSR5_22,
5260 GP_5_21_FN, GPSR5_21,
5261 GP_5_20_FN, GPSR5_20,
5262 GP_5_19_FN, GPSR5_19,
5263 GP_5_18_FN, GPSR5_18,
5264 GP_5_17_FN, GPSR5_17,
5265 GP_5_16_FN, GPSR5_16,
5266 GP_5_15_FN, GPSR5_15,
5267 GP_5_14_FN, GPSR5_14,
5268 GP_5_13_FN, GPSR5_13,
5269 GP_5_12_FN, GPSR5_12,
5270 GP_5_11_FN, GPSR5_11,
5271 GP_5_10_FN, GPSR5_10,
5272 GP_5_9_FN, GPSR5_9,
5273 GP_5_8_FN, GPSR5_8,
5274 GP_5_7_FN, GPSR5_7,
5275 GP_5_6_FN, GPSR5_6,
5276 GP_5_5_FN, GPSR5_5,
5277 GP_5_4_FN, GPSR5_4,
5278 GP_5_3_FN, GPSR5_3,
5279 GP_5_2_FN, GPSR5_2,
5280 GP_5_1_FN, GPSR5_1,
5281 GP_5_0_FN, GPSR5_0, }
5282 },
5283 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5284 GP_6_31_FN, GPSR6_31,
5285 GP_6_30_FN, GPSR6_30,
5286 GP_6_29_FN, GPSR6_29,
5287 GP_6_28_FN, GPSR6_28,
5288 GP_6_27_FN, GPSR6_27,
5289 GP_6_26_FN, GPSR6_26,
5290 GP_6_25_FN, GPSR6_25,
5291 GP_6_24_FN, GPSR6_24,
5292 GP_6_23_FN, GPSR6_23,
5293 GP_6_22_FN, GPSR6_22,
5294 GP_6_21_FN, GPSR6_21,
5295 GP_6_20_FN, GPSR6_20,
5296 GP_6_19_FN, GPSR6_19,
5297 GP_6_18_FN, GPSR6_18,
5298 GP_6_17_FN, GPSR6_17,
5299 GP_6_16_FN, GPSR6_16,
5300 GP_6_15_FN, GPSR6_15,
5301 GP_6_14_FN, GPSR6_14,
5302 GP_6_13_FN, GPSR6_13,
5303 GP_6_12_FN, GPSR6_12,
5304 GP_6_11_FN, GPSR6_11,
5305 GP_6_10_FN, GPSR6_10,
5306 GP_6_9_FN, GPSR6_9,
5307 GP_6_8_FN, GPSR6_8,
5308 GP_6_7_FN, GPSR6_7,
5309 GP_6_6_FN, GPSR6_6,
5310 GP_6_5_FN, GPSR6_5,
5311 GP_6_4_FN, GPSR6_4,
5312 GP_6_3_FN, GPSR6_3,
5313 GP_6_2_FN, GPSR6_2,
5314 GP_6_1_FN, GPSR6_1,
5315 GP_6_0_FN, GPSR6_0, }
5316 },
5317 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5318 0, 0,
5319 0, 0,
5320 0, 0,
5321 0, 0,
5322 0, 0,
5323 0, 0,
5324 0, 0,
5325 0, 0,
5326 0, 0,
5327 0, 0,
5328 0, 0,
5329 0, 0,
5330 0, 0,
5331 0, 0,
5332 0, 0,
5333 0, 0,
5334 0, 0,
5335 0, 0,
5336 0, 0,
5337 0, 0,
5338 0, 0,
5339 0, 0,
5340 0, 0,
5341 0, 0,
5342 0, 0,
5343 0, 0,
5344 0, 0,
5345 0, 0,
5346 GP_7_3_FN, GPSR7_3,
5347 GP_7_2_FN, GPSR7_2,
5348 GP_7_1_FN, GPSR7_1,
5349 GP_7_0_FN, GPSR7_0, }
5350 },
5351 #undef F_
5352 #undef FM
5353
5354 #define F_(x, y) x,
5355 #define FM(x) FN_##x,
5356 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5357 IP0_31_28
5358 IP0_27_24
5359 IP0_23_20
5360 IP0_19_16
5361 IP0_15_12
5362 IP0_11_8
5363 IP0_7_4
5364 IP0_3_0 }
5365 },
5366 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5367 IP1_31_28
5368 IP1_27_24
5369 IP1_23_20
5370 IP1_19_16
5371 IP1_15_12
5372 IP1_11_8
5373 IP1_7_4
5374 IP1_3_0 }
5375 },
5376 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5377 IP2_31_28
5378 IP2_27_24
5379 IP2_23_20
5380 IP2_19_16
5381 IP2_15_12
5382 IP2_11_8
5383 IP2_7_4
5384 IP2_3_0 }
5385 },
5386 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5387 IP3_31_28
5388 IP3_27_24
5389 IP3_23_20
5390 IP3_19_16
5391 IP3_15_12
5392 IP3_11_8
5393 IP3_7_4
5394 IP3_3_0 }
5395 },
5396 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5397 IP4_31_28
5398 IP4_27_24
5399 IP4_23_20
5400 IP4_19_16
5401 IP4_15_12
5402 IP4_11_8
5403 IP4_7_4
5404 IP4_3_0 }
5405 },
5406 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5407 IP5_31_28
5408 IP5_27_24
5409 IP5_23_20
5410 IP5_19_16
5411 IP5_15_12
5412 IP5_11_8
5413 IP5_7_4
5414 IP5_3_0 }
5415 },
5416 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5417 IP6_31_28
5418 IP6_27_24
5419 IP6_23_20
5420 IP6_19_16
5421 IP6_15_12
5422 IP6_11_8
5423 IP6_7_4
5424 IP6_3_0 }
5425 },
5426 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5427 IP7_31_28
5428 IP7_27_24
5429 IP7_23_20
5430 IP7_19_16
5431 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5432 IP7_11_8
5433 IP7_7_4
5434 IP7_3_0 }
5435 },
5436 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5437 IP8_31_28
5438 IP8_27_24
5439 IP8_23_20
5440 IP8_19_16
5441 IP8_15_12
5442 IP8_11_8
5443 IP8_7_4
5444 IP8_3_0 }
5445 },
5446 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5447 IP9_31_28
5448 IP9_27_24
5449 IP9_23_20
5450 IP9_19_16
5451 IP9_15_12
5452 IP9_11_8
5453 IP9_7_4
5454 IP9_3_0 }
5455 },
5456 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5457 IP10_31_28
5458 IP10_27_24
5459 IP10_23_20
5460 IP10_19_16
5461 IP10_15_12
5462 IP10_11_8
5463 IP10_7_4
5464 IP10_3_0 }
5465 },
5466 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5467 IP11_31_28
5468 IP11_27_24
5469 IP11_23_20
5470 IP11_19_16
5471 IP11_15_12
5472 IP11_11_8
5473 IP11_7_4
5474 IP11_3_0 }
5475 },
5476 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5477 IP12_31_28
5478 IP12_27_24
5479 IP12_23_20
5480 IP12_19_16
5481 IP12_15_12
5482 IP12_11_8
5483 IP12_7_4
5484 IP12_3_0 }
5485 },
5486 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5487 IP13_31_28
5488 IP13_27_24
5489 IP13_23_20
5490 IP13_19_16
5491 IP13_15_12
5492 IP13_11_8
5493 IP13_7_4
5494 IP13_3_0 }
5495 },
5496 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5497 IP14_31_28
5498 IP14_27_24
5499 IP14_23_20
5500 IP14_19_16
5501 IP14_15_12
5502 IP14_11_8
5503 IP14_7_4
5504 IP14_3_0 }
5505 },
5506 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5507 IP15_31_28
5508 IP15_27_24
5509 IP15_23_20
5510 IP15_19_16
5511 IP15_15_12
5512 IP15_11_8
5513 IP15_7_4
5514 IP15_3_0 }
5515 },
5516 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5517 IP16_31_28
5518 IP16_27_24
5519 IP16_23_20
5520 IP16_19_16
5521 IP16_15_12
5522 IP16_11_8
5523 IP16_7_4
5524 IP16_3_0 }
5525 },
5526 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5527 IP17_31_28
5528 IP17_27_24
5529 IP17_23_20
5530 IP17_19_16
5531 IP17_15_12
5532 IP17_11_8
5533 IP17_7_4
5534 IP17_3_0 }
5535 },
5536 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5537 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5538 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5539 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5540 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5541 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5542 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5543 IP18_7_4
5544 IP18_3_0 }
5545 },
5546 #undef F_
5547 #undef FM
5548
5549 #define F_(x, y) x,
5550 #define FM(x) FN_##x,
5551 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5552 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5553 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5554 MOD_SEL0_31_30_29
5555 MOD_SEL0_28_27
5556 MOD_SEL0_26_25_24
5557 MOD_SEL0_23
5558 MOD_SEL0_22
5559 MOD_SEL0_21
5560 MOD_SEL0_20
5561 MOD_SEL0_19
5562 MOD_SEL0_18_17
5563 MOD_SEL0_16
5564 0, 0, /* RESERVED 15 */
5565 MOD_SEL0_14_13
5566 MOD_SEL0_12
5567 MOD_SEL0_11
5568 MOD_SEL0_10
5569 MOD_SEL0_9_8
5570 MOD_SEL0_7_6
5571 MOD_SEL0_5
5572 MOD_SEL0_4_3
5573 /* RESERVED 2, 1, 0 */
5574 0, 0, 0, 0, 0, 0, 0, 0 }
5575 },
5576 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5577 2, 3, 1, 2, 3, 1, 1, 2, 1,
5578 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5579 MOD_SEL1_31_30
5580 MOD_SEL1_29_28_27
5581 MOD_SEL1_26
5582 MOD_SEL1_25_24
5583 MOD_SEL1_23_22_21
5584 MOD_SEL1_20
5585 MOD_SEL1_19
5586 MOD_SEL1_18_17
5587 MOD_SEL1_16
5588 MOD_SEL1_15_14
5589 MOD_SEL1_13
5590 MOD_SEL1_12
5591 MOD_SEL1_11
5592 MOD_SEL1_10
5593 MOD_SEL1_9
5594 0, 0, 0, 0, /* RESERVED 8, 7 */
5595 MOD_SEL1_6
5596 MOD_SEL1_5
5597 MOD_SEL1_4
5598 MOD_SEL1_3
5599 MOD_SEL1_2
5600 MOD_SEL1_1
5601 MOD_SEL1_0 }
5602 },
5603 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5604 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5605 4, 4, 4, 3, 1) {
5606 MOD_SEL2_31
5607 MOD_SEL2_30
5608 MOD_SEL2_29
5609 MOD_SEL2_28_27
5610 MOD_SEL2_26
5611 MOD_SEL2_25_24_23
5612 /* RESERVED 22 */
5613 0, 0,
5614 MOD_SEL2_21
5615 MOD_SEL2_20
5616 MOD_SEL2_19
5617 MOD_SEL2_18
5618 MOD_SEL2_17
5619 /* RESERVED 16 */
5620 0, 0,
5621 /* RESERVED 15, 14, 13, 12 */
5622 0, 0, 0, 0, 0, 0, 0, 0,
5623 0, 0, 0, 0, 0, 0, 0, 0,
5624 /* RESERVED 11, 10, 9, 8 */
5625 0, 0, 0, 0, 0, 0, 0, 0,
5626 0, 0, 0, 0, 0, 0, 0, 0,
5627 /* RESERVED 7, 6, 5, 4 */
5628 0, 0, 0, 0, 0, 0, 0, 0,
5629 0, 0, 0, 0, 0, 0, 0, 0,
5630 /* RESERVED 3, 2, 1 */
5631 0, 0, 0, 0, 0, 0, 0, 0,
5632 MOD_SEL2_0 }
5633 },
5634 { },
5635 };
5636
5637 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5638 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5639 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5640 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5641 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5642 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5643 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5644 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5645 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5646 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5647 } },
5648 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5649 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5650 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5651 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5652 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5653 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5654 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5655 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5656 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5657 } },
5658 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5659 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5660 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5661 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5662 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5663 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5664 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5665 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5666 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5667 } },
5668 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5669 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5670 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5671 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5672 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5673 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5674 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5675 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5676 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5677 } },
5678 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5679 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5680 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5681 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5682 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5683 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5684 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5685 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5686 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5687 } },
5688 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5689 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5690 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5691 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5692 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5693 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5694 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5695 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5696 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5697 } },
5698 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5699 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5700 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5701 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5702 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5703 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5704 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5705 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5706 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5707 } },
5708 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5709 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5710 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5711 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5712 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5713 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5714 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5715 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5716 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5717 } },
5718 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5719 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5720 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5721 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5722 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5723 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5724 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5725 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5726 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5727 } },
5728 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5729 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5730 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5731 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5732 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5733 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5734 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5735 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5736 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5737 } },
5738 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5739 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5740 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5741 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5742 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5743 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5744 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5745 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5746 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5747 } },
5748 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5749 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5750 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5751 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5752 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5753 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5754 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5755 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5756 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5757 } },
5758 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5759 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5760 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5761 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5762 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5763 } },
5764 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5765 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5766 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5767 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5768 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5769 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5770 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5771 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5772 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5773 } },
5774 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5775 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5776 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5777 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5778 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5779 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5780 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5781 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5782 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5783 } },
5784 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5785 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5786 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5787 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5788 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5789 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5790 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5791 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5792 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5793 } },
5794 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5795 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5796 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5797 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5798 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5799 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5800 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5801 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5802 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5803 } },
5804 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5805 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5806 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5807 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5808 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5809 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5810 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5811 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5812 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5813 } },
5814 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5815 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5816 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5817 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5818 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5819 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5820 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5821 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5822 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5823 } },
5824 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5825 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5826 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5827 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5828 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5829 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5830 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5831 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5832 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5833 } },
5834 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5835 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5836 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5837 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5838 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5839 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5840 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5841 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5842 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5843 } },
5844 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5845 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5846 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5847 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5848 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5849 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5850 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5851 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5852 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5853 } },
5854 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5855 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5856 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5857 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5858 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5859 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5860 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5861 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5862 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5863 } },
5864 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5865 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5866 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5867 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5868 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5869 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5870 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5871 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5872 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5873 } },
5874 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5875 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5876 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5877 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5878 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5879 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5880 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5881 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
5882 } },
5883 { },
5884 };
5885
5886 enum ioctrl_regs {
5887 POCCTRL,
5888 };
5889
5890 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5891 [POCCTRL] = { 0xe6060380, },
5892 { /* sentinel */ },
5893 };
5894
r8a7795_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)5895 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5896 {
5897 int bit = -EINVAL;
5898
5899 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5900
5901 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5902 bit = pin & 0x1f;
5903
5904 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5905 bit = (pin & 0x1f) + 12;
5906
5907 return bit;
5908 }
5909
5910 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5911 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5912 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5913 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5914 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5915 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5916 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5917 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5918 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5919 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5920 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5921 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5922 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5923 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5924 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5925 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5926 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5927 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5928 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5929 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5930 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5931 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5932 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5933 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5934 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5935 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5936 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5937 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5938 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5939 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5940 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5941 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5942 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5943 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5944 } },
5945 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5946 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5947 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5948 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5949 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5950 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5951 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5952 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5953 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5954 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5955 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5956 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5957 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5958 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5959 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5960 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5961 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5962 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5963 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5964 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5965 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5966 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5967 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5968 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5969 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5970 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5971 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5972 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5973 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5974 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5975 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5976 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5977 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5978 } },
5979 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5980 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5981 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5982 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5983 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5984 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5985 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5986 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5987 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5988 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5989 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5990 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5991 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5992 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5993 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5994 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5995 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5996 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5997 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5998 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5999 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6000 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6001 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6002 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6003 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6004 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6005 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6006 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6007 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
6008 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
6009 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
6010 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6011 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6012 } },
6013 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6014 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
6015 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
6016 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
6017 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6018 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6019 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6020 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6021 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6022 [ 8] = PIN_NONE,
6023 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6024 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6025 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6026 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6027 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6028 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6029 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6030 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6031 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6032 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6033 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6034 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6035 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6036 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6037 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6038 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6039 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6040 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6041 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6042 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6043 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6044 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6045 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6046 } },
6047 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6048 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6049 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6050 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6051 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6052 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6053 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6054 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6055 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6056 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6057 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6058 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6059 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6060 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6061 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6062 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6063 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6064 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6065 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6066 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6067 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6068 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6069 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6070 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6071 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6072 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6073 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6074 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6075 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6076 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6077 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6078 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6079 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6080 } },
6081 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6082 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6083 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6084 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6085 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6086 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6087 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6088 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6089 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6090 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6091 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6092 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6093 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6094 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6095 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6096 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6097 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6098 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6099 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6100 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6101 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6102 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6103 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6104 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6105 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6106 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6107 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6108 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6109 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6110 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6111 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6112 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6113 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6114 } },
6115 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6116 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6117 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6118 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6119 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6120 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6121 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6122 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
6123 [ 7] = PIN_NONE,
6124 [ 8] = PIN_NONE,
6125 [ 9] = PIN_NONE,
6126 [10] = PIN_NONE,
6127 [11] = PIN_NONE,
6128 [12] = PIN_NONE,
6129 [13] = PIN_NONE,
6130 [14] = PIN_NONE,
6131 [15] = PIN_NONE,
6132 [16] = PIN_NONE,
6133 [17] = PIN_NONE,
6134 [18] = PIN_NONE,
6135 [19] = PIN_NONE,
6136 [20] = PIN_NONE,
6137 [21] = PIN_NONE,
6138 [22] = PIN_NONE,
6139 [23] = PIN_NONE,
6140 [24] = PIN_NONE,
6141 [25] = PIN_NONE,
6142 [26] = PIN_NONE,
6143 [27] = PIN_NONE,
6144 [28] = PIN_NONE,
6145 [29] = PIN_NONE,
6146 [30] = PIN_NONE,
6147 [31] = PIN_NONE,
6148 } },
6149 { /* sentinel */ },
6150 };
6151
r8a7795_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)6152 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
6153 unsigned int pin)
6154 {
6155 const struct pinmux_bias_reg *reg;
6156 unsigned int bit;
6157
6158 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6159 if (!reg)
6160 return PIN_CONFIG_BIAS_DISABLE;
6161
6162 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6163 return PIN_CONFIG_BIAS_DISABLE;
6164 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6165 return PIN_CONFIG_BIAS_PULL_UP;
6166 else
6167 return PIN_CONFIG_BIAS_PULL_DOWN;
6168 }
6169
r8a7795_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)6170 static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6171 unsigned int bias)
6172 {
6173 const struct pinmux_bias_reg *reg;
6174 u32 enable, updown;
6175 unsigned int bit;
6176
6177 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6178 if (!reg)
6179 return;
6180
6181 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6182 if (bias != PIN_CONFIG_BIAS_DISABLE)
6183 enable |= BIT(bit);
6184
6185 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6186 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6187 updown |= BIT(bit);
6188
6189 sh_pfc_write(pfc, reg->pud, updown);
6190 sh_pfc_write(pfc, reg->puen, enable);
6191 }
6192
6193 static const struct soc_device_attribute r8a7795es1[] = {
6194 { .soc_id = "r8a7795", .revision = "ES1.*" },
6195 { /* sentinel */ }
6196 };
6197
r8a7795_pinmux_init(struct sh_pfc * pfc)6198 static int r8a7795_pinmux_init(struct sh_pfc *pfc)
6199 {
6200 if (soc_device_match(r8a7795es1))
6201 pfc->info = &r8a7795es1_pinmux_info;
6202
6203 return 0;
6204 }
6205
6206 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
6207 .init = r8a7795_pinmux_init,
6208 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
6209 .get_bias = r8a7795_pinmux_get_bias,
6210 .set_bias = r8a7795_pinmux_set_bias,
6211 };
6212
6213 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
6214 .name = "r8a77951_pfc",
6215 .ops = &r8a7795_pinmux_ops,
6216 .unlock_reg = 0xe6060000, /* PMMR */
6217
6218 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6219
6220 .pins = pinmux_pins,
6221 .nr_pins = ARRAY_SIZE(pinmux_pins),
6222 .groups = pinmux_groups,
6223 .nr_groups = ARRAY_SIZE(pinmux_groups),
6224 .functions = pinmux_functions,
6225 .nr_functions = ARRAY_SIZE(pinmux_functions),
6226
6227 .cfg_regs = pinmux_config_regs,
6228 .drive_regs = pinmux_drive_regs,
6229 .bias_regs = pinmux_bias_regs,
6230 .ioctrl_regs = pinmux_ioctrl_regs,
6231
6232 .pinmux_data = pinmux_data,
6233 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6234 };
6235
