1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6
7 #include "qla_def.h"
8
9 /*
10 * Firmware Dump structure definition
11 */
12
13 struct qla2300_fw_dump {
14 __be16 hccr;
15 __be16 pbiu_reg[8];
16 __be16 risc_host_reg[8];
17 __be16 mailbox_reg[32];
18 __be16 resp_dma_reg[32];
19 __be16 dma_reg[48];
20 __be16 risc_hdw_reg[16];
21 __be16 risc_gp0_reg[16];
22 __be16 risc_gp1_reg[16];
23 __be16 risc_gp2_reg[16];
24 __be16 risc_gp3_reg[16];
25 __be16 risc_gp4_reg[16];
26 __be16 risc_gp5_reg[16];
27 __be16 risc_gp6_reg[16];
28 __be16 risc_gp7_reg[16];
29 __be16 frame_buf_hdw_reg[64];
30 __be16 fpm_b0_reg[64];
31 __be16 fpm_b1_reg[64];
32 __be16 risc_ram[0xf800];
33 __be16 stack_ram[0x1000];
34 __be16 data_ram[1];
35 };
36
37 struct qla2100_fw_dump {
38 __be16 hccr;
39 __be16 pbiu_reg[8];
40 __be16 mailbox_reg[32];
41 __be16 dma_reg[48];
42 __be16 risc_hdw_reg[16];
43 __be16 risc_gp0_reg[16];
44 __be16 risc_gp1_reg[16];
45 __be16 risc_gp2_reg[16];
46 __be16 risc_gp3_reg[16];
47 __be16 risc_gp4_reg[16];
48 __be16 risc_gp5_reg[16];
49 __be16 risc_gp6_reg[16];
50 __be16 risc_gp7_reg[16];
51 __be16 frame_buf_hdw_reg[16];
52 __be16 fpm_b0_reg[64];
53 __be16 fpm_b1_reg[64];
54 __be16 risc_ram[0xf000];
55 u8 queue_dump[];
56 };
57
58 struct qla24xx_fw_dump {
59 __be32 host_status;
60 __be32 host_reg[32];
61 __be32 shadow_reg[7];
62 __be16 mailbox_reg[32];
63 __be32 xseq_gp_reg[128];
64 __be32 xseq_0_reg[16];
65 __be32 xseq_1_reg[16];
66 __be32 rseq_gp_reg[128];
67 __be32 rseq_0_reg[16];
68 __be32 rseq_1_reg[16];
69 __be32 rseq_2_reg[16];
70 __be32 cmd_dma_reg[16];
71 __be32 req0_dma_reg[15];
72 __be32 resp0_dma_reg[15];
73 __be32 req1_dma_reg[15];
74 __be32 xmt0_dma_reg[32];
75 __be32 xmt1_dma_reg[32];
76 __be32 xmt2_dma_reg[32];
77 __be32 xmt3_dma_reg[32];
78 __be32 xmt4_dma_reg[32];
79 __be32 xmt_data_dma_reg[16];
80 __be32 rcvt0_data_dma_reg[32];
81 __be32 rcvt1_data_dma_reg[32];
82 __be32 risc_gp_reg[128];
83 __be32 lmc_reg[112];
84 __be32 fpm_hdw_reg[192];
85 __be32 fb_hdw_reg[176];
86 __be32 code_ram[0x2000];
87 __be32 ext_mem[1];
88 };
89
90 struct qla25xx_fw_dump {
91 __be32 host_status;
92 __be32 host_risc_reg[32];
93 __be32 pcie_regs[4];
94 __be32 host_reg[32];
95 __be32 shadow_reg[11];
96 __be32 risc_io_reg;
97 __be16 mailbox_reg[32];
98 __be32 xseq_gp_reg[128];
99 __be32 xseq_0_reg[48];
100 __be32 xseq_1_reg[16];
101 __be32 rseq_gp_reg[128];
102 __be32 rseq_0_reg[32];
103 __be32 rseq_1_reg[16];
104 __be32 rseq_2_reg[16];
105 __be32 aseq_gp_reg[128];
106 __be32 aseq_0_reg[32];
107 __be32 aseq_1_reg[16];
108 __be32 aseq_2_reg[16];
109 __be32 cmd_dma_reg[16];
110 __be32 req0_dma_reg[15];
111 __be32 resp0_dma_reg[15];
112 __be32 req1_dma_reg[15];
113 __be32 xmt0_dma_reg[32];
114 __be32 xmt1_dma_reg[32];
115 __be32 xmt2_dma_reg[32];
116 __be32 xmt3_dma_reg[32];
117 __be32 xmt4_dma_reg[32];
118 __be32 xmt_data_dma_reg[16];
119 __be32 rcvt0_data_dma_reg[32];
120 __be32 rcvt1_data_dma_reg[32];
121 __be32 risc_gp_reg[128];
122 __be32 lmc_reg[128];
123 __be32 fpm_hdw_reg[192];
124 __be32 fb_hdw_reg[192];
125 __be32 code_ram[0x2000];
126 __be32 ext_mem[1];
127 };
128
129 struct qla81xx_fw_dump {
130 __be32 host_status;
131 __be32 host_risc_reg[32];
132 __be32 pcie_regs[4];
133 __be32 host_reg[32];
134 __be32 shadow_reg[11];
135 __be32 risc_io_reg;
136 __be16 mailbox_reg[32];
137 __be32 xseq_gp_reg[128];
138 __be32 xseq_0_reg[48];
139 __be32 xseq_1_reg[16];
140 __be32 rseq_gp_reg[128];
141 __be32 rseq_0_reg[32];
142 __be32 rseq_1_reg[16];
143 __be32 rseq_2_reg[16];
144 __be32 aseq_gp_reg[128];
145 __be32 aseq_0_reg[32];
146 __be32 aseq_1_reg[16];
147 __be32 aseq_2_reg[16];
148 __be32 cmd_dma_reg[16];
149 __be32 req0_dma_reg[15];
150 __be32 resp0_dma_reg[15];
151 __be32 req1_dma_reg[15];
152 __be32 xmt0_dma_reg[32];
153 __be32 xmt1_dma_reg[32];
154 __be32 xmt2_dma_reg[32];
155 __be32 xmt3_dma_reg[32];
156 __be32 xmt4_dma_reg[32];
157 __be32 xmt_data_dma_reg[16];
158 __be32 rcvt0_data_dma_reg[32];
159 __be32 rcvt1_data_dma_reg[32];
160 __be32 risc_gp_reg[128];
161 __be32 lmc_reg[128];
162 __be32 fpm_hdw_reg[224];
163 __be32 fb_hdw_reg[208];
164 __be32 code_ram[0x2000];
165 __be32 ext_mem[1];
166 };
167
168 struct qla83xx_fw_dump {
169 __be32 host_status;
170 __be32 host_risc_reg[48];
171 __be32 pcie_regs[4];
172 __be32 host_reg[32];
173 __be32 shadow_reg[11];
174 __be32 risc_io_reg;
175 __be16 mailbox_reg[32];
176 __be32 xseq_gp_reg[256];
177 __be32 xseq_0_reg[48];
178 __be32 xseq_1_reg[16];
179 __be32 xseq_2_reg[16];
180 __be32 rseq_gp_reg[256];
181 __be32 rseq_0_reg[32];
182 __be32 rseq_1_reg[16];
183 __be32 rseq_2_reg[16];
184 __be32 rseq_3_reg[16];
185 __be32 aseq_gp_reg[256];
186 __be32 aseq_0_reg[32];
187 __be32 aseq_1_reg[16];
188 __be32 aseq_2_reg[16];
189 __be32 aseq_3_reg[16];
190 __be32 cmd_dma_reg[64];
191 __be32 req0_dma_reg[15];
192 __be32 resp0_dma_reg[15];
193 __be32 req1_dma_reg[15];
194 __be32 xmt0_dma_reg[32];
195 __be32 xmt1_dma_reg[32];
196 __be32 xmt2_dma_reg[32];
197 __be32 xmt3_dma_reg[32];
198 __be32 xmt4_dma_reg[32];
199 __be32 xmt_data_dma_reg[16];
200 __be32 rcvt0_data_dma_reg[32];
201 __be32 rcvt1_data_dma_reg[32];
202 __be32 risc_gp_reg[128];
203 __be32 lmc_reg[128];
204 __be32 fpm_hdw_reg[256];
205 __be32 rq0_array_reg[256];
206 __be32 rq1_array_reg[256];
207 __be32 rp0_array_reg[256];
208 __be32 rp1_array_reg[256];
209 __be32 queue_control_reg[16];
210 __be32 fb_hdw_reg[432];
211 __be32 at0_array_reg[128];
212 __be32 code_ram[0x2400];
213 __be32 ext_mem[1];
214 };
215
216 #define EFT_NUM_BUFFERS 4
217 #define EFT_BYTES_PER_BUFFER 0x4000
218 #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
219
220 #define FCE_NUM_BUFFERS 64
221 #define FCE_BYTES_PER_BUFFER 0x400
222 #define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
223 #define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b))
224
225 struct qla2xxx_fce_chain {
226 __be32 type;
227 __be32 chain_size;
228
229 __be32 size;
230 __be32 addr_l;
231 __be32 addr_h;
232 __be32 eregs[8];
233 };
234
235 /* used by exchange off load and extended login offload */
236 struct qla2xxx_offld_chain {
237 __be32 type;
238 __be32 chain_size;
239
240 __be32 size;
241 __be32 reserved;
242 __be64 addr;
243 };
244
245 struct qla2xxx_mq_chain {
246 __be32 type;
247 __be32 chain_size;
248
249 __be32 count;
250 __be32 qregs[4 * QLA_MQ_SIZE];
251 };
252
253 struct qla2xxx_mqueue_header {
254 __be32 queue;
255 #define TYPE_REQUEST_QUEUE 0x1
256 #define TYPE_RESPONSE_QUEUE 0x2
257 #define TYPE_ATIO_QUEUE 0x3
258 __be32 number;
259 __be32 size;
260 };
261
262 struct qla2xxx_mqueue_chain {
263 __be32 type;
264 __be32 chain_size;
265 };
266
267 #define DUMP_CHAIN_VARIANT 0x80000000
268 #define DUMP_CHAIN_FCE 0x7FFFFAF0
269 #define DUMP_CHAIN_MQ 0x7FFFFAF1
270 #define DUMP_CHAIN_QUEUE 0x7FFFFAF2
271 #define DUMP_CHAIN_EXLOGIN 0x7FFFFAF3
272 #define DUMP_CHAIN_EXCHG 0x7FFFFAF4
273 #define DUMP_CHAIN_LAST 0x80000000
274
275 struct qla2xxx_fw_dump {
276 uint8_t signature[4];
277 __be32 version;
278
279 __be32 fw_major_version;
280 __be32 fw_minor_version;
281 __be32 fw_subminor_version;
282 __be32 fw_attributes;
283
284 __be32 vendor;
285 __be32 device;
286 __be32 subsystem_vendor;
287 __be32 subsystem_device;
288
289 __be32 fixed_size;
290 __be32 mem_size;
291 __be32 req_q_size;
292 __be32 rsp_q_size;
293
294 __be32 eft_size;
295 __be32 eft_addr_l;
296 __be32 eft_addr_h;
297
298 __be32 header_size;
299
300 union {
301 struct qla2100_fw_dump isp21;
302 struct qla2300_fw_dump isp23;
303 struct qla24xx_fw_dump isp24;
304 struct qla25xx_fw_dump isp25;
305 struct qla81xx_fw_dump isp81;
306 struct qla83xx_fw_dump isp83;
307 } isp;
308 };
309
310 #define QL_MSGHDR "qla2xxx"
311 #define QL_DBG_DEFAULT1_MASK 0x1e600000
312
313 #define ql_log_fatal 0 /* display fatal errors */
314 #define ql_log_warn 1 /* display critical errors */
315 #define ql_log_info 2 /* display all recovered errors */
316 #define ql_log_all 3 /* This value is only used by ql_errlev.
317 * No messages will use this value.
318 * This should be always highest value
319 * as compared to other log levels.
320 */
321
322 extern uint ql_errlev;
323
324 void __attribute__((format (printf, 4, 5)))
325 ql_dbg(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
326 void __attribute__((format (printf, 4, 5)))
327 ql_dbg_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
328 void __attribute__((format (printf, 4, 5)))
329 ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
330
331
332 void __attribute__((format (printf, 4, 5)))
333 ql_log(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
334 void __attribute__((format (printf, 4, 5)))
335 ql_log_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
336
337 void __attribute__((format (printf, 4, 5)))
338 ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
339
340 /* Debug Levels */
341 /* The 0x40000000 is the max value any debug level can have
342 * as ql2xextended_error_logging is of type signed int
343 */
344 #define ql_dbg_init 0x40000000 /* Init Debug */
345 #define ql_dbg_mbx 0x20000000 /* MBX Debug */
346 #define ql_dbg_disc 0x10000000 /* Device Discovery Debug */
347 #define ql_dbg_io 0x08000000 /* IO Tracing Debug */
348 #define ql_dbg_dpc 0x04000000 /* DPC Thead Debug */
349 #define ql_dbg_async 0x02000000 /* Async events Debug */
350 #define ql_dbg_timer 0x01000000 /* Timer Debug */
351 #define ql_dbg_user 0x00800000 /* User Space Interations Debug */
352 #define ql_dbg_taskm 0x00400000 /* Task Management Debug */
353 #define ql_dbg_aer 0x00200000 /* AER/EEH Debug */
354 #define ql_dbg_multiq 0x00100000 /* MultiQ Debug */
355 #define ql_dbg_p3p 0x00080000 /* P3P specific Debug */
356 #define ql_dbg_vport 0x00040000 /* Virtual Port Debug */
357 #define ql_dbg_buffer 0x00020000 /* For dumping the buffer/regs */
358 #define ql_dbg_misc 0x00010000 /* For dumping everything that is not
359 * not covered by upper categories
360 */
361 #define ql_dbg_verbose 0x00008000 /* More verbosity for each level
362 * This is to be used with other levels where
363 * more verbosity is required. It might not
364 * be applicable to all the levels.
365 */
366 #define ql_dbg_tgt 0x00004000 /* Target mode */
367 #define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */
368 #define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */
369 #define ql_dbg_tgt_dif 0x00000800 /* Target mode dif */
370 #define ql_dbg_edif 0x00000400 /* edif and purex debug */
371
372 extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *,
373 uint32_t, void **);
374 extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, __be32 *,
375 uint32_t, void **);
376 extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *,
377 struct qla_hw_data *);
378 extern int qla24xx_soft_reset(struct qla_hw_data *);
379
380 static inline int
ql_mask_match(uint level)381 ql_mask_match(uint level)
382 {
383 if (ql2xextended_error_logging == 1)
384 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
385
386 return (level & ql2xextended_error_logging) == level;
387 }
388
