1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <linux/types.h>
33 #include <asm/byteorder.h>
34 #include <linux/bitops.h>
35 #include <linux/delay.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/errno.h>
38 #include <linux/io.h>
39 #include <linux/kernel.h>
40 #include <linux/list.h>
41 #include <linux/module.h>
42 #include <linux/mutex.h>
43 #include <linux/pci.h>
44 #include <linux/slab.h>
45 #include <linux/spinlock.h>
46 #include <linux/string.h>
47 #include "qed.h"
48 #include "qed_cxt.h"
49 #include "qed_hsi.h"
50 #include "qed_hw.h"
51 #include "qed_init_ops.h"
52 #include "qed_int.h"
53 #include "qed_ll2.h"
54 #include "qed_mcp.h"
55 #include "qed_reg_addr.h"
56 #include <linux/qed/qed_rdma_if.h>
57 #include "qed_rdma.h"
58 #include "qed_roce.h"
59 #include "qed_sp.h"
60
61
qed_rdma_bmap_alloc(struct qed_hwfn * p_hwfn,struct qed_bmap * bmap,u32 max_count,char * name)62 int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn,
63 struct qed_bmap *bmap, u32 max_count, char *name)
64 {
65 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count);
66
67 bmap->max_count = max_count;
68
69 bmap->bitmap = kcalloc(BITS_TO_LONGS(max_count), sizeof(long),
70 GFP_KERNEL);
71 if (!bmap->bitmap)
72 return -ENOMEM;
73
74 snprintf(bmap->name, QED_RDMA_MAX_BMAP_NAME, "%s", name);
75
76 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n");
77 return 0;
78 }
79
qed_rdma_bmap_alloc_id(struct qed_hwfn * p_hwfn,struct qed_bmap * bmap,u32 * id_num)80 int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn,
81 struct qed_bmap *bmap, u32 *id_num)
82 {
83 *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count);
84 if (*id_num >= bmap->max_count)
85 return -EINVAL;
86
87 __set_bit(*id_num, bmap->bitmap);
88
89 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: allocated id %d\n",
90 bmap->name, *id_num);
91
92 return 0;
93 }
94
qed_bmap_set_id(struct qed_hwfn * p_hwfn,struct qed_bmap * bmap,u32 id_num)95 void qed_bmap_set_id(struct qed_hwfn *p_hwfn,
96 struct qed_bmap *bmap, u32 id_num)
97 {
98 if (id_num >= bmap->max_count)
99 return;
100
101 __set_bit(id_num, bmap->bitmap);
102 }
103
qed_bmap_release_id(struct qed_hwfn * p_hwfn,struct qed_bmap * bmap,u32 id_num)104 void qed_bmap_release_id(struct qed_hwfn *p_hwfn,
105 struct qed_bmap *bmap, u32 id_num)
106 {
107 bool b_acquired;
108
109 if (id_num >= bmap->max_count)
110 return;
111
112 b_acquired = test_and_clear_bit(id_num, bmap->bitmap);
113 if (!b_acquired) {
114 DP_NOTICE(p_hwfn, "%s bitmap: id %d already released\n",
115 bmap->name, id_num);
116 return;
117 }
118
119 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: released id %d\n",
120 bmap->name, id_num);
121 }
122
qed_bmap_test_id(struct qed_hwfn * p_hwfn,struct qed_bmap * bmap,u32 id_num)123 int qed_bmap_test_id(struct qed_hwfn *p_hwfn,
124 struct qed_bmap *bmap, u32 id_num)
125 {
126 if (id_num >= bmap->max_count)
127 return -1;
128
129 return test_bit(id_num, bmap->bitmap);
130 }
131
qed_bmap_is_empty(struct qed_bmap * bmap)132 static bool qed_bmap_is_empty(struct qed_bmap *bmap)
133 {
134 return bmap->max_count == find_first_bit(bmap->bitmap, bmap->max_count);
135 }
136
qed_rdma_get_sb_id(void * p_hwfn,u32 rel_sb_id)137 static u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id)
138 {
139 /* First sb id for RoCE is after all the l2 sb */
140 return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id;
141 }
142
qed_rdma_info_alloc(struct qed_hwfn * p_hwfn)143 int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn)
144 {
145 struct qed_rdma_info *p_rdma_info;
146
147 p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL);
148 if (!p_rdma_info)
149 return -ENOMEM;
150
151 spin_lock_init(&p_rdma_info->lock);
152
153 p_hwfn->p_rdma_info = p_rdma_info;
154 return 0;
155 }
156
qed_rdma_info_free(struct qed_hwfn * p_hwfn)157 void qed_rdma_info_free(struct qed_hwfn *p_hwfn)
158 {
159 kfree(p_hwfn->p_rdma_info);
160 p_hwfn->p_rdma_info = NULL;
161 }
162
qed_rdma_alloc(struct qed_hwfn * p_hwfn)163 static int qed_rdma_alloc(struct qed_hwfn *p_hwfn)
164 {
165 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
166 u32 num_cons, num_tasks;
167 int rc = -ENOMEM;
168
169 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n");
170
171 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
172 p_rdma_info->proto = PROTOCOLID_IWARP;
173 else
174 p_rdma_info->proto = PROTOCOLID_ROCE;
175
176 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto,
177 NULL);
178
179 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
180 p_rdma_info->num_qps = num_cons;
181 else
182 p_rdma_info->num_qps = num_cons / 2; /* 2 cids per qp */
183
184 num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE);
185
186 /* Each MR uses a single task */
187 p_rdma_info->num_mrs = num_tasks;
188
189 /* Queue zone lines are shared between RoCE and L2 in such a way that
190 * they can be used by each without obstructing the other.
191 */
192 p_rdma_info->queue_zone_base = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
193 p_rdma_info->max_queue_zones = (u16)RESC_NUM(p_hwfn, QED_L2_QUEUE);
194
195 /* Allocate a struct with device params and fill it */
196 p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL);
197 if (!p_rdma_info->dev)
198 return rc;
199
200 /* Allocate a struct with port params and fill it */
201 p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL);
202 if (!p_rdma_info->port)
203 goto free_rdma_dev;
204
205 /* Allocate bit map for pd's */
206 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS,
207 "PD");
208 if (rc) {
209 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
210 "Failed to allocate pd_map, rc = %d\n",
211 rc);
212 goto free_rdma_port;
213 }
214
215 /* Allocate DPI bitmap */
216 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map,
217 p_hwfn->dpi_count, "DPI");
218 if (rc) {
219 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
220 "Failed to allocate DPI bitmap, rc = %d\n", rc);
221 goto free_pd_map;
222 }
223
224 /* Allocate bitmap for cq's. The maximum number of CQs is bound to
225 * the number of connections we support. (num_qps in iWARP or
226 * num_qps/2 in RoCE).
227 */
228 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map, num_cons, "CQ");
229 if (rc) {
230 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
231 "Failed to allocate cq bitmap, rc = %d\n", rc);
232 goto free_dpi_map;
233 }
234
235 /* Allocate bitmap for toggle bit for cq icids
236 * We toggle the bit every time we create or resize cq for a given icid.
237 * Size needs to equal the size of the cq bmap.
238 */
239 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits,
240 num_cons, "Toggle");
241 if (rc) {
242 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
243 "Failed to allocate toggle bits, rc = %d\n", rc);
244 goto free_cq_map;
245 }
246
247 /* Allocate bitmap for itids */
248 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map,
249 p_rdma_info->num_mrs, "MR");
250 if (rc) {
251 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
252 "Failed to allocate itids bitmaps, rc = %d\n", rc);
253 goto free_toggle_map;
254 }
255
256 /* Allocate bitmap for cids used for qps. */
257 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons,
258 "CID");
259 if (rc) {
260 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
261 "Failed to allocate cid bitmap, rc = %d\n", rc);
262 goto free_tid_map;
263 }
264
265 /* Allocate bitmap for cids used for responders/requesters. */
266 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->real_cid_map, num_cons,
267 "REAL_CID");
268 if (rc) {
269 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
270 "Failed to allocate real cid bitmap, rc = %d\n", rc);
271 goto free_cid_map;
272 }
273
274 /* Allocate bitmap for srqs */
275 p_rdma_info->num_srqs = qed_cxt_get_srq_count(p_hwfn);
276 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->srq_map,
277 p_rdma_info->num_srqs, "SRQ");
278 if (rc) {
279 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
280 "Failed to allocate srq bitmap, rc = %d\n", rc);
281 goto free_real_cid_map;
282 }
283
284 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
285 rc = qed_iwarp_alloc(p_hwfn);
286
287 if (rc)
288 goto free_srq_map;
289
290 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n");
291 return 0;
292
293 free_srq_map:
294 kfree(p_rdma_info->srq_map.bitmap);
295 free_real_cid_map:
296 kfree(p_rdma_info->real_cid_map.bitmap);
297 free_cid_map:
298 kfree(p_rdma_info->cid_map.bitmap);
299 free_tid_map:
300 kfree(p_rdma_info->tid_map.bitmap);
301 free_toggle_map:
302 kfree(p_rdma_info->toggle_bits.bitmap);
303 free_cq_map:
304 kfree(p_rdma_info->cq_map.bitmap);
305 free_dpi_map:
306 kfree(p_rdma_info->dpi_map.bitmap);
307 free_pd_map:
308 kfree(p_rdma_info->pd_map.bitmap);
309 free_rdma_port:
310 kfree(p_rdma_info->port);
311 free_rdma_dev:
312 kfree(p_rdma_info->dev);
313
314 return rc;
315 }
316
qed_rdma_bmap_free(struct qed_hwfn * p_hwfn,struct qed_bmap * bmap,bool check)317 void qed_rdma_bmap_free(struct qed_hwfn *p_hwfn,
318 struct qed_bmap *bmap, bool check)
319 {
320 int weight = bitmap_weight(bmap->bitmap, bmap->max_count);
321 int last_line = bmap->max_count / (64 * 8);
322 int last_item = last_line * 8 +
323 DIV_ROUND_UP(bmap->max_count % (64 * 8), 64);
324 u64 *pmap = (u64 *)bmap->bitmap;
325 int line, item, offset;
326 u8 str_last_line[200] = { 0 };
327
328 if (!weight || !check)
329 goto end;
330
331 DP_NOTICE(p_hwfn,
332 "%s bitmap not free - size=%d, weight=%d, 512 bits per line\n",
333 bmap->name, bmap->max_count, weight);
334
335 /* print aligned non-zero lines, if any */
336 for (item = 0, line = 0; line < last_line; line++, item += 8)
337 if (bitmap_weight((unsigned long *)&pmap[item], 64 * 8))
338 DP_NOTICE(p_hwfn,
339 "line 0x%04x: 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx\n",
340 line,
341 pmap[item],
342 pmap[item + 1],
343 pmap[item + 2],
344 pmap[item + 3],
345 pmap[item + 4],
346 pmap[item + 5],
347 pmap[item + 6], pmap[item + 7]);
348
349 /* print last unaligned non-zero line, if any */
350 if ((bmap->max_count % (64 * 8)) &&
351 (bitmap_weight((unsigned long *)&pmap[item],
352 bmap->max_count - item * 64))) {
353 offset = sprintf(str_last_line, "line 0x%04x: ", line);
354 for (; item < last_item; item++)
355 offset += sprintf(str_last_line + offset,
356 "0x%016llx ", pmap[item]);
357 DP_NOTICE(p_hwfn, "%s\n", str_last_line);
358 }
359
360 end:
361 kfree(bmap->bitmap);
362 bmap->bitmap = NULL;
363 }
364
qed_rdma_resc_free(struct qed_hwfn * p_hwfn)365 static void qed_rdma_resc_free(struct qed_hwfn *p_hwfn)
366 {
367 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
368
369 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
370 qed_iwarp_resc_free(p_hwfn);
371
372 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cid_map, 1);
373 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->pd_map, 1);
374 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 1);
375 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cq_map, 1);
376 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->toggle_bits, 0);
377 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->tid_map, 1);
378 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->srq_map, 1);
379 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, 1);
380
381 kfree(p_rdma_info->port);
382 kfree(p_rdma_info->dev);
383 }
384
qed_rdma_free_tid(void * rdma_cxt,u32 itid)385 static void qed_rdma_free_tid(void *rdma_cxt, u32 itid)
386 {
387 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
388
389 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid);
390
391 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
392 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid);
393 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
394 }
395
qed_rdma_free_reserved_lkey(struct qed_hwfn * p_hwfn)396 static void qed_rdma_free_reserved_lkey(struct qed_hwfn *p_hwfn)
397 {
398 qed_rdma_free_tid(p_hwfn, p_hwfn->p_rdma_info->dev->reserved_lkey);
399 }
400
qed_rdma_free(struct qed_hwfn * p_hwfn)401 static void qed_rdma_free(struct qed_hwfn *p_hwfn)
402 {
403 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n");
404
405 qed_rdma_free_reserved_lkey(p_hwfn);
406 qed_cxt_free_proto_ilt(p_hwfn, p_hwfn->p_rdma_info->proto);
407 qed_rdma_resc_free(p_hwfn);
408 }
409
qed_rdma_get_guid(struct qed_hwfn * p_hwfn,u8 * guid)410 static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid)
411 {
412 guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2;
413 guid[1] = p_hwfn->hw_info.hw_mac_addr[1];
414 guid[2] = p_hwfn->hw_info.hw_mac_addr[2];
415 guid[3] = 0xff;
416 guid[4] = 0xfe;
417 guid[5] = p_hwfn->hw_info.hw_mac_addr[3];
418 guid[6] = p_hwfn->hw_info.hw_mac_addr[4];
419 guid[7] = p_hwfn->hw_info.hw_mac_addr[5];
420 }
421
qed_rdma_init_events(struct qed_hwfn * p_hwfn,struct qed_rdma_start_in_params * params)422 static void qed_rdma_init_events(struct qed_hwfn *p_hwfn,
423 struct qed_rdma_start_in_params *params)
424 {
425 struct qed_rdma_events *events;
426
427 events = &p_hwfn->p_rdma_info->events;
428
429 events->unaffiliated_event = params->events->unaffiliated_event;
430 events->affiliated_event = params->events->affiliated_event;
431 events->context = params->events->context;
432 }
433
qed_rdma_init_devinfo(struct qed_hwfn * p_hwfn,struct qed_rdma_start_in_params * params)434 static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn,
435 struct qed_rdma_start_in_params *params)
436 {
437 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
438 struct qed_dev *cdev = p_hwfn->cdev;
439 u32 pci_status_control;
440 u32 num_qps;
441
442 /* Vendor specific information */
443 dev->vendor_id = cdev->vendor_id;
444 dev->vendor_part_id = cdev->device_id;
445 dev->hw_ver = cdev->chip_rev;
446 dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |
447 (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION);
448
449 qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid);
450 dev->node_guid = dev->sys_image_guid;
451
452 dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE,
453 RDMA_MAX_SGE_PER_RQ_WQE);
454
455 if (cdev->rdma_max_sge)
456 dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge);
457
458 dev->max_srq_sge = QED_RDMA_MAX_SGE_PER_SRQ_WQE;
459 if (p_hwfn->cdev->rdma_max_srq_sge) {
460 dev->max_srq_sge = min_t(u32,
461 p_hwfn->cdev->rdma_max_srq_sge,
462 dev->max_srq_sge);
463 }
464 dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE;
465
466 dev->max_inline = (cdev->rdma_max_inline) ?
467 min_t(u32, cdev->rdma_max_inline, dev->max_inline) :
468 dev->max_inline;
469
470 dev->max_wqe = QED_RDMA_MAX_WQE;
471 dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ);
472
473 /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because
474 * it is up-aligned to 16 and then to ILT page size within qed cxt.
475 * This is OK in terms of ILT but we don't want to configure the FW
476 * above its abilities
477 */
478 num_qps = ROCE_MAX_QPS;
479 num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps);
480 dev->max_qp = num_qps;
481
482 /* CQs uses the same icids that QPs use hence they are limited by the
483 * number of icids. There are two icids per QP.
484 */
485 dev->max_cq = num_qps * 2;
486
487 /* The number of mrs is smaller by 1 since the first is reserved */
488 dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1;
489 dev->max_mr_size = QED_RDMA_MAX_MR_SIZE;
490
491 /* The maximum CQE capacity per CQ supported.
492 * max number of cqes will be in two layer pbl,
493 * 8 is the pointer size in bytes
494 * 32 is the size of cq element in bytes
495 */
496 if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS)
497 dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT;
498 else
499 dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT;
500
501 dev->max_mw = 0;
502 dev->max_fmr = QED_RDMA_MAX_FMR;
503 dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8);
504 dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE;
505 dev->max_pkey = QED_RDMA_MAX_P_KEY;
506
507 dev->max_srq = p_hwfn->p_rdma_info->num_srqs;
508 dev->max_srq_wr = QED_RDMA_MAX_SRQ_WQE_ELEM;
509 dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
510 (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2);
511 dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
512 RDMA_REQ_RD_ATOMIC_ELM_SIZE;
513 dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc *
514 p_hwfn->p_rdma_info->num_qps;
515 dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS;
516 dev->dev_ack_delay = QED_RDMA_ACK_DELAY;
517 dev->max_pd = RDMA_MAX_PDS;
518 dev->max_ah = p_hwfn->p_rdma_info->num_qps;
519 dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE);
520
521 /* Set capablities */
522 dev->dev_caps = 0;
523 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1);
524 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1);
525 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1);
526 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1);
527 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1);
528 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1);
529 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1);
530 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1);
531
532 /* Check atomic operations support in PCI configuration space. */
533 pcie_capability_read_dword(cdev->pdev, PCI_EXP_DEVCTL2,
534 &pci_status_control);
535
536 if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN)
537 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1);
538
539 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
540 qed_iwarp_init_devinfo(p_hwfn);
541 }
542
qed_rdma_init_port(struct qed_hwfn * p_hwfn)543 static void qed_rdma_init_port(struct qed_hwfn *p_hwfn)
544 {
545 struct qed_rdma_port *port = p_hwfn->p_rdma_info->port;
546 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
547
548 port->port_state = p_hwfn->mcp_info->link_output.link_up ?
549 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
550
551 port->max_msg_size = min_t(u64,
552 (dev->max_mr_mw_fmr_size *
553 p_hwfn->cdev->rdma_max_sge),
554 BIT(31));
555
556 port->pkey_bad_counter = 0;
557 }
558
qed_rdma_init_hw(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)559 static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
560 {
561 int rc = 0;
562
563 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n");
564 p_hwfn->b_rdma_enabled_in_prs = false;
565
566 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
567 qed_iwarp_init_hw(p_hwfn, p_ptt);
568 else
569 rc = qed_roce_init_hw(p_hwfn, p_ptt);
570
571 return rc;
572 }
573
qed_rdma_start_fw(struct qed_hwfn * p_hwfn,struct qed_rdma_start_in_params * params,struct qed_ptt * p_ptt)574 static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn,
575 struct qed_rdma_start_in_params *params,
576 struct qed_ptt *p_ptt)
577 {
578 struct rdma_init_func_ramrod_data *p_ramrod;
579 struct qed_rdma_cnq_params *p_cnq_pbl_list;
580 struct rdma_init_func_hdr *p_params_header;
581 struct rdma_cnq_params *p_cnq_params;
582 struct qed_sp_init_data init_data;
583 struct qed_spq_entry *p_ent;
584 u32 cnq_id, sb_id;
585 u16 igu_sb_id;
586 int rc;
587
588 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n");
589
590 /* Save the number of cnqs for the function close ramrod */
591 p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq;
592
593 /* Get SPQ entry */
594 memset(&init_data, 0, sizeof(init_data));
595 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
596 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
597
598 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT,
599 p_hwfn->p_rdma_info->proto, &init_data);
600 if (rc)
601 return rc;
602
603 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
604 qed_iwarp_init_fw_ramrod(p_hwfn,
605 &p_ent->ramrod.iwarp_init_func);
606 p_ramrod = &p_ent->ramrod.iwarp_init_func.rdma;
607 } else {
608 p_ramrod = &p_ent->ramrod.roce_init_func.rdma;
609 }
610
611 p_params_header = &p_ramrod->params_header;
612 p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn,
613 QED_RDMA_CNQ_RAM);
614 p_params_header->num_cnqs = params->desired_cnq;
615
616 if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS)
617 p_params_header->cq_ring_mode = 1;
618 else
619 p_params_header->cq_ring_mode = 0;
620
621 for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) {
622 sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id);
623 igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
624 p_ramrod->cnq_params[cnq_id].sb_num = cpu_to_le16(igu_sb_id);
625 p_cnq_params = &p_ramrod->cnq_params[cnq_id];
626 p_cnq_pbl_list = ¶ms->cnq_pbl_list[cnq_id];
627
628 p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi;
629 p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages;
630
631 DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr,
632 p_cnq_pbl_list->pbl_ptr);
633
634 /* we assume here that cnq_id and qz_offset are the same */
635 p_cnq_params->queue_zone_num =
636 cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base +
637 cnq_id);
638 }
639
640 return qed_spq_post(p_hwfn, p_ent, NULL);
641 }
642
qed_rdma_alloc_tid(void * rdma_cxt,u32 * itid)643 static int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid)
644 {
645 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
646 int rc;
647
648 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n");
649
650 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
651 rc = qed_rdma_bmap_alloc_id(p_hwfn,
652 &p_hwfn->p_rdma_info->tid_map, itid);
653 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
654 if (rc)
655 goto out;
656
657 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid);
658 out:
659 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc);
660 return rc;
661 }
662
qed_rdma_reserve_lkey(struct qed_hwfn * p_hwfn)663 static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn)
664 {
665 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
666
667 /* Tid 0 will be used as the key for "reserved MR".
668 * The driver should allocate memory for it so it can be loaded but no
669 * ramrod should be passed on it.
670 */
671 qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey);
672 if (dev->reserved_lkey != RDMA_RESERVED_LKEY) {
673 DP_NOTICE(p_hwfn,
674 "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n");
675 return -EINVAL;
676 }
677
678 return 0;
679 }
680
qed_rdma_setup(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_rdma_start_in_params * params)681 static int qed_rdma_setup(struct qed_hwfn *p_hwfn,
682 struct qed_ptt *p_ptt,
683 struct qed_rdma_start_in_params *params)
684 {
685 int rc;
686
687 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n");
688
689 qed_rdma_init_devinfo(p_hwfn, params);
690 qed_rdma_init_port(p_hwfn);
691 qed_rdma_init_events(p_hwfn, params);
692
693 rc = qed_rdma_reserve_lkey(p_hwfn);
694 if (rc)
695 return rc;
696
697 rc = qed_rdma_init_hw(p_hwfn, p_ptt);
698 if (rc)
699 return rc;
700
701 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
702 rc = qed_iwarp_setup(p_hwfn, params);
703 if (rc)
704 return rc;
705 } else {
706 rc = qed_roce_setup(p_hwfn);
707 if (rc)
708 return rc;
709 }
710
711 return qed_rdma_start_fw(p_hwfn, params, p_ptt);
712 }
713
qed_rdma_stop(void * rdma_cxt)714 static int qed_rdma_stop(void *rdma_cxt)
715 {
716 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
717 struct rdma_close_func_ramrod_data *p_ramrod;
718 struct qed_sp_init_data init_data;
719 struct qed_spq_entry *p_ent;
720 struct qed_ptt *p_ptt;
721 u32 ll2_ethertype_en;
722 int rc = -EBUSY;
723
724 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n");
725
726 p_ptt = qed_ptt_acquire(p_hwfn);
727 if (!p_ptt) {
728 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n");
729 return rc;
730 }
731
732 /* Disable RoCE search */
733 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0);
734 p_hwfn->b_rdma_enabled_in_prs = false;
735 p_hwfn->p_rdma_info->active = 0;
736 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0);
737
738 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
739
740 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN,
741 (ll2_ethertype_en & 0xFFFE));
742
743 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
744 rc = qed_iwarp_stop(p_hwfn);
745 if (rc) {
746 qed_ptt_release(p_hwfn, p_ptt);
747 return rc;
748 }
749 } else {
750 qed_roce_stop(p_hwfn);
751 }
752
753 qed_ptt_release(p_hwfn, p_ptt);
754
755 /* Get SPQ entry */
756 memset(&init_data, 0, sizeof(init_data));
757 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
758 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
759
760 /* Stop RoCE */
761 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE,
762 p_hwfn->p_rdma_info->proto, &init_data);
763 if (rc)
764 goto out;
765
766 p_ramrod = &p_ent->ramrod.rdma_close_func;
767
768 p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs;
769 p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM);
770
771 rc = qed_spq_post(p_hwfn, p_ent, NULL);
772
773 out:
774 qed_rdma_free(p_hwfn);
775
776 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc);
777 return rc;
778 }
779
qed_rdma_add_user(void * rdma_cxt,struct qed_rdma_add_user_out_params * out_params)780 static int qed_rdma_add_user(void *rdma_cxt,
781 struct qed_rdma_add_user_out_params *out_params)
782 {
783 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
784 u32 dpi_start_offset;
785 u32 returned_id = 0;
786 int rc;
787
788 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n");
789
790 /* Allocate DPI */
791 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
792 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map,
793 &returned_id);
794 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
795
796 out_params->dpi = (u16)returned_id;
797
798 /* Calculate the corresponding DPI address */
799 dpi_start_offset = p_hwfn->dpi_start_offset;
800
801 out_params->dpi_addr = p_hwfn->doorbells + dpi_start_offset +
802 out_params->dpi * p_hwfn->dpi_size;
803
804 out_params->dpi_phys_addr = p_hwfn->db_phys_addr +
805 dpi_start_offset +
806 ((out_params->dpi) * p_hwfn->dpi_size);
807
808 out_params->dpi_size = p_hwfn->dpi_size;
809 out_params->wid_count = p_hwfn->wid_count;
810
811 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc);
812 return rc;
813 }
814
qed_rdma_query_port(void * rdma_cxt)815 static struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt)
816 {
817 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
818 struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port;
819 struct qed_mcp_link_state *p_link_output;
820
821 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n");
822
823 /* The link state is saved only for the leading hwfn */
824 p_link_output = &QED_LEADING_HWFN(p_hwfn->cdev)->mcp_info->link_output;
825
826 p_port->port_state = p_link_output->link_up ? QED_RDMA_PORT_UP
827 : QED_RDMA_PORT_DOWN;
828
829 p_port->link_speed = p_link_output->speed;
830
831 p_port->max_msg_size = RDMA_MAX_DATA_SIZE_IN_WQE;
832
833 return p_port;
834 }
835
qed_rdma_query_device(void * rdma_cxt)836 static struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt)
837 {
838 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
839
840 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n");
841
842 /* Return struct with device parameters */
843 return p_hwfn->p_rdma_info->dev;
844 }
845
qed_rdma_cnq_prod_update(void * rdma_cxt,u8 qz_offset,u16 prod)846 static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod)
847 {
848 struct qed_hwfn *p_hwfn;
849 u16 qz_num;
850 u32 addr;
851
852 p_hwfn = (struct qed_hwfn *)rdma_cxt;
853
854 if (qz_offset > p_hwfn->p_rdma_info->max_queue_zones) {
855 DP_NOTICE(p_hwfn,
856 "queue zone offset %d is too large (max is %d)\n",
857 qz_offset, p_hwfn->p_rdma_info->max_queue_zones);
858 return;
859 }
860
861 qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset;
862 addr = GTT_BAR0_MAP_REG_USDM_RAM +
863 USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num);
864
865 REG_WR16(p_hwfn, addr, prod);
866
867 /* keep prod updates ordered */
868 wmb();
869 }
870
qed_fill_rdma_dev_info(struct qed_dev * cdev,struct qed_dev_rdma_info * info)871 static int qed_fill_rdma_dev_info(struct qed_dev *cdev,
872 struct qed_dev_rdma_info *info)
873 {
874 struct qed_hwfn *p_hwfn = QED_AFFIN_HWFN(cdev);
875
876 memset(info, 0, sizeof(*info));
877
878 info->rdma_type = QED_IS_ROCE_PERSONALITY(p_hwfn) ?
879 QED_RDMA_TYPE_ROCE : QED_RDMA_TYPE_IWARP;
880
881 info->user_dpm_enabled = (p_hwfn->db_bar_no_edpm == 0);
882
883 qed_fill_dev_info(cdev, &info->common);
884
885 return 0;
886 }
887
qed_rdma_get_sb_start(struct qed_dev * cdev)888 static int qed_rdma_get_sb_start(struct qed_dev *cdev)
889 {
890 int feat_num;
891
892 if (cdev->num_hwfns > 1)
893 feat_num = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_PF_L2_QUE);
894 else
895 feat_num = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_PF_L2_QUE) *
896 cdev->num_hwfns;
897
898 return feat_num;
899 }
900
qed_rdma_get_min_cnq_msix(struct qed_dev * cdev)901 static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev)
902 {
903 int n_cnq = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_RDMA_CNQ);
904 int n_msix = cdev->int_params.rdma_msix_cnt;
905
906 return min_t(int, n_cnq, n_msix);
907 }
908
qed_rdma_set_int(struct qed_dev * cdev,u16 cnt)909 static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt)
910 {
911 int limit = 0;
912
913 /* Mark the fastpath as free/used */
914 cdev->int_params.fp_initialized = cnt ? true : false;
915
916 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) {
917 DP_ERR(cdev,
918 "qed roce supports only MSI-X interrupts (detected %d).\n",
919 cdev->int_params.out.int_mode);
920 return -EINVAL;
921 } else if (cdev->int_params.fp_msix_cnt) {
922 limit = cdev->int_params.rdma_msix_cnt;
923 }
924
925 if (!limit)
926 return -ENOMEM;
927
928 return min_t(int, cnt, limit);
929 }
930
qed_rdma_get_int(struct qed_dev * cdev,struct qed_int_info * info)931 static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info)
932 {
933 memset(info, 0, sizeof(*info));
934
935 if (!cdev->int_params.fp_initialized) {
936 DP_INFO(cdev,
937 "Protocol driver requested interrupt information, but its support is not yet configured\n");
938 return -EINVAL;
939 }
940
941 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
942 int msix_base = cdev->int_params.rdma_msix_base;
943
944 info->msix_cnt = cdev->int_params.rdma_msix_cnt;
945 info->msix = &cdev->int_params.msix_table[msix_base];
946
947 DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n",
948 info->msix_cnt, msix_base);
949 }
950
951 return 0;
952 }
953
qed_rdma_alloc_pd(void * rdma_cxt,u16 * pd)954 static int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd)
955 {
956 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
957 u32 returned_id;
958 int rc;
959
960 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n");
961
962 /* Allocates an unused protection domain */
963 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
964 rc = qed_rdma_bmap_alloc_id(p_hwfn,
965 &p_hwfn->p_rdma_info->pd_map, &returned_id);
966 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
967
968 *pd = (u16)returned_id;
969
970 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc);
971 return rc;
972 }
973
qed_rdma_free_pd(void * rdma_cxt,u16 pd)974 static void qed_rdma_free_pd(void *rdma_cxt, u16 pd)
975 {
976 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
977
978 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd);
979
980 /* Returns a previously allocated protection domain for reuse */
981 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
982 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd);
983 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
984 }
985
986 static enum qed_rdma_toggle_bit
qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn * p_hwfn,u16 icid)987 qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid)
988 {
989 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
990 enum qed_rdma_toggle_bit toggle_bit;
991 u32 bmap_id;
992
993 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid);
994
995 /* the function toggle the bit that is related to a given icid
996 * and returns the new toggle bit's value
997 */
998 bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto);
999
1000 spin_lock_bh(&p_info->lock);
1001 toggle_bit = !test_and_change_bit(bmap_id,
1002 p_info->toggle_bits.bitmap);
1003 spin_unlock_bh(&p_info->lock);
1004
1005 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n",
1006 toggle_bit);
1007
1008 return toggle_bit;
1009 }
1010
qed_rdma_create_cq(void * rdma_cxt,struct qed_rdma_create_cq_in_params * params,u16 * icid)1011 static int qed_rdma_create_cq(void *rdma_cxt,
1012 struct qed_rdma_create_cq_in_params *params,
1013 u16 *icid)
1014 {
1015 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1016 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
1017 struct rdma_create_cq_ramrod_data *p_ramrod;
1018 enum qed_rdma_toggle_bit toggle_bit;
1019 struct qed_sp_init_data init_data;
1020 struct qed_spq_entry *p_ent;
1021 u32 returned_id, start_cid;
1022 int rc;
1023
1024 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n",
1025 params->cq_handle_hi, params->cq_handle_lo);
1026
1027 /* Allocate icid */
1028 spin_lock_bh(&p_info->lock);
1029 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_info->cq_map, &returned_id);
1030 spin_unlock_bh(&p_info->lock);
1031
1032 if (rc) {
1033 DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc);
1034 return rc;
1035 }
1036
1037 start_cid = qed_cxt_get_proto_cid_start(p_hwfn,
1038 p_info->proto);
1039 *icid = returned_id + start_cid;
1040
1041 /* Check if icid requires a page allocation */
1042 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid);
1043 if (rc)
1044 goto err;
1045
1046 /* Get SPQ entry */
1047 memset(&init_data, 0, sizeof(init_data));
1048 init_data.cid = *icid;
1049 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1050 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1051
1052 /* Send create CQ ramrod */
1053 rc = qed_sp_init_request(p_hwfn, &p_ent,
1054 RDMA_RAMROD_CREATE_CQ,
1055 p_info->proto, &init_data);
1056 if (rc)
1057 goto err;
1058
1059 p_ramrod = &p_ent->ramrod.rdma_create_cq;
1060
1061 p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi);
1062 p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo);
1063 p_ramrod->dpi = cpu_to_le16(params->dpi);
1064 p_ramrod->is_two_level_pbl = params->pbl_two_level;
1065 p_ramrod->max_cqes = cpu_to_le32(params->cq_size);
1066 DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr);
1067 p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages);
1068 p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) +
1069 params->cnq_id;
1070 p_ramrod->int_timeout = params->int_timeout;
1071
1072 /* toggle the bit for every resize or create cq for a given icid */
1073 toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
1074
1075 p_ramrod->toggle_bit = toggle_bit;
1076
1077 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1078 if (rc) {
1079 /* restore toggle bit */
1080 qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
1081 goto err;
1082 }
1083
1084 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc);
1085 return rc;
1086
1087 err:
1088 /* release allocated icid */
1089 spin_lock_bh(&p_info->lock);
1090 qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id);
1091 spin_unlock_bh(&p_info->lock);
1092 DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc);
1093
1094 return rc;
1095 }
1096
1097 static int
qed_rdma_destroy_cq(void * rdma_cxt,struct qed_rdma_destroy_cq_in_params * in_params,struct qed_rdma_destroy_cq_out_params * out_params)1098 qed_rdma_destroy_cq(void *rdma_cxt,
1099 struct qed_rdma_destroy_cq_in_params *in_params,
1100 struct qed_rdma_destroy_cq_out_params *out_params)
1101 {
1102 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1103 struct rdma_destroy_cq_output_params *p_ramrod_res;
1104 struct rdma_destroy_cq_ramrod_data *p_ramrod;
1105 struct qed_sp_init_data init_data;
1106 struct qed_spq_entry *p_ent;
1107 dma_addr_t ramrod_res_phys;
1108 enum protocol_type proto;
1109 int rc = -ENOMEM;
1110
1111 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid);
1112
1113 p_ramrod_res =
1114 (struct rdma_destroy_cq_output_params *)
1115 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1116 sizeof(struct rdma_destroy_cq_output_params),
1117 &ramrod_res_phys, GFP_KERNEL);
1118 if (!p_ramrod_res) {
1119 DP_NOTICE(p_hwfn,
1120 "qed destroy cq failed: cannot allocate memory (ramrod)\n");
1121 return rc;
1122 }
1123
1124 /* Get SPQ entry */
1125 memset(&init_data, 0, sizeof(init_data));
1126 init_data.cid = in_params->icid;
1127 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1128 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1129 proto = p_hwfn->p_rdma_info->proto;
1130 /* Send destroy CQ ramrod */
1131 rc = qed_sp_init_request(p_hwfn, &p_ent,
1132 RDMA_RAMROD_DESTROY_CQ,
1133 proto, &init_data);
1134 if (rc)
1135 goto err;
1136
1137 p_ramrod = &p_ent->ramrod.rdma_destroy_cq;
1138 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1139
1140 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1141 if (rc)
1142 goto err;
1143
1144 out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num);
1145
1146 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1147 sizeof(struct rdma_destroy_cq_output_params),
1148 p_ramrod_res, ramrod_res_phys);
1149
1150 /* Free icid */
1151 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1152
1153 qed_bmap_release_id(p_hwfn,
1154 &p_hwfn->p_rdma_info->cq_map,
1155 (in_params->icid -
1156 qed_cxt_get_proto_cid_start(p_hwfn, proto)));
1157
1158 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1159
1160 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc);
1161 return rc;
1162
1163 err: dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1164 sizeof(struct rdma_destroy_cq_output_params),
1165 p_ramrod_res, ramrod_res_phys);
1166
1167 return rc;
1168 }
1169
qed_rdma_set_fw_mac(u16 * p_fw_mac,u8 * p_qed_mac)1170 void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac)
1171 {
1172 p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]);
1173 p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]);
1174 p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]);
1175 }
1176
qed_rdma_query_qp(void * rdma_cxt,struct qed_rdma_qp * qp,struct qed_rdma_query_qp_out_params * out_params)1177 static int qed_rdma_query_qp(void *rdma_cxt,
1178 struct qed_rdma_qp *qp,
1179 struct qed_rdma_query_qp_out_params *out_params)
1180 {
1181 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1182 int rc = 0;
1183
1184 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1185
1186 /* The following fields are filled in from qp and not FW as they can't
1187 * be modified by FW
1188 */
1189 out_params->mtu = qp->mtu;
1190 out_params->dest_qp = qp->dest_qp;
1191 out_params->incoming_atomic_en = qp->incoming_atomic_en;
1192 out_params->e2e_flow_control_en = qp->e2e_flow_control_en;
1193 out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en;
1194 out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en;
1195 out_params->dgid = qp->dgid;
1196 out_params->flow_label = qp->flow_label;
1197 out_params->hop_limit_ttl = qp->hop_limit_ttl;
1198 out_params->traffic_class_tos = qp->traffic_class_tos;
1199 out_params->timeout = qp->ack_timeout;
1200 out_params->rnr_retry = qp->rnr_retry_cnt;
1201 out_params->retry_cnt = qp->retry_cnt;
1202 out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer;
1203 out_params->pkey_index = 0;
1204 out_params->max_rd_atomic = qp->max_rd_atomic_req;
1205 out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp;
1206 out_params->sqd_async = qp->sqd_async;
1207
1208 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
1209 qed_iwarp_query_qp(qp, out_params);
1210 else
1211 rc = qed_roce_query_qp(p_hwfn, qp, out_params);
1212
1213 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc);
1214 return rc;
1215 }
1216
qed_rdma_destroy_qp(void * rdma_cxt,struct qed_rdma_qp * qp)1217 static int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp)
1218 {
1219 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1220 int rc = 0;
1221
1222 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1223
1224 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
1225 rc = qed_iwarp_destroy_qp(p_hwfn, qp);
1226 else
1227 rc = qed_roce_destroy_qp(p_hwfn, qp);
1228
1229 /* free qp params struct */
1230 kfree(qp);
1231
1232 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n");
1233 return rc;
1234 }
1235
1236 static struct qed_rdma_qp *
qed_rdma_create_qp(void * rdma_cxt,struct qed_rdma_create_qp_in_params * in_params,struct qed_rdma_create_qp_out_params * out_params)1237 qed_rdma_create_qp(void *rdma_cxt,
1238 struct qed_rdma_create_qp_in_params *in_params,
1239 struct qed_rdma_create_qp_out_params *out_params)
1240 {
1241 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1242 struct qed_rdma_qp *qp;
1243 u8 max_stats_queues;
1244 int rc;
1245
1246 if (!rdma_cxt || !in_params || !out_params ||
1247 !p_hwfn->p_rdma_info->active) {
1248 DP_ERR(p_hwfn->cdev,
1249 "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n",
1250 rdma_cxt, in_params, out_params);
1251 return NULL;
1252 }
1253
1254 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1255 "qed rdma create qp called with qp_handle = %08x%08x\n",
1256 in_params->qp_handle_hi, in_params->qp_handle_lo);
1257
1258 /* Some sanity checks... */
1259 max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues;
1260 if (in_params->stats_queue >= max_stats_queues) {
1261 DP_ERR(p_hwfn->cdev,
1262 "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n",
1263 in_params->stats_queue, max_stats_queues);
1264 return NULL;
1265 }
1266
1267 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
1268 if (in_params->sq_num_pages * sizeof(struct regpair) >
1269 IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE) {
1270 DP_NOTICE(p_hwfn->cdev,
1271 "Sq num pages: %d exceeds maximum\n",
1272 in_params->sq_num_pages);
1273 return NULL;
1274 }
1275 if (in_params->rq_num_pages * sizeof(struct regpair) >
1276 IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE) {
1277 DP_NOTICE(p_hwfn->cdev,
1278 "Rq num pages: %d exceeds maximum\n",
1279 in_params->rq_num_pages);
1280 return NULL;
1281 }
1282 }
1283
1284 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1285 if (!qp)
1286 return NULL;
1287
1288 qp->cur_state = QED_ROCE_QP_STATE_RESET;
1289 qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi);
1290 qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo);
1291 qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi);
1292 qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo);
1293 qp->use_srq = in_params->use_srq;
1294 qp->signal_all = in_params->signal_all;
1295 qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey;
1296 qp->pd = in_params->pd;
1297 qp->dpi = in_params->dpi;
1298 qp->sq_cq_id = in_params->sq_cq_id;
1299 qp->sq_num_pages = in_params->sq_num_pages;
1300 qp->sq_pbl_ptr = in_params->sq_pbl_ptr;
1301 qp->rq_cq_id = in_params->rq_cq_id;
1302 qp->rq_num_pages = in_params->rq_num_pages;
1303 qp->rq_pbl_ptr = in_params->rq_pbl_ptr;
1304 qp->srq_id = in_params->srq_id;
1305 qp->req_offloaded = false;
1306 qp->resp_offloaded = false;
1307 qp->e2e_flow_control_en = qp->use_srq ? false : true;
1308 qp->stats_queue = in_params->stats_queue;
1309
1310 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
1311 rc = qed_iwarp_create_qp(p_hwfn, qp, out_params);
1312 qp->qpid = qp->icid;
1313 } else {
1314 rc = qed_roce_alloc_cid(p_hwfn, &qp->icid);
1315 qp->qpid = ((0xFF << 16) | qp->icid);
1316 }
1317
1318 if (rc) {
1319 kfree(qp);
1320 return NULL;
1321 }
1322
1323 out_params->icid = qp->icid;
1324 out_params->qp_id = qp->qpid;
1325
1326 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc);
1327 return qp;
1328 }
1329
qed_rdma_modify_qp(void * rdma_cxt,struct qed_rdma_qp * qp,struct qed_rdma_modify_qp_in_params * params)1330 static int qed_rdma_modify_qp(void *rdma_cxt,
1331 struct qed_rdma_qp *qp,
1332 struct qed_rdma_modify_qp_in_params *params)
1333 {
1334 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1335 enum qed_roce_qp_state prev_state;
1336 int rc = 0;
1337
1338 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n",
1339 qp->icid, params->new_state);
1340
1341 if (rc) {
1342 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1343 return rc;
1344 }
1345
1346 if (GET_FIELD(params->modify_flags,
1347 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) {
1348 qp->incoming_rdma_read_en = params->incoming_rdma_read_en;
1349 qp->incoming_rdma_write_en = params->incoming_rdma_write_en;
1350 qp->incoming_atomic_en = params->incoming_atomic_en;
1351 }
1352
1353 /* Update QP structure with the updated values */
1354 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE))
1355 qp->roce_mode = params->roce_mode;
1356 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY))
1357 qp->pkey = params->pkey;
1358 if (GET_FIELD(params->modify_flags,
1359 QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN))
1360 qp->e2e_flow_control_en = params->e2e_flow_control_en;
1361 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP))
1362 qp->dest_qp = params->dest_qp;
1363 if (GET_FIELD(params->modify_flags,
1364 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) {
1365 /* Indicates that the following parameters have changed:
1366 * Traffic class, flow label, hop limit, source GID,
1367 * destination GID, loopback indicator
1368 */
1369 qp->traffic_class_tos = params->traffic_class_tos;
1370 qp->flow_label = params->flow_label;
1371 qp->hop_limit_ttl = params->hop_limit_ttl;
1372
1373 qp->sgid = params->sgid;
1374 qp->dgid = params->dgid;
1375 qp->udp_src_port = 0;
1376 qp->vlan_id = params->vlan_id;
1377 qp->mtu = params->mtu;
1378 qp->lb_indication = params->lb_indication;
1379 memcpy((u8 *)&qp->remote_mac_addr[0],
1380 (u8 *)¶ms->remote_mac_addr[0], ETH_ALEN);
1381 if (params->use_local_mac) {
1382 memcpy((u8 *)&qp->local_mac_addr[0],
1383 (u8 *)¶ms->local_mac_addr[0], ETH_ALEN);
1384 } else {
1385 memcpy((u8 *)&qp->local_mac_addr[0],
1386 (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN);
1387 }
1388 }
1389 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN))
1390 qp->rq_psn = params->rq_psn;
1391 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN))
1392 qp->sq_psn = params->sq_psn;
1393 if (GET_FIELD(params->modify_flags,
1394 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ))
1395 qp->max_rd_atomic_req = params->max_rd_atomic_req;
1396 if (GET_FIELD(params->modify_flags,
1397 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP))
1398 qp->max_rd_atomic_resp = params->max_rd_atomic_resp;
1399 if (GET_FIELD(params->modify_flags,
1400 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT))
1401 qp->ack_timeout = params->ack_timeout;
1402 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT))
1403 qp->retry_cnt = params->retry_cnt;
1404 if (GET_FIELD(params->modify_flags,
1405 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT))
1406 qp->rnr_retry_cnt = params->rnr_retry_cnt;
1407 if (GET_FIELD(params->modify_flags,
1408 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER))
1409 qp->min_rnr_nak_timer = params->min_rnr_nak_timer;
1410
1411 qp->sqd_async = params->sqd_async;
1412
1413 prev_state = qp->cur_state;
1414 if (GET_FIELD(params->modify_flags,
1415 QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) {
1416 qp->cur_state = params->new_state;
1417 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n",
1418 qp->cur_state);
1419 }
1420
1421 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
1422 enum qed_iwarp_qp_state new_state =
1423 qed_roce2iwarp_state(qp->cur_state);
1424
1425 rc = qed_iwarp_modify_qp(p_hwfn, qp, new_state, 0);
1426 } else {
1427 rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params);
1428 }
1429
1430 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc);
1431 return rc;
1432 }
1433
1434 static int
qed_rdma_register_tid(void * rdma_cxt,struct qed_rdma_register_tid_in_params * params)1435 qed_rdma_register_tid(void *rdma_cxt,
1436 struct qed_rdma_register_tid_in_params *params)
1437 {
1438 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1439 struct rdma_register_tid_ramrod_data *p_ramrod;
1440 struct qed_sp_init_data init_data;
1441 struct qed_spq_entry *p_ent;
1442 enum rdma_tid_type tid_type;
1443 u8 fw_return_code;
1444 int rc;
1445
1446 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid);
1447
1448 /* Get SPQ entry */
1449 memset(&init_data, 0, sizeof(init_data));
1450 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1451 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1452
1453 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR,
1454 p_hwfn->p_rdma_info->proto, &init_data);
1455 if (rc) {
1456 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1457 return rc;
1458 }
1459
1460 if (p_hwfn->p_rdma_info->last_tid < params->itid)
1461 p_hwfn->p_rdma_info->last_tid = params->itid;
1462
1463 p_ramrod = &p_ent->ramrod.rdma_register_tid;
1464
1465 p_ramrod->flags = 0;
1466 SET_FIELD(p_ramrod->flags,
1467 RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL,
1468 params->pbl_two_level);
1469
1470 SET_FIELD(p_ramrod->flags,
1471 RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, params->zbva);
1472
1473 SET_FIELD(p_ramrod->flags,
1474 RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr);
1475
1476 /* Don't initialize D/C field, as it may override other bits. */
1477 if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr))
1478 SET_FIELD(p_ramrod->flags,
1479 RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG,
1480 params->page_size_log - 12);
1481
1482 SET_FIELD(p_ramrod->flags,
1483 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ,
1484 params->remote_read);
1485
1486 SET_FIELD(p_ramrod->flags,
1487 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE,
1488 params->remote_write);
1489
1490 SET_FIELD(p_ramrod->flags,
1491 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC,
1492 params->remote_atomic);
1493
1494 SET_FIELD(p_ramrod->flags,
1495 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE,
1496 params->local_write);
1497
1498 SET_FIELD(p_ramrod->flags,
1499 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, params->local_read);
1500
1501 SET_FIELD(p_ramrod->flags,
1502 RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND,
1503 params->mw_bind);
1504
1505 SET_FIELD(p_ramrod->flags1,
1506 RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG,
1507 params->pbl_page_size_log - 12);
1508
1509 SET_FIELD(p_ramrod->flags2,
1510 RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, params->dma_mr);
1511
1512 switch (params->tid_type) {
1513 case QED_RDMA_TID_REGISTERED_MR:
1514 tid_type = RDMA_TID_REGISTERED_MR;
1515 break;
1516 case QED_RDMA_TID_FMR:
1517 tid_type = RDMA_TID_FMR;
1518 break;
1519 case QED_RDMA_TID_MW:
1520 tid_type = RDMA_TID_MW;
1521 break;
1522 default:
1523 rc = -EINVAL;
1524 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1525 qed_sp_destroy_request(p_hwfn, p_ent);
1526 return rc;
1527 }
1528 SET_FIELD(p_ramrod->flags1,
1529 RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, tid_type);
1530
1531 p_ramrod->itid = cpu_to_le32(params->itid);
1532 p_ramrod->key = params->key;
1533 p_ramrod->pd = cpu_to_le16(params->pd);
1534 p_ramrod->length_hi = (u8)(params->length >> 32);
1535 p_ramrod->length_lo = DMA_LO_LE(params->length);
1536 if (params->zbva) {
1537 /* Lower 32 bits of the registered MR address.
1538 * In case of zero based MR, will hold FBO
1539 */
1540 p_ramrod->va.hi = 0;
1541 p_ramrod->va.lo = cpu_to_le32(params->fbo);
1542 } else {
1543 DMA_REGPAIR_LE(p_ramrod->va, params->vaddr);
1544 }
1545 DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr);
1546
1547 /* DIF */
1548 if (params->dif_enabled) {
1549 SET_FIELD(p_ramrod->flags2,
1550 RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1);
1551 DMA_REGPAIR_LE(p_ramrod->dif_error_addr,
1552 params->dif_error_addr);
1553 }
1554
1555 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1556 if (rc)
1557 return rc;
1558
1559 if (fw_return_code != RDMA_RETURN_OK) {
1560 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
1561 return -EINVAL;
1562 }
1563
1564 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc);
1565 return rc;
1566 }
1567
qed_rdma_deregister_tid(void * rdma_cxt,u32 itid)1568 static int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid)
1569 {
1570 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1571 struct rdma_deregister_tid_ramrod_data *p_ramrod;
1572 struct qed_sp_init_data init_data;
1573 struct qed_spq_entry *p_ent;
1574 struct qed_ptt *p_ptt;
1575 u8 fw_return_code;
1576 int rc;
1577
1578 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid);
1579
1580 /* Get SPQ entry */
1581 memset(&init_data, 0, sizeof(init_data));
1582 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1583 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1584
1585 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR,
1586 p_hwfn->p_rdma_info->proto, &init_data);
1587 if (rc) {
1588 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1589 return rc;
1590 }
1591
1592 p_ramrod = &p_ent->ramrod.rdma_deregister_tid;
1593 p_ramrod->itid = cpu_to_le32(itid);
1594
1595 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1596 if (rc) {
1597 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1598 return rc;
1599 }
1600
1601 if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) {
1602 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
1603 return -EINVAL;
1604 } else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) {
1605 /* Bit indicating that the TID is in use and a nig drain is
1606 * required before sending the ramrod again
1607 */
1608 p_ptt = qed_ptt_acquire(p_hwfn);
1609 if (!p_ptt) {
1610 rc = -EBUSY;
1611 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1612 "Failed to acquire PTT\n");
1613 return rc;
1614 }
1615
1616 rc = qed_mcp_drain(p_hwfn, p_ptt);
1617 if (rc) {
1618 qed_ptt_release(p_hwfn, p_ptt);
1619 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1620 "Drain failed\n");
1621 return rc;
1622 }
1623
1624 qed_ptt_release(p_hwfn, p_ptt);
1625
1626 /* Resend the ramrod */
1627 rc = qed_sp_init_request(p_hwfn, &p_ent,
1628 RDMA_RAMROD_DEREGISTER_MR,
1629 p_hwfn->p_rdma_info->proto,
1630 &init_data);
1631 if (rc) {
1632 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1633 "Failed to init sp-element\n");
1634 return rc;
1635 }
1636
1637 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1638 if (rc) {
1639 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1640 "Ramrod failed\n");
1641 return rc;
1642 }
1643
1644 if (fw_return_code != RDMA_RETURN_OK) {
1645 DP_NOTICE(p_hwfn, "fw_return_code = %d\n",
1646 fw_return_code);
1647 return rc;
1648 }
1649 }
1650
1651 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc);
1652 return rc;
1653 }
1654
qed_rdma_get_rdma_ctx(struct qed_dev * cdev)1655 static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev)
1656 {
1657 return QED_AFFIN_HWFN(cdev);
1658 }
1659
qed_rdma_modify_srq(void * rdma_cxt,struct qed_rdma_modify_srq_in_params * in_params)1660 static int qed_rdma_modify_srq(void *rdma_cxt,
1661 struct qed_rdma_modify_srq_in_params *in_params)
1662 {
1663 struct rdma_srq_modify_ramrod_data *p_ramrod;
1664 struct qed_sp_init_data init_data = {};
1665 struct qed_hwfn *p_hwfn = rdma_cxt;
1666 struct qed_spq_entry *p_ent;
1667 u16 opaque_fid;
1668 int rc;
1669
1670 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1671 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1672
1673 rc = qed_sp_init_request(p_hwfn, &p_ent,
1674 RDMA_RAMROD_MODIFY_SRQ,
1675 p_hwfn->p_rdma_info->proto, &init_data);
1676 if (rc)
1677 return rc;
1678
1679 p_ramrod = &p_ent->ramrod.rdma_modify_srq;
1680 p_ramrod->srq_id.srq_idx = cpu_to_le16(in_params->srq_id);
1681 opaque_fid = p_hwfn->hw_info.opaque_fid;
1682 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid);
1683 p_ramrod->wqe_limit = cpu_to_le32(in_params->wqe_limit);
1684
1685 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1686 if (rc)
1687 return rc;
1688
1689 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "modified SRQ id = %x",
1690 in_params->srq_id);
1691
1692 return rc;
1693 }
1694
1695 static int
qed_rdma_destroy_srq(void * rdma_cxt,struct qed_rdma_destroy_srq_in_params * in_params)1696 qed_rdma_destroy_srq(void *rdma_cxt,
1697 struct qed_rdma_destroy_srq_in_params *in_params)
1698 {
1699 struct rdma_srq_destroy_ramrod_data *p_ramrod;
1700 struct qed_sp_init_data init_data = {};
1701 struct qed_hwfn *p_hwfn = rdma_cxt;
1702 struct qed_spq_entry *p_ent;
1703 struct qed_bmap *bmap;
1704 u16 opaque_fid;
1705 int rc;
1706
1707 opaque_fid = p_hwfn->hw_info.opaque_fid;
1708
1709 init_data.opaque_fid = opaque_fid;
1710 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1711
1712 rc = qed_sp_init_request(p_hwfn, &p_ent,
1713 RDMA_RAMROD_DESTROY_SRQ,
1714 p_hwfn->p_rdma_info->proto, &init_data);
1715 if (rc)
1716 return rc;
1717
1718 p_ramrod = &p_ent->ramrod.rdma_destroy_srq;
1719 p_ramrod->srq_id.srq_idx = cpu_to_le16(in_params->srq_id);
1720 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid);
1721
1722 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1723 if (rc)
1724 return rc;
1725
1726 bmap = &p_hwfn->p_rdma_info->srq_map;
1727
1728 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1729 qed_bmap_release_id(p_hwfn, bmap, in_params->srq_id);
1730 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1731
1732 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "SRQ destroyed Id = %x",
1733 in_params->srq_id);
1734
1735 return rc;
1736 }
1737
1738 static int
qed_rdma_create_srq(void * rdma_cxt,struct qed_rdma_create_srq_in_params * in_params,struct qed_rdma_create_srq_out_params * out_params)1739 qed_rdma_create_srq(void *rdma_cxt,
1740 struct qed_rdma_create_srq_in_params *in_params,
1741 struct qed_rdma_create_srq_out_params *out_params)
1742 {
1743 struct rdma_srq_create_ramrod_data *p_ramrod;
1744 struct qed_sp_init_data init_data = {};
1745 struct qed_hwfn *p_hwfn = rdma_cxt;
1746 enum qed_cxt_elem_type elem_type;
1747 struct qed_spq_entry *p_ent;
1748 u16 opaque_fid, srq_id;
1749 struct qed_bmap *bmap;
1750 u32 returned_id;
1751 int rc;
1752
1753 bmap = &p_hwfn->p_rdma_info->srq_map;
1754 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1755 rc = qed_rdma_bmap_alloc_id(p_hwfn, bmap, &returned_id);
1756 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1757
1758 if (rc) {
1759 DP_NOTICE(p_hwfn, "failed to allocate srq id\n");
1760 return rc;
1761 }
1762
1763 elem_type = QED_ELEM_SRQ;
1764 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, elem_type, returned_id);
1765 if (rc)
1766 goto err;
1767 /* returned id is no greater than u16 */
1768 srq_id = (u16)returned_id;
1769 opaque_fid = p_hwfn->hw_info.opaque_fid;
1770
1771 opaque_fid = p_hwfn->hw_info.opaque_fid;
1772 init_data.opaque_fid = opaque_fid;
1773 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1774
1775 rc = qed_sp_init_request(p_hwfn, &p_ent,
1776 RDMA_RAMROD_CREATE_SRQ,
1777 p_hwfn->p_rdma_info->proto, &init_data);
1778 if (rc)
1779 goto err;
1780
1781 p_ramrod = &p_ent->ramrod.rdma_create_srq;
1782 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, in_params->pbl_base_addr);
1783 p_ramrod->pages_in_srq_pbl = cpu_to_le16(in_params->num_pages);
1784 p_ramrod->pd_id = cpu_to_le16(in_params->pd_id);
1785 p_ramrod->srq_id.srq_idx = cpu_to_le16(srq_id);
1786 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid);
1787 p_ramrod->page_size = cpu_to_le16(in_params->page_size);
1788 DMA_REGPAIR_LE(p_ramrod->producers_addr, in_params->prod_pair_addr);
1789
1790 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1791 if (rc)
1792 goto err;
1793
1794 out_params->srq_id = srq_id;
1795
1796 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1797 "SRQ created Id = %x\n", out_params->srq_id);
1798
1799 return rc;
1800
1801 err:
1802 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1803 qed_bmap_release_id(p_hwfn, bmap, returned_id);
1804 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1805
1806 return rc;
1807 }
1808
qed_rdma_allocated_qps(struct qed_hwfn * p_hwfn)1809 bool qed_rdma_allocated_qps(struct qed_hwfn *p_hwfn)
1810 {
1811 bool result;
1812
1813 /* if rdma wasn't activated yet, naturally there are no qps */
1814 if (!p_hwfn->p_rdma_info->active)
1815 return false;
1816
1817 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1818 if (!p_hwfn->p_rdma_info->cid_map.bitmap)
1819 result = false;
1820 else
1821 result = !qed_bmap_is_empty(&p_hwfn->p_rdma_info->cid_map);
1822 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1823 return result;
1824 }
1825
qed_rdma_dpm_conf(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)1826 void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1827 {
1828 u32 val;
1829
1830 val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1;
1831
1832 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val);
1833 DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA),
1834 "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n",
1835 val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm);
1836 }
1837
1838
qed_rdma_dpm_bar(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)1839 void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1840 {
1841 p_hwfn->db_bar_no_edpm = true;
1842
1843 qed_rdma_dpm_conf(p_hwfn, p_ptt);
1844 }
1845
qed_rdma_start(void * rdma_cxt,struct qed_rdma_start_in_params * params)1846 static int qed_rdma_start(void *rdma_cxt,
1847 struct qed_rdma_start_in_params *params)
1848 {
1849 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1850 struct qed_ptt *p_ptt;
1851 int rc = -EBUSY;
1852
1853 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1854 "desired_cnq = %08x\n", params->desired_cnq);
1855
1856 p_ptt = qed_ptt_acquire(p_hwfn);
1857 if (!p_ptt)
1858 goto err;
1859
1860 rc = qed_rdma_alloc(p_hwfn);
1861 if (rc)
1862 goto err1;
1863
1864 rc = qed_rdma_setup(p_hwfn, p_ptt, params);
1865 if (rc)
1866 goto err2;
1867
1868 qed_ptt_release(p_hwfn, p_ptt);
1869 p_hwfn->p_rdma_info->active = 1;
1870
1871 return rc;
1872
1873 err2:
1874 qed_rdma_free(p_hwfn);
1875 err1:
1876 qed_ptt_release(p_hwfn, p_ptt);
1877 err:
1878 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc);
1879 return rc;
1880 }
1881
qed_rdma_init(struct qed_dev * cdev,struct qed_rdma_start_in_params * params)1882 static int qed_rdma_init(struct qed_dev *cdev,
1883 struct qed_rdma_start_in_params *params)
1884 {
1885 return qed_rdma_start(QED_AFFIN_HWFN(cdev), params);
1886 }
1887
qed_rdma_remove_user(void * rdma_cxt,u16 dpi)1888 static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi)
1889 {
1890 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1891
1892 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi);
1893
1894 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1895 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi);
1896 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1897 }
1898
qed_roce_ll2_set_mac_filter(struct qed_dev * cdev,u8 * old_mac_address,u8 * new_mac_address)1899 static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev,
1900 u8 *old_mac_address,
1901 u8 *new_mac_address)
1902 {
1903 int rc = 0;
1904
1905 if (old_mac_address)
1906 qed_llh_remove_mac_filter(cdev, 0, old_mac_address);
1907 if (new_mac_address)
1908 rc = qed_llh_add_mac_filter(cdev, 0, new_mac_address);
1909
1910 if (rc)
1911 DP_ERR(cdev,
1912 "qed roce ll2 mac filter set: failed to add MAC filter\n");
1913
1914 return rc;
1915 }
1916
qed_iwarp_set_engine_affin(struct qed_dev * cdev,bool b_reset)1917 static int qed_iwarp_set_engine_affin(struct qed_dev *cdev, bool b_reset)
1918 {
1919 enum qed_eng eng;
1920 u8 ppfid = 0;
1921 int rc;
1922
1923 /* Make sure iwarp cmt mode is enabled before setting affinity */
1924 if (!cdev->iwarp_cmt)
1925 return -EINVAL;
1926
1927 if (b_reset)
1928 eng = QED_BOTH_ENG;
1929 else
1930 eng = cdev->l2_affin_hint ? QED_ENG1 : QED_ENG0;
1931
1932 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng);
1933 if (rc) {
1934 DP_NOTICE(cdev,
1935 "Failed to set the engine affinity of ppfid %d\n",
1936 ppfid);
1937 return rc;
1938 }
1939
1940 DP_VERBOSE(cdev, (QED_MSG_RDMA | QED_MSG_SP),
1941 "LLH: Set the engine affinity of non-RoCE packets as %d\n",
1942 eng);
1943
1944 return 0;
1945 }
1946
1947 static const struct qed_rdma_ops qed_rdma_ops_pass = {
1948 .common = &qed_common_ops_pass,
1949 .fill_dev_info = &qed_fill_rdma_dev_info,
1950 .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx,
1951 .rdma_init = &qed_rdma_init,
1952 .rdma_add_user = &qed_rdma_add_user,
1953 .rdma_remove_user = &qed_rdma_remove_user,
1954 .rdma_stop = &qed_rdma_stop,
1955 .rdma_query_port = &qed_rdma_query_port,
1956 .rdma_query_device = &qed_rdma_query_device,
1957 .rdma_get_start_sb = &qed_rdma_get_sb_start,
1958 .rdma_get_rdma_int = &qed_rdma_get_int,
1959 .rdma_set_rdma_int = &qed_rdma_set_int,
1960 .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix,
1961 .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update,
1962 .rdma_alloc_pd = &qed_rdma_alloc_pd,
1963 .rdma_dealloc_pd = &qed_rdma_free_pd,
1964 .rdma_create_cq = &qed_rdma_create_cq,
1965 .rdma_destroy_cq = &qed_rdma_destroy_cq,
1966 .rdma_create_qp = &qed_rdma_create_qp,
1967 .rdma_modify_qp = &qed_rdma_modify_qp,
1968 .rdma_query_qp = &qed_rdma_query_qp,
1969 .rdma_destroy_qp = &qed_rdma_destroy_qp,
1970 .rdma_alloc_tid = &qed_rdma_alloc_tid,
1971 .rdma_free_tid = &qed_rdma_free_tid,
1972 .rdma_register_tid = &qed_rdma_register_tid,
1973 .rdma_deregister_tid = &qed_rdma_deregister_tid,
1974 .rdma_create_srq = &qed_rdma_create_srq,
1975 .rdma_modify_srq = &qed_rdma_modify_srq,
1976 .rdma_destroy_srq = &qed_rdma_destroy_srq,
1977 .ll2_acquire_connection = &qed_ll2_acquire_connection,
1978 .ll2_establish_connection = &qed_ll2_establish_connection,
1979 .ll2_terminate_connection = &qed_ll2_terminate_connection,
1980 .ll2_release_connection = &qed_ll2_release_connection,
1981 .ll2_post_rx_buffer = &qed_ll2_post_rx_buffer,
1982 .ll2_prepare_tx_packet = &qed_ll2_prepare_tx_packet,
1983 .ll2_set_fragment_of_tx_packet = &qed_ll2_set_fragment_of_tx_packet,
1984 .ll2_set_mac_filter = &qed_roce_ll2_set_mac_filter,
1985 .ll2_get_stats = &qed_ll2_get_stats,
1986 .iwarp_set_engine_affin = &qed_iwarp_set_engine_affin,
1987 .iwarp_connect = &qed_iwarp_connect,
1988 .iwarp_create_listen = &qed_iwarp_create_listen,
1989 .iwarp_destroy_listen = &qed_iwarp_destroy_listen,
1990 .iwarp_accept = &qed_iwarp_accept,
1991 .iwarp_reject = &qed_iwarp_reject,
1992 .iwarp_send_rtr = &qed_iwarp_send_rtr,
1993 };
1994
qed_get_rdma_ops(void)1995 const struct qed_rdma_ops *qed_get_rdma_ops(void)
1996 {
1997 return &qed_rdma_ops_pass;
1998 }
1999 EXPORT_SYMBOL(qed_get_rdma_ops);
2000
