1 /*
2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
3 * which contain:
4 *
5 * Author: Nicolas Pitre
6 * Created: Dec 02, 2004
7 * Copyright: MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/of_gpio.h>
23
24 #include <sound/pxa2xx-lib.h>
25
26 #include <mach/irqs.h>
27 #include <mach/regs-ac97.h>
28 #include <mach/audio.h>
29
30 static DEFINE_MUTEX(car_mutex);
31 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
32 static volatile long gsr_bits;
33 static struct clk *ac97_clk;
34 static struct clk *ac97conf_clk;
35 static int reset_gpio;
36
37 extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
38
39 /*
40 * Beware PXA27x bugs:
41 *
42 * o Slot 12 read from modem space will hang controller.
43 * o CDONE, SDONE interrupt fails after any slot 12 IO.
44 *
45 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
46 * 1 jiffy timeout if interrupt never comes).
47 */
48
pxa2xx_ac97_read(int slot,unsigned short reg)49 int pxa2xx_ac97_read(int slot, unsigned short reg)
50 {
51 int val = -ENODEV;
52 volatile u32 *reg_addr;
53
54 if (slot > 0)
55 return -ENODEV;
56
57 mutex_lock(&car_mutex);
58
59 /* set up primary or secondary codec space */
60 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
61 reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
62 else
63 reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
64 reg_addr += (reg >> 1);
65
66 /* start read access across the ac97 link */
67 GSR = GSR_CDONE | GSR_SDONE;
68 gsr_bits = 0;
69 val = (*reg_addr & 0xffff);
70 if (reg == AC97_GPIO_STATUS)
71 goto out;
72 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
73 !((GSR | gsr_bits) & GSR_SDONE)) {
74 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
75 __func__, reg, GSR | gsr_bits);
76 val = -ETIMEDOUT;
77 goto out;
78 }
79
80 /* valid data now */
81 GSR = GSR_CDONE | GSR_SDONE;
82 gsr_bits = 0;
83 val = (*reg_addr & 0xffff);
84 /* but we've just started another cycle... */
85 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
86
87 out: mutex_unlock(&car_mutex);
88 return val;
89 }
90 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
91
pxa2xx_ac97_write(int slot,unsigned short reg,unsigned short val)92 int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
93 {
94 volatile u32 *reg_addr;
95 int ret = 0;
96
97 mutex_lock(&car_mutex);
98
99 /* set up primary or secondary codec space */
100 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
101 reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
102 else
103 reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
104 reg_addr += (reg >> 1);
105
106 GSR = GSR_CDONE | GSR_SDONE;
107 gsr_bits = 0;
108 *reg_addr = val;
109 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
110 !((GSR | gsr_bits) & GSR_CDONE)) {
111 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
112 __func__, reg, GSR | gsr_bits);
113 ret = -EIO;
114 }
115
116 mutex_unlock(&car_mutex);
117 return ret;
118 }
119 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
120
121 #ifdef CONFIG_PXA25x
pxa_ac97_warm_pxa25x(void)122 static inline void pxa_ac97_warm_pxa25x(void)
123 {
124 gsr_bits = 0;
125
126 GCR |= GCR_WARM_RST;
127 }
128
pxa_ac97_cold_pxa25x(void)129 static inline void pxa_ac97_cold_pxa25x(void)
130 {
131 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
132 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
133
134 gsr_bits = 0;
135
136 GCR = GCR_COLD_RST;
137 }
138 #endif
139
140 #ifdef CONFIG_PXA27x
pxa_ac97_warm_pxa27x(void)141 static inline void pxa_ac97_warm_pxa27x(void)
142 {
143 gsr_bits = 0;
144
145 /* warm reset broken on Bulverde, so manually keep AC97 reset high */
146 pxa27x_configure_ac97reset(reset_gpio, true);
147 udelay(10);
148 GCR |= GCR_WARM_RST;
149 pxa27x_configure_ac97reset(reset_gpio, false);
150 udelay(500);
151 }
152
pxa_ac97_cold_pxa27x(void)153 static inline void pxa_ac97_cold_pxa27x(void)
154 {
155 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
156 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
157
158 gsr_bits = 0;
159
160 /* PXA27x Developers Manual section 13.5.2.2.1 */
161 clk_prepare_enable(ac97conf_clk);
162 udelay(5);
163 clk_disable_unprepare(ac97conf_clk);
164 GCR = GCR_COLD_RST | GCR_WARM_RST;
165 }
166 #endif
167
168 #ifdef CONFIG_PXA3xx
pxa_ac97_warm_pxa3xx(void)169 static inline void pxa_ac97_warm_pxa3xx(void)
170 {
171 gsr_bits = 0;
172
173 /* Can't use interrupts */
174 GCR |= GCR_WARM_RST;
175 }
176
pxa_ac97_cold_pxa3xx(void)177 static inline void pxa_ac97_cold_pxa3xx(void)
178 {
179 /* Hold CLKBPB for 100us */
180 GCR = 0;
181 GCR = GCR_CLKBPB;
182 udelay(100);
183 GCR = 0;
184
185 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
186 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
187
188 gsr_bits = 0;
189
190 /* Can't use interrupts on PXA3xx */
191 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
192
193 GCR = GCR_WARM_RST | GCR_COLD_RST;
194 }
195 #endif
196
pxa2xx_ac97_try_warm_reset(void)197 bool pxa2xx_ac97_try_warm_reset(void)
198 {
199 unsigned long gsr;
200 unsigned int timeout = 100;
201
202 #ifdef CONFIG_PXA25x
203 if (cpu_is_pxa25x())
204 pxa_ac97_warm_pxa25x();
205 else
206 #endif
207 #ifdef CONFIG_PXA27x
208 if (cpu_is_pxa27x())
209 pxa_ac97_warm_pxa27x();
210 else
211 #endif
212 #ifdef CONFIG_PXA3xx
213 if (cpu_is_pxa3xx())
214 pxa_ac97_warm_pxa3xx();
215 else
216 #endif
217 snd_BUG();
218
219 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
220 mdelay(1);
221
222 gsr = GSR | gsr_bits;
223 if (!(gsr & (GSR_PCR | GSR_SCR))) {
224 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
225 __func__, gsr);
226
227 return false;
228 }
229
230 return true;
231 }
232 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
233
pxa2xx_ac97_try_cold_reset(void)234 bool pxa2xx_ac97_try_cold_reset(void)
235 {
236 unsigned long gsr;
237 unsigned int timeout = 1000;
238
239 #ifdef CONFIG_PXA25x
240 if (cpu_is_pxa25x())
241 pxa_ac97_cold_pxa25x();
242 else
243 #endif
244 #ifdef CONFIG_PXA27x
245 if (cpu_is_pxa27x())
246 pxa_ac97_cold_pxa27x();
247 else
248 #endif
249 #ifdef CONFIG_PXA3xx
250 if (cpu_is_pxa3xx())
251 pxa_ac97_cold_pxa3xx();
252 else
253 #endif
254 snd_BUG();
255
256 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
257 mdelay(1);
258
259 gsr = GSR | gsr_bits;
260 if (!(gsr & (GSR_PCR | GSR_SCR))) {
261 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
262 __func__, gsr);
263
264 return false;
265 }
266
267 return true;
268 }
269 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
270
271
pxa2xx_ac97_finish_reset(void)272 void pxa2xx_ac97_finish_reset(void)
273 {
274 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
275 GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
276 }
277 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
278
pxa2xx_ac97_irq(int irq,void * dev_id)279 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
280 {
281 long status;
282
283 status = GSR;
284 if (status) {
285 GSR = status;
286 gsr_bits |= status;
287 wake_up(&gsr_wq);
288
289 /* Although we don't use those we still need to clear them
290 since they tend to spuriously trigger when MMC is used
291 (hardware bug? go figure)... */
292 if (cpu_is_pxa27x()) {
293 MISR = MISR_EOC;
294 PISR = PISR_EOC;
295 MCSR = MCSR_EOC;
296 }
297
298 return IRQ_HANDLED;
299 }
300
301 return IRQ_NONE;
302 }
303
304 #ifdef CONFIG_PM
pxa2xx_ac97_hw_suspend(void)305 int pxa2xx_ac97_hw_suspend(void)
306 {
307 GCR |= GCR_ACLINK_OFF;
308 clk_disable_unprepare(ac97_clk);
309 return 0;
310 }
311 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
312
pxa2xx_ac97_hw_resume(void)313 int pxa2xx_ac97_hw_resume(void)
314 {
315 clk_prepare_enable(ac97_clk);
316 return 0;
317 }
318 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
319 #endif
320
pxa2xx_ac97_hw_probe(struct platform_device * dev)321 int pxa2xx_ac97_hw_probe(struct platform_device *dev)
322 {
323 int ret;
324 pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
325
326 if (pdata) {
327 switch (pdata->reset_gpio) {
328 case 95:
329 case 113:
330 reset_gpio = pdata->reset_gpio;
331 break;
332 case 0:
333 reset_gpio = 113;
334 break;
335 case -1:
336 break;
337 default:
338 dev_err(&dev->dev, "Invalid reset GPIO %d\n",
339 pdata->reset_gpio);
340 }
341 } else if (!pdata && dev->dev.of_node) {
342 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
343 if (!pdata)
344 return -ENOMEM;
345 pdata->reset_gpio = of_get_named_gpio(dev->dev.of_node,
346 "reset-gpios", 0);
347 if (pdata->reset_gpio == -ENOENT)
348 pdata->reset_gpio = -1;
349 else if (pdata->reset_gpio < 0)
350 return pdata->reset_gpio;
351 reset_gpio = pdata->reset_gpio;
352 } else {
353 if (cpu_is_pxa27x())
354 reset_gpio = 113;
355 }
356
357 if (cpu_is_pxa27x()) {
358 /*
359 * This gpio is needed for a work-around to a bug in the ac97
360 * controller during warm reset. The direction and level is set
361 * here so that it is an output driven high when switching from
362 * AC97_nRESET alt function to generic gpio.
363 */
364 ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
365 "pxa27x ac97 reset");
366 if (ret < 0) {
367 pr_err("%s: gpio_request_one() failed: %d\n",
368 __func__, ret);
369 goto err_conf;
370 }
371 pxa27x_configure_ac97reset(reset_gpio, false);
372
373 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
374 if (IS_ERR(ac97conf_clk)) {
375 ret = PTR_ERR(ac97conf_clk);
376 ac97conf_clk = NULL;
377 goto err_conf;
378 }
379 }
380
381 ac97_clk = clk_get(&dev->dev, "AC97CLK");
382 if (IS_ERR(ac97_clk)) {
383 ret = PTR_ERR(ac97_clk);
384 ac97_clk = NULL;
385 goto err_clk;
386 }
387
388 ret = clk_prepare_enable(ac97_clk);
389 if (ret)
390 goto err_clk2;
391
392 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
393 if (ret < 0)
394 goto err_irq;
395
396 return 0;
397
398 err_irq:
399 GCR |= GCR_ACLINK_OFF;
400 err_clk2:
401 clk_put(ac97_clk);
402 ac97_clk = NULL;
403 err_clk:
404 if (ac97conf_clk) {
405 clk_put(ac97conf_clk);
406 ac97conf_clk = NULL;
407 }
408 err_conf:
409 return ret;
410 }
411 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
412
pxa2xx_ac97_hw_remove(struct platform_device * dev)413 void pxa2xx_ac97_hw_remove(struct platform_device *dev)
414 {
415 if (cpu_is_pxa27x())
416 gpio_free(reset_gpio);
417 GCR |= GCR_ACLINK_OFF;
418 free_irq(IRQ_AC97, NULL);
419 if (ac97conf_clk) {
420 clk_put(ac97conf_clk);
421 ac97conf_clk = NULL;
422 }
423 clk_disable_unprepare(ac97_clk);
424 clk_put(ac97_clk);
425 ac97_clk = NULL;
426 }
427 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
428
429 MODULE_AUTHOR("Nicolas Pitre");
430 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
431 MODULE_LICENSE("GPL");
432
433
