1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6 * Jeffy Chen <jeffy.chen@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10
11 #include "hantro.h"
12 #include "hantro_jpeg.h"
13 #include "hantro_g1_regs.h"
14 #include "hantro_h1_regs.h"
15 #include "rockchip_vpu2_regs.h"
16
17 #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
18 #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
19
20 /*
21 * Supported formats.
22 */
23
24 static const struct hantro_fmt rockchip_vpu_enc_fmts[] = {
25 {
26 .fourcc = V4L2_PIX_FMT_YUV420M,
27 .codec_mode = HANTRO_MODE_NONE,
28 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
29 },
30 {
31 .fourcc = V4L2_PIX_FMT_NV12M,
32 .codec_mode = HANTRO_MODE_NONE,
33 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
34 },
35 {
36 .fourcc = V4L2_PIX_FMT_YUYV,
37 .codec_mode = HANTRO_MODE_NONE,
38 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
39 },
40 {
41 .fourcc = V4L2_PIX_FMT_UYVY,
42 .codec_mode = HANTRO_MODE_NONE,
43 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
44 },
45 {
46 .fourcc = V4L2_PIX_FMT_JPEG,
47 .codec_mode = HANTRO_MODE_JPEG_ENC,
48 .max_depth = 2,
49 .header_size = JPEG_HEADER_SIZE,
50 .frmsize = {
51 .min_width = 96,
52 .max_width = 8192,
53 .step_width = MB_DIM,
54 .min_height = 32,
55 .max_height = 8192,
56 .step_height = MB_DIM,
57 },
58 },
59 };
60
61 static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
62 {
63 .fourcc = V4L2_PIX_FMT_YUYV,
64 .codec_mode = HANTRO_MODE_NONE,
65 },
66 };
67
68 static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {
69 {
70 .fourcc = V4L2_PIX_FMT_NV12,
71 .codec_mode = HANTRO_MODE_NONE,
72 },
73 {
74 .fourcc = V4L2_PIX_FMT_H264_SLICE,
75 .codec_mode = HANTRO_MODE_H264_DEC,
76 .max_depth = 2,
77 .frmsize = {
78 .min_width = 48,
79 .max_width = 1920,
80 .step_width = MB_DIM,
81 .min_height = 48,
82 .max_height = 1088,
83 .step_height = MB_DIM,
84 },
85 },
86 {
87 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
88 .codec_mode = HANTRO_MODE_MPEG2_DEC,
89 .max_depth = 2,
90 .frmsize = {
91 .min_width = 48,
92 .max_width = 1920,
93 .step_width = MB_DIM,
94 .min_height = 48,
95 .max_height = 1088,
96 .step_height = MB_DIM,
97 },
98 },
99 {
100 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
101 .codec_mode = HANTRO_MODE_VP8_DEC,
102 .max_depth = 2,
103 .frmsize = {
104 .min_width = 48,
105 .max_width = 1920,
106 .step_width = MB_DIM,
107 .min_height = 48,
108 .max_height = 1088,
109 .step_height = MB_DIM,
110 },
111 },
112 };
113
114 static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
115 {
116 .fourcc = V4L2_PIX_FMT_NV12,
117 .codec_mode = HANTRO_MODE_NONE,
118 },
119 {
120 .fourcc = V4L2_PIX_FMT_H264_SLICE,
121 .codec_mode = HANTRO_MODE_H264_DEC,
122 .max_depth = 2,
123 .frmsize = {
124 .min_width = 48,
125 .max_width = 4096,
126 .step_width = MB_DIM,
127 .min_height = 48,
128 .max_height = 2304,
129 .step_height = MB_DIM,
130 },
131 },
132 {
133 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
134 .codec_mode = HANTRO_MODE_MPEG2_DEC,
135 .max_depth = 2,
136 .frmsize = {
137 .min_width = 48,
138 .max_width = 1920,
139 .step_width = MB_DIM,
140 .min_height = 48,
141 .max_height = 1088,
142 .step_height = MB_DIM,
143 },
144 },
145 {
146 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
147 .codec_mode = HANTRO_MODE_VP8_DEC,
148 .max_depth = 2,
149 .frmsize = {
150 .min_width = 48,
151 .max_width = 3840,
152 .step_width = MB_DIM,
153 .min_height = 48,
154 .max_height = 2160,
155 .step_height = MB_DIM,
156 },
157 },
158 };
159
160 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
161 {
162 .fourcc = V4L2_PIX_FMT_NV12,
163 .codec_mode = HANTRO_MODE_NONE,
164 },
165 {
166 .fourcc = V4L2_PIX_FMT_H264_SLICE,
167 .codec_mode = HANTRO_MODE_H264_DEC,
168 .max_depth = 2,
169 .frmsize = {
170 .min_width = 48,
171 .max_width = 1920,
172 .step_width = MB_DIM,
173 .min_height = 48,
174 .max_height = 1088,
175 .step_height = MB_DIM,
176 },
177 },
178 {
179 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
180 .codec_mode = HANTRO_MODE_MPEG2_DEC,
181 .max_depth = 2,
182 .frmsize = {
183 .min_width = 48,
184 .max_width = 1920,
185 .step_width = MB_DIM,
186 .min_height = 48,
187 .max_height = 1088,
188 .step_height = MB_DIM,
189 },
190 },
191 {
192 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
193 .codec_mode = HANTRO_MODE_VP8_DEC,
194 .max_depth = 2,
195 .frmsize = {
196 .min_width = 48,
197 .max_width = 3840,
198 .step_width = MB_DIM,
199 .min_height = 48,
200 .max_height = 2160,
201 .step_height = MB_DIM,
202 },
203 },
204 };
205
rockchip_vpu1_vepu_irq(int irq,void * dev_id)206 static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
207 {
208 struct hantro_dev *vpu = dev_id;
209 enum vb2_buffer_state state;
210 u32 status;
211
212 status = vepu_read(vpu, H1_REG_INTERRUPT);
213 state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
214 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
215
216 vepu_write(vpu, 0, H1_REG_INTERRUPT);
217 vepu_write(vpu, 0, H1_REG_AXI_CTRL);
218
219 hantro_irq_done(vpu, state);
220
221 return IRQ_HANDLED;
222 }
223
rockchip_vpu2_vdpu_irq(int irq,void * dev_id)224 static irqreturn_t rockchip_vpu2_vdpu_irq(int irq, void *dev_id)
225 {
226 struct hantro_dev *vpu = dev_id;
227 enum vb2_buffer_state state;
228 u32 status;
229
230 status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
231 state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
232 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
233
234 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
235 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
236
237 hantro_irq_done(vpu, state);
238
239 return IRQ_HANDLED;
240 }
241
rockchip_vpu2_vepu_irq(int irq,void * dev_id)242 static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id)
243 {
244 struct hantro_dev *vpu = dev_id;
245 enum vb2_buffer_state state;
246 u32 status;
247
248 status = vepu_read(vpu, VEPU_REG_INTERRUPT);
249 state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
250 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
251
252 vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
253 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
254
255 hantro_irq_done(vpu, state);
256
257 return IRQ_HANDLED;
258 }
259
rk3036_vpu_hw_init(struct hantro_dev * vpu)260 static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
261 {
262 /* Bump ACLK to max. possible freq. to improve performance. */
263 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
264 return 0;
265 }
266
rk3066_vpu_hw_init(struct hantro_dev * vpu)267 static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
268 {
269 /* Bump ACLKs to max. possible freq. to improve performance. */
270 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
271 clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);
272 return 0;
273 }
274
rockchip_vpu_hw_init(struct hantro_dev * vpu)275 static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
276 {
277 /* Bump ACLK to max. possible freq. to improve performance. */
278 clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
279 return 0;
280 }
281
rk3066_vpu_dec_reset(struct hantro_ctx * ctx)282 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
283 {
284 struct hantro_dev *vpu = ctx->dev;
285
286 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
287 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
288 }
289
rockchip_vpu1_enc_reset(struct hantro_ctx * ctx)290 static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx)
291 {
292 struct hantro_dev *vpu = ctx->dev;
293
294 vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
295 vepu_write(vpu, 0, H1_REG_ENC_CTRL);
296 vepu_write(vpu, 0, H1_REG_AXI_CTRL);
297 }
298
rockchip_vpu2_dec_reset(struct hantro_ctx * ctx)299 static void rockchip_vpu2_dec_reset(struct hantro_ctx *ctx)
300 {
301 struct hantro_dev *vpu = ctx->dev;
302
303 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
304 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
305 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
306 }
307
rockchip_vpu2_enc_reset(struct hantro_ctx * ctx)308 static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx)
309 {
310 struct hantro_dev *vpu = ctx->dev;
311
312 vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
313 vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
314 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
315 }
316
317 /*
318 * Supported codec ops.
319 */
320 static const struct hantro_codec_ops rk3036_vpu_codec_ops[] = {
321 [HANTRO_MODE_H264_DEC] = {
322 .run = hantro_g1_h264_dec_run,
323 .reset = hantro_g1_reset,
324 .init = hantro_h264_dec_init,
325 .exit = hantro_h264_dec_exit,
326 },
327 [HANTRO_MODE_MPEG2_DEC] = {
328 .run = hantro_g1_mpeg2_dec_run,
329 .reset = hantro_g1_reset,
330 .init = hantro_mpeg2_dec_init,
331 .exit = hantro_mpeg2_dec_exit,
332 },
333 [HANTRO_MODE_VP8_DEC] = {
334 .run = hantro_g1_vp8_dec_run,
335 .reset = hantro_g1_reset,
336 .init = hantro_vp8_dec_init,
337 .exit = hantro_vp8_dec_exit,
338 },
339 };
340
341 static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = {
342 [HANTRO_MODE_JPEG_ENC] = {
343 .run = hantro_h1_jpeg_enc_run,
344 .reset = rockchip_vpu1_enc_reset,
345 .init = hantro_jpeg_enc_init,
346 .done = hantro_jpeg_enc_done,
347 .exit = hantro_jpeg_enc_exit,
348 },
349 [HANTRO_MODE_H264_DEC] = {
350 .run = hantro_g1_h264_dec_run,
351 .reset = rk3066_vpu_dec_reset,
352 .init = hantro_h264_dec_init,
353 .exit = hantro_h264_dec_exit,
354 },
355 [HANTRO_MODE_MPEG2_DEC] = {
356 .run = hantro_g1_mpeg2_dec_run,
357 .reset = rk3066_vpu_dec_reset,
358 .init = hantro_mpeg2_dec_init,
359 .exit = hantro_mpeg2_dec_exit,
360 },
361 [HANTRO_MODE_VP8_DEC] = {
362 .run = hantro_g1_vp8_dec_run,
363 .reset = rk3066_vpu_dec_reset,
364 .init = hantro_vp8_dec_init,
365 .exit = hantro_vp8_dec_exit,
366 },
367 };
368
369 static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
370 [HANTRO_MODE_JPEG_ENC] = {
371 .run = hantro_h1_jpeg_enc_run,
372 .reset = rockchip_vpu1_enc_reset,
373 .init = hantro_jpeg_enc_init,
374 .done = hantro_jpeg_enc_done,
375 .exit = hantro_jpeg_enc_exit,
376 },
377 [HANTRO_MODE_H264_DEC] = {
378 .run = hantro_g1_h264_dec_run,
379 .reset = hantro_g1_reset,
380 .init = hantro_h264_dec_init,
381 .exit = hantro_h264_dec_exit,
382 },
383 [HANTRO_MODE_MPEG2_DEC] = {
384 .run = hantro_g1_mpeg2_dec_run,
385 .reset = hantro_g1_reset,
386 .init = hantro_mpeg2_dec_init,
387 .exit = hantro_mpeg2_dec_exit,
388 },
389 [HANTRO_MODE_VP8_DEC] = {
390 .run = hantro_g1_vp8_dec_run,
391 .reset = hantro_g1_reset,
392 .init = hantro_vp8_dec_init,
393 .exit = hantro_vp8_dec_exit,
394 },
395 };
396
397 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
398 [HANTRO_MODE_JPEG_ENC] = {
399 .run = rockchip_vpu2_jpeg_enc_run,
400 .reset = rockchip_vpu2_enc_reset,
401 .init = hantro_jpeg_enc_init,
402 .exit = hantro_jpeg_enc_exit,
403 },
404 [HANTRO_MODE_H264_DEC] = {
405 .run = rockchip_vpu2_h264_dec_run,
406 .reset = rockchip_vpu2_dec_reset,
407 .init = hantro_h264_dec_init,
408 .exit = hantro_h264_dec_exit,
409 },
410 [HANTRO_MODE_MPEG2_DEC] = {
411 .run = rockchip_vpu2_mpeg2_dec_run,
412 .reset = rockchip_vpu2_dec_reset,
413 .init = hantro_mpeg2_dec_init,
414 .exit = hantro_mpeg2_dec_exit,
415 },
416 [HANTRO_MODE_VP8_DEC] = {
417 .run = rockchip_vpu2_vp8_dec_run,
418 .reset = rockchip_vpu2_dec_reset,
419 .init = hantro_vp8_dec_init,
420 .exit = hantro_vp8_dec_exit,
421 },
422 };
423
424 /*
425 * VPU variant.
426 */
427
428 static const struct hantro_irq rockchip_vdpu1_irqs[] = {
429 { "vdpu", hantro_g1_irq },
430 };
431
432 static const struct hantro_irq rockchip_vpu1_irqs[] = {
433 { "vepu", rockchip_vpu1_vepu_irq },
434 { "vdpu", hantro_g1_irq },
435 };
436
437 static const struct hantro_irq rockchip_vdpu2_irqs[] = {
438 { "vdpu", rockchip_vpu2_vdpu_irq },
439 };
440
441 static const struct hantro_irq rockchip_vpu2_irqs[] = {
442 { "vepu", rockchip_vpu2_vepu_irq },
443 { "vdpu", rockchip_vpu2_vdpu_irq },
444 };
445
446 static const char * const rk3066_vpu_clk_names[] = {
447 "aclk_vdpu", "hclk_vdpu",
448 "aclk_vepu", "hclk_vepu"
449 };
450
451 static const char * const rockchip_vpu_clk_names[] = {
452 "aclk", "hclk"
453 };
454
455 /* VDPU1/VEPU1 */
456
457 const struct hantro_variant rk3036_vpu_variant = {
458 .dec_offset = 0x400,
459 .dec_fmts = rk3066_vpu_dec_fmts,
460 .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
461 .postproc_fmts = rockchip_vpu1_postproc_fmts,
462 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
463 .postproc_regs = &hantro_g1_postproc_regs,
464 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
465 HANTRO_H264_DECODER,
466 .codec_ops = rk3036_vpu_codec_ops,
467 .irqs = rockchip_vdpu1_irqs,
468 .num_irqs = ARRAY_SIZE(rockchip_vdpu1_irqs),
469 .init = rk3036_vpu_hw_init,
470 .clk_names = rockchip_vpu_clk_names,
471 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
472 };
473
474 /*
475 * Despite this variant has separate clocks for decoder and encoder,
476 * it's still required to enable all four of them for either decoding
477 * or encoding and we can't split it in separate g1/h1 variants.
478 */
479 const struct hantro_variant rk3066_vpu_variant = {
480 .enc_offset = 0x0,
481 .enc_fmts = rockchip_vpu_enc_fmts,
482 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
483 .dec_offset = 0x400,
484 .dec_fmts = rk3066_vpu_dec_fmts,
485 .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
486 .postproc_fmts = rockchip_vpu1_postproc_fmts,
487 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
488 .postproc_regs = &hantro_g1_postproc_regs,
489 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
490 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
491 .codec_ops = rk3066_vpu_codec_ops,
492 .irqs = rockchip_vpu1_irqs,
493 .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
494 .init = rk3066_vpu_hw_init,
495 .clk_names = rk3066_vpu_clk_names,
496 .num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names)
497 };
498
499 const struct hantro_variant rk3288_vpu_variant = {
500 .enc_offset = 0x0,
501 .enc_fmts = rockchip_vpu_enc_fmts,
502 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
503 .dec_offset = 0x400,
504 .dec_fmts = rk3288_vpu_dec_fmts,
505 .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
506 .postproc_fmts = rockchip_vpu1_postproc_fmts,
507 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
508 .postproc_regs = &hantro_g1_postproc_regs,
509 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
510 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
511 .codec_ops = rk3288_vpu_codec_ops,
512 .irqs = rockchip_vpu1_irqs,
513 .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
514 .init = rockchip_vpu_hw_init,
515 .clk_names = rockchip_vpu_clk_names,
516 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
517 };
518
519 /* VDPU2/VEPU2 */
520
521 const struct hantro_variant rk3328_vpu_variant = {
522 .dec_offset = 0x400,
523 .dec_fmts = rk3399_vpu_dec_fmts,
524 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
525 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
526 HANTRO_H264_DECODER,
527 .codec_ops = rk3399_vpu_codec_ops,
528 .irqs = rockchip_vdpu2_irqs,
529 .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
530 .init = rockchip_vpu_hw_init,
531 .clk_names = rockchip_vpu_clk_names,
532 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
533 };
534
535 const struct hantro_variant rk3399_vpu_variant = {
536 .enc_offset = 0x0,
537 .enc_fmts = rockchip_vpu_enc_fmts,
538 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
539 .dec_offset = 0x400,
540 .dec_fmts = rk3399_vpu_dec_fmts,
541 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
542 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
543 HANTRO_VP8_DECODER,
544 .codec_ops = rk3399_vpu_codec_ops,
545 .irqs = rockchip_vpu2_irqs,
546 .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
547 .init = rockchip_vpu_hw_init,
548 .clk_names = rockchip_vpu_clk_names,
549 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
550 };
551
552 const struct hantro_variant px30_vpu_variant = {
553 .enc_offset = 0x0,
554 .enc_fmts = rockchip_vpu_enc_fmts,
555 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
556 .dec_offset = 0x400,
557 .dec_fmts = rk3399_vpu_dec_fmts,
558 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
559 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
560 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
561 .codec_ops = rk3399_vpu_codec_ops,
562 .irqs = rockchip_vpu2_irqs,
563 .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
564 .init = rk3036_vpu_hw_init,
565 .clk_names = rockchip_vpu_clk_names,
566 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
567 };
568
