1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 4 * 5 * Register definitions taken from original Realtek rtl8723au driver 6 */ 7 8 #include <asm/byteorder.h> 9 10 #define RTL8XXXU_DEBUG_REG_WRITE 0x01 11 #define RTL8XXXU_DEBUG_REG_READ 0x02 12 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 13 #define RTL8XXXU_DEBUG_RFREG_READ 0x08 14 #define RTL8XXXU_DEBUG_CHANNEL 0x10 15 #define RTL8XXXU_DEBUG_TX 0x20 16 #define RTL8XXXU_DEBUG_TX_DUMP 0x40 17 #define RTL8XXXU_DEBUG_RX 0x80 18 #define RTL8XXXU_DEBUG_RX_DUMP 0x100 19 #define RTL8XXXU_DEBUG_USB 0x200 20 #define RTL8XXXU_DEBUG_KEY 0x400 21 #define RTL8XXXU_DEBUG_H2C 0x800 22 #define RTL8XXXU_DEBUG_ACTION 0x1000 23 #define RTL8XXXU_DEBUG_EFUSE 0x2000 24 #define RTL8XXXU_DEBUG_INTERRUPT 0x4000 25 26 #define RTW_USB_CONTROL_MSG_TIMEOUT 500 27 #define RTL8XXXU_MAX_REG_POLL 500 28 #define USB_INTR_CONTENT_LENGTH 56 29 30 #define RTL8XXXU_OUT_ENDPOINTS 6 31 32 #define REALTEK_USB_READ 0xc0 33 #define REALTEK_USB_WRITE 0x40 34 #define REALTEK_USB_CMD_REQ 0x05 35 #define REALTEK_USB_CMD_IDX 0x00 36 37 #define TX_TOTAL_PAGE_NUM 0xf8 38 #define TX_TOTAL_PAGE_NUM_8188F 0xf7 39 #define TX_TOTAL_PAGE_NUM_8188E 0xa9 40 #define TX_TOTAL_PAGE_NUM_8192E 0xf3 41 #define TX_TOTAL_PAGE_NUM_8723B 0xf7 42 #define TX_TOTAL_PAGE_NUM_8192F 0xf7 43 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ 44 #define TX_PAGE_NUM_PUBQ 0xe7 45 #define TX_PAGE_NUM_HI_PQ 0x0c 46 #define TX_PAGE_NUM_LO_PQ 0x02 47 #define TX_PAGE_NUM_NORM_PQ 0x02 48 49 #define TX_PAGE_NUM_PUBQ_8188F 0xe5 50 #define TX_PAGE_NUM_HI_PQ_8188F 0x0c 51 #define TX_PAGE_NUM_LO_PQ_8188F 0x02 52 #define TX_PAGE_NUM_NORM_PQ_8188F 0x02 53 54 #define TX_PAGE_NUM_PUBQ_8188E 0x47 55 #define TX_PAGE_NUM_HI_PQ_8188E 0x29 56 #define TX_PAGE_NUM_LO_PQ_8188E 0x1c 57 #define TX_PAGE_NUM_NORM_PQ_8188E 0x1c 58 59 #define TX_PAGE_NUM_PUBQ_8192E 0xe7 60 #define TX_PAGE_NUM_HI_PQ_8192E 0x08 61 #define TX_PAGE_NUM_LO_PQ_8192E 0x0c 62 #define TX_PAGE_NUM_NORM_PQ_8192E 0x00 63 64 #define TX_PAGE_NUM_PUBQ_8723B 0xe7 65 #define TX_PAGE_NUM_HI_PQ_8723B 0x0c 66 #define TX_PAGE_NUM_LO_PQ_8723B 0x02 67 #define TX_PAGE_NUM_NORM_PQ_8723B 0x02 68 69 #define TX_PAGE_NUM_PUBQ_8192F 0xde 70 #define TX_PAGE_NUM_HI_PQ_8192F 0x08 71 #define TX_PAGE_NUM_LO_PQ_8192F 0x08 72 #define TX_PAGE_NUM_NORM_PQ_8192F 0x08 73 74 #define RTL_FW_PAGE_SIZE 4096 75 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000 76 77 #define RTL8723A_CHANNEL_GROUPS 3 78 #define RTL8723A_MAX_RF_PATHS 2 79 #define RTL8723B_CHANNEL_GROUPS 6 80 #define RTL8723B_TX_COUNT 4 81 #define RTL8723B_MAX_RF_PATHS 4 82 #define RTL8XXXU_MAX_CHANNEL_GROUPS 6 83 #define RF6052_MAX_TX_PWR 0x3f 84 85 #define EFUSE_MAP_LEN 512 86 #define EFUSE_MAX_SECTION_8723A 64 87 #define EFUSE_REAL_CONTENT_LEN_8723A 512 88 #define EFUSE_BT_MAP_LEN_8723A 1024 89 #define EFUSE_MAX_WORD_UNIT 4 90 #define EFUSE_UNDEFINED 0xff 91 92 enum rtl8xxxu_rtl_chip { 93 RTL8192S = 0x81920, 94 RTL8191S = 0x81910, 95 RTL8192C = 0x8192c, 96 RTL8191C = 0x8191c, 97 RTL8188C = 0x8188c, 98 RTL8188R = 0x81889, 99 RTL8192D = 0x8192d, 100 RTL8723A = 0x8723a, 101 RTL8188E = 0x8188e, 102 RTL8812 = 0x88120, 103 RTL8821 = 0x88210, 104 RTL8192E = 0x8192e, 105 RTL8191E = 0x8191e, 106 RTL8723B = 0x8723b, 107 RTL8814A = 0x8814a, 108 RTL8881A = 0x8881a, 109 RTL8821B = 0x8821b, 110 RTL8822B = 0x8822b, 111 RTL8703B = 0x8703b, 112 RTL8195A = 0x8195a, 113 RTL8188F = 0x8188f, 114 RTL8710B = 0x8710b, 115 RTL8192F = 0x8192f, 116 }; 117 118 enum rtl8xxxu_rx_type { 119 RX_TYPE_DATA_PKT = 0, 120 RX_TYPE_C2H = 1, 121 RX_TYPE_ERROR = -1 122 }; 123 124 struct rtl8xxxu_rxdesc16 { 125 #ifdef __LITTLE_ENDIAN 126 u32 pktlen:14; 127 u32 crc32:1; 128 u32 icverr:1; 129 u32 drvinfo_sz:4; 130 u32 security:3; 131 u32 qos:1; 132 u32 shift:2; 133 u32 phy_stats:1; 134 u32 swdec:1; 135 u32 ls:1; 136 u32 fs:1; 137 u32 eor:1; 138 u32 own:1; 139 140 u32 macid:5; 141 u32 tid:4; 142 u32 hwrsvd:4; 143 u32 amsdu:1; 144 u32 paggr:1; 145 u32 faggr:1; 146 u32 a1fit:4; 147 u32 a2fit:4; 148 u32 pam:1; 149 u32 pwr:1; 150 u32 md:1; 151 u32 mf:1; 152 u32 type:2; 153 u32 mc:1; 154 u32 bc:1; 155 156 u32 seq:12; 157 u32 frag:4; 158 u32 pkt_cnt:8; 159 u32 reserved:6; 160 u32 nextind:1; 161 u32 reserved0:1; 162 163 u32 rxmcs:6; 164 u32 rxht:1; 165 u32 gf:1; 166 u32 splcp:1; 167 u32 bw:1; 168 u32 htc:1; 169 u32 eosp:1; 170 u32 bssidfit:2; 171 u32 rpt_sel:2; /* 8188e */ 172 u32 reserved1:14; 173 u32 unicastwake:1; 174 u32 magicwake:1; 175 176 u32 pattern0match:1; 177 u32 pattern1match:1; 178 u32 pattern2match:1; 179 u32 pattern3match:1; 180 u32 pattern4match:1; 181 u32 pattern5match:1; 182 u32 pattern6match:1; 183 u32 pattern7match:1; 184 u32 pattern8match:1; 185 u32 pattern9match:1; 186 u32 patternamatch:1; 187 u32 patternbmatch:1; 188 u32 patterncmatch:1; 189 u32 reserved2:19; 190 #else 191 u32 own:1; 192 u32 eor:1; 193 u32 fs:1; 194 u32 ls:1; 195 u32 swdec:1; 196 u32 phy_stats:1; 197 u32 shift:2; 198 u32 qos:1; 199 u32 security:3; 200 u32 drvinfo_sz:4; 201 u32 icverr:1; 202 u32 crc32:1; 203 u32 pktlen:14; 204 205 u32 bc:1; 206 u32 mc:1; 207 u32 type:2; 208 u32 mf:1; 209 u32 md:1; 210 u32 pwr:1; 211 u32 pam:1; 212 u32 a2fit:4; 213 u32 a1fit:4; 214 u32 faggr:1; 215 u32 paggr:1; 216 u32 amsdu:1; 217 u32 hwrsvd:4; 218 u32 tid:4; 219 u32 macid:5; 220 221 u32 reserved0:1; 222 u32 nextind:1; 223 u32 reserved:6; 224 u32 pkt_cnt:8; 225 u32 frag:4; 226 u32 seq:12; 227 228 u32 magicwake:1; 229 u32 unicastwake:1; 230 u32 reserved1:14; 231 u32 rpt_sel:2; /* 8188e */ 232 u32 bssidfit:2; 233 u32 eosp:1; 234 u32 htc:1; 235 u32 bw:1; 236 u32 splcp:1; 237 u32 gf:1; 238 u32 rxht:1; 239 u32 rxmcs:6; 240 241 u32 reserved2:19; 242 u32 patterncmatch:1; 243 u32 patternbmatch:1; 244 u32 patternamatch:1; 245 u32 pattern9match:1; 246 u32 pattern8match:1; 247 u32 pattern7match:1; 248 u32 pattern6match:1; 249 u32 pattern5match:1; 250 u32 pattern4match:1; 251 u32 pattern3match:1; 252 u32 pattern2match:1; 253 u32 pattern1match:1; 254 u32 pattern0match:1; 255 #endif 256 u32 tsfl; 257 #if 0 258 u32 bassn:12; 259 u32 bavld:1; 260 u32 reserved3:19; 261 #endif 262 }; 263 264 struct rtl8xxxu_rxdesc24 { 265 #ifdef __LITTLE_ENDIAN 266 u32 pktlen:14; 267 u32 crc32:1; 268 u32 icverr:1; 269 u32 drvinfo_sz:4; 270 u32 security:3; 271 u32 qos:1; 272 u32 shift:2; 273 u32 phy_stats:1; 274 u32 swdec:1; 275 u32 ls:1; 276 u32 fs:1; 277 u32 eor:1; 278 u32 own:1; 279 280 u32 macid:7; 281 u32 dummy1_0:1; 282 u32 tid:4; 283 u32 dummy1_1:1; 284 u32 amsdu:1; 285 u32 rxid_match:1; 286 u32 paggr:1; 287 u32 a1fit:4; /* 16 */ 288 u32 chkerr:1; 289 u32 ipver:1; 290 u32 tcpudp:1; 291 u32 chkvld:1; 292 u32 pam:1; 293 u32 pwr:1; 294 u32 more_data:1; 295 u32 more_frag:1; 296 u32 type:2; 297 u32 mc:1; 298 u32 bc:1; 299 300 u32 seq:12; 301 u32 frag:4; 302 u32 rx_is_qos:1; /* 16 */ 303 u32 dummy2_0:1; 304 u32 wlanhd_iv_len:6; 305 u32 dummy2_1:4; 306 u32 rpt_sel:1; 307 u32 dummy2_2:3; 308 309 u32 rxmcs:7; 310 u32 dummy3_0:3; 311 u32 htc:1; 312 u32 eosp:1; 313 u32 bssidfit:2; 314 u32 dummy3_1:2; 315 u32 usb_agg_pktnum:8; /* 16 */ 316 u32 dummy3_2:5; 317 u32 pattern_match:1; 318 u32 unicast_match:1; 319 u32 magic_match:1; 320 321 u32 splcp:1; 322 u32 ldcp:1; 323 u32 stbc:1; 324 u32 dummy4_0:1; 325 u32 bw:2; 326 u32 dummy4_1:26; 327 #else 328 u32 own:1; 329 u32 eor:1; 330 u32 fs:1; 331 u32 ls:1; 332 u32 swdec:1; 333 u32 phy_stats:1; 334 u32 shift:2; 335 u32 qos:1; 336 u32 security:3; 337 u32 drvinfo_sz:4; 338 u32 icverr:1; 339 u32 crc32:1; 340 u32 pktlen:14; 341 342 u32 bc:1; 343 u32 mc:1; 344 u32 type:2; 345 u32 mf:1; 346 u32 md:1; 347 u32 pwr:1; 348 u32 pam:1; 349 u32 a2fit:4; 350 u32 a1fit:4; 351 u32 faggr:1; 352 u32 paggr:1; 353 u32 amsdu:1; 354 u32 hwrsvd:4; 355 u32 tid:4; 356 u32 macid:5; 357 358 u32 dummy2_2:3; 359 u32 rpt_sel:1; 360 u32 dummy2_1:4; 361 u32 wlanhd_iv_len:6; 362 u32 dummy2_0:1; 363 u32 rx_is_qos:1; 364 u32 frag:4; /* 16 */ 365 u32 seq:12; 366 367 u32 magic_match:1; 368 u32 unicast_match:1; 369 u32 pattern_match:1; 370 u32 dummy3_2:5; 371 u32 usb_agg_pktnum:8; 372 u32 dummy3_1:2; /* 16 */ 373 u32 bssidfit:2; 374 u32 eosp:1; 375 u32 htc:1; 376 u32 dummy3_0:3; 377 u32 rxmcs:7; 378 379 u32 dumm4_1:26; 380 u32 bw:2; 381 u32 dummy4_0:1; 382 u32 stbc:1; 383 u32 ldcp:1; 384 u32 splcp:1; 385 #endif 386 u32 tsfl; 387 }; 388 389 struct rtl8xxxu_txdesc32 { 390 __le16 pkt_size; 391 u8 pkt_offset; 392 u8 txdw0; 393 __le32 txdw1; 394 __le32 txdw2; 395 __le32 txdw3; 396 __le32 txdw4; 397 __le32 txdw5; 398 __le32 txdw6; 399 __le16 csum; 400 __le16 txdw7; 401 }; 402 403 struct rtl8xxxu_txdesc40 { 404 __le16 pkt_size; 405 u8 pkt_offset; 406 u8 txdw0; 407 __le32 txdw1; 408 __le32 txdw2; 409 __le32 txdw3; 410 __le32 txdw4; 411 __le32 txdw5; 412 __le32 txdw6; 413 __le16 csum; 414 __le16 txdw7; 415 __le32 txdw8; 416 __le32 txdw9; 417 }; 418 419 /* CCK Rates, TxHT = 0 */ 420 #define DESC_RATE_1M 0x00 421 #define DESC_RATE_2M 0x01 422 #define DESC_RATE_5_5M 0x02 423 #define DESC_RATE_11M 0x03 424 425 /* OFDM Rates, TxHT = 0 */ 426 #define DESC_RATE_6M 0x04 427 #define DESC_RATE_9M 0x05 428 #define DESC_RATE_12M 0x06 429 #define DESC_RATE_18M 0x07 430 #define DESC_RATE_24M 0x08 431 #define DESC_RATE_36M 0x09 432 #define DESC_RATE_48M 0x0a 433 #define DESC_RATE_54M 0x0b 434 435 /* MCS Rates, TxHT = 1 */ 436 #define DESC_RATE_MCS0 0x0c 437 #define DESC_RATE_MCS1 0x0d 438 #define DESC_RATE_MCS2 0x0e 439 #define DESC_RATE_MCS3 0x0f 440 #define DESC_RATE_MCS4 0x10 441 #define DESC_RATE_MCS5 0x11 442 #define DESC_RATE_MCS6 0x12 443 #define DESC_RATE_MCS7 0x13 444 #define DESC_RATE_MCS8 0x14 445 #define DESC_RATE_MCS9 0x15 446 #define DESC_RATE_MCS10 0x16 447 #define DESC_RATE_MCS11 0x17 448 #define DESC_RATE_MCS12 0x18 449 #define DESC_RATE_MCS13 0x19 450 #define DESC_RATE_MCS14 0x1a 451 #define DESC_RATE_MCS15 0x1b 452 #define DESC_RATE_MCS15_SG 0x1c 453 #define DESC_RATE_MCS32 0x20 454 455 #define TXDESC_OFFSET_SZ 0 456 #define TXDESC_OFFSET_SHT 16 457 #if 0 458 #define TXDESC_BMC BIT(24) 459 #define TXDESC_LSG BIT(26) 460 #define TXDESC_FSG BIT(27) 461 #define TXDESC_OWN BIT(31) 462 #else 463 #define TXDESC_BROADMULTICAST BIT(0) 464 #define TXDESC_HTC BIT(1) 465 #define TXDESC_LAST_SEGMENT BIT(2) 466 #define TXDESC_FIRST_SEGMENT BIT(3) 467 #define TXDESC_LINIP BIT(4) 468 #define TXDESC_NO_ACM BIT(5) 469 #define TXDESC_GF BIT(6) 470 #define TXDESC_OWN BIT(7) 471 #endif 472 473 /* Word 1 */ 474 /* 475 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are 476 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. 477 */ 478 #define TXDESC_PKT_OFFSET_SZ 0 479 #define TXDESC32_AGG_ENABLE BIT(5) 480 #define TXDESC32_AGG_BREAK BIT(6) 481 #define TXDESC40_MACID_SHIFT 0 482 #define TXDESC40_MACID_MASK 0x00f0 483 #define TXDESC_QUEUE_SHIFT 8 484 #define TXDESC_QUEUE_MASK 0x1f00 485 #define TXDESC_QUEUE_BK 0x2 486 #define TXDESC_QUEUE_BE 0x0 487 #define TXDESC_QUEUE_VI 0x5 488 #define TXDESC_QUEUE_VO 0x7 489 #define TXDESC_QUEUE_BEACON 0x10 490 #define TXDESC_QUEUE_HIGH 0x11 491 #define TXDESC_QUEUE_MGNT 0x12 492 #define TXDESC_QUEUE_CMD 0x13 493 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) 494 #define TXDESC40_RDG_NAV_EXT BIT(13) 495 #define TXDESC40_LSIG_TXOP_ENABLE BIT(14) 496 #define TXDESC40_PIFS BIT(15) 497 498 #define DESC_RATE_ID_SHIFT 16 499 #define DESC_RATE_ID_MASK 0xf 500 #define TXDESC_NAVUSEHDR BIT(20) 501 #define TXDESC_SEC_RC4 0x00400000 502 #define TXDESC_SEC_AES 0x00c00000 503 #define TXDESC_PKT_OFFSET_SHIFT 26 504 #define TXDESC_AGG_EN BIT(29) 505 #define TXDESC_HWPC BIT(31) 506 507 /* Word 2 */ 508 #define TXDESC40_PAID_SHIFT 0 509 #define TXDESC40_PAID_MASK 0x1ff 510 #define TXDESC40_CCA_RTS_SHIFT 10 511 #define TXDESC40_CCA_RTS_MASK 0xc00 512 #define TXDESC40_AGG_ENABLE BIT(12) 513 #define TXDESC40_RDG_ENABLE BIT(13) 514 #define TXDESC40_AGG_BREAK BIT(16) 515 #define TXDESC40_MORE_FRAG BIT(17) 516 #define TXDESC40_RAW BIT(18) 517 #define TXDESC32_ACK_REPORT BIT(19) 518 #define TXDESC40_SPE_RPT BIT(19) 519 #define TXDESC_AMPDU_DENSITY_SHIFT 20 520 #define TXDESC40_BT_INT BIT(23) 521 #define TXDESC40_GID_SHIFT 24 522 #define TXDESC_ANTENNA_SELECT_A BIT(24) 523 #define TXDESC_ANTENNA_SELECT_B BIT(25) 524 525 /* Word 3 */ 526 #define TXDESC40_USE_DRIVER_RATE BIT(8) 527 #define TXDESC40_CTS_SELF_ENABLE BIT(11) 528 #define TXDESC40_RTS_CTS_ENABLE BIT(12) 529 #define TXDESC40_HW_RTS_ENABLE BIT(13) 530 #define TXDESC32_SEQ_SHIFT 16 531 #define TXDESC32_SEQ_MASK 0x0fff0000 532 533 /* Word 4 */ 534 #define TXDESC32_RTS_RATE_SHIFT 0 535 #define TXDESC32_RTS_RATE_MASK 0x3f 536 #define TXDESC32_QOS BIT(6) 537 #define TXDESC32_HW_SEQ_ENABLE BIT(7) 538 #define TXDESC32_USE_DRIVER_RATE BIT(8) 539 #define TXDESC_DISABLE_DATA_FB BIT(10) 540 #define TXDESC32_CTS_SELF_ENABLE BIT(11) 541 #define TXDESC32_RTS_CTS_ENABLE BIT(12) 542 #define TXDESC32_HW_RTS_ENABLE BIT(13) 543 #define TXDESC32_PT_STAGE_MASK GENMASK(17, 15) 544 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) 545 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) 546 #define TXDESC32_SHORT_PREAMBLE BIT(24) 547 #define TXDESC_DATA_BW BIT(25) 548 #define TXDESC_RTS_DATA_BW BIT(27) 549 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) 550 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) 551 #define TXDESC40_DATA_RATE_FB_SHIFT 8 552 #define TXDESC40_DATA_RATE_FB_MASK 0x00001f00 553 #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17) 554 #define TXDESC40_RETRY_LIMIT_SHIFT 18 555 #define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000 556 #define TXDESC40_RTS_RATE_SHIFT 24 557 #define TXDESC40_RTS_RATE_MASK 0x3f000000 558 559 /* Word 5 */ 560 #define TXDESC40_SHORT_PREAMBLE BIT(4) 561 #define TXDESC32_SHORT_GI BIT(6) 562 #define TXDESC_CCX_TAG BIT(7) 563 #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17) 564 #define TXDESC32_RETRY_LIMIT_SHIFT 18 565 #define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000 566 567 /* Word 6 */ 568 #define TXDESC_MAX_AGG_SHIFT 11 569 #define TXDESC_USB_TX_AGG_SHIT 24 570 571 /* Word 7 */ 572 #define TXDESC_ANTENNA_SELECT_C BIT(29) 573 574 /* Word 8 */ 575 #define TXDESC40_HW_SEQ_ENABLE BIT(15) 576 577 /* Word 9 */ 578 #define TXDESC40_SEQ_SHIFT 12 579 #define TXDESC40_SEQ_MASK 0x00fff000 580 581 struct phy_rx_agc_info { 582 #ifdef __LITTLE_ENDIAN 583 u8 gain:7, trsw:1; 584 #else 585 u8 trsw:1, gain:7; 586 #endif 587 }; 588 589 #define CCK_AGC_RPT_LNA_IDX_MASK GENMASK(7, 5) 590 #define CCK_AGC_RPT_VGA_IDX_MASK GENMASK(4, 0) 591 592 struct rtl8723au_phy_stats { 593 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; 594 u8 ch_corr[RTL8723A_MAX_RF_PATHS]; 595 u8 cck_sig_qual_ofdm_pwdb_all; 596 u8 cck_agc_rpt_ofdm_cfosho_a; 597 u8 cck_rpt_b_ofdm_cfosho_b; 598 u8 reserved_1; 599 u8 noise_power_db_msb; 600 s8 path_cfotail[RTL8723A_MAX_RF_PATHS]; 601 u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; 602 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; 603 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; 604 u8 noise_power_db_lsb; 605 u8 reserved_2[3]; 606 u8 stream_csi[RTL8723A_MAX_RF_PATHS]; 607 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; 608 s8 sig_evm; 609 u8 reserved_3; 610 611 #ifdef __LITTLE_ENDIAN 612 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 613 u8 sgi_en:1; 614 u8 rxsc:2; 615 u8 idle_long:1; 616 u8 r_ant_train_en:1; 617 u8 antenna_select_b:1; 618 u8 antenna_select:1; 619 #else /* _BIG_ENDIAN_ */ 620 u8 antenna_select:1; 621 u8 antenna_select_b:1; 622 u8 r_ant_train_en:1; 623 u8 idle_long:1; 624 u8 rxsc:2; 625 u8 sgi_en:1; 626 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 627 #endif 628 }; 629 630 struct jaguar2_phy_stats_type0 { 631 /* DW0 */ 632 u8 page_num; 633 u8 pwdb; 634 #ifdef __LITTLE_ENDIAN 635 u8 gain: 6; 636 u8 rsvd_0: 1; 637 u8 trsw: 1; 638 #else 639 u8 trsw: 1; 640 u8 rsvd_0: 1; 641 u8 gain: 6; 642 #endif 643 u8 rsvd_1; 644 645 /* DW1 */ 646 u8 rsvd_2; 647 #ifdef __LITTLE_ENDIAN 648 u8 rxsc: 4; 649 u8 agc_table: 4; 650 #else 651 u8 agc_table: 4; 652 u8 rxsc: 4; 653 #endif 654 u8 channel; 655 u8 band; 656 657 /* DW2 */ 658 u16 length; 659 #ifdef __LITTLE_ENDIAN 660 u8 antidx_a: 3; 661 u8 antidx_b: 3; 662 u8 rsvd_3: 2; 663 u8 antidx_c: 3; 664 u8 antidx_d: 3; 665 u8 rsvd_4:2; 666 #else 667 u8 rsvd_3: 2; 668 u8 antidx_b: 3; 669 u8 antidx_a: 3; 670 u8 rsvd_4:2; 671 u8 antidx_d: 3; 672 u8 antidx_c: 3; 673 #endif 674 675 /* DW3 */ 676 u8 signal_quality; 677 #ifdef __LITTLE_ENDIAN 678 u8 vga:5; 679 u8 lna_l:3; 680 u8 bb_power:6; 681 u8 rsvd_9:1; 682 u8 lna_h:1; 683 #else 684 u8 lna_l:3; 685 u8 vga:5; 686 u8 lna_h:1; 687 u8 rsvd_9:1; 688 u8 bb_power:6; 689 #endif 690 u8 rsvd_5; 691 692 /* DW4 */ 693 u32 rsvd_6; 694 695 /* DW5 */ 696 u32 rsvd_7; 697 698 /* DW6 */ 699 u32 rsvd_8; 700 } __packed; 701 702 struct jaguar2_phy_stats_type1 { 703 /* DW0 and DW1 */ 704 u8 page_num; 705 u8 pwdb[4]; 706 #ifdef __LITTLE_ENDIAN 707 u8 l_rxsc: 4; 708 u8 ht_rxsc: 4; 709 #else 710 u8 ht_rxsc: 4; 711 u8 l_rxsc: 4; 712 #endif 713 u8 channel; 714 #ifdef __LITTLE_ENDIAN 715 u8 band: 2; 716 u8 rsvd_0: 1; 717 u8 hw_antsw_occu: 1; 718 u8 gnt_bt: 1; 719 u8 ldpc: 1; 720 u8 stbc: 1; 721 u8 beamformed: 1; 722 #else 723 u8 beamformed: 1; 724 u8 stbc: 1; 725 u8 ldpc: 1; 726 u8 gnt_bt: 1; 727 u8 hw_antsw_occu: 1; 728 u8 rsvd_0: 1; 729 u8 band: 2; 730 #endif 731 732 /* DW2 */ 733 u16 lsig_length; 734 #ifdef __LITTLE_ENDIAN 735 u8 antidx_a: 3; 736 u8 antidx_b: 3; 737 u8 rsvd_1: 2; 738 u8 antidx_c: 3; 739 u8 antidx_d: 3; 740 u8 rsvd_2: 2; 741 #else 742 u8 rsvd_1: 2; 743 u8 antidx_b: 3; 744 u8 antidx_a: 3; 745 u8 rsvd_2: 2; 746 u8 antidx_d: 3; 747 u8 antidx_c: 3; 748 #endif 749 750 /* DW3 */ 751 u8 paid; 752 #ifdef __LITTLE_ENDIAN 753 u8 paid_msb: 1; 754 u8 gid: 6; 755 u8 rsvd_3: 1; 756 #else 757 u8 rsvd_3: 1; 758 u8 gid: 6; 759 u8 paid_msb: 1; 760 #endif 761 u8 intf_pos; 762 #ifdef __LITTLE_ENDIAN 763 u8 intf_pos_msb: 1; 764 u8 rsvd_4: 2; 765 u8 nb_intf_flag: 1; 766 u8 rf_mode: 2; 767 u8 rsvd_5: 2; 768 #else 769 u8 rsvd_5: 2; 770 u8 rf_mode: 2; 771 u8 nb_intf_flag: 1; 772 u8 rsvd_4: 2; 773 u8 intf_pos_msb: 1; 774 #endif 775 776 /* DW4 */ 777 s8 rxevm[4]; /* s(8,1) */ 778 779 /* DW5 */ 780 s8 cfo_tail[4]; /* s(8,7) */ 781 782 /* DW6 */ 783 s8 rxsnr[4]; /* s(8,1) */ 784 } __packed; 785 786 struct jaguar2_phy_stats_type2 { 787 /* DW0 ane DW1 */ 788 u8 page_num; 789 u8 pwdb[4]; 790 #ifdef __LITTLE_ENDIAN 791 u8 l_rxsc: 4; 792 u8 ht_rxsc: 4; 793 #else 794 u8 ht_rxsc: 4; 795 u8 l_rxsc: 4; 796 #endif 797 u8 channel; 798 #ifdef __LITTLE_ENDIAN 799 u8 band: 2; 800 u8 rsvd_0: 1; 801 u8 hw_antsw_occu: 1; 802 u8 gnt_bt: 1; 803 u8 ldpc: 1; 804 u8 stbc: 1; 805 u8 beamformed: 1; 806 #else 807 u8 beamformed: 1; 808 u8 stbc: 1; 809 u8 ldpc: 1; 810 u8 gnt_bt: 1; 811 u8 hw_antsw_occu: 1; 812 u8 rsvd_0: 1; 813 u8 band: 2; 814 #endif 815 816 /* DW2 */ 817 #ifdef __LITTLE_ENDIAN 818 u8 shift_l_map: 6; 819 u8 rsvd_1: 2; 820 #else 821 u8 rsvd_1: 2; 822 u8 shift_l_map: 6; 823 #endif 824 u8 cnt_pw2cca; 825 #ifdef __LITTLE_ENDIAN 826 u8 agc_table_a: 4; 827 u8 agc_table_b: 4; 828 u8 agc_table_c: 4; 829 u8 agc_table_d: 4; 830 #else 831 u8 agc_table_b: 4; 832 u8 agc_table_a: 4; 833 u8 agc_table_d: 4; 834 u8 agc_table_c: 4; 835 #endif 836 837 /* DW3 ~ DW6*/ 838 u8 cnt_cca2agc_rdy; 839 #ifdef __LITTLE_ENDIAN 840 u8 gain_a: 6; 841 u8 rsvd_2: 1; 842 u8 trsw_a: 1; 843 u8 gain_b: 6; 844 u8 rsvd_3: 1; 845 u8 trsw_b: 1; 846 u8 gain_c: 6; 847 u8 rsvd_4: 1; 848 u8 trsw_c: 1; 849 u8 gain_d: 6; 850 u8 rsvd_5: 1; 851 u8 trsw_d: 1; 852 u8 aagc_step_a: 2; 853 u8 aagc_step_b: 2; 854 u8 aagc_step_c: 2; 855 u8 aagc_step_d: 2; 856 #else 857 u8 trsw_a: 1; 858 u8 rsvd_2: 1; 859 u8 gain_a: 6; 860 u8 trsw_b: 1; 861 u8 rsvd_3: 1; 862 u8 gain_b: 6; 863 u8 trsw_c: 1; 864 u8 rsvd_4: 1; 865 u8 gain_c: 6; 866 u8 trsw_d: 1; 867 u8 rsvd_5: 1; 868 u8 gain_d: 6; 869 u8 aagc_step_d: 2; 870 u8 aagc_step_c: 2; 871 u8 aagc_step_b: 2; 872 u8 aagc_step_a: 2; 873 #endif 874 u8 ht_aagc_gain[4]; 875 u8 dagc_gain[4]; 876 #ifdef __LITTLE_ENDIAN 877 u8 counter: 6; 878 u8 rsvd_6: 2; 879 u8 syn_count: 5; 880 u8 rsvd_7:3; 881 #else 882 u8 rsvd_6: 2; 883 u8 counter: 6; 884 u8 rsvd_7:3; 885 u8 syn_count: 5; 886 #endif 887 } __packed; 888 889 /* 890 * Regs to backup 891 */ 892 #define RTL8XXXU_ADDA_REGS 16 893 #define RTL8XXXU_MAC_REGS 4 894 #define RTL8XXXU_BB_REGS 9 895 896 struct rtl8xxxu_firmware_header { 897 __le16 signature; /* 92C0: test chip; 92C, 898 88C0: test chip; 899 88C1: MP A-cut; 900 92C1: MP A-cut */ 901 u8 category; /* AP/NIC and USB/PCI */ 902 u8 function; 903 904 __le16 major_version; /* FW Version */ 905 u8 minor_version; /* FW Subversion, default 0x00 */ 906 u8 reserved1; 907 908 u8 month; /* Release time Month field */ 909 u8 date; /* Release time Date field */ 910 u8 hour; /* Release time Hour field */ 911 u8 minute; /* Release time Minute field */ 912 913 __le16 ramcodesize; /* Size of RAM code */ 914 u16 reserved2; 915 916 __le32 svn_idx; /* SVN entry index */ 917 u32 reserved3; 918 919 u32 reserved4; 920 u32 reserved5; 921 922 u8 data[]; 923 }; 924 925 /* 926 * 8723au/8192cu/8188ru required base power index offset tables. 927 */ 928 struct rtl8xxxu_power_base { 929 u32 reg_0e00; 930 u32 reg_0e04; 931 u32 reg_0e08; 932 u32 reg_086c; 933 934 u32 reg_0e10; 935 u32 reg_0e14; 936 u32 reg_0e18; 937 u32 reg_0e1c; 938 939 u32 reg_0830; 940 u32 reg_0834; 941 u32 reg_0838; 942 u32 reg_086c_2; 943 944 u32 reg_083c; 945 u32 reg_0848; 946 u32 reg_084c; 947 u32 reg_0868; 948 }; 949 950 /* 951 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 952 */ 953 struct rtl8723au_idx { 954 #ifdef __LITTLE_ENDIAN 955 int a:4; 956 int b:4; 957 #else 958 int b:4; 959 int a:4; 960 #endif 961 } __attribute__((packed)); 962 963 struct rtl8723au_efuse { 964 __le16 rtl_id; 965 u8 res0[0xe]; 966 u8 cck_tx_power_index_A[3]; /* 0x10 */ 967 u8 cck_tx_power_index_B[3]; 968 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 969 u8 ht40_1s_tx_power_index_B[3]; 970 /* 971 * The following entries are half-bytes split as: 972 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 973 */ 974 struct rtl8723au_idx ht20_tx_power_index_diff[3]; 975 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 976 struct rtl8723au_idx ht40_max_power_offset[3]; 977 struct rtl8723au_idx ht20_max_power_offset[3]; 978 u8 channel_plan; /* 0x28 */ 979 u8 tssi_a; 980 u8 thermal_meter; 981 u8 rf_regulatory; 982 u8 rf_option_2; 983 u8 rf_option_3; 984 u8 rf_option_4; 985 u8 res7; 986 u8 version /* 0x30 */; 987 u8 customer_id_major; 988 u8 customer_id_minor; 989 u8 xtal_k; 990 u8 chipset; /* 0x34 */ 991 u8 res8[0x82]; 992 u8 vid; /* 0xb7 */ 993 u8 res9; 994 u8 pid; /* 0xb9 */ 995 u8 res10[0x0c]; 996 u8 mac_addr[ETH_ALEN]; /* 0xc6 */ 997 u8 res11[2]; 998 u8 vendor_name[7]; 999 u8 res12[2]; 1000 u8 device_name[0x29]; /* 0xd7 */ 1001 }; 1002 1003 struct rtl8192cu_efuse { 1004 __le16 rtl_id; 1005 __le16 hpon; 1006 u8 res0[2]; 1007 __le16 clk; 1008 __le16 testr; 1009 __le16 vid; 1010 __le16 did; 1011 __le16 svid; 1012 __le16 smid; /* 0x10 */ 1013 u8 res1[4]; 1014 u8 mac_addr[ETH_ALEN]; /* 0x16 */ 1015 u8 res2[2]; 1016 u8 vendor_name[7]; 1017 u8 res3[3]; 1018 u8 device_name[0x14]; /* 0x28 */ 1019 u8 res4[0x1e]; /* 0x3c */ 1020 u8 cck_tx_power_index_A[3]; /* 0x5a */ 1021 u8 cck_tx_power_index_B[3]; 1022 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ 1023 u8 ht40_1s_tx_power_index_B[3]; 1024 /* 1025 * The following entries are half-bytes split as: 1026 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1027 */ 1028 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 1029 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ 1030 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 1031 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ 1032 struct rtl8723au_idx ht20_max_power_offset[3]; 1033 u8 channel_plan; /* 0x75 */ 1034 u8 tssi_a; 1035 u8 tssi_b; 1036 u8 thermal_meter; /* xtal_k */ /* 0x78 */ 1037 u8 rf_regulatory; 1038 u8 rf_option_2; 1039 u8 rf_option_3; 1040 u8 rf_option_4; 1041 u8 res5[1]; /* 0x7d */ 1042 u8 version; 1043 u8 customer_id; 1044 }; 1045 1046 struct rtl8723bu_pwr_idx { 1047 #ifdef __LITTLE_ENDIAN 1048 int ht20:4; 1049 int ht40:4; 1050 int ofdm:4; 1051 int cck:4; 1052 #else 1053 int cck:4; 1054 int ofdm:4; 1055 int ht40:4; 1056 int ht20:4; 1057 #endif 1058 } __attribute__((packed)); 1059 1060 struct rtl8723bu_efuse_tx_power { 1061 u8 cck_base[6]; 1062 u8 ht40_base[5]; 1063 struct rtl8723au_idx ht20_ofdm_1s_diff; 1064 struct rtl8723bu_pwr_idx pwr_diff[3]; 1065 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 1066 }; 1067 1068 struct rtl8723bu_efuse { 1069 __le16 rtl_id; 1070 u8 res0[0x0e]; 1071 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1072 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1073 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */ 1074 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */ 1075 u8 channel_plan; /* 0xb8 */ 1076 u8 xtal_k; 1077 u8 thermal_meter; 1078 u8 iqk_lck; 1079 u8 pa_type; /* 0xbc */ 1080 u8 lna_type_2g; /* 0xbd */ 1081 u8 res2[3]; 1082 u8 rf_board_option; 1083 u8 rf_feature_option; 1084 u8 rf_bt_setting; 1085 u8 eeprom_version; 1086 u8 eeprom_customer_id; 1087 u8 res3[2]; 1088 u8 tx_pwr_calibrate_rate; 1089 u8 rf_antenna_option; /* 0xc9 */ 1090 u8 rfe_option; 1091 u8 res4[9]; 1092 u8 usb_optional_function; 1093 u8 res5[0x1e]; 1094 u8 res6[2]; 1095 u8 serial[0x0b]; /* 0xf5 */ 1096 u8 vid; /* 0x100 */ 1097 u8 res7; 1098 u8 pid; 1099 u8 res8[4]; 1100 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 1101 u8 res9[2]; 1102 u8 vendor_name[0x07]; 1103 u8 res10[2]; 1104 u8 device_name[0x14]; 1105 u8 res11[0xcf]; 1106 u8 package_type; /* 0x1fb */ 1107 u8 res12[0x4]; 1108 }; 1109 1110 struct rtl8192eu_efuse_tx_power { 1111 u8 cck_base[6]; 1112 u8 ht40_base[5]; 1113 struct rtl8723au_idx ht20_ofdm_1s_diff; 1114 struct rtl8723bu_pwr_idx pwr_diff[3]; 1115 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 1116 }; 1117 1118 struct rtl8192eu_efuse { 1119 __le16 rtl_id; 1120 u8 res0[0x0e]; 1121 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1122 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1123 u8 res2[0x54]; 1124 u8 channel_plan; /* 0xb8 */ 1125 u8 xtal_k; 1126 u8 thermal_meter; 1127 u8 iqk_lck; 1128 u8 pa_type; /* 0xbc */ 1129 u8 lna_type_2g; /* 0xbd */ 1130 u8 res3[1]; 1131 u8 lna_type_5g; /* 0xbf */ 1132 u8 res4[1]; 1133 u8 rf_board_option; 1134 u8 rf_feature_option; 1135 u8 rf_bt_setting; 1136 u8 eeprom_version; 1137 u8 eeprom_customer_id; 1138 u8 res5[3]; 1139 u8 rf_antenna_option; /* 0xc9 */ 1140 u8 res6[6]; 1141 u8 vid; /* 0xd0 */ 1142 u8 res7[1]; 1143 u8 pid; /* 0xd2 */ 1144 u8 res8[1]; 1145 u8 usb_optional_function; 1146 u8 res9[2]; 1147 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1148 u8 device_info[80]; 1149 u8 res11[3]; 1150 u8 unknown[0x0d]; /* 0x130 */ 1151 u8 res12[0xc3]; 1152 }; 1153 1154 struct rtl8188fu_efuse_tx_power { 1155 u8 cck_base[6]; 1156 u8 ht40_base[5]; 1157 /* a: ofdm; b: ht20 */ 1158 struct rtl8723au_idx ht20_ofdm_1s_diff; 1159 }; 1160 1161 struct rtl8188fu_efuse { 1162 __le16 rtl_id; 1163 u8 res0[0x0e]; 1164 struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1165 u8 res1[0x9c]; /* 0x1c */ 1166 u8 channel_plan; /* 0xb8 */ 1167 u8 xtal_k; 1168 u8 thermal_meter; 1169 u8 iqk_lck; 1170 u8 res2[5]; 1171 u8 rf_board_option; 1172 u8 rf_feature_option; 1173 u8 rf_bt_setting; 1174 u8 eeprom_version; 1175 u8 eeprom_customer_id; 1176 u8 res3[2]; 1177 u8 kfree_thermal_k_on; 1178 u8 rf_antenna_option; /* 0xc9 */ 1179 u8 rfe_option; 1180 u8 country_code; 1181 u8 res4[4]; 1182 u8 vid; /* 0xd0 */ 1183 u8 res5[1]; 1184 u8 pid; /* 0xd2 */ 1185 u8 res6[1]; 1186 u8 usb_optional_function; 1187 u8 res7[2]; 1188 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1189 u8 res8[2]; 1190 u8 vendor_name[7]; 1191 u8 res9[2]; 1192 u8 device_name[7]; /* 0xe8 */ 1193 u8 res10[0x41]; 1194 u8 unknown[0x0d]; /* 0x130 */ 1195 u8 res11[0xc3]; 1196 }; 1197 1198 struct rtl8188eu_efuse { 1199 __le16 rtl_id; 1200 u8 res0[0x0e]; 1201 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1202 u8 res1[0x7e]; /* 0x3a */ 1203 u8 channel_plan; /* 0xb8 */ 1204 u8 xtal_k; 1205 u8 thermal_meter; 1206 u8 iqk_lck; 1207 u8 res2[5]; 1208 u8 rf_board_option; 1209 u8 rf_feature_option; 1210 u8 rf_bt_setting; 1211 u8 eeprom_version; 1212 u8 eeprom_customer_id; 1213 u8 res3[3]; 1214 u8 rf_antenna_option; /* 0xc9 */ 1215 u8 res4[6]; 1216 u8 vid; /* 0xd0 */ 1217 u8 res5[1]; 1218 u8 pid; /* 0xd2 */ 1219 u8 res6[1]; 1220 u8 usb_optional_function; 1221 u8 res7[2]; 1222 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1223 u8 res8[2]; 1224 u8 vendor_name[7]; 1225 u8 res9[2]; 1226 u8 device_name[0x0b]; /* 0xe8 */ 1227 u8 res10[2]; 1228 u8 serial[0x0b]; /* 0xf5 */ 1229 u8 res11[0x30]; 1230 u8 unknown[0x0d]; /* 0x130 */ 1231 u8 res12[0xc3]; 1232 } __packed; 1233 1234 struct rtl8710bu_efuse { 1235 __le16 rtl_id; 1236 u8 res0[0x1e]; 1237 struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x20 */ 1238 u8 res1[0x9c]; /* 0x2c */ 1239 u8 channel_plan; /* 0xc8 */ 1240 u8 xtal_k; /* 0xc9 */ 1241 u8 thermal_meter; /* 0xca */ 1242 u8 res2[0x4f]; 1243 u8 mac_addr[ETH_ALEN]; /* 0x11a */ 1244 u8 res3[0x11]; 1245 u8 rf_board_option; /* 0x131 */ 1246 u8 res4[2]; 1247 u8 eeprom_version; /* 0x134 */ 1248 u8 eeprom_customer_id; /* 0x135 */ 1249 u8 res5[5]; 1250 u8 country_code; /* 0x13b */ 1251 u8 res6[0x84]; 1252 u8 vid[2]; /* 0x1c0 */ 1253 u8 pid[2]; /* 0x1c2 */ 1254 u8 res7[0x3c]; 1255 } __packed; 1256 1257 struct rtl8192fu_efuse { 1258 __le16 rtl_id; 1259 u8 res0[0x0e]; 1260 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1261 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1262 u8 res2[0x54]; 1263 u8 channel_plan; /* 0xb8 */ 1264 u8 xtal_k; /* 0xb9 */ 1265 u8 thermal_meter; /* 0xba */ 1266 u8 iqk_lck; /* 0xbb */ 1267 u8 pa_type; /* 0xbc */ 1268 u8 lna_type_2g; /* 0xbd */ 1269 u8 res3[1]; 1270 u8 lna_type_5g; /* 0xbf */ 1271 u8 res4[1]; 1272 u8 rf_board_option; /* 0xc1 */ 1273 u8 rf_feature_option; /* 0xc2 */ 1274 u8 rf_bt_setting; /* 0xc3 */ 1275 u8 eeprom_version; /* 0xc4 */ 1276 u8 eeprom_customer_id; /* 0xc5 */ 1277 u8 res5[3]; 1278 u8 rf_antenna_option; /* 0xc9 */ 1279 u8 rfe_option; /* 0xca */ 1280 u8 country_code; /* 0xcb */ 1281 u8 res6[52]; 1282 u8 vid[2]; /* 0x100 */ 1283 u8 pid[2]; /* 0x102 */ 1284 u8 usb_optional_function; /* 0x104 */ 1285 u8 res7[2]; 1286 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 1287 u8 device_info[80]; /* 0x10d */ 1288 u8 res9[163]; 1289 } __packed; 1290 1291 struct rtl8xxxu_reg8val { 1292 u16 reg; 1293 u8 val; 1294 }; 1295 1296 struct rtl8xxxu_reg32val { 1297 u16 reg; 1298 u32 val; 1299 }; 1300 1301 struct rtl8xxxu_rfregval { 1302 u8 reg; 1303 u32 val; 1304 }; 1305 1306 enum rtl8xxxu_rfpath { 1307 RF_A = 0, 1308 RF_B = 1, 1309 }; 1310 1311 struct rtl8xxxu_rfregs { 1312 u16 hssiparm1; 1313 u16 hssiparm2; 1314 u16 lssiparm; 1315 u16 hspiread; 1316 u16 lssiread; 1317 u16 rf_sw_ctrl; 1318 }; 1319 1320 #define H2C_MAX_MBOX 4 1321 #define H2C_EXT BIT(7) 1322 #define H2C_JOIN_BSS_DISCONNECT 0 1323 #define H2C_JOIN_BSS_CONNECT 1 1324 1325 #define H2C_MACID_ROLE_STA 1 1326 #define H2C_MACID_ROLE_AP 2 1327 1328 /* 1329 * H2C (firmware) commands differ between the older generation chips 1330 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, 1331 * 8192[de]u, 8192eu, and 8812. 1332 */ 1333 enum h2c_cmd_8723a { 1334 H2C_SET_POWER_MODE = 1, 1335 H2C_JOIN_BSS_REPORT = 2, 1336 H2C_SET_RSSI = 5, 1337 H2C_SET_RATE_MASK = (6 | H2C_EXT), 1338 }; 1339 1340 enum h2c_cmd_8723b { 1341 /* 1342 * Common Class: 000 1343 */ 1344 H2C_8723B_RSVD_PAGE = 0x00, 1345 H2C_8723B_MEDIA_STATUS_RPT = 0x01, 1346 H2C_8723B_SCAN_ENABLE = 0x02, 1347 H2C_8723B_KEEP_ALIVE = 0x03, 1348 H2C_8723B_DISCON_DECISION = 0x04, 1349 H2C_8723B_PSD_OFFLOAD = 0x05, 1350 H2C_8723B_AP_OFFLOAD = 0x08, 1351 H2C_8723B_BCN_RSVDPAGE = 0x09, 1352 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, 1353 H2C_8723B_FCS_RSVDPAGE = 0x10, 1354 H2C_8723B_FCS_INFO = 0x11, 1355 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, 1356 1357 /* 1358 * PoweSave Class: 001 1359 */ 1360 H2C_8723B_SET_PWR_MODE = 0x20, 1361 H2C_8723B_PS_TUNING_PARA = 0x21, 1362 H2C_8723B_PS_TUNING_PARA2 = 0x22, 1363 H2C_8723B_P2P_LPS_PARAM = 0x23, 1364 H2C_8723B_P2P_PS_OFFLOAD = 0x24, 1365 H2C_8723B_PS_SCAN_ENABLE = 0x25, 1366 H2C_8723B_SAP_PS_ = 0x26, 1367 H2C_8723B_INACTIVE_PS_ = 0x27, 1368 H2C_8723B_FWLPS_IN_IPS_ = 0x28, 1369 1370 /* 1371 * Dynamic Mechanism Class: 010 1372 */ 1373 H2C_8723B_MACID_CFG_RAID = 0x40, 1374 H2C_8723B_TXBF = 0x41, 1375 H2C_8723B_RSSI_SETTING = 0x42, 1376 H2C_8723B_AP_REQ_TXRPT = 0x43, 1377 H2C_8723B_INIT_RATE_COLLECT = 0x44, 1378 1379 /* 1380 * BT Class: 011 1381 */ 1382 H2C_8723B_B_TYPE_TDMA = 0x60, 1383 H2C_8723B_BT_INFO = 0x61, 1384 H2C_8723B_FORCE_BT_TXPWR = 0x62, 1385 H2C_8723B_BT_IGNORE_WLANACT = 0x63, 1386 H2C_8723B_DAC_SWING_VALUE = 0x64, 1387 H2C_8723B_ANT_SEL_RSV = 0x65, 1388 H2C_8723B_WL_OPMODE = 0x66, 1389 H2C_8723B_BT_MP_OPER = 0x67, 1390 H2C_8723B_BT_CONTROL = 0x68, 1391 H2C_8723B_BT_WIFI_CTRL = 0x69, 1392 H2C_8723B_BT_FW_PATCH = 0x6a, 1393 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, 1394 H2C_8723B_BT_GRANT = 0x6e, 1395 1396 /* 1397 * WOWLAN Class: 100 1398 */ 1399 H2C_8723B_WOWLAN = 0x80, 1400 H2C_8723B_REMOTE_WAKE_CTRL = 0x81, 1401 H2C_8723B_AOAC_GLOBAL_INFO = 0x82, 1402 H2C_8723B_AOAC_RSVD_PAGE = 0x83, 1403 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, 1404 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, 1405 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, 1406 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, 1407 1408 H2C_8723B_RESET_TSF = 0xC0, 1409 }; 1410 1411 1412 struct h2c_cmd { 1413 union { 1414 struct { 1415 u8 cmd; 1416 u8 data[7]; 1417 } __packed cmd; 1418 struct { 1419 __le32 data; 1420 __le16 ext; 1421 } __packed raw; 1422 struct { 1423 __le32 data; 1424 __le32 ext; 1425 } __packed raw_wide; 1426 struct { 1427 u8 cmd; 1428 u8 data; 1429 } __packed joinbss; 1430 struct { 1431 u8 cmd; 1432 __le16 mask_hi; 1433 u8 arg; 1434 __le16 mask_lo; 1435 } __packed ramask; 1436 struct { 1437 u8 cmd; 1438 u8 parm; 1439 u8 macid; 1440 u8 macid_end; 1441 } __packed media_status_rpt; 1442 struct { 1443 u8 cmd; 1444 u8 macid; 1445 /* 1446 * [0:4] - RAID 1447 * [7] - SGI 1448 */ 1449 u8 data1; 1450 /* 1451 * [0:1] - Bandwidth 1452 * [3] - No Update 1453 * [4:5] - VHT enable 1454 * [6] - DISPT 1455 * [7] - DISRA 1456 */ 1457 u8 data2; 1458 u8 ramask0; 1459 u8 ramask1; 1460 u8 ramask2; 1461 u8 ramask3; 1462 } __packed b_macid_cfg; 1463 struct { 1464 u8 cmd; 1465 u8 data1; 1466 u8 data2; 1467 u8 data3; 1468 u8 data4; 1469 u8 data5; 1470 } __packed b_type_dma; 1471 struct { 1472 u8 cmd; 1473 u8 data; 1474 } __packed bt_info; 1475 struct { 1476 u8 cmd; 1477 u8 operreq; 1478 u8 opcode; 1479 u8 data; 1480 u8 addr; 1481 } __packed bt_mp_oper; 1482 struct { 1483 u8 cmd; 1484 u8 data; 1485 } __packed bt_wlan_calibration; 1486 struct { 1487 u8 cmd; 1488 u8 data; 1489 } __packed ignore_wlan; 1490 struct { 1491 u8 cmd; 1492 u8 ant_inverse; 1493 u8 int_switch_type; 1494 } __packed ant_sel_rsv; 1495 struct { 1496 u8 cmd; 1497 u8 data; 1498 } __packed bt_grant; 1499 struct { 1500 u8 cmd; 1501 u8 macid; 1502 u8 unknown0; 1503 u8 rssi; 1504 /* 1505 * [0] - is_rx 1506 * [1] - stbc_en 1507 * [2] - noisy_decision 1508 * [6] - bf_en 1509 */ 1510 u8 data; 1511 /* 1512 * [0:6] - ra_th_offset 1513 * [7] - ra_offset_direction 1514 */ 1515 u8 ra_th_offset; 1516 u8 unknown1; 1517 u8 unknown2; 1518 } __packed rssi_report; 1519 }; 1520 }; 1521 1522 enum c2h_evt_8723b { 1523 C2H_8723B_DEBUG = 0, 1524 C2H_8723B_TSF = 1, 1525 C2H_8723B_AP_RPT_RSP = 2, 1526 C2H_8723B_CCX_TX_RPT = 3, 1527 C2H_8723B_BT_RSSI = 4, 1528 C2H_8723B_BT_OP_MODE = 5, 1529 C2H_8723B_EXT_RA_RPT = 6, 1530 C2H_8723B_BT_INFO = 9, 1531 C2H_8723B_HW_INFO_EXCH = 0x0a, 1532 C2H_8723B_BT_MP_INFO = 0x0b, 1533 C2H_8723B_RA_REPORT = 0x0c, 1534 C2H_8723B_FW_DEBUG = 0xff, 1535 }; 1536 1537 enum bt_info_src_8723b { 1538 BT_INFO_SRC_8723B_WIFI_FW = 0x0, 1539 BT_INFO_SRC_8723B_BT_RSP = 0x1, 1540 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, 1541 }; 1542 1543 enum bt_mp_oper_opcode_8723b { 1544 BT_MP_OP_GET_BT_VERSION = 0x00, 1545 BT_MP_OP_RESET = 0x01, 1546 BT_MP_OP_TEST_CTRL = 0x02, 1547 BT_MP_OP_SET_BT_MODE = 0x03, 1548 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, 1549 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, 1550 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, 1551 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, 1552 BT_MP_OP_SET_PKT_HEADER = 0x08, 1553 BT_MP_OP_SET_WHITENCOEFF = 0x09, 1554 BT_MP_OP_SET_BD_ADDR_L = 0x0a, 1555 BT_MP_OP_SET_BD_ADDR_H = 0x0b, 1556 BT_MP_OP_WRITE_REG_ADDR = 0x0c, 1557 BT_MP_OP_WRITE_REG_VALUE = 0x0d, 1558 BT_MP_OP_GET_BT_STATUS = 0x0e, 1559 BT_MP_OP_GET_BD_ADDR_L = 0x0f, 1560 BT_MP_OP_GET_BD_ADDR_H = 0x10, 1561 BT_MP_OP_READ_REG = 0x11, 1562 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, 1563 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, 1564 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, 1565 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, 1566 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, 1567 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, 1568 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, 1569 BT_MP_OP_GET_RSSI = 0x19, 1570 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, 1571 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, 1572 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, 1573 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, 1574 BT_MP_OP_GET_AFH_MAP_L = 0x1e, 1575 BT_MP_OP_GET_AFH_MAP_M = 0x1f, 1576 BT_MP_OP_GET_AFH_MAP_H = 0x20, 1577 BT_MP_OP_GET_AFH_STATUS = 0x21, 1578 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, 1579 BT_MP_OP_SET_THERMAL_METER = 0x23, 1580 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, 1581 }; 1582 1583 enum rtl8xxxu_bw_mode { 1584 RTL8XXXU_CHANNEL_WIDTH_20 = 0, 1585 RTL8XXXU_CHANNEL_WIDTH_40 = 1, 1586 RTL8XXXU_CHANNEL_WIDTH_80 = 2, 1587 RTL8XXXU_CHANNEL_WIDTH_160 = 3, 1588 RTL8XXXU_CHANNEL_WIDTH_80_80 = 4, 1589 RTL8XXXU_CHANNEL_WIDTH_MAX = 5, 1590 }; 1591 1592 struct rtl8723bu_c2h { 1593 u8 id; 1594 u8 seq; 1595 union { 1596 struct { 1597 u8 payload[0]; 1598 } __packed raw; 1599 struct { 1600 u8 ext_id; 1601 u8 status:4; 1602 u8 retlen:4; 1603 u8 opcode_ver:4; 1604 u8 req_num:4; 1605 u8 payload[2]; 1606 } __packed bt_mp_info; 1607 struct { 1608 u8 response_source:4; 1609 u8 dummy0_0:4; 1610 1611 u8 bt_info; 1612 1613 u8 retry_count:4; 1614 u8 dummy2_0:1; 1615 u8 bt_page:1; 1616 u8 tx_rx_mask:1; 1617 u8 dummy2_2:1; 1618 1619 u8 rssi; 1620 1621 u8 basic_rate:1; 1622 u8 bt_has_reset:1; 1623 u8 dummy4_1:1; 1624 u8 ignore_wlan:1; 1625 u8 auto_report:1; 1626 u8 dummy4_2:3; 1627 1628 u8 a4; 1629 u8 a5; 1630 } __packed bt_info; 1631 struct { 1632 u8 rate:7; 1633 u8 sgi:1; 1634 u8 macid; 1635 u8 ldpc:1; 1636 u8 txbf:1; 1637 u8 noisy_state:1; 1638 u8 dummy2_0:5; 1639 u8 dummy3_0; 1640 u8 dummy4_0; 1641 u8 dummy5_0; 1642 u8 bw; 1643 } __packed ra_report; 1644 }; 1645 } __packed; 1646 1647 struct rtl8xxxu_fileops; 1648 1649 /*mlme related.*/ 1650 enum wireless_mode { 1651 WIRELESS_MODE_UNKNOWN = 0, 1652 /* Sub-Element */ 1653 WIRELESS_MODE_B = BIT(0), 1654 WIRELESS_MODE_G = BIT(1), 1655 WIRELESS_MODE_A = BIT(2), 1656 WIRELESS_MODE_N_24G = BIT(3), 1657 WIRELESS_MODE_N_5G = BIT(4), 1658 WIRELESS_AUTO = BIT(5), 1659 WIRELESS_MODE_AC = BIT(6), 1660 WIRELESS_MODE_MAX = 0x7F, 1661 }; 1662 1663 /* from rtlwifi/wifi.h */ 1664 enum ratr_table_mode_new { 1665 RATEID_IDX_BGN_40M_2SS = 0, 1666 RATEID_IDX_BGN_40M_1SS = 1, 1667 RATEID_IDX_BGN_20M_2SS_BN = 2, 1668 RATEID_IDX_BGN_20M_1SS_BN = 3, 1669 RATEID_IDX_GN_N2SS = 4, 1670 RATEID_IDX_GN_N1SS = 5, 1671 RATEID_IDX_BG = 6, 1672 RATEID_IDX_G = 7, 1673 RATEID_IDX_B = 8, 1674 RATEID_IDX_VHT_2SS = 9, 1675 RATEID_IDX_VHT_1SS = 10, 1676 RATEID_IDX_MIX1 = 11, 1677 RATEID_IDX_MIX2 = 12, 1678 RATEID_IDX_VHT_3SS = 13, 1679 RATEID_IDX_BGN_3SS = 14, 1680 }; 1681 1682 #define BT_INFO_8723B_1ANT_B_FTP BIT(7) 1683 #define BT_INFO_8723B_1ANT_B_A2DP BIT(6) 1684 #define BT_INFO_8723B_1ANT_B_HID BIT(5) 1685 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) 1686 #define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) 1687 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) 1688 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) 1689 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) 1690 1691 enum _BT_8723B_1ANT_STATUS { 1692 BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE = 0x0, 1693 BT_8723B_1ANT_STATUS_CONNECTED_IDLE = 0x1, 1694 BT_8723B_1ANT_STATUS_INQ_PAGE = 0x2, 1695 BT_8723B_1ANT_STATUS_ACL_BUSY = 0x3, 1696 BT_8723B_1ANT_STATUS_SCO_BUSY = 0x4, 1697 BT_8723B_1ANT_STATUS_ACL_SCO_BUSY = 0x5, 1698 BT_8723B_1ANT_STATUS_MAX 1699 }; 1700 1701 struct rtl8xxxu_btcoex { 1702 u8 bt_status; 1703 bool bt_busy; 1704 bool has_sco; 1705 bool has_a2dp; 1706 bool has_hid; 1707 bool has_pan; 1708 bool hid_only; 1709 bool a2dp_only; 1710 bool c2h_bt_inquiry; 1711 }; 1712 1713 #define RTL8XXXU_RATR_STA_INIT 0 1714 #define RTL8XXXU_RATR_STA_HIGH 1 1715 #define RTL8XXXU_RATR_STA_MID 2 1716 #define RTL8XXXU_RATR_STA_LOW 3 1717 1718 #define RTL8XXXU_NOISE_FLOOR_MIN -100 1719 #define RTL8XXXU_SNR_THRESH_HIGH 50 1720 #define RTL8XXXU_SNR_THRESH_LOW 20 1721 1722 struct rtl8xxxu_ra_report { 1723 struct rate_info txrate; 1724 u32 bit_rate; 1725 u8 desc_rate; 1726 }; 1727 1728 struct rtl8xxxu_ra_info { 1729 u8 rate_id; 1730 u32 rate_mask; 1731 u32 ra_use_rate; 1732 u8 rate_sgi; 1733 u8 rssi_sta_ra; /* Percentage */ 1734 u8 pre_rssi_sta_ra; 1735 u8 sgi_enable; 1736 u8 decision_rate; 1737 u8 pre_rate; 1738 u8 highest_rate; 1739 u8 lowest_rate; 1740 u32 nsc_up; 1741 u32 nsc_down; 1742 u32 total; 1743 u16 retry[5]; 1744 u16 drop; 1745 u16 rpt_time; 1746 u16 pre_min_rpt_time; 1747 u8 dynamic_tx_rpt_timing_counter; 1748 u8 ra_waiting_counter; 1749 u8 ra_pending_counter; 1750 u8 ra_drop_after_down; 1751 u8 pt_try_state; /* 0 trying state, 1 for decision state */ 1752 u8 pt_stage; /* 0~6 */ 1753 u8 pt_stop_count; /* Stop PT counter */ 1754 u8 pt_pre_rate; /* if rate change do PT */ 1755 u8 pt_pre_rssi; /* if RSSI change 5% do PT */ 1756 u8 pt_mode_ss; /* decide which rate should do PT */ 1757 u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */ 1758 u8 pt_smooth_factor; 1759 }; 1760 1761 #define CFO_TH_XTAL_HIGH 20 /* kHz */ 1762 #define CFO_TH_XTAL_LOW 10 /* kHz */ 1763 #define CFO_TH_ATC 80 /* kHz */ 1764 1765 struct rtl8xxxu_cfo_tracking { 1766 bool adjust; 1767 bool atc_status; 1768 int cfo_tail[2]; 1769 u8 crystal_cap; 1770 u32 packet_count; 1771 u32 packet_count_pre; 1772 }; 1773 1774 #define RTL8XXXU_HW_LED_CONTROL 2 1775 #define RTL8XXXU_MAX_MAC_ID_NUM 128 1776 #define RTL8XXXU_BC_MC_MACID 0 1777 1778 struct rtl8xxxu_priv { 1779 struct ieee80211_hw *hw; 1780 struct usb_device *udev; 1781 struct rtl8xxxu_fileops *fops; 1782 1783 spinlock_t tx_urb_lock; 1784 struct list_head tx_urb_free_list; 1785 int tx_urb_free_count; 1786 bool tx_stopped; 1787 1788 spinlock_t rx_urb_lock; 1789 struct list_head rx_urb_pending_list; 1790 int rx_urb_pending_count; 1791 bool shutdown; 1792 struct work_struct rx_urb_wq; 1793 1794 u8 mac_addr[ETH_ALEN]; 1795 char chip_name[8]; 1796 char chip_vendor[8]; 1797 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1798 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1799 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1800 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1801 /* 1802 * The following entries are half-bytes split as: 1803 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1804 */ 1805 struct rtl8723au_idx ht40_2s_tx_power_index_diff[ 1806 RTL8723A_CHANNEL_GROUPS]; 1807 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1808 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1809 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1810 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1811 /* 1812 * Newer generation chips only keep power diffs per TX count, 1813 * not per channel group. 1814 */ 1815 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT]; 1816 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT]; 1817 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT]; 1818 struct rtl8xxxu_power_base *power_base; 1819 u8 package_type; 1820 u32 chip_cut:4; 1821 u32 rom_rev:4; 1822 u32 is_multi_func:1; 1823 u32 has_wifi:1; 1824 u32 has_bluetooth:1; 1825 u32 enable_bluetooth:1; 1826 u32 has_gps:1; 1827 u32 hi_pa:1; 1828 u32 vendor_umc:1; 1829 u32 vendor_smic:1; 1830 u32 has_polarity_ctrl:1; 1831 u32 has_eeprom:1; 1832 u32 boot_eeprom:1; 1833 u32 usb_interrupts:1; 1834 u32 ep_tx_high_queue:1; 1835 u32 ep_tx_normal_queue:1; 1836 u32 ep_tx_low_queue:1; 1837 u32 rx_buf_aggregation:1; 1838 u32 cck_agc_report_type:1; 1839 u32 cck_new_agc:1; 1840 u8 default_crystal_cap; 1841 u8 rfe_type; 1842 unsigned int pipe_interrupt; 1843 unsigned int pipe_in; 1844 unsigned int pipe_out[TXDESC_QUEUE_MAX]; 1845 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; 1846 u8 ep_tx_count; 1847 u8 rf_paths; 1848 u8 rx_paths; 1849 u8 tx_paths; 1850 u32 rege94; 1851 u32 rege9c; 1852 u32 regeb4; 1853 u32 regebc; 1854 u32 regrcr; 1855 int next_mbox; 1856 int nr_out_eps; 1857 1858 struct mutex h2c_mutex; 1859 /* Protect the indirect register accesses of RTL8710BU. */ 1860 struct mutex syson_indirect_access_mutex; 1861 1862 struct usb_anchor rx_anchor; 1863 struct usb_anchor tx_anchor; 1864 struct usb_anchor int_anchor; 1865 struct rtl8xxxu_firmware_header *fw_data; 1866 size_t fw_size; 1867 struct mutex usb_buf_mutex; 1868 union { 1869 __le32 val32; 1870 __le16 val16; 1871 u8 val8; 1872 } usb_buf; 1873 union { 1874 u8 raw[EFUSE_MAP_LEN]; 1875 struct rtl8723au_efuse efuse8723; 1876 struct rtl8723bu_efuse efuse8723bu; 1877 struct rtl8192cu_efuse efuse8192; 1878 struct rtl8192eu_efuse efuse8192eu; 1879 struct rtl8188fu_efuse efuse8188fu; 1880 struct rtl8188eu_efuse efuse8188eu; 1881 struct rtl8710bu_efuse efuse8710bu; 1882 struct rtl8192fu_efuse efuse8192fu; 1883 } efuse_wifi; 1884 u32 adda_backup[RTL8XXXU_ADDA_REGS]; 1885 u32 mac_backup[RTL8XXXU_MAC_REGS]; 1886 u32 bb_backup[RTL8XXXU_BB_REGS]; 1887 u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; 1888 enum rtl8xxxu_rtl_chip rtl_chip; 1889 u8 pi_enabled:1; 1890 u8 no_pape:1; 1891 u8 int_buf[USB_INTR_CONTENT_LENGTH]; 1892 u8 rssi_level; 1893 DECLARE_BITMAP(tx_aggr_started, IEEE80211_NUM_TIDS); 1894 DECLARE_BITMAP(tid_tx_operational, IEEE80211_NUM_TIDS); 1895 /* 1896 * Only one virtual interface permitted because only STA mode 1897 * is supported and no iface_combinations are provided. 1898 */ 1899 struct ieee80211_vif *vif; 1900 struct delayed_work ra_watchdog; 1901 struct work_struct c2hcmd_work; 1902 struct sk_buff_head c2hcmd_queue; 1903 struct work_struct update_beacon_work; 1904 struct rtl8xxxu_btcoex bt_coex; 1905 struct rtl8xxxu_ra_report ra_report; 1906 struct rtl8xxxu_cfo_tracking cfo_tracking; 1907 struct rtl8xxxu_ra_info ra_info; 1908 1909 bool led_registered; 1910 char led_name[32]; 1911 struct led_classdev led_cdev; 1912 DECLARE_BITMAP(mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM); 1913 }; 1914 1915 struct rtl8xxxu_sta_info { 1916 struct ieee80211_sta *sta; 1917 struct ieee80211_vif *vif; 1918 1919 u8 macid; 1920 }; 1921 1922 struct rtl8xxxu_rx_urb { 1923 struct urb urb; 1924 struct ieee80211_hw *hw; 1925 struct list_head list; 1926 }; 1927 1928 struct rtl8xxxu_tx_urb { 1929 struct urb urb; 1930 struct ieee80211_hw *hw; 1931 struct list_head list; 1932 }; 1933 1934 struct rtl8xxxu_fileops { 1935 int (*identify_chip) (struct rtl8xxxu_priv *priv); 1936 int (*read_efuse) (struct rtl8xxxu_priv *priv); 1937 int (*parse_efuse) (struct rtl8xxxu_priv *priv); 1938 int (*load_firmware) (struct rtl8xxxu_priv *priv); 1939 int (*power_on) (struct rtl8xxxu_priv *priv); 1940 void (*power_off) (struct rtl8xxxu_priv *priv); 1941 void (*reset_8051) (struct rtl8xxxu_priv *priv); 1942 int (*llt_init) (struct rtl8xxxu_priv *priv); 1943 void (*init_phy_bb) (struct rtl8xxxu_priv *priv); 1944 int (*init_phy_rf) (struct rtl8xxxu_priv *priv); 1945 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); 1946 void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv); 1947 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); 1948 void (*config_channel) (struct ieee80211_hw *hw); 1949 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1950 void (*parse_phystats) (struct rtl8xxxu_priv *priv, 1951 struct ieee80211_rx_status *rx_status, 1952 struct rtl8723au_phy_stats *phy_stats, 1953 u32 rxmcs, struct ieee80211_hdr *hdr, 1954 bool crc_icv_err); 1955 void (*init_aggregation) (struct rtl8xxxu_priv *priv); 1956 void (*init_statistics) (struct rtl8xxxu_priv *priv); 1957 void (*init_burst) (struct rtl8xxxu_priv *priv); 1958 void (*enable_rf) (struct rtl8xxxu_priv *priv); 1959 void (*disable_rf) (struct rtl8xxxu_priv *priv); 1960 void (*usb_quirks) (struct rtl8xxxu_priv *priv); 1961 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel, 1962 bool ht40); 1963 void (*update_rate_mask) (struct rtl8xxxu_priv *priv, 1964 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, 1965 u8 macid); 1966 void (*report_connect) (struct rtl8xxxu_priv *priv, 1967 u8 macid, u8 role, bool connect); 1968 void (*report_rssi) (struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 1969 void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1970 struct ieee80211_tx_info *tx_info, 1971 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1972 bool short_preamble, bool ampdu_enable, 1973 u32 rts_rate, u8 macid); 1974 void (*set_crystal_cap) (struct rtl8xxxu_priv *priv, u8 crystal_cap); 1975 s8 (*cck_rssi) (struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); 1976 int (*led_classdev_brightness_set) (struct led_classdev *led_cdev, 1977 enum led_brightness brightness); 1978 int writeN_block_size; 1979 int rx_agg_buf_size; 1980 char tx_desc_size; 1981 char rx_desc_size; 1982 u8 has_s0s1:1; 1983 u8 has_tx_report:1; 1984 u8 gen2_thermal_meter:1; 1985 u8 needs_full_init:1; 1986 u8 init_reg_rxfltmap:1; 1987 u8 init_reg_pkt_life_time:1; 1988 u8 init_reg_hmtfr:1; 1989 u8 ampdu_max_time; 1990 u8 ustime_tsf_edca; 1991 u16 max_aggr_num; 1992 u8 supports_ap:1; 1993 u16 max_macid_num; 1994 u32 adda_1t_init; 1995 u32 adda_1t_path_on; 1996 u32 adda_2t_path_on_a; 1997 u32 adda_2t_path_on_b; 1998 u16 trxff_boundary; 1999 u8 pbp_rx; 2000 u8 pbp_tx; 2001 const struct rtl8xxxu_reg8val *mactable; 2002 u8 total_page_num; 2003 u8 page_num_hi; 2004 u8 page_num_lo; 2005 u8 page_num_norm; 2006 u8 last_llt_entry; 2007 }; 2008 2009 extern int rtl8xxxu_debug; 2010 2011 extern const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; 2012 extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; 2013 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); 2014 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); 2015 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr); 2016 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); 2017 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); 2018 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); 2019 int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); 2020 int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); 2021 int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); 2022 int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); 2023 int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); 2024 int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); 2025 int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, 2026 u32 mask, u32 val); 2027 2028 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 2029 enum rtl8xxxu_rfpath path, u8 reg); 2030 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 2031 enum rtl8xxxu_rfpath path, u8 reg, u32 data); 2032 int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, 2033 enum rtl8xxxu_rfpath path, u8 reg, 2034 u32 mask, u32 val); 2035 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2036 u32 *backup, int count); 2037 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2038 u32 *backup, int count); 2039 void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, 2040 const u32 *reg, u32 *backup); 2041 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 2042 const u32 *reg, u32 *backup); 2043 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 2044 bool path_a_on); 2045 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 2046 const u32 *regs, u32 *backup); 2047 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2048 int result[][8], int candidate, bool tx_only); 2049 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2050 int result[][8], int candidate, bool tx_only); 2051 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2052 const struct rtl8xxxu_rfregval *table, 2053 enum rtl8xxxu_rfpath path); 2054 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2055 const struct rtl8xxxu_reg32val *array); 2056 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name); 2057 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); 2058 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); 2059 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor); 2060 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor); 2061 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv); 2062 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv); 2063 int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data); 2064 int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv); 2065 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); 2066 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); 2067 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); 2068 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 2069 void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 2070 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); 2071 int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, 2072 struct h2c_cmd *h2c, int len); 2073 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv); 2074 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv); 2075 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv); 2076 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv); 2077 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv); 2078 void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, 2079 int channel, bool ht40); 2080 void rtl8188f_channel_to_group(int channel, int *group, int *cck_group); 2081 void rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, 2082 int channel, bool ht40); 2083 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw); 2084 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw); 2085 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv); 2086 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv); 2087 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 2088 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid); 2089 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 2090 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid); 2091 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 2092 u8 macid, u8 role, bool connect); 2093 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 2094 u8 macid, u8 role, bool connect); 2095 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 2096 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 2097 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv); 2098 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv); 2099 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv); 2100 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv); 2101 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv); 2102 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2103 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2104 void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, 2105 struct ieee80211_rx_status *rx_status, 2106 struct rtl8723au_phy_stats *phy_stats, 2107 u32 rxmcs, struct ieee80211_hdr *hdr, 2108 bool crc_icv_err); 2109 void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, 2110 struct ieee80211_rx_status *rx_status, 2111 struct rtl8723au_phy_stats *phy_stats, 2112 u32 rxmcs, struct ieee80211_hdr *hdr, 2113 bool crc_icv_err); 2114 int rtl8xxxu_gen2_channel_to_group(int channel); 2115 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2116 int result[][8], int c1, int c2); 2117 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2118 int result[][8], int c1, int c2); 2119 void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2120 struct ieee80211_tx_info *tx_info, 2121 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 2122 bool short_preamble, bool ampdu_enable, 2123 u32 rts_rate, u8 macid); 2124 void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2125 struct ieee80211_tx_info *tx_info, 2126 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 2127 bool short_preamble, bool ampdu_enable, 2128 u32 rts_rate, u8 macid); 2129 void rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2130 struct ieee80211_tx_info *tx_info, 2131 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 2132 bool short_preamble, bool ampdu_enable, 2133 u32 rts_rate, u8 macid); 2134 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 2135 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); 2136 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv); 2137 void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 2138 void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 2139 s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); 2140 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 2141 u8 rate, u8 sgi, u8 bw); 2142 void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra); 2143 void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2144 2145 extern struct rtl8xxxu_fileops rtl8192fu_fops; 2146 extern struct rtl8xxxu_fileops rtl8710bu_fops; 2147 extern struct rtl8xxxu_fileops rtl8188fu_fops; 2148 extern struct rtl8xxxu_fileops rtl8188eu_fops; 2149 extern struct rtl8xxxu_fileops rtl8192cu_fops; 2150 extern struct rtl8xxxu_fileops rtl8192eu_fops; 2151 extern struct rtl8xxxu_fileops rtl8723au_fops; 2152 extern struct rtl8xxxu_fileops rtl8723bu_fops; 2153
