1 /*
2 * Based on arch/arm/include/asm/traps.h
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18 #ifndef __ASM_TRAP_H
19 #define __ASM_TRAP_H
20
21 #include <linux/list.h>
22 #include <asm/esr.h>
23 #include <asm/sections.h>
24
25 struct pt_regs;
26
27 struct undef_hook {
28 struct list_head node;
29 u32 instr_mask;
30 u32 instr_val;
31 u64 pstate_mask;
32 u64 pstate_val;
33 int (*fn)(struct pt_regs *regs, u32 instr);
34 };
35
36 void register_undef_hook(struct undef_hook *hook);
37 void unregister_undef_hook(struct undef_hook *hook);
38 void force_signal_inject(int signal, int code, unsigned long address);
39 void arm64_notify_segfault(unsigned long addr);
40 void arm64_force_sig_info(struct siginfo *info, const char *str,
41 struct task_struct *tsk);
42
43 /*
44 * Move regs->pc to next instruction and do necessary setup before it
45 * is executed.
46 */
47 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size);
48
__in_irqentry_text(unsigned long ptr)49 static inline int __in_irqentry_text(unsigned long ptr)
50 {
51 return ptr >= (unsigned long)&__irqentry_text_start &&
52 ptr < (unsigned long)&__irqentry_text_end;
53 }
54
in_exception_text(unsigned long ptr)55 static inline int in_exception_text(unsigned long ptr)
56 {
57 int in;
58
59 in = ptr >= (unsigned long)&__exception_text_start &&
60 ptr < (unsigned long)&__exception_text_end;
61
62 return in ? : __in_irqentry_text(ptr);
63 }
64
in_entry_text(unsigned long ptr)65 static inline int in_entry_text(unsigned long ptr)
66 {
67 return ptr >= (unsigned long)&__entry_text_start &&
68 ptr < (unsigned long)&__entry_text_end;
69 }
70
71 /*
72 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit
73 * to indicate whether this ESR has a RAS encoding. CPUs without this feature
74 * have a ISS-Valid bit in the same position.
75 * If this bit is set, we know its not a RAS SError.
76 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS
77 * errors share the same encoding as an all-zeros encoding from a CPU that
78 * doesn't support RAS.
79 */
arm64_is_ras_serror(u32 esr)80 static inline bool arm64_is_ras_serror(u32 esr)
81 {
82 WARN_ON(preemptible());
83
84 if (esr & ESR_ELx_IDS)
85 return false;
86
87 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN))
88 return true;
89 else
90 return false;
91 }
92
93 /*
94 * Return the AET bits from a RAS SError's ESR.
95 *
96 * It is implementation defined whether Uncategorized errors are containable.
97 * We treat them as Uncontainable.
98 * Non-RAS SError's are reported as Uncontained/Uncategorized.
99 */
arm64_ras_serror_get_severity(u32 esr)100 static inline u32 arm64_ras_serror_get_severity(u32 esr)
101 {
102 u32 aet = esr & ESR_ELx_AET;
103
104 if (!arm64_is_ras_serror(esr)) {
105 /* Not a RAS error, we can't interpret the ESR. */
106 return ESR_ELx_AET_UC;
107 }
108
109 /*
110 * AET is RES0 if 'the value returned in the DFSC field is not
111 * [ESR_ELx_FSC_SERROR]'
112 */
113 if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) {
114 /* No severity information : Uncategorized */
115 return ESR_ELx_AET_UC;
116 }
117
118 return aet;
119 }
120
121 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr);
122 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr);
123 #endif
124
