1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26 #include <linux/firmware.h>
27 #include <drm/drm_drv.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_xgmi.h"
33 #include "soc15_common.h"
34 #include "psp_v3_1.h"
35 #include "psp_v10_0.h"
36 #include "psp_v11_0.h"
37 #include "psp_v11_0_8.h"
38 #include "psp_v12_0.h"
39 #include "psp_v13_0.h"
40
41 #include "amdgpu_ras.h"
42 #include "amdgpu_securedisplay.h"
43 #include "amdgpu_atomfirmware.h"
44
45 static int psp_sysfs_init(struct amdgpu_device *adev);
46 static void psp_sysfs_fini(struct amdgpu_device *adev);
47
48 static int psp_load_smu_fw(struct psp_context *psp);
49
50 /*
51 * Due to DF Cstate management centralized to PMFW, the firmware
52 * loading sequence will be updated as below:
53 * - Load KDB
54 * - Load SYS_DRV
55 * - Load tOS
56 * - Load PMFW
57 * - Setup TMR
58 * - Load other non-psp fw
59 * - Load ASD
60 * - Load XGMI/RAS/HDCP/DTM TA if any
61 *
62 * This new sequence is required for
63 * - Arcturus and onwards
64 * - Navi12 and onwards
65 */
psp_check_pmfw_centralized_cstate_management(struct psp_context * psp)66 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
67 {
68 struct amdgpu_device *adev = psp->adev;
69
70 psp->pmfw_centralized_cstate_management = false;
71
72 if (amdgpu_sriov_vf(adev))
73 return;
74
75 if (adev->flags & AMD_IS_APU)
76 return;
77
78 if ((adev->asic_type >= CHIP_ARCTURUS) ||
79 (adev->asic_type >= CHIP_NAVI12))
80 psp->pmfw_centralized_cstate_management = true;
81 }
82
psp_early_init(void * handle)83 static int psp_early_init(void *handle)
84 {
85 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
86 struct psp_context *psp = &adev->psp;
87
88 switch (adev->asic_type) {
89 case CHIP_VEGA10:
90 case CHIP_VEGA12:
91 psp_v3_1_set_psp_funcs(psp);
92 psp->autoload_supported = false;
93 break;
94 case CHIP_RAVEN:
95 psp_v10_0_set_psp_funcs(psp);
96 psp->autoload_supported = false;
97 break;
98 case CHIP_VEGA20:
99 case CHIP_ARCTURUS:
100 psp_v11_0_set_psp_funcs(psp);
101 psp->autoload_supported = false;
102 break;
103 case CHIP_NAVI10:
104 case CHIP_NAVI14:
105 case CHIP_NAVI12:
106 case CHIP_SIENNA_CICHLID:
107 case CHIP_NAVY_FLOUNDER:
108 case CHIP_VANGOGH:
109 case CHIP_DIMGREY_CAVEFISH:
110 case CHIP_BEIGE_GOBY:
111 psp_v11_0_set_psp_funcs(psp);
112 psp->autoload_supported = true;
113 break;
114 case CHIP_RENOIR:
115 psp_v12_0_set_psp_funcs(psp);
116 break;
117 case CHIP_ALDEBARAN:
118 psp_v13_0_set_psp_funcs(psp);
119 break;
120 case CHIP_YELLOW_CARP:
121 psp_v13_0_set_psp_funcs(psp);
122 psp->autoload_supported = true;
123 break;
124 case CHIP_CYAN_SKILLFISH:
125 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
126 psp_v11_0_8_set_psp_funcs(psp);
127 psp->autoload_supported = false;
128 }
129 break;
130 default:
131 return -EINVAL;
132 }
133
134 psp->adev = adev;
135
136 psp_check_pmfw_centralized_cstate_management(psp);
137
138 return 0;
139 }
140
psp_memory_training_fini(struct psp_context * psp)141 static void psp_memory_training_fini(struct psp_context *psp)
142 {
143 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
144
145 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
146 kfree(ctx->sys_cache);
147 ctx->sys_cache = NULL;
148 }
149
psp_memory_training_init(struct psp_context * psp)150 static int psp_memory_training_init(struct psp_context *psp)
151 {
152 int ret;
153 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
154
155 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
156 DRM_DEBUG("memory training is not supported!\n");
157 return 0;
158 }
159
160 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
161 if (ctx->sys_cache == NULL) {
162 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
163 ret = -ENOMEM;
164 goto Err_out;
165 }
166
167 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
168 ctx->train_data_size,
169 ctx->p2c_train_data_offset,
170 ctx->c2p_train_data_offset);
171 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
172 return 0;
173
174 Err_out:
175 psp_memory_training_fini(psp);
176 return ret;
177 }
178
179 /*
180 * Helper funciton to query psp runtime database entry
181 *
182 * @adev: amdgpu_device pointer
183 * @entry_type: the type of psp runtime database entry
184 * @db_entry: runtime database entry pointer
185 *
186 * Return false if runtime database doesn't exit or entry is invalid
187 * or true if the specific database entry is found, and copy to @db_entry
188 */
psp_get_runtime_db_entry(struct amdgpu_device * adev,enum psp_runtime_entry_type entry_type,void * db_entry)189 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
190 enum psp_runtime_entry_type entry_type,
191 void *db_entry)
192 {
193 uint64_t db_header_pos, db_dir_pos;
194 struct psp_runtime_data_header db_header = {0};
195 struct psp_runtime_data_directory db_dir = {0};
196 bool ret = false;
197 int i;
198
199 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
200 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
201
202 /* read runtime db header from vram */
203 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
204 sizeof(struct psp_runtime_data_header), false);
205
206 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
207 /* runtime db doesn't exist, exit */
208 dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
209 return false;
210 }
211
212 /* read runtime database entry from vram */
213 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
214 sizeof(struct psp_runtime_data_directory), false);
215
216 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
217 /* invalid db entry count, exit */
218 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
219 return false;
220 }
221
222 /* look up for requested entry type */
223 for (i = 0; i < db_dir.entry_count && !ret; i++) {
224 if (db_dir.entry_list[i].entry_type == entry_type) {
225 switch (entry_type) {
226 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
227 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
228 /* invalid db entry size */
229 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n");
230 return false;
231 }
232 /* read runtime database entry */
233 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
234 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
235 ret = true;
236 break;
237 default:
238 ret = false;
239 break;
240 }
241 }
242 }
243
244 return ret;
245 }
246
psp_sw_init(void * handle)247 static int psp_sw_init(void *handle)
248 {
249 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
250 struct psp_context *psp = &adev->psp;
251 int ret;
252 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
253 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
254
255 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
256 if (!psp->cmd) {
257 DRM_ERROR("Failed to allocate memory to command buffer!\n");
258 ret = -ENOMEM;
259 }
260
261 if (!amdgpu_sriov_vf(adev)) {
262 ret = psp_init_microcode(psp);
263 if (ret) {
264 DRM_ERROR("Failed to load psp firmware!\n");
265 return ret;
266 }
267 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) {
268 ret = psp_init_ta_microcode(psp, "aldebaran");
269 if (ret) {
270 DRM_ERROR("Failed to initialize ta microcode!\n");
271 return ret;
272 }
273 }
274
275 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
276 if (psp_get_runtime_db_entry(adev,
277 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
278 &boot_cfg_entry)) {
279 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
280 if ((psp->boot_cfg_bitmask) &
281 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
282 /* If psp runtime database exists, then
283 * only enable two stage memory training
284 * when TWO_STAGE_DRAM_TRAINING bit is set
285 * in runtime database */
286 mem_training_ctx->enable_mem_training = true;
287 }
288
289 } else {
290 /* If psp runtime database doesn't exist or
291 * is invalid, force enable two stage memory
292 * training */
293 mem_training_ctx->enable_mem_training = true;
294 }
295
296 if (mem_training_ctx->enable_mem_training) {
297 ret = psp_memory_training_init(psp);
298 if (ret) {
299 DRM_ERROR("Failed to initialize memory training!\n");
300 return ret;
301 }
302
303 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
304 if (ret) {
305 DRM_ERROR("Failed to process memory training!\n");
306 return ret;
307 }
308 }
309
310 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
311 ret= psp_sysfs_init(adev);
312 if (ret) {
313 return ret;
314 }
315 }
316
317 return 0;
318 }
319
psp_sw_fini(void * handle)320 static int psp_sw_fini(void *handle)
321 {
322 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
323 struct psp_context *psp = &adev->psp;
324 struct psp_gfx_cmd_resp *cmd = psp->cmd;
325
326 psp_memory_training_fini(psp);
327 if (psp->sos_fw) {
328 release_firmware(psp->sos_fw);
329 psp->sos_fw = NULL;
330 }
331 if (psp->asd_fw) {
332 release_firmware(psp->asd_fw);
333 psp->asd_fw = NULL;
334 }
335 if (psp->ta_fw) {
336 release_firmware(psp->ta_fw);
337 psp->ta_fw = NULL;
338 }
339
340 if (adev->asic_type == CHIP_NAVI10 ||
341 adev->asic_type == CHIP_SIENNA_CICHLID)
342 psp_sysfs_fini(adev);
343
344 kfree(cmd);
345 cmd = NULL;
346
347 return 0;
348 }
349
psp_wait_for(struct psp_context * psp,uint32_t reg_index,uint32_t reg_val,uint32_t mask,bool check_changed)350 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
351 uint32_t reg_val, uint32_t mask, bool check_changed)
352 {
353 uint32_t val;
354 int i;
355 struct amdgpu_device *adev = psp->adev;
356
357 if (psp->adev->no_hw_access)
358 return 0;
359
360 for (i = 0; i < adev->usec_timeout; i++) {
361 val = RREG32(reg_index);
362 if (check_changed) {
363 if (val != reg_val)
364 return 0;
365 } else {
366 if ((val & mask) == reg_val)
367 return 0;
368 }
369 udelay(1);
370 }
371
372 return -ETIME;
373 }
374
psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)375 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
376 {
377 switch (cmd_id) {
378 case GFX_CMD_ID_LOAD_TA:
379 return "LOAD_TA";
380 case GFX_CMD_ID_UNLOAD_TA:
381 return "UNLOAD_TA";
382 case GFX_CMD_ID_INVOKE_CMD:
383 return "INVOKE_CMD";
384 case GFX_CMD_ID_LOAD_ASD:
385 return "LOAD_ASD";
386 case GFX_CMD_ID_SETUP_TMR:
387 return "SETUP_TMR";
388 case GFX_CMD_ID_LOAD_IP_FW:
389 return "LOAD_IP_FW";
390 case GFX_CMD_ID_DESTROY_TMR:
391 return "DESTROY_TMR";
392 case GFX_CMD_ID_SAVE_RESTORE:
393 return "SAVE_RESTORE_IP_FW";
394 case GFX_CMD_ID_SETUP_VMR:
395 return "SETUP_VMR";
396 case GFX_CMD_ID_DESTROY_VMR:
397 return "DESTROY_VMR";
398 case GFX_CMD_ID_PROG_REG:
399 return "PROG_REG";
400 case GFX_CMD_ID_GET_FW_ATTESTATION:
401 return "GET_FW_ATTESTATION";
402 case GFX_CMD_ID_LOAD_TOC:
403 return "ID_LOAD_TOC";
404 case GFX_CMD_ID_AUTOLOAD_RLC:
405 return "AUTOLOAD_RLC";
406 case GFX_CMD_ID_BOOT_CFG:
407 return "BOOT_CFG";
408 default:
409 return "UNKNOWN CMD";
410 }
411 }
412
413 static int
psp_cmd_submit_buf(struct psp_context * psp,struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd,uint64_t fence_mc_addr)414 psp_cmd_submit_buf(struct psp_context *psp,
415 struct amdgpu_firmware_info *ucode,
416 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
417 {
418 int ret;
419 int index, idx;
420 int timeout = 20000;
421 bool ras_intr = false;
422 bool skip_unsupport = false;
423
424 if (psp->adev->no_hw_access)
425 return 0;
426
427 if (!drm_dev_enter(&psp->adev->ddev, &idx))
428 return 0;
429
430 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
431
432 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
433
434 index = atomic_inc_return(&psp->fence_value);
435 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
436 if (ret) {
437 atomic_dec(&psp->fence_value);
438 goto exit;
439 }
440
441 amdgpu_device_invalidate_hdp(psp->adev, NULL);
442 while (*((unsigned int *)psp->fence_buf) != index) {
443 if (--timeout == 0)
444 break;
445 /*
446 * Shouldn't wait for timeout when err_event_athub occurs,
447 * because gpu reset thread triggered and lock resource should
448 * be released for psp resume sequence.
449 */
450 ras_intr = amdgpu_ras_intr_triggered();
451 if (ras_intr)
452 break;
453 usleep_range(10, 100);
454 amdgpu_device_invalidate_hdp(psp->adev, NULL);
455 }
456
457 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
458 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
459 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
460
461 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
462
463 /* In some cases, psp response status is not 0 even there is no
464 * problem while the command is submitted. Some version of PSP FW
465 * doesn't write 0 to that field.
466 * So here we would like to only print a warning instead of an error
467 * during psp initialization to avoid breaking hw_init and it doesn't
468 * return -EINVAL.
469 */
470 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
471 if (ucode)
472 DRM_WARN("failed to load ucode %s(0x%X) ",
473 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
474 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
475 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
476 psp->cmd_buf_mem->resp.status);
477 if (!timeout) {
478 ret = -EINVAL;
479 goto exit;
480 }
481 }
482
483 if (ucode) {
484 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
485 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
486 }
487
488 exit:
489 drm_dev_exit(idx);
490 return ret;
491 }
492
acquire_psp_cmd_buf(struct psp_context * psp)493 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
494 {
495 struct psp_gfx_cmd_resp *cmd = psp->cmd;
496
497 mutex_lock(&psp->mutex);
498
499 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
500
501 return cmd;
502 }
503
release_psp_cmd_buf(struct psp_context * psp)504 void release_psp_cmd_buf(struct psp_context *psp)
505 {
506 mutex_unlock(&psp->mutex);
507 }
508
psp_prep_tmr_cmd_buf(struct psp_context * psp,struct psp_gfx_cmd_resp * cmd,uint64_t tmr_mc,struct amdgpu_bo * tmr_bo)509 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
510 struct psp_gfx_cmd_resp *cmd,
511 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
512 {
513 struct amdgpu_device *adev = psp->adev;
514 uint32_t size = amdgpu_bo_size(tmr_bo);
515 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
516
517 if (amdgpu_sriov_vf(psp->adev))
518 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
519 else
520 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
521 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
522 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
523 cmd->cmd.cmd_setup_tmr.buf_size = size;
524 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
525 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
526 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
527 }
528
psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t pri_buf_mc,uint32_t size)529 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
530 uint64_t pri_buf_mc, uint32_t size)
531 {
532 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
533 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
534 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
535 cmd->cmd.cmd_load_toc.toc_size = size;
536 }
537
538 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
psp_load_toc(struct psp_context * psp,uint32_t * tmr_size)539 static int psp_load_toc(struct psp_context *psp,
540 uint32_t *tmr_size)
541 {
542 int ret;
543 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
544
545 /* Copy toc to psp firmware private buffer */
546 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
547
548 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
549
550 ret = psp_cmd_submit_buf(psp, NULL, cmd,
551 psp->fence_buf_mc_addr);
552 if (!ret)
553 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
554
555 release_psp_cmd_buf(psp);
556
557 return ret;
558 }
559
560 /* Set up Trusted Memory Region */
psp_tmr_init(struct psp_context * psp)561 static int psp_tmr_init(struct psp_context *psp)
562 {
563 int ret;
564 int tmr_size;
565 void *tmr_buf;
566 void **pptr;
567
568 /*
569 * According to HW engineer, they prefer the TMR address be "naturally
570 * aligned" , e.g. the start address be an integer divide of TMR size.
571 *
572 * Note: this memory need be reserved till the driver
573 * uninitializes.
574 */
575 tmr_size = PSP_TMR_SIZE(psp->adev);
576
577 /* For ASICs support RLC autoload, psp will parse the toc
578 * and calculate the total size of TMR needed */
579 if (!amdgpu_sriov_vf(psp->adev) &&
580 psp->toc.start_addr &&
581 psp->toc.size_bytes &&
582 psp->fw_pri_buf) {
583 ret = psp_load_toc(psp, &tmr_size);
584 if (ret) {
585 DRM_ERROR("Failed to load toc\n");
586 return ret;
587 }
588 }
589
590 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
591 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
592 AMDGPU_GEM_DOMAIN_VRAM,
593 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
594
595 return ret;
596 }
597
psp_skip_tmr(struct psp_context * psp)598 static bool psp_skip_tmr(struct psp_context *psp)
599 {
600 switch (psp->adev->asic_type) {
601 case CHIP_NAVI12:
602 case CHIP_SIENNA_CICHLID:
603 case CHIP_ALDEBARAN:
604 return true;
605 default:
606 return false;
607 }
608 }
609
psp_tmr_load(struct psp_context * psp)610 static int psp_tmr_load(struct psp_context *psp)
611 {
612 int ret;
613 struct psp_gfx_cmd_resp *cmd;
614
615 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
616 * Already set up by host driver.
617 */
618 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
619 return 0;
620
621 cmd = acquire_psp_cmd_buf(psp);
622
623 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
624 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
625 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
626
627 ret = psp_cmd_submit_buf(psp, NULL, cmd,
628 psp->fence_buf_mc_addr);
629
630 release_psp_cmd_buf(psp);
631
632 return ret;
633 }
634
psp_prep_tmr_unload_cmd_buf(struct psp_context * psp,struct psp_gfx_cmd_resp * cmd)635 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
636 struct psp_gfx_cmd_resp *cmd)
637 {
638 if (amdgpu_sriov_vf(psp->adev))
639 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
640 else
641 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
642 }
643
psp_tmr_unload(struct psp_context * psp)644 static int psp_tmr_unload(struct psp_context *psp)
645 {
646 int ret;
647 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
648
649 psp_prep_tmr_unload_cmd_buf(psp, cmd);
650 DRM_INFO("free PSP TMR buffer\n");
651
652 ret = psp_cmd_submit_buf(psp, NULL, cmd,
653 psp->fence_buf_mc_addr);
654
655 release_psp_cmd_buf(psp);
656
657 return ret;
658 }
659
psp_tmr_terminate(struct psp_context * psp)660 static int psp_tmr_terminate(struct psp_context *psp)
661 {
662 int ret;
663 void *tmr_buf;
664 void **pptr;
665
666 ret = psp_tmr_unload(psp);
667 if (ret)
668 return ret;
669
670 /* free TMR memory buffer */
671 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
672 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
673
674 return 0;
675 }
676
psp_get_fw_attestation_records_addr(struct psp_context * psp,uint64_t * output_ptr)677 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
678 uint64_t *output_ptr)
679 {
680 int ret;
681 struct psp_gfx_cmd_resp *cmd;
682
683 if (!output_ptr)
684 return -EINVAL;
685
686 if (amdgpu_sriov_vf(psp->adev))
687 return 0;
688
689 cmd = acquire_psp_cmd_buf(psp);
690
691 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
692
693 ret = psp_cmd_submit_buf(psp, NULL, cmd,
694 psp->fence_buf_mc_addr);
695
696 if (!ret) {
697 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
698 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
699 }
700
701 release_psp_cmd_buf(psp);
702
703 return ret;
704 }
705
psp_boot_config_get(struct amdgpu_device * adev,uint32_t * boot_cfg)706 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
707 {
708 struct psp_context *psp = &adev->psp;
709 struct psp_gfx_cmd_resp *cmd;
710 int ret;
711
712 if (amdgpu_sriov_vf(adev))
713 return 0;
714
715 cmd = acquire_psp_cmd_buf(psp);
716
717 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
718 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
719
720 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
721 if (!ret) {
722 *boot_cfg =
723 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
724 }
725
726 release_psp_cmd_buf(psp);
727
728 return ret;
729 }
730
psp_boot_config_set(struct amdgpu_device * adev,uint32_t boot_cfg)731 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
732 {
733 int ret;
734 struct psp_context *psp = &adev->psp;
735 struct psp_gfx_cmd_resp *cmd;
736
737 if (amdgpu_sriov_vf(adev))
738 return 0;
739
740 cmd = acquire_psp_cmd_buf(psp);
741
742 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
743 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
744 cmd->cmd.boot_cfg.boot_config = boot_cfg;
745 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
746
747 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
748
749 release_psp_cmd_buf(psp);
750
751 return ret;
752 }
753
psp_rl_load(struct amdgpu_device * adev)754 static int psp_rl_load(struct amdgpu_device *adev)
755 {
756 int ret;
757 struct psp_context *psp = &adev->psp;
758 struct psp_gfx_cmd_resp *cmd;
759
760 if (!is_psp_fw_valid(psp->rl))
761 return 0;
762
763 cmd = acquire_psp_cmd_buf(psp);
764
765 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
766 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
767
768 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
769 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
770 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
771 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
772 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
773
774 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
775
776 release_psp_cmd_buf(psp);
777
778 return ret;
779 }
780
psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t asd_mc,uint32_t size)781 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
782 uint64_t asd_mc, uint32_t size)
783 {
784 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
785 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
786 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
787 cmd->cmd.cmd_load_ta.app_len = size;
788
789 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
790 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
791 cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
792 }
793
psp_asd_load(struct psp_context * psp)794 static int psp_asd_load(struct psp_context *psp)
795 {
796 int ret;
797 struct psp_gfx_cmd_resp *cmd;
798
799 /* If PSP version doesn't match ASD version, asd loading will be failed.
800 * add workaround to bypass it for sriov now.
801 * TODO: add version check to make it common
802 */
803 if (amdgpu_sriov_vf(psp->adev) || !psp->asd.size_bytes)
804 return 0;
805
806 cmd = acquire_psp_cmd_buf(psp);
807
808 psp_copy_fw(psp, psp->asd.start_addr, psp->asd.size_bytes);
809
810 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
811 psp->asd.size_bytes);
812
813 ret = psp_cmd_submit_buf(psp, NULL, cmd,
814 psp->fence_buf_mc_addr);
815 if (!ret) {
816 psp->asd_context.asd_initialized = true;
817 psp->asd_context.session_id = cmd->resp.session_id;
818 }
819
820 release_psp_cmd_buf(psp);
821
822 return ret;
823 }
824
psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t session_id)825 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
826 uint32_t session_id)
827 {
828 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
829 cmd->cmd.cmd_unload_ta.session_id = session_id;
830 }
831
psp_asd_unload(struct psp_context * psp)832 static int psp_asd_unload(struct psp_context *psp)
833 {
834 int ret;
835 struct psp_gfx_cmd_resp *cmd;
836
837 if (amdgpu_sriov_vf(psp->adev))
838 return 0;
839
840 if (!psp->asd_context.asd_initialized)
841 return 0;
842
843 cmd = acquire_psp_cmd_buf(psp);
844
845 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
846
847 ret = psp_cmd_submit_buf(psp, NULL, cmd,
848 psp->fence_buf_mc_addr);
849 if (!ret)
850 psp->asd_context.asd_initialized = false;
851
852 release_psp_cmd_buf(psp);
853
854 return ret;
855 }
856
psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t id,uint32_t value)857 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
858 uint32_t id, uint32_t value)
859 {
860 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
861 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
862 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
863 }
864
psp_reg_program(struct psp_context * psp,enum psp_reg_prog_id reg,uint32_t value)865 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
866 uint32_t value)
867 {
868 struct psp_gfx_cmd_resp *cmd;
869 int ret = 0;
870
871 if (reg >= PSP_REG_LAST)
872 return -EINVAL;
873
874 cmd = acquire_psp_cmd_buf(psp);
875
876 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
877 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
878 if (ret)
879 DRM_ERROR("PSP failed to program reg id %d", reg);
880
881 release_psp_cmd_buf(psp);
882
883 return ret;
884 }
885
psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t ta_bin_mc,uint32_t ta_bin_size,uint64_t ta_shared_mc,uint32_t ta_shared_size)886 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
887 uint64_t ta_bin_mc,
888 uint32_t ta_bin_size,
889 uint64_t ta_shared_mc,
890 uint32_t ta_shared_size)
891 {
892 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
893 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
894 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
895 cmd->cmd.cmd_load_ta.app_len = ta_bin_size;
896
897 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
898 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
899 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size;
900 }
901
psp_ta_init_shared_buf(struct psp_context * psp,struct ta_mem_context * mem_ctx,uint32_t shared_mem_size)902 static int psp_ta_init_shared_buf(struct psp_context *psp,
903 struct ta_mem_context *mem_ctx,
904 uint32_t shared_mem_size)
905 {
906 int ret;
907
908 /*
909 * Allocate 16k memory aligned to 4k from Frame Buffer (local
910 * physical) for ta to host memory
911 */
912 ret = amdgpu_bo_create_kernel(psp->adev, shared_mem_size, PAGE_SIZE,
913 AMDGPU_GEM_DOMAIN_VRAM,
914 &mem_ctx->shared_bo,
915 &mem_ctx->shared_mc_addr,
916 &mem_ctx->shared_buf);
917
918 return ret;
919 }
920
psp_ta_free_shared_buf(struct ta_mem_context * mem_ctx)921 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
922 {
923 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
924 &mem_ctx->shared_buf);
925 }
926
psp_xgmi_init_shared_buf(struct psp_context * psp)927 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
928 {
929 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context,
930 PSP_XGMI_SHARED_MEM_SIZE);
931 }
932
psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t ta_cmd_id,uint32_t session_id)933 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
934 uint32_t ta_cmd_id,
935 uint32_t session_id)
936 {
937 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
938 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
939 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
940 }
941
psp_ta_invoke(struct psp_context * psp,uint32_t ta_cmd_id,uint32_t session_id)942 static int psp_ta_invoke(struct psp_context *psp,
943 uint32_t ta_cmd_id,
944 uint32_t session_id)
945 {
946 int ret;
947 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
948
949 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
950
951 ret = psp_cmd_submit_buf(psp, NULL, cmd,
952 psp->fence_buf_mc_addr);
953
954 release_psp_cmd_buf(psp);
955
956 return ret;
957 }
958
psp_xgmi_load(struct psp_context * psp)959 static int psp_xgmi_load(struct psp_context *psp)
960 {
961 int ret;
962 struct psp_gfx_cmd_resp *cmd;
963
964 /*
965 * TODO: bypass the loading in sriov for now
966 */
967
968 cmd = acquire_psp_cmd_buf(psp);
969
970 psp_copy_fw(psp, psp->xgmi.start_addr, psp->xgmi.size_bytes);
971
972 psp_prep_ta_load_cmd_buf(cmd,
973 psp->fw_pri_mc_addr,
974 psp->xgmi.size_bytes,
975 psp->xgmi_context.context.mem_context.shared_mc_addr,
976 PSP_XGMI_SHARED_MEM_SIZE);
977
978 ret = psp_cmd_submit_buf(psp, NULL, cmd,
979 psp->fence_buf_mc_addr);
980
981 if (!ret) {
982 psp->xgmi_context.context.initialized = true;
983 psp->xgmi_context.context.session_id = cmd->resp.session_id;
984 }
985
986 release_psp_cmd_buf(psp);
987
988 return ret;
989 }
990
psp_xgmi_unload(struct psp_context * psp)991 static int psp_xgmi_unload(struct psp_context *psp)
992 {
993 int ret;
994 struct psp_gfx_cmd_resp *cmd;
995 struct amdgpu_device *adev = psp->adev;
996
997 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
998 if (adev->asic_type == CHIP_ARCTURUS ||
999 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu))
1000 return 0;
1001
1002 /*
1003 * TODO: bypass the unloading in sriov for now
1004 */
1005
1006 cmd = acquire_psp_cmd_buf(psp);
1007
1008 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.context.session_id);
1009
1010 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1011 psp->fence_buf_mc_addr);
1012
1013 release_psp_cmd_buf(psp);
1014
1015 return ret;
1016 }
1017
psp_xgmi_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1018 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1019 {
1020 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.context.session_id);
1021 }
1022
psp_xgmi_terminate(struct psp_context * psp)1023 int psp_xgmi_terminate(struct psp_context *psp)
1024 {
1025 int ret;
1026
1027 if (!psp->xgmi_context.context.initialized)
1028 return 0;
1029
1030 ret = psp_xgmi_unload(psp);
1031 if (ret)
1032 return ret;
1033
1034 psp->xgmi_context.context.initialized = false;
1035
1036 /* free xgmi shared memory */
1037 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
1038
1039 return 0;
1040 }
1041
psp_xgmi_initialize(struct psp_context * psp,bool set_extended_data,bool load_ta)1042 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1043 {
1044 struct ta_xgmi_shared_memory *xgmi_cmd;
1045 int ret;
1046
1047 if (!psp->ta_fw ||
1048 !psp->xgmi.size_bytes ||
1049 !psp->xgmi.start_addr)
1050 return -ENOENT;
1051
1052 if (!load_ta)
1053 goto invoke;
1054
1055 if (!psp->xgmi_context.context.initialized) {
1056 ret = psp_xgmi_init_shared_buf(psp);
1057 if (ret)
1058 return ret;
1059 }
1060
1061 /* Load XGMI TA */
1062 ret = psp_xgmi_load(psp);
1063 if (ret)
1064 return ret;
1065
1066 invoke:
1067 /* Initialize XGMI session */
1068 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1069 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1070 xgmi_cmd->flag_extend_link_record = set_extended_data;
1071 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1072
1073 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1074
1075 return ret;
1076 }
1077
psp_xgmi_get_hive_id(struct psp_context * psp,uint64_t * hive_id)1078 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1079 {
1080 struct ta_xgmi_shared_memory *xgmi_cmd;
1081 int ret;
1082
1083 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1084 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1085
1086 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1087
1088 /* Invoke xgmi ta to get hive id */
1089 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1090 if (ret)
1091 return ret;
1092
1093 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1094
1095 return 0;
1096 }
1097
psp_xgmi_get_node_id(struct psp_context * psp,uint64_t * node_id)1098 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1099 {
1100 struct ta_xgmi_shared_memory *xgmi_cmd;
1101 int ret;
1102
1103 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1104 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1105
1106 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1107
1108 /* Invoke xgmi ta to get the node id */
1109 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1110 if (ret)
1111 return ret;
1112
1113 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1114
1115 return 0;
1116 }
1117
psp_xgmi_peer_link_info_supported(struct psp_context * psp)1118 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1119 {
1120 return psp->adev->asic_type == CHIP_ALDEBARAN &&
1121 psp->xgmi.feature_version >= 0x2000000b;
1122 }
1123
1124 /*
1125 * Chips that support extended topology information require the driver to
1126 * reflect topology information in the opposite direction. This is
1127 * because the TA has already exceeded its link record limit and if the
1128 * TA holds bi-directional information, the driver would have to do
1129 * multiple fetches instead of just two.
1130 */
psp_xgmi_reflect_topology_info(struct psp_context * psp,struct psp_xgmi_node_info node_info)1131 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1132 struct psp_xgmi_node_info node_info)
1133 {
1134 struct amdgpu_device *mirror_adev;
1135 struct amdgpu_hive_info *hive;
1136 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1137 uint64_t dst_node_id = node_info.node_id;
1138 uint8_t dst_num_hops = node_info.num_hops;
1139 uint8_t dst_num_links = node_info.num_links;
1140
1141 hive = amdgpu_get_xgmi_hive(psp->adev);
1142 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1143 struct psp_xgmi_topology_info *mirror_top_info;
1144 int j;
1145
1146 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1147 continue;
1148
1149 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1150 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1151 if (mirror_top_info->nodes[j].node_id != src_node_id)
1152 continue;
1153
1154 mirror_top_info->nodes[j].num_hops = dst_num_hops;
1155 /*
1156 * prevent 0 num_links value re-reflection since reflection
1157 * criteria is based on num_hops (direct or indirect).
1158 *
1159 */
1160 if (dst_num_links)
1161 mirror_top_info->nodes[j].num_links = dst_num_links;
1162
1163 break;
1164 }
1165
1166 break;
1167 }
1168 }
1169
psp_xgmi_get_topology_info(struct psp_context * psp,int number_devices,struct psp_xgmi_topology_info * topology,bool get_extended_data)1170 int psp_xgmi_get_topology_info(struct psp_context *psp,
1171 int number_devices,
1172 struct psp_xgmi_topology_info *topology,
1173 bool get_extended_data)
1174 {
1175 struct ta_xgmi_shared_memory *xgmi_cmd;
1176 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1177 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1178 int i;
1179 int ret;
1180
1181 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1182 return -EINVAL;
1183
1184 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1185 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1186 xgmi_cmd->flag_extend_link_record = get_extended_data;
1187
1188 /* Fill in the shared memory with topology information as input */
1189 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1190 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1191 topology_info_input->num_nodes = number_devices;
1192
1193 for (i = 0; i < topology_info_input->num_nodes; i++) {
1194 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1195 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1196 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1197 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1198 }
1199
1200 /* Invoke xgmi ta to get the topology information */
1201 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1202 if (ret)
1203 return ret;
1204
1205 /* Read the output topology information from the shared memory */
1206 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1207 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1208 for (i = 0; i < topology->num_nodes; i++) {
1209 /* extended data will either be 0 or equal to non-extended data */
1210 if (topology_info_output->nodes[i].num_hops)
1211 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1212
1213 /* non-extended data gets everything here so no need to update */
1214 if (!get_extended_data) {
1215 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1216 topology->nodes[i].is_sharing_enabled =
1217 topology_info_output->nodes[i].is_sharing_enabled;
1218 topology->nodes[i].sdma_engine =
1219 topology_info_output->nodes[i].sdma_engine;
1220 }
1221
1222 }
1223
1224 /* Invoke xgmi ta again to get the link information */
1225 if (psp_xgmi_peer_link_info_supported(psp)) {
1226 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1227
1228 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1229
1230 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1231
1232 if (ret)
1233 return ret;
1234
1235 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1236 for (i = 0; i < topology->num_nodes; i++) {
1237 /* accumulate num_links on extended data */
1238 topology->nodes[i].num_links = get_extended_data ?
1239 topology->nodes[i].num_links +
1240 link_info_output->nodes[i].num_links :
1241 link_info_output->nodes[i].num_links;
1242
1243 /* reflect the topology information for bi-directionality */
1244 if (psp->xgmi_context.supports_extended_data &&
1245 get_extended_data && topology->nodes[i].num_hops)
1246 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1247 }
1248 }
1249
1250 return 0;
1251 }
1252
psp_xgmi_set_topology_info(struct psp_context * psp,int number_devices,struct psp_xgmi_topology_info * topology)1253 int psp_xgmi_set_topology_info(struct psp_context *psp,
1254 int number_devices,
1255 struct psp_xgmi_topology_info *topology)
1256 {
1257 struct ta_xgmi_shared_memory *xgmi_cmd;
1258 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1259 int i;
1260
1261 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1262 return -EINVAL;
1263
1264 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1265 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1266
1267 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1268 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1269 topology_info_input->num_nodes = number_devices;
1270
1271 for (i = 0; i < topology_info_input->num_nodes; i++) {
1272 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1273 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1274 topology_info_input->nodes[i].is_sharing_enabled = 1;
1275 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1276 }
1277
1278 /* Invoke xgmi ta to set topology information */
1279 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1280 }
1281
1282 // ras begin
psp_ras_init_shared_buf(struct psp_context * psp)1283 static int psp_ras_init_shared_buf(struct psp_context *psp)
1284 {
1285 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context,
1286 PSP_RAS_SHARED_MEM_SIZE);
1287 }
1288
psp_ras_load(struct psp_context * psp)1289 static int psp_ras_load(struct psp_context *psp)
1290 {
1291 int ret;
1292 struct psp_gfx_cmd_resp *cmd;
1293 struct ta_ras_shared_memory *ras_cmd;
1294
1295 /*
1296 * TODO: bypass the loading in sriov for now
1297 */
1298 if (amdgpu_sriov_vf(psp->adev))
1299 return 0;
1300
1301 psp_copy_fw(psp, psp->ras.start_addr, psp->ras.size_bytes);
1302
1303 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1304
1305 if (psp->adev->gmc.xgmi.connected_to_cpu)
1306 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1307 else
1308 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1309
1310 cmd = acquire_psp_cmd_buf(psp);
1311
1312 psp_prep_ta_load_cmd_buf(cmd,
1313 psp->fw_pri_mc_addr,
1314 psp->ras.size_bytes,
1315 psp->ras_context.context.mem_context.shared_mc_addr,
1316 PSP_RAS_SHARED_MEM_SIZE);
1317
1318 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1319 psp->fence_buf_mc_addr);
1320
1321 if (!ret) {
1322 psp->ras_context.context.session_id = cmd->resp.session_id;
1323
1324 if (!ras_cmd->ras_status)
1325 psp->ras_context.context.initialized = true;
1326 else
1327 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1328 }
1329
1330 release_psp_cmd_buf(psp);
1331
1332 if (ret || ras_cmd->ras_status)
1333 amdgpu_ras_fini(psp->adev);
1334
1335 return ret;
1336 }
1337
psp_ras_unload(struct psp_context * psp)1338 static int psp_ras_unload(struct psp_context *psp)
1339 {
1340 int ret;
1341 struct psp_gfx_cmd_resp *cmd;
1342
1343 /*
1344 * TODO: bypass the unloading in sriov for now
1345 */
1346 if (amdgpu_sriov_vf(psp->adev))
1347 return 0;
1348
1349 cmd = acquire_psp_cmd_buf(psp);
1350
1351 psp_prep_ta_unload_cmd_buf(cmd, psp->ras_context.context.session_id);
1352
1353 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1354 psp->fence_buf_mc_addr);
1355
1356 release_psp_cmd_buf(psp);
1357
1358 return ret;
1359 }
1360
psp_ras_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1361 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1362 {
1363 struct ta_ras_shared_memory *ras_cmd;
1364 int ret;
1365
1366 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1367
1368 /*
1369 * TODO: bypass the loading in sriov for now
1370 */
1371 if (amdgpu_sriov_vf(psp->adev))
1372 return 0;
1373
1374 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras_context.context.session_id);
1375
1376 if (amdgpu_ras_intr_triggered())
1377 return ret;
1378
1379 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1380 {
1381 DRM_WARN("RAS: Unsupported Interface");
1382 return -EINVAL;
1383 }
1384
1385 if (!ret) {
1386 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1387 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1388
1389 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1390 }
1391 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1392 dev_warn(psp->adev->dev,
1393 "RAS internal register access blocked\n");
1394 }
1395
1396 return ret;
1397 }
1398
psp_ras_status_to_errno(struct amdgpu_device * adev,enum ta_ras_status ras_status)1399 static int psp_ras_status_to_errno(struct amdgpu_device *adev,
1400 enum ta_ras_status ras_status)
1401 {
1402 int ret = -EINVAL;
1403
1404 switch (ras_status) {
1405 case TA_RAS_STATUS__SUCCESS:
1406 ret = 0;
1407 break;
1408 case TA_RAS_STATUS__RESET_NEEDED:
1409 ret = -EAGAIN;
1410 break;
1411 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
1412 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n");
1413 break;
1414 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE:
1415 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n");
1416 break;
1417 default:
1418 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret);
1419 }
1420
1421 return ret;
1422 }
1423
psp_ras_enable_features(struct psp_context * psp,union ta_ras_cmd_input * info,bool enable)1424 int psp_ras_enable_features(struct psp_context *psp,
1425 union ta_ras_cmd_input *info, bool enable)
1426 {
1427 struct ta_ras_shared_memory *ras_cmd;
1428 int ret;
1429
1430 if (!psp->ras_context.context.initialized)
1431 return -EINVAL;
1432
1433 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1434 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1435
1436 if (enable)
1437 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1438 else
1439 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1440
1441 ras_cmd->ras_in_message = *info;
1442
1443 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1444 if (ret)
1445 return -EINVAL;
1446
1447 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1448 }
1449
psp_ras_terminate(struct psp_context * psp)1450 static int psp_ras_terminate(struct psp_context *psp)
1451 {
1452 int ret;
1453
1454 /*
1455 * TODO: bypass the terminate in sriov for now
1456 */
1457 if (amdgpu_sriov_vf(psp->adev))
1458 return 0;
1459
1460 if (!psp->ras_context.context.initialized)
1461 return 0;
1462
1463 ret = psp_ras_unload(psp);
1464 if (ret)
1465 return ret;
1466
1467 psp->ras_context.context.initialized = false;
1468
1469 /* free ras shared memory */
1470 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
1471
1472 return 0;
1473 }
1474
psp_ras_initialize(struct psp_context * psp)1475 static int psp_ras_initialize(struct psp_context *psp)
1476 {
1477 int ret;
1478 uint32_t boot_cfg = 0xFF;
1479 struct amdgpu_device *adev = psp->adev;
1480
1481 /*
1482 * TODO: bypass the initialize in sriov for now
1483 */
1484 if (amdgpu_sriov_vf(adev))
1485 return 0;
1486
1487 if (!adev->psp.ras.size_bytes ||
1488 !adev->psp.ras.start_addr) {
1489 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1490 return 0;
1491 }
1492
1493 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1494 /* query GECC enablement status from boot config
1495 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1496 */
1497 ret = psp_boot_config_get(adev, &boot_cfg);
1498 if (ret)
1499 dev_warn(adev->dev, "PSP get boot config failed\n");
1500
1501 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1502 if (!boot_cfg) {
1503 dev_info(adev->dev, "GECC is disabled\n");
1504 } else {
1505 /* disable GECC in next boot cycle if ras is
1506 * disabled by module parameter amdgpu_ras_enable
1507 * and/or amdgpu_ras_mask, or boot_config_get call
1508 * is failed
1509 */
1510 ret = psp_boot_config_set(adev, 0);
1511 if (ret)
1512 dev_warn(adev->dev, "PSP set boot config failed\n");
1513 else
1514 dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1515 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1516 }
1517 } else {
1518 if (1 == boot_cfg) {
1519 dev_info(adev->dev, "GECC is enabled\n");
1520 } else {
1521 /* enable GECC in next boot cycle if it is disabled
1522 * in boot config, or force enable GECC if failed to
1523 * get boot configuration
1524 */
1525 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1526 if (ret)
1527 dev_warn(adev->dev, "PSP set boot config failed\n");
1528 else
1529 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1530 }
1531 }
1532 }
1533
1534 if (!psp->ras_context.context.initialized) {
1535 ret = psp_ras_init_shared_buf(psp);
1536 if (ret)
1537 return ret;
1538 }
1539
1540 ret = psp_ras_load(psp);
1541 if (ret)
1542 return ret;
1543
1544 return 0;
1545 }
1546
psp_ras_trigger_error(struct psp_context * psp,struct ta_ras_trigger_error_input * info)1547 int psp_ras_trigger_error(struct psp_context *psp,
1548 struct ta_ras_trigger_error_input *info)
1549 {
1550 struct ta_ras_shared_memory *ras_cmd;
1551 int ret;
1552
1553 if (!psp->ras_context.context.initialized)
1554 return -EINVAL;
1555
1556 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1557 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1558
1559 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1560 ras_cmd->ras_in_message.trigger_error = *info;
1561
1562 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1563 if (ret)
1564 return -EINVAL;
1565
1566 /* If err_event_athub occurs error inject was successful, however
1567 return status from TA is no long reliable */
1568 if (amdgpu_ras_intr_triggered())
1569 return 0;
1570
1571 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1572 }
1573 // ras end
1574
1575 // HDCP start
psp_hdcp_init_shared_buf(struct psp_context * psp)1576 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1577 {
1578 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context,
1579 PSP_HDCP_SHARED_MEM_SIZE);
1580 }
1581
psp_hdcp_load(struct psp_context * psp)1582 static int psp_hdcp_load(struct psp_context *psp)
1583 {
1584 int ret;
1585 struct psp_gfx_cmd_resp *cmd;
1586
1587 /*
1588 * TODO: bypass the loading in sriov for now
1589 */
1590 if (amdgpu_sriov_vf(psp->adev))
1591 return 0;
1592
1593 psp_copy_fw(psp, psp->hdcp.start_addr,
1594 psp->hdcp.size_bytes);
1595
1596 cmd = acquire_psp_cmd_buf(psp);
1597
1598 psp_prep_ta_load_cmd_buf(cmd,
1599 psp->fw_pri_mc_addr,
1600 psp->hdcp.size_bytes,
1601 psp->hdcp_context.context.mem_context.shared_mc_addr,
1602 PSP_HDCP_SHARED_MEM_SIZE);
1603
1604 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1605
1606 if (!ret) {
1607 psp->hdcp_context.context.initialized = true;
1608 psp->hdcp_context.context.session_id = cmd->resp.session_id;
1609 mutex_init(&psp->hdcp_context.mutex);
1610 }
1611
1612 release_psp_cmd_buf(psp);
1613
1614 return ret;
1615 }
psp_hdcp_initialize(struct psp_context * psp)1616 static int psp_hdcp_initialize(struct psp_context *psp)
1617 {
1618 int ret;
1619
1620 /*
1621 * TODO: bypass the initialize in sriov for now
1622 */
1623 if (amdgpu_sriov_vf(psp->adev))
1624 return 0;
1625
1626 if (!psp->hdcp.size_bytes ||
1627 !psp->hdcp.start_addr) {
1628 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1629 return 0;
1630 }
1631
1632 if (!psp->hdcp_context.context.initialized) {
1633 ret = psp_hdcp_init_shared_buf(psp);
1634 if (ret)
1635 return ret;
1636 }
1637
1638 ret = psp_hdcp_load(psp);
1639 if (ret)
1640 return ret;
1641
1642 return 0;
1643 }
1644
psp_hdcp_unload(struct psp_context * psp)1645 static int psp_hdcp_unload(struct psp_context *psp)
1646 {
1647 int ret;
1648 struct psp_gfx_cmd_resp *cmd;
1649
1650 /*
1651 * TODO: bypass the unloading in sriov for now
1652 */
1653 if (amdgpu_sriov_vf(psp->adev))
1654 return 0;
1655
1656 cmd = acquire_psp_cmd_buf(psp);
1657
1658 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.context.session_id);
1659
1660 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1661
1662 release_psp_cmd_buf(psp);
1663
1664 return ret;
1665 }
1666
psp_hdcp_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1667 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1668 {
1669 /*
1670 * TODO: bypass the loading in sriov for now
1671 */
1672 if (amdgpu_sriov_vf(psp->adev))
1673 return 0;
1674
1675 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.context.session_id);
1676 }
1677
psp_hdcp_terminate(struct psp_context * psp)1678 static int psp_hdcp_terminate(struct psp_context *psp)
1679 {
1680 int ret;
1681
1682 /*
1683 * TODO: bypass the terminate in sriov for now
1684 */
1685 if (amdgpu_sriov_vf(psp->adev))
1686 return 0;
1687
1688 if (!psp->hdcp_context.context.initialized) {
1689 if (psp->hdcp_context.context.mem_context.shared_buf)
1690 goto out;
1691 else
1692 return 0;
1693 }
1694
1695 ret = psp_hdcp_unload(psp);
1696 if (ret)
1697 return ret;
1698
1699 psp->hdcp_context.context.initialized = false;
1700
1701 out:
1702 /* free hdcp shared memory */
1703 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
1704
1705 return 0;
1706 }
1707 // HDCP end
1708
1709 // DTM start
psp_dtm_init_shared_buf(struct psp_context * psp)1710 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1711 {
1712 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context,
1713 PSP_DTM_SHARED_MEM_SIZE);
1714 }
1715
psp_dtm_load(struct psp_context * psp)1716 static int psp_dtm_load(struct psp_context *psp)
1717 {
1718 int ret;
1719 struct psp_gfx_cmd_resp *cmd;
1720
1721 /*
1722 * TODO: bypass the loading in sriov for now
1723 */
1724 if (amdgpu_sriov_vf(psp->adev))
1725 return 0;
1726
1727 psp_copy_fw(psp, psp->dtm.start_addr, psp->dtm.size_bytes);
1728
1729 cmd = acquire_psp_cmd_buf(psp);
1730
1731 psp_prep_ta_load_cmd_buf(cmd,
1732 psp->fw_pri_mc_addr,
1733 psp->dtm.size_bytes,
1734 psp->dtm_context.context.mem_context.shared_mc_addr,
1735 PSP_DTM_SHARED_MEM_SIZE);
1736
1737 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1738
1739 if (!ret) {
1740 psp->dtm_context.context.initialized = true;
1741 psp->dtm_context.context.session_id = cmd->resp.session_id;
1742 mutex_init(&psp->dtm_context.mutex);
1743 }
1744
1745 release_psp_cmd_buf(psp);
1746
1747 return ret;
1748 }
1749
psp_dtm_initialize(struct psp_context * psp)1750 static int psp_dtm_initialize(struct psp_context *psp)
1751 {
1752 int ret;
1753
1754 /*
1755 * TODO: bypass the initialize in sriov for now
1756 */
1757 if (amdgpu_sriov_vf(psp->adev))
1758 return 0;
1759
1760 if (!psp->dtm.size_bytes ||
1761 !psp->dtm.start_addr) {
1762 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1763 return 0;
1764 }
1765
1766 if (!psp->dtm_context.context.initialized) {
1767 ret = psp_dtm_init_shared_buf(psp);
1768 if (ret)
1769 return ret;
1770 }
1771
1772 ret = psp_dtm_load(psp);
1773 if (ret)
1774 return ret;
1775
1776 return 0;
1777 }
1778
psp_dtm_unload(struct psp_context * psp)1779 static int psp_dtm_unload(struct psp_context *psp)
1780 {
1781 int ret;
1782 struct psp_gfx_cmd_resp *cmd;
1783
1784 /*
1785 * TODO: bypass the unloading in sriov for now
1786 */
1787 if (amdgpu_sriov_vf(psp->adev))
1788 return 0;
1789
1790 cmd = acquire_psp_cmd_buf(psp);
1791
1792 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.context.session_id);
1793
1794 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1795
1796 release_psp_cmd_buf(psp);
1797
1798 return ret;
1799 }
1800
psp_dtm_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1801 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1802 {
1803 /*
1804 * TODO: bypass the loading in sriov for now
1805 */
1806 if (amdgpu_sriov_vf(psp->adev))
1807 return 0;
1808
1809 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.context.session_id);
1810 }
1811
psp_dtm_terminate(struct psp_context * psp)1812 static int psp_dtm_terminate(struct psp_context *psp)
1813 {
1814 int ret;
1815
1816 /*
1817 * TODO: bypass the terminate in sriov for now
1818 */
1819 if (amdgpu_sriov_vf(psp->adev))
1820 return 0;
1821
1822 if (!psp->dtm_context.context.initialized) {
1823 if (psp->dtm_context.context.mem_context.shared_buf)
1824 goto out;
1825 else
1826 return 0;
1827 }
1828
1829 ret = psp_dtm_unload(psp);
1830 if (ret)
1831 return ret;
1832
1833 psp->dtm_context.context.initialized = false;
1834
1835 out:
1836 /* free dtm shared memory */
1837 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
1838
1839 return 0;
1840 }
1841 // DTM end
1842
1843 // RAP start
psp_rap_init_shared_buf(struct psp_context * psp)1844 static int psp_rap_init_shared_buf(struct psp_context *psp)
1845 {
1846 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context,
1847 PSP_RAP_SHARED_MEM_SIZE);
1848 }
1849
psp_rap_load(struct psp_context * psp)1850 static int psp_rap_load(struct psp_context *psp)
1851 {
1852 int ret;
1853 struct psp_gfx_cmd_resp *cmd;
1854
1855 psp_copy_fw(psp, psp->rap.start_addr, psp->rap.size_bytes);
1856
1857 cmd = acquire_psp_cmd_buf(psp);
1858
1859 psp_prep_ta_load_cmd_buf(cmd,
1860 psp->fw_pri_mc_addr,
1861 psp->rap.size_bytes,
1862 psp->rap_context.context.mem_context.shared_mc_addr,
1863 PSP_RAP_SHARED_MEM_SIZE);
1864
1865 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1866
1867 if (!ret) {
1868 psp->rap_context.context.initialized = true;
1869 psp->rap_context.context.session_id = cmd->resp.session_id;
1870 mutex_init(&psp->rap_context.mutex);
1871 }
1872
1873 release_psp_cmd_buf(psp);
1874
1875 return ret;
1876 }
1877
psp_rap_unload(struct psp_context * psp)1878 static int psp_rap_unload(struct psp_context *psp)
1879 {
1880 int ret;
1881 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1882
1883 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.context.session_id);
1884
1885 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1886
1887 release_psp_cmd_buf(psp);
1888
1889 return ret;
1890 }
1891
psp_rap_initialize(struct psp_context * psp)1892 static int psp_rap_initialize(struct psp_context *psp)
1893 {
1894 int ret;
1895 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1896
1897 /*
1898 * TODO: bypass the initialize in sriov for now
1899 */
1900 if (amdgpu_sriov_vf(psp->adev))
1901 return 0;
1902
1903 if (!psp->rap.size_bytes ||
1904 !psp->rap.start_addr) {
1905 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1906 return 0;
1907 }
1908
1909 if (!psp->rap_context.context.initialized) {
1910 ret = psp_rap_init_shared_buf(psp);
1911 if (ret)
1912 return ret;
1913 }
1914
1915 ret = psp_rap_load(psp);
1916 if (ret)
1917 return ret;
1918
1919 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1920 if (ret || status != TA_RAP_STATUS__SUCCESS) {
1921 psp_rap_unload(psp);
1922
1923 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1924
1925 psp->rap_context.context.initialized = false;
1926
1927 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1928 ret, status);
1929
1930 return ret;
1931 }
1932
1933 return 0;
1934 }
1935
psp_rap_terminate(struct psp_context * psp)1936 static int psp_rap_terminate(struct psp_context *psp)
1937 {
1938 int ret;
1939
1940 if (!psp->rap_context.context.initialized)
1941 return 0;
1942
1943 ret = psp_rap_unload(psp);
1944
1945 psp->rap_context.context.initialized = false;
1946
1947 /* free rap shared memory */
1948 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1949
1950 return ret;
1951 }
1952
psp_rap_invoke(struct psp_context * psp,uint32_t ta_cmd_id,enum ta_rap_status * status)1953 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1954 {
1955 struct ta_rap_shared_memory *rap_cmd;
1956 int ret = 0;
1957
1958 if (!psp->rap_context.context.initialized)
1959 return 0;
1960
1961 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1962 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1963 return -EINVAL;
1964
1965 mutex_lock(&psp->rap_context.mutex);
1966
1967 rap_cmd = (struct ta_rap_shared_memory *)
1968 psp->rap_context.context.mem_context.shared_buf;
1969 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1970
1971 rap_cmd->cmd_id = ta_cmd_id;
1972 rap_cmd->validation_method_id = METHOD_A;
1973
1974 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.context.session_id);
1975 if (ret)
1976 goto out_unlock;
1977
1978 if (status)
1979 *status = rap_cmd->rap_status;
1980
1981 out_unlock:
1982 mutex_unlock(&psp->rap_context.mutex);
1983
1984 return ret;
1985 }
1986 // RAP end
1987
1988 /* securedisplay start */
psp_securedisplay_init_shared_buf(struct psp_context * psp)1989 static int psp_securedisplay_init_shared_buf(struct psp_context *psp)
1990 {
1991 return psp_ta_init_shared_buf(
1992 psp, &psp->securedisplay_context.context.mem_context,
1993 PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
1994 }
1995
psp_securedisplay_load(struct psp_context * psp)1996 static int psp_securedisplay_load(struct psp_context *psp)
1997 {
1998 int ret;
1999 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2000
2001 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
2002 memcpy(psp->fw_pri_buf, psp->securedisplay.start_addr, psp->securedisplay.size_bytes);
2003
2004 psp_prep_ta_load_cmd_buf(cmd,
2005 psp->fw_pri_mc_addr,
2006 psp->securedisplay.size_bytes,
2007 psp->securedisplay_context.context.mem_context.shared_mc_addr,
2008 PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
2009
2010 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
2011
2012 if (!ret) {
2013 psp->securedisplay_context.context.initialized = true;
2014 psp->securedisplay_context.context.session_id = cmd->resp.session_id;
2015 mutex_init(&psp->securedisplay_context.mutex);
2016 }
2017
2018 release_psp_cmd_buf(psp);
2019
2020 return ret;
2021 }
2022
psp_securedisplay_unload(struct psp_context * psp)2023 static int psp_securedisplay_unload(struct psp_context *psp)
2024 {
2025 int ret;
2026 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2027
2028 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.context.session_id);
2029
2030 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
2031
2032 release_psp_cmd_buf(psp);
2033
2034 return ret;
2035 }
2036
psp_securedisplay_initialize(struct psp_context * psp)2037 static int psp_securedisplay_initialize(struct psp_context *psp)
2038 {
2039 int ret;
2040 struct securedisplay_cmd *securedisplay_cmd;
2041
2042 /*
2043 * TODO: bypass the initialize in sriov for now
2044 */
2045 if (amdgpu_sriov_vf(psp->adev))
2046 return 0;
2047
2048 if (!psp->securedisplay.size_bytes ||
2049 !psp->securedisplay.start_addr) {
2050 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
2051 return 0;
2052 }
2053
2054 if (!psp->securedisplay_context.context.initialized) {
2055 ret = psp_securedisplay_init_shared_buf(psp);
2056 if (ret)
2057 return ret;
2058 }
2059
2060 ret = psp_securedisplay_load(psp);
2061 if (ret)
2062 return ret;
2063
2064 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2065 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2066
2067 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2068 if (ret) {
2069 psp_securedisplay_unload(psp);
2070
2071 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2072
2073 psp->securedisplay_context.context.initialized = false;
2074
2075 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2076 return -EINVAL;
2077 }
2078
2079 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2080 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2081 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2082 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2083 }
2084
2085 return 0;
2086 }
2087
psp_securedisplay_terminate(struct psp_context * psp)2088 static int psp_securedisplay_terminate(struct psp_context *psp)
2089 {
2090 int ret;
2091
2092 /*
2093 * TODO:bypass the terminate in sriov for now
2094 */
2095 if (amdgpu_sriov_vf(psp->adev))
2096 return 0;
2097
2098 if (!psp->securedisplay_context.context.initialized)
2099 return 0;
2100
2101 ret = psp_securedisplay_unload(psp);
2102 if (ret)
2103 return ret;
2104
2105 psp->securedisplay_context.context.initialized = false;
2106
2107 /* free securedisplay shared memory */
2108 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2109
2110 return ret;
2111 }
2112
psp_securedisplay_invoke(struct psp_context * psp,uint32_t ta_cmd_id)2113 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2114 {
2115 int ret;
2116
2117 if (!psp->securedisplay_context.context.initialized)
2118 return -EINVAL;
2119
2120 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2121 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2122 return -EINVAL;
2123
2124 mutex_lock(&psp->securedisplay_context.mutex);
2125
2126 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.context.session_id);
2127
2128 mutex_unlock(&psp->securedisplay_context.mutex);
2129
2130 return ret;
2131 }
2132 /* SECUREDISPLAY end */
2133
psp_hw_start(struct psp_context * psp)2134 static int psp_hw_start(struct psp_context *psp)
2135 {
2136 struct amdgpu_device *adev = psp->adev;
2137 int ret;
2138
2139 if (!amdgpu_sriov_vf(adev)) {
2140 if ((is_psp_fw_valid(psp->kdb)) &&
2141 (psp->funcs->bootloader_load_kdb != NULL)) {
2142 ret = psp_bootloader_load_kdb(psp);
2143 if (ret) {
2144 DRM_ERROR("PSP load kdb failed!\n");
2145 return ret;
2146 }
2147 }
2148
2149 if ((is_psp_fw_valid(psp->spl)) &&
2150 (psp->funcs->bootloader_load_spl != NULL)) {
2151 ret = psp_bootloader_load_spl(psp);
2152 if (ret) {
2153 DRM_ERROR("PSP load spl failed!\n");
2154 return ret;
2155 }
2156 }
2157
2158 if ((is_psp_fw_valid(psp->sys)) &&
2159 (psp->funcs->bootloader_load_sysdrv != NULL)) {
2160 ret = psp_bootloader_load_sysdrv(psp);
2161 if (ret) {
2162 DRM_ERROR("PSP load sys drv failed!\n");
2163 return ret;
2164 }
2165 }
2166
2167 if ((is_psp_fw_valid(psp->soc_drv)) &&
2168 (psp->funcs->bootloader_load_soc_drv != NULL)) {
2169 ret = psp_bootloader_load_soc_drv(psp);
2170 if (ret) {
2171 DRM_ERROR("PSP load soc drv failed!\n");
2172 return ret;
2173 }
2174 }
2175
2176 if ((is_psp_fw_valid(psp->intf_drv)) &&
2177 (psp->funcs->bootloader_load_intf_drv != NULL)) {
2178 ret = psp_bootloader_load_intf_drv(psp);
2179 if (ret) {
2180 DRM_ERROR("PSP load intf drv failed!\n");
2181 return ret;
2182 }
2183 }
2184
2185 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2186 (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2187 ret = psp_bootloader_load_dbg_drv(psp);
2188 if (ret) {
2189 DRM_ERROR("PSP load dbg drv failed!\n");
2190 return ret;
2191 }
2192 }
2193
2194 if ((is_psp_fw_valid(psp->sos)) &&
2195 (psp->funcs->bootloader_load_sos != NULL)) {
2196 ret = psp_bootloader_load_sos(psp);
2197 if (ret) {
2198 DRM_ERROR("PSP load sos failed!\n");
2199 return ret;
2200 }
2201 }
2202 }
2203
2204 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2205 if (ret) {
2206 DRM_ERROR("PSP create ring failed!\n");
2207 return ret;
2208 }
2209
2210 ret = psp_tmr_init(psp);
2211 if (ret) {
2212 DRM_ERROR("PSP tmr init failed!\n");
2213 return ret;
2214 }
2215
2216 /*
2217 * For ASICs with DF Cstate management centralized
2218 * to PMFW, TMR setup should be performed after PMFW
2219 * loaded and before other non-psp firmware loaded.
2220 */
2221 if (psp->pmfw_centralized_cstate_management) {
2222 ret = psp_load_smu_fw(psp);
2223 if (ret)
2224 return ret;
2225 }
2226
2227 ret = psp_tmr_load(psp);
2228 if (ret) {
2229 DRM_ERROR("PSP load tmr failed!\n");
2230 return ret;
2231 }
2232
2233 return 0;
2234 }
2235
psp_get_fw_type(struct amdgpu_firmware_info * ucode,enum psp_gfx_fw_type * type)2236 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2237 enum psp_gfx_fw_type *type)
2238 {
2239 switch (ucode->ucode_id) {
2240 case AMDGPU_UCODE_ID_SDMA0:
2241 *type = GFX_FW_TYPE_SDMA0;
2242 break;
2243 case AMDGPU_UCODE_ID_SDMA1:
2244 *type = GFX_FW_TYPE_SDMA1;
2245 break;
2246 case AMDGPU_UCODE_ID_SDMA2:
2247 *type = GFX_FW_TYPE_SDMA2;
2248 break;
2249 case AMDGPU_UCODE_ID_SDMA3:
2250 *type = GFX_FW_TYPE_SDMA3;
2251 break;
2252 case AMDGPU_UCODE_ID_SDMA4:
2253 *type = GFX_FW_TYPE_SDMA4;
2254 break;
2255 case AMDGPU_UCODE_ID_SDMA5:
2256 *type = GFX_FW_TYPE_SDMA5;
2257 break;
2258 case AMDGPU_UCODE_ID_SDMA6:
2259 *type = GFX_FW_TYPE_SDMA6;
2260 break;
2261 case AMDGPU_UCODE_ID_SDMA7:
2262 *type = GFX_FW_TYPE_SDMA7;
2263 break;
2264 case AMDGPU_UCODE_ID_CP_MES:
2265 *type = GFX_FW_TYPE_CP_MES;
2266 break;
2267 case AMDGPU_UCODE_ID_CP_MES_DATA:
2268 *type = GFX_FW_TYPE_MES_STACK;
2269 break;
2270 case AMDGPU_UCODE_ID_CP_CE:
2271 *type = GFX_FW_TYPE_CP_CE;
2272 break;
2273 case AMDGPU_UCODE_ID_CP_PFP:
2274 *type = GFX_FW_TYPE_CP_PFP;
2275 break;
2276 case AMDGPU_UCODE_ID_CP_ME:
2277 *type = GFX_FW_TYPE_CP_ME;
2278 break;
2279 case AMDGPU_UCODE_ID_CP_MEC1:
2280 *type = GFX_FW_TYPE_CP_MEC;
2281 break;
2282 case AMDGPU_UCODE_ID_CP_MEC1_JT:
2283 *type = GFX_FW_TYPE_CP_MEC_ME1;
2284 break;
2285 case AMDGPU_UCODE_ID_CP_MEC2:
2286 *type = GFX_FW_TYPE_CP_MEC;
2287 break;
2288 case AMDGPU_UCODE_ID_CP_MEC2_JT:
2289 *type = GFX_FW_TYPE_CP_MEC_ME2;
2290 break;
2291 case AMDGPU_UCODE_ID_RLC_G:
2292 *type = GFX_FW_TYPE_RLC_G;
2293 break;
2294 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2295 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2296 break;
2297 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2298 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2299 break;
2300 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2301 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2302 break;
2303 case AMDGPU_UCODE_ID_RLC_IRAM:
2304 *type = GFX_FW_TYPE_RLC_IRAM;
2305 break;
2306 case AMDGPU_UCODE_ID_RLC_DRAM:
2307 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2308 break;
2309 case AMDGPU_UCODE_ID_SMC:
2310 *type = GFX_FW_TYPE_SMU;
2311 break;
2312 case AMDGPU_UCODE_ID_UVD:
2313 *type = GFX_FW_TYPE_UVD;
2314 break;
2315 case AMDGPU_UCODE_ID_UVD1:
2316 *type = GFX_FW_TYPE_UVD1;
2317 break;
2318 case AMDGPU_UCODE_ID_VCE:
2319 *type = GFX_FW_TYPE_VCE;
2320 break;
2321 case AMDGPU_UCODE_ID_VCN:
2322 *type = GFX_FW_TYPE_VCN;
2323 break;
2324 case AMDGPU_UCODE_ID_VCN1:
2325 *type = GFX_FW_TYPE_VCN1;
2326 break;
2327 case AMDGPU_UCODE_ID_DMCU_ERAM:
2328 *type = GFX_FW_TYPE_DMCU_ERAM;
2329 break;
2330 case AMDGPU_UCODE_ID_DMCU_INTV:
2331 *type = GFX_FW_TYPE_DMCU_ISR;
2332 break;
2333 case AMDGPU_UCODE_ID_VCN0_RAM:
2334 *type = GFX_FW_TYPE_VCN0_RAM;
2335 break;
2336 case AMDGPU_UCODE_ID_VCN1_RAM:
2337 *type = GFX_FW_TYPE_VCN1_RAM;
2338 break;
2339 case AMDGPU_UCODE_ID_DMCUB:
2340 *type = GFX_FW_TYPE_DMUB;
2341 break;
2342 case AMDGPU_UCODE_ID_MAXIMUM:
2343 default:
2344 return -EINVAL;
2345 }
2346
2347 return 0;
2348 }
2349
psp_print_fw_hdr(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2350 static void psp_print_fw_hdr(struct psp_context *psp,
2351 struct amdgpu_firmware_info *ucode)
2352 {
2353 struct amdgpu_device *adev = psp->adev;
2354 struct common_firmware_header *hdr;
2355
2356 switch (ucode->ucode_id) {
2357 case AMDGPU_UCODE_ID_SDMA0:
2358 case AMDGPU_UCODE_ID_SDMA1:
2359 case AMDGPU_UCODE_ID_SDMA2:
2360 case AMDGPU_UCODE_ID_SDMA3:
2361 case AMDGPU_UCODE_ID_SDMA4:
2362 case AMDGPU_UCODE_ID_SDMA5:
2363 case AMDGPU_UCODE_ID_SDMA6:
2364 case AMDGPU_UCODE_ID_SDMA7:
2365 hdr = (struct common_firmware_header *)
2366 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2367 amdgpu_ucode_print_sdma_hdr(hdr);
2368 break;
2369 case AMDGPU_UCODE_ID_CP_CE:
2370 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2371 amdgpu_ucode_print_gfx_hdr(hdr);
2372 break;
2373 case AMDGPU_UCODE_ID_CP_PFP:
2374 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2375 amdgpu_ucode_print_gfx_hdr(hdr);
2376 break;
2377 case AMDGPU_UCODE_ID_CP_ME:
2378 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2379 amdgpu_ucode_print_gfx_hdr(hdr);
2380 break;
2381 case AMDGPU_UCODE_ID_CP_MEC1:
2382 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2383 amdgpu_ucode_print_gfx_hdr(hdr);
2384 break;
2385 case AMDGPU_UCODE_ID_RLC_G:
2386 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2387 amdgpu_ucode_print_rlc_hdr(hdr);
2388 break;
2389 case AMDGPU_UCODE_ID_SMC:
2390 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2391 amdgpu_ucode_print_smc_hdr(hdr);
2392 break;
2393 default:
2394 break;
2395 }
2396 }
2397
psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd)2398 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2399 struct psp_gfx_cmd_resp *cmd)
2400 {
2401 int ret;
2402 uint64_t fw_mem_mc_addr = ucode->mc_addr;
2403
2404 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2405 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2406 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2407 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2408
2409 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2410 if (ret)
2411 DRM_ERROR("Unknown firmware type\n");
2412
2413 return ret;
2414 }
2415
psp_execute_non_psp_fw_load(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2416 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2417 struct amdgpu_firmware_info *ucode)
2418 {
2419 int ret = 0;
2420 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2421
2422 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2423 if (!ret) {
2424 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2425 psp->fence_buf_mc_addr);
2426 }
2427
2428 release_psp_cmd_buf(psp);
2429
2430 return ret;
2431 }
2432
psp_load_smu_fw(struct psp_context * psp)2433 static int psp_load_smu_fw(struct psp_context *psp)
2434 {
2435 int ret;
2436 struct amdgpu_device *adev = psp->adev;
2437 struct amdgpu_firmware_info *ucode =
2438 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2439 struct amdgpu_ras *ras = psp->ras_context.ras;
2440
2441 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2442 return 0;
2443
2444 if ((amdgpu_in_reset(adev) &&
2445 ras && adev->ras_enabled &&
2446 (adev->asic_type == CHIP_ARCTURUS ||
2447 adev->asic_type == CHIP_VEGA20))) {
2448 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2449 if (ret) {
2450 DRM_WARN("Failed to set MP1 state prepare for reload\n");
2451 }
2452 }
2453
2454 ret = psp_execute_non_psp_fw_load(psp, ucode);
2455
2456 if (ret)
2457 DRM_ERROR("PSP load smu failed!\n");
2458
2459 return ret;
2460 }
2461
fw_load_skip_check(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2462 static bool fw_load_skip_check(struct psp_context *psp,
2463 struct amdgpu_firmware_info *ucode)
2464 {
2465 if (!ucode->fw)
2466 return true;
2467
2468 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2469 (psp_smu_reload_quirk(psp) ||
2470 psp->autoload_supported ||
2471 psp->pmfw_centralized_cstate_management))
2472 return true;
2473
2474 if (amdgpu_sriov_vf(psp->adev) &&
2475 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2476 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2477 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2478 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2479 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2480 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2481 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2482 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2483 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2484 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2485 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2486 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2487 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2488 /*skip ucode loading in SRIOV VF */
2489 return true;
2490
2491 if (psp->autoload_supported &&
2492 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2493 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2494 /* skip mec JT when autoload is enabled */
2495 return true;
2496
2497 return false;
2498 }
2499
psp_load_fw_list(struct psp_context * psp,struct amdgpu_firmware_info ** ucode_list,int ucode_count)2500 int psp_load_fw_list(struct psp_context *psp,
2501 struct amdgpu_firmware_info **ucode_list, int ucode_count)
2502 {
2503 int ret = 0, i;
2504 struct amdgpu_firmware_info *ucode;
2505
2506 for (i = 0; i < ucode_count; ++i) {
2507 ucode = ucode_list[i];
2508 psp_print_fw_hdr(psp, ucode);
2509 ret = psp_execute_non_psp_fw_load(psp, ucode);
2510 if (ret)
2511 return ret;
2512 }
2513 return ret;
2514 }
2515
psp_load_non_psp_fw(struct psp_context * psp)2516 static int psp_load_non_psp_fw(struct psp_context *psp)
2517 {
2518 int i, ret;
2519 struct amdgpu_firmware_info *ucode;
2520 struct amdgpu_device *adev = psp->adev;
2521
2522 if (psp->autoload_supported &&
2523 !psp->pmfw_centralized_cstate_management) {
2524 ret = psp_load_smu_fw(psp);
2525 if (ret)
2526 return ret;
2527 }
2528
2529 for (i = 0; i < adev->firmware.max_ucodes; i++) {
2530 ucode = &adev->firmware.ucode[i];
2531
2532 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2533 !fw_load_skip_check(psp, ucode)) {
2534 ret = psp_load_smu_fw(psp);
2535 if (ret)
2536 return ret;
2537 continue;
2538 }
2539
2540 if (fw_load_skip_check(psp, ucode))
2541 continue;
2542
2543 if (psp->autoload_supported &&
2544 (adev->asic_type >= CHIP_SIENNA_CICHLID &&
2545 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
2546 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2547 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2548 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2549 /* PSP only receive one SDMA fw for sienna_cichlid,
2550 * as all four sdma fw are same */
2551 continue;
2552
2553 psp_print_fw_hdr(psp, ucode);
2554
2555 ret = psp_execute_non_psp_fw_load(psp, ucode);
2556 if (ret)
2557 return ret;
2558
2559 /* Start rlc autoload after psp recieved all the gfx firmware */
2560 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2561 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2562 ret = psp_rlc_autoload_start(psp);
2563 if (ret) {
2564 DRM_ERROR("Failed to start rlc autoload\n");
2565 return ret;
2566 }
2567 }
2568 }
2569
2570 return 0;
2571 }
2572
psp_load_fw(struct amdgpu_device * adev)2573 static int psp_load_fw(struct amdgpu_device *adev)
2574 {
2575 int ret;
2576 struct psp_context *psp = &adev->psp;
2577
2578 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2579 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2580 goto skip_memalloc;
2581 }
2582
2583 if (amdgpu_sriov_vf(adev)) {
2584 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2585 AMDGPU_GEM_DOMAIN_VRAM,
2586 &psp->fw_pri_bo,
2587 &psp->fw_pri_mc_addr,
2588 &psp->fw_pri_buf);
2589 } else {
2590 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2591 AMDGPU_GEM_DOMAIN_GTT,
2592 &psp->fw_pri_bo,
2593 &psp->fw_pri_mc_addr,
2594 &psp->fw_pri_buf);
2595 }
2596
2597 if (ret)
2598 goto failed;
2599
2600 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2601 AMDGPU_GEM_DOMAIN_VRAM,
2602 &psp->fence_buf_bo,
2603 &psp->fence_buf_mc_addr,
2604 &psp->fence_buf);
2605 if (ret)
2606 goto failed;
2607
2608 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2609 AMDGPU_GEM_DOMAIN_VRAM,
2610 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2611 (void **)&psp->cmd_buf_mem);
2612 if (ret)
2613 goto failed;
2614
2615 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2616
2617 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2618 if (ret) {
2619 DRM_ERROR("PSP ring init failed!\n");
2620 goto failed;
2621 }
2622
2623 skip_memalloc:
2624 ret = psp_hw_start(psp);
2625 if (ret)
2626 goto failed;
2627
2628 ret = psp_load_non_psp_fw(psp);
2629 if (ret)
2630 goto failed;
2631
2632 ret = psp_asd_load(psp);
2633 if (ret) {
2634 DRM_ERROR("PSP load asd failed!\n");
2635 return ret;
2636 }
2637
2638 ret = psp_rl_load(adev);
2639 if (ret) {
2640 DRM_ERROR("PSP load RL failed!\n");
2641 return ret;
2642 }
2643
2644 if (psp->ta_fw) {
2645 ret = psp_ras_initialize(psp);
2646 if (ret)
2647 dev_err(psp->adev->dev,
2648 "RAS: Failed to initialize RAS\n");
2649
2650 ret = psp_hdcp_initialize(psp);
2651 if (ret)
2652 dev_err(psp->adev->dev,
2653 "HDCP: Failed to initialize HDCP\n");
2654
2655 ret = psp_dtm_initialize(psp);
2656 if (ret)
2657 dev_err(psp->adev->dev,
2658 "DTM: Failed to initialize DTM\n");
2659
2660 ret = psp_rap_initialize(psp);
2661 if (ret)
2662 dev_err(psp->adev->dev,
2663 "RAP: Failed to initialize RAP\n");
2664
2665 ret = psp_securedisplay_initialize(psp);
2666 if (ret)
2667 dev_err(psp->adev->dev,
2668 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2669 }
2670
2671 return 0;
2672
2673 failed:
2674 /*
2675 * all cleanup jobs (xgmi terminate, ras terminate,
2676 * ring destroy, cmd/fence/fw buffers destory,
2677 * psp->cmd destory) are delayed to psp_hw_fini
2678 */
2679 return ret;
2680 }
2681
psp_hw_init(void * handle)2682 static int psp_hw_init(void *handle)
2683 {
2684 int ret;
2685 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2686
2687 mutex_lock(&adev->firmware.mutex);
2688 /*
2689 * This sequence is just used on hw_init only once, no need on
2690 * resume.
2691 */
2692 ret = amdgpu_ucode_init_bo(adev);
2693 if (ret)
2694 goto failed;
2695
2696 ret = psp_load_fw(adev);
2697 if (ret) {
2698 DRM_ERROR("PSP firmware loading failed\n");
2699 goto failed;
2700 }
2701
2702 mutex_unlock(&adev->firmware.mutex);
2703 return 0;
2704
2705 failed:
2706 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2707 mutex_unlock(&adev->firmware.mutex);
2708 return -EINVAL;
2709 }
2710
psp_hw_fini(void * handle)2711 static int psp_hw_fini(void *handle)
2712 {
2713 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2714 struct psp_context *psp = &adev->psp;
2715
2716 if (psp->ta_fw) {
2717 psp_ras_terminate(psp);
2718 psp_securedisplay_terminate(psp);
2719 psp_rap_terminate(psp);
2720 psp_dtm_terminate(psp);
2721 psp_hdcp_terminate(psp);
2722 }
2723
2724 psp_asd_unload(psp);
2725
2726 psp_tmr_terminate(psp);
2727 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2728
2729 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2730 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2731 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2732 &psp->fence_buf_mc_addr, &psp->fence_buf);
2733 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2734 (void **)&psp->cmd_buf_mem);
2735
2736 return 0;
2737 }
2738
psp_suspend(void * handle)2739 static int psp_suspend(void *handle)
2740 {
2741 int ret;
2742 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2743 struct psp_context *psp = &adev->psp;
2744
2745 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2746 psp->xgmi_context.context.initialized) {
2747 ret = psp_xgmi_terminate(psp);
2748 if (ret) {
2749 DRM_ERROR("Failed to terminate xgmi ta\n");
2750 return ret;
2751 }
2752 }
2753
2754 if (psp->ta_fw) {
2755 ret = psp_ras_terminate(psp);
2756 if (ret) {
2757 DRM_ERROR("Failed to terminate ras ta\n");
2758 return ret;
2759 }
2760 ret = psp_hdcp_terminate(psp);
2761 if (ret) {
2762 DRM_ERROR("Failed to terminate hdcp ta\n");
2763 return ret;
2764 }
2765 ret = psp_dtm_terminate(psp);
2766 if (ret) {
2767 DRM_ERROR("Failed to terminate dtm ta\n");
2768 return ret;
2769 }
2770 ret = psp_rap_terminate(psp);
2771 if (ret) {
2772 DRM_ERROR("Failed to terminate rap ta\n");
2773 return ret;
2774 }
2775 ret = psp_securedisplay_terminate(psp);
2776 if (ret) {
2777 DRM_ERROR("Failed to terminate securedisplay ta\n");
2778 return ret;
2779 }
2780 }
2781
2782 ret = psp_asd_unload(psp);
2783 if (ret) {
2784 DRM_ERROR("Failed to unload asd\n");
2785 return ret;
2786 }
2787
2788 ret = psp_tmr_terminate(psp);
2789 if (ret) {
2790 DRM_ERROR("Failed to terminate tmr\n");
2791 return ret;
2792 }
2793
2794 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2795 if (ret) {
2796 DRM_ERROR("PSP ring stop failed\n");
2797 return ret;
2798 }
2799
2800 return 0;
2801 }
2802
psp_resume(void * handle)2803 static int psp_resume(void *handle)
2804 {
2805 int ret;
2806 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2807 struct psp_context *psp = &adev->psp;
2808
2809 DRM_INFO("PSP is resuming...\n");
2810
2811 if (psp->mem_train_ctx.enable_mem_training) {
2812 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2813 if (ret) {
2814 DRM_ERROR("Failed to process memory training!\n");
2815 return ret;
2816 }
2817 }
2818
2819 mutex_lock(&adev->firmware.mutex);
2820
2821 ret = psp_hw_start(psp);
2822 if (ret)
2823 goto failed;
2824
2825 ret = psp_load_non_psp_fw(psp);
2826 if (ret)
2827 goto failed;
2828
2829 ret = psp_asd_load(psp);
2830 if (ret) {
2831 DRM_ERROR("PSP load asd failed!\n");
2832 goto failed;
2833 }
2834
2835 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2836 ret = psp_xgmi_initialize(psp, false, true);
2837 /* Warning the XGMI seesion initialize failure
2838 * Instead of stop driver initialization
2839 */
2840 if (ret)
2841 dev_err(psp->adev->dev,
2842 "XGMI: Failed to initialize XGMI session\n");
2843 }
2844
2845 if (psp->ta_fw) {
2846 ret = psp_ras_initialize(psp);
2847 if (ret)
2848 dev_err(psp->adev->dev,
2849 "RAS: Failed to initialize RAS\n");
2850
2851 ret = psp_hdcp_initialize(psp);
2852 if (ret)
2853 dev_err(psp->adev->dev,
2854 "HDCP: Failed to initialize HDCP\n");
2855
2856 ret = psp_dtm_initialize(psp);
2857 if (ret)
2858 dev_err(psp->adev->dev,
2859 "DTM: Failed to initialize DTM\n");
2860
2861 ret = psp_rap_initialize(psp);
2862 if (ret)
2863 dev_err(psp->adev->dev,
2864 "RAP: Failed to initialize RAP\n");
2865
2866 ret = psp_securedisplay_initialize(psp);
2867 if (ret)
2868 dev_err(psp->adev->dev,
2869 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2870 }
2871
2872 mutex_unlock(&adev->firmware.mutex);
2873
2874 return 0;
2875
2876 failed:
2877 DRM_ERROR("PSP resume failed\n");
2878 mutex_unlock(&adev->firmware.mutex);
2879 return ret;
2880 }
2881
psp_gpu_reset(struct amdgpu_device * adev)2882 int psp_gpu_reset(struct amdgpu_device *adev)
2883 {
2884 int ret;
2885
2886 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2887 return 0;
2888
2889 mutex_lock(&adev->psp.mutex);
2890 ret = psp_mode1_reset(&adev->psp);
2891 mutex_unlock(&adev->psp.mutex);
2892
2893 return ret;
2894 }
2895
psp_rlc_autoload_start(struct psp_context * psp)2896 int psp_rlc_autoload_start(struct psp_context *psp)
2897 {
2898 int ret;
2899 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2900
2901 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2902
2903 ret = psp_cmd_submit_buf(psp, NULL, cmd,
2904 psp->fence_buf_mc_addr);
2905
2906 release_psp_cmd_buf(psp);
2907
2908 return ret;
2909 }
2910
psp_update_vcn_sram(struct amdgpu_device * adev,int inst_idx,uint64_t cmd_gpu_addr,int cmd_size)2911 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2912 uint64_t cmd_gpu_addr, int cmd_size)
2913 {
2914 struct amdgpu_firmware_info ucode = {0};
2915
2916 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2917 AMDGPU_UCODE_ID_VCN0_RAM;
2918 ucode.mc_addr = cmd_gpu_addr;
2919 ucode.ucode_size = cmd_size;
2920
2921 return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2922 }
2923
psp_ring_cmd_submit(struct psp_context * psp,uint64_t cmd_buf_mc_addr,uint64_t fence_mc_addr,int index)2924 int psp_ring_cmd_submit(struct psp_context *psp,
2925 uint64_t cmd_buf_mc_addr,
2926 uint64_t fence_mc_addr,
2927 int index)
2928 {
2929 unsigned int psp_write_ptr_reg = 0;
2930 struct psp_gfx_rb_frame *write_frame;
2931 struct psp_ring *ring = &psp->km_ring;
2932 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2933 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2934 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2935 struct amdgpu_device *adev = psp->adev;
2936 uint32_t ring_size_dw = ring->ring_size / 4;
2937 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2938
2939 /* KM (GPCOM) prepare write pointer */
2940 psp_write_ptr_reg = psp_ring_get_wptr(psp);
2941
2942 /* Update KM RB frame pointer to new frame */
2943 /* write_frame ptr increments by size of rb_frame in bytes */
2944 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2945 if ((psp_write_ptr_reg % ring_size_dw) == 0)
2946 write_frame = ring_buffer_start;
2947 else
2948 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2949 /* Check invalid write_frame ptr address */
2950 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2951 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2952 ring_buffer_start, ring_buffer_end, write_frame);
2953 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2954 return -EINVAL;
2955 }
2956
2957 /* Initialize KM RB frame */
2958 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2959
2960 /* Update KM RB frame */
2961 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2962 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2963 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2964 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2965 write_frame->fence_value = index;
2966 amdgpu_device_flush_hdp(adev, NULL);
2967
2968 /* Update the write Pointer in DWORDs */
2969 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2970 psp_ring_set_wptr(psp, psp_write_ptr_reg);
2971 return 0;
2972 }
2973
psp_init_asd_microcode(struct psp_context * psp,const char * chip_name)2974 int psp_init_asd_microcode(struct psp_context *psp,
2975 const char *chip_name)
2976 {
2977 struct amdgpu_device *adev = psp->adev;
2978 char fw_name[PSP_FW_NAME_LEN];
2979 const struct psp_firmware_header_v1_0 *asd_hdr;
2980 int err = 0;
2981
2982 if (!chip_name) {
2983 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2984 return -EINVAL;
2985 }
2986
2987 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2988 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2989 if (err)
2990 goto out;
2991
2992 err = amdgpu_ucode_validate(adev->psp.asd_fw);
2993 if (err)
2994 goto out;
2995
2996 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2997 adev->psp.asd.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2998 adev->psp.asd.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2999 adev->psp.asd.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
3000 adev->psp.asd.start_addr = (uint8_t *)asd_hdr +
3001 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3002 return 0;
3003 out:
3004 dev_err(adev->dev, "fail to initialize asd microcode\n");
3005 release_firmware(adev->psp.asd_fw);
3006 adev->psp.asd_fw = NULL;
3007 return err;
3008 }
3009
psp_init_toc_microcode(struct psp_context * psp,const char * chip_name)3010 int psp_init_toc_microcode(struct psp_context *psp,
3011 const char *chip_name)
3012 {
3013 struct amdgpu_device *adev = psp->adev;
3014 char fw_name[PSP_FW_NAME_LEN];
3015 const struct psp_firmware_header_v1_0 *toc_hdr;
3016 int err = 0;
3017
3018 if (!chip_name) {
3019 dev_err(adev->dev, "invalid chip name for toc microcode\n");
3020 return -EINVAL;
3021 }
3022
3023 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
3024 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
3025 if (err)
3026 goto out;
3027
3028 err = amdgpu_ucode_validate(adev->psp.toc_fw);
3029 if (err)
3030 goto out;
3031
3032 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3033 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3034 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3035 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3036 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3037 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3038 return 0;
3039 out:
3040 dev_err(adev->dev, "fail to request/validate toc microcode\n");
3041 release_firmware(adev->psp.toc_fw);
3042 adev->psp.toc_fw = NULL;
3043 return err;
3044 }
3045
parse_sos_bin_descriptor(struct psp_context * psp,const struct psp_fw_bin_desc * desc,const struct psp_firmware_header_v2_0 * sos_hdr)3046 static int parse_sos_bin_descriptor(struct psp_context *psp,
3047 const struct psp_fw_bin_desc *desc,
3048 const struct psp_firmware_header_v2_0 *sos_hdr)
3049 {
3050 uint8_t *ucode_start_addr = NULL;
3051
3052 if (!psp || !desc || !sos_hdr)
3053 return -EINVAL;
3054
3055 ucode_start_addr = (uint8_t *)sos_hdr +
3056 le32_to_cpu(desc->offset_bytes) +
3057 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3058
3059 switch (desc->fw_type) {
3060 case PSP_FW_TYPE_PSP_SOS:
3061 psp->sos.fw_version = le32_to_cpu(desc->fw_version);
3062 psp->sos.feature_version = le32_to_cpu(desc->fw_version);
3063 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
3064 psp->sos.start_addr = ucode_start_addr;
3065 break;
3066 case PSP_FW_TYPE_PSP_SYS_DRV:
3067 psp->sys.fw_version = le32_to_cpu(desc->fw_version);
3068 psp->sys.feature_version = le32_to_cpu(desc->fw_version);
3069 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
3070 psp->sys.start_addr = ucode_start_addr;
3071 break;
3072 case PSP_FW_TYPE_PSP_KDB:
3073 psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
3074 psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
3075 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
3076 psp->kdb.start_addr = ucode_start_addr;
3077 break;
3078 case PSP_FW_TYPE_PSP_TOC:
3079 psp->toc.fw_version = le32_to_cpu(desc->fw_version);
3080 psp->toc.feature_version = le32_to_cpu(desc->fw_version);
3081 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
3082 psp->toc.start_addr = ucode_start_addr;
3083 break;
3084 case PSP_FW_TYPE_PSP_SPL:
3085 psp->spl.fw_version = le32_to_cpu(desc->fw_version);
3086 psp->spl.feature_version = le32_to_cpu(desc->fw_version);
3087 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
3088 psp->spl.start_addr = ucode_start_addr;
3089 break;
3090 case PSP_FW_TYPE_PSP_RL:
3091 psp->rl.fw_version = le32_to_cpu(desc->fw_version);
3092 psp->rl.feature_version = le32_to_cpu(desc->fw_version);
3093 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
3094 psp->rl.start_addr = ucode_start_addr;
3095 break;
3096 case PSP_FW_TYPE_PSP_SOC_DRV:
3097 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
3098 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
3099 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3100 psp->soc_drv.start_addr = ucode_start_addr;
3101 break;
3102 case PSP_FW_TYPE_PSP_INTF_DRV:
3103 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
3104 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
3105 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3106 psp->intf_drv.start_addr = ucode_start_addr;
3107 break;
3108 case PSP_FW_TYPE_PSP_DBG_DRV:
3109 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
3110 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
3111 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3112 psp->dbg_drv.start_addr = ucode_start_addr;
3113 break;
3114 default:
3115 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3116 break;
3117 }
3118
3119 return 0;
3120 }
3121
psp_init_sos_base_fw(struct amdgpu_device * adev)3122 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3123 {
3124 const struct psp_firmware_header_v1_0 *sos_hdr;
3125 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3126 uint8_t *ucode_array_start_addr;
3127
3128 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3129 ucode_array_start_addr = (uint8_t *)sos_hdr +
3130 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3131
3132 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) {
3133 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3134 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3135
3136 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3137 adev->psp.sys.start_addr = ucode_array_start_addr;
3138
3139 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3140 adev->psp.sos.start_addr = ucode_array_start_addr +
3141 le32_to_cpu(sos_hdr->sos.offset_bytes);
3142 adev->psp.xgmi_context.supports_extended_data = false;
3143 } else {
3144 /* Load alternate PSP SOS FW */
3145 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3146
3147 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3148 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3149
3150 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3151 adev->psp.sys.start_addr = ucode_array_start_addr +
3152 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3153
3154 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3155 adev->psp.sos.start_addr = ucode_array_start_addr +
3156 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3157 adev->psp.xgmi_context.supports_extended_data = true;
3158 }
3159
3160 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3161 dev_warn(adev->dev, "PSP SOS FW not available");
3162 return -EINVAL;
3163 }
3164
3165 return 0;
3166 }
3167
psp_init_sos_microcode(struct psp_context * psp,const char * chip_name)3168 int psp_init_sos_microcode(struct psp_context *psp,
3169 const char *chip_name)
3170 {
3171 struct amdgpu_device *adev = psp->adev;
3172 char fw_name[PSP_FW_NAME_LEN];
3173 const struct psp_firmware_header_v1_0 *sos_hdr;
3174 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3175 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3176 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3177 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3178 int err = 0;
3179 uint8_t *ucode_array_start_addr;
3180 int fw_index = 0;
3181
3182 if (!chip_name) {
3183 dev_err(adev->dev, "invalid chip name for sos microcode\n");
3184 return -EINVAL;
3185 }
3186
3187 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3188 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3189 if (err)
3190 goto out;
3191
3192 err = amdgpu_ucode_validate(adev->psp.sos_fw);
3193 if (err)
3194 goto out;
3195
3196 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3197 ucode_array_start_addr = (uint8_t *)sos_hdr +
3198 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3199 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3200
3201 switch (sos_hdr->header.header_version_major) {
3202 case 1:
3203 err = psp_init_sos_base_fw(adev);
3204 if (err)
3205 goto out;
3206
3207 if (sos_hdr->header.header_version_minor == 1) {
3208 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3209 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3210 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3211 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3212 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3213 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3214 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3215 }
3216 if (sos_hdr->header.header_version_minor == 2) {
3217 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3218 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3219 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3220 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3221 }
3222 if (sos_hdr->header.header_version_minor == 3) {
3223 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3224 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3225 adev->psp.toc.start_addr = ucode_array_start_addr +
3226 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3227 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3228 adev->psp.kdb.start_addr = ucode_array_start_addr +
3229 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3230 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3231 adev->psp.spl.start_addr = ucode_array_start_addr +
3232 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3233 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3234 adev->psp.rl.start_addr = ucode_array_start_addr +
3235 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3236 }
3237 break;
3238 case 2:
3239 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3240
3241 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3242 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3243 err = -EINVAL;
3244 goto out;
3245 }
3246
3247 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3248 err = parse_sos_bin_descriptor(psp,
3249 &sos_hdr_v2_0->psp_fw_bin[fw_index],
3250 sos_hdr_v2_0);
3251 if (err)
3252 goto out;
3253 }
3254 break;
3255 default:
3256 dev_err(adev->dev,
3257 "unsupported psp sos firmware\n");
3258 err = -EINVAL;
3259 goto out;
3260 }
3261
3262 return 0;
3263 out:
3264 dev_err(adev->dev,
3265 "failed to init sos firmware\n");
3266 release_firmware(adev->psp.sos_fw);
3267 adev->psp.sos_fw = NULL;
3268
3269 return err;
3270 }
3271
parse_ta_bin_descriptor(struct psp_context * psp,const struct psp_fw_bin_desc * desc,const struct ta_firmware_header_v2_0 * ta_hdr)3272 static int parse_ta_bin_descriptor(struct psp_context *psp,
3273 const struct psp_fw_bin_desc *desc,
3274 const struct ta_firmware_header_v2_0 *ta_hdr)
3275 {
3276 uint8_t *ucode_start_addr = NULL;
3277
3278 if (!psp || !desc || !ta_hdr)
3279 return -EINVAL;
3280
3281 ucode_start_addr = (uint8_t *)ta_hdr +
3282 le32_to_cpu(desc->offset_bytes) +
3283 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3284
3285 switch (desc->fw_type) {
3286 case TA_FW_TYPE_PSP_ASD:
3287 psp->asd.fw_version = le32_to_cpu(desc->fw_version);
3288 psp->asd.feature_version = le32_to_cpu(desc->fw_version);
3289 psp->asd.size_bytes = le32_to_cpu(desc->size_bytes);
3290 psp->asd.start_addr = ucode_start_addr;
3291 break;
3292 case TA_FW_TYPE_PSP_XGMI:
3293 psp->xgmi.feature_version = le32_to_cpu(desc->fw_version);
3294 psp->xgmi.size_bytes = le32_to_cpu(desc->size_bytes);
3295 psp->xgmi.start_addr = ucode_start_addr;
3296 break;
3297 case TA_FW_TYPE_PSP_RAS:
3298 psp->ras.feature_version = le32_to_cpu(desc->fw_version);
3299 psp->ras.size_bytes = le32_to_cpu(desc->size_bytes);
3300 psp->ras.start_addr = ucode_start_addr;
3301 break;
3302 case TA_FW_TYPE_PSP_HDCP:
3303 psp->hdcp.feature_version = le32_to_cpu(desc->fw_version);
3304 psp->hdcp.size_bytes = le32_to_cpu(desc->size_bytes);
3305 psp->hdcp.start_addr = ucode_start_addr;
3306 break;
3307 case TA_FW_TYPE_PSP_DTM:
3308 psp->dtm.feature_version = le32_to_cpu(desc->fw_version);
3309 psp->dtm.size_bytes = le32_to_cpu(desc->size_bytes);
3310 psp->dtm.start_addr = ucode_start_addr;
3311 break;
3312 case TA_FW_TYPE_PSP_RAP:
3313 psp->rap.feature_version = le32_to_cpu(desc->fw_version);
3314 psp->rap.size_bytes = le32_to_cpu(desc->size_bytes);
3315 psp->rap.start_addr = ucode_start_addr;
3316 break;
3317 case TA_FW_TYPE_PSP_SECUREDISPLAY:
3318 psp->securedisplay.feature_version = le32_to_cpu(desc->fw_version);
3319 psp->securedisplay.size_bytes = le32_to_cpu(desc->size_bytes);
3320 psp->securedisplay.start_addr = ucode_start_addr;
3321 break;
3322 default:
3323 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3324 break;
3325 }
3326
3327 return 0;
3328 }
3329
psp_init_ta_microcode(struct psp_context * psp,const char * chip_name)3330 int psp_init_ta_microcode(struct psp_context *psp,
3331 const char *chip_name)
3332 {
3333 struct amdgpu_device *adev = psp->adev;
3334 char fw_name[PSP_FW_NAME_LEN];
3335 const struct ta_firmware_header_v2_0 *ta_hdr;
3336 int err = 0;
3337 int ta_index = 0;
3338
3339 if (!chip_name) {
3340 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3341 return -EINVAL;
3342 }
3343
3344 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3345 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3346 if (err)
3347 goto out;
3348
3349 err = amdgpu_ucode_validate(adev->psp.ta_fw);
3350 if (err)
3351 goto out;
3352
3353 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3354
3355 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3356 dev_err(adev->dev, "unsupported TA header version\n");
3357 err = -EINVAL;
3358 goto out;
3359 }
3360
3361 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3362 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3363 err = -EINVAL;
3364 goto out;
3365 }
3366
3367 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3368 err = parse_ta_bin_descriptor(psp,
3369 &ta_hdr->ta_fw_bin[ta_index],
3370 ta_hdr);
3371 if (err)
3372 goto out;
3373 }
3374
3375 return 0;
3376 out:
3377 dev_err(adev->dev, "fail to initialize ta microcode\n");
3378 release_firmware(adev->psp.ta_fw);
3379 adev->psp.ta_fw = NULL;
3380 return err;
3381 }
3382
psp_set_clockgating_state(void * handle,enum amd_clockgating_state state)3383 static int psp_set_clockgating_state(void *handle,
3384 enum amd_clockgating_state state)
3385 {
3386 return 0;
3387 }
3388
psp_set_powergating_state(void * handle,enum amd_powergating_state state)3389 static int psp_set_powergating_state(void *handle,
3390 enum amd_powergating_state state)
3391 {
3392 return 0;
3393 }
3394
psp_usbc_pd_fw_sysfs_read(struct device * dev,struct device_attribute * attr,char * buf)3395 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3396 struct device_attribute *attr,
3397 char *buf)
3398 {
3399 struct drm_device *ddev = dev_get_drvdata(dev);
3400 struct amdgpu_device *adev = drm_to_adev(ddev);
3401 uint32_t fw_ver;
3402 int ret;
3403
3404 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3405 DRM_INFO("PSP block is not ready yet.");
3406 return -EBUSY;
3407 }
3408
3409 mutex_lock(&adev->psp.mutex);
3410 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3411 mutex_unlock(&adev->psp.mutex);
3412
3413 if (ret) {
3414 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3415 return ret;
3416 }
3417
3418 return sysfs_emit(buf, "%x\n", fw_ver);
3419 }
3420
psp_usbc_pd_fw_sysfs_write(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3421 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3422 struct device_attribute *attr,
3423 const char *buf,
3424 size_t count)
3425 {
3426 struct drm_device *ddev = dev_get_drvdata(dev);
3427 struct amdgpu_device *adev = drm_to_adev(ddev);
3428 int ret, idx;
3429 char fw_name[100];
3430 const struct firmware *usbc_pd_fw;
3431 struct amdgpu_bo *fw_buf_bo = NULL;
3432 uint64_t fw_pri_mc_addr;
3433 void *fw_pri_cpu_addr;
3434
3435 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3436 DRM_INFO("PSP block is not ready yet.");
3437 return -EBUSY;
3438 }
3439
3440 if (!drm_dev_enter(ddev, &idx))
3441 return -ENODEV;
3442
3443 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3444 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3445 if (ret)
3446 goto fail;
3447
3448 /* LFB address which is aligned to 1MB boundary per PSP request */
3449 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3450 AMDGPU_GEM_DOMAIN_VRAM,
3451 &fw_buf_bo,
3452 &fw_pri_mc_addr,
3453 &fw_pri_cpu_addr);
3454 if (ret)
3455 goto rel_buf;
3456
3457 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3458
3459 mutex_lock(&adev->psp.mutex);
3460 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3461 mutex_unlock(&adev->psp.mutex);
3462
3463 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3464
3465 rel_buf:
3466 release_firmware(usbc_pd_fw);
3467 fail:
3468 if (ret) {
3469 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3470 count = ret;
3471 }
3472
3473 drm_dev_exit(idx);
3474 return count;
3475 }
3476
psp_copy_fw(struct psp_context * psp,uint8_t * start_addr,uint32_t bin_size)3477 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3478 {
3479 int idx;
3480
3481 if (!drm_dev_enter(&psp->adev->ddev, &idx))
3482 return;
3483
3484 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3485 memcpy(psp->fw_pri_buf, start_addr, bin_size);
3486
3487 drm_dev_exit(idx);
3488 }
3489
3490 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3491 psp_usbc_pd_fw_sysfs_read,
3492 psp_usbc_pd_fw_sysfs_write);
3493
is_psp_fw_valid(struct psp_bin_desc bin)3494 int is_psp_fw_valid(struct psp_bin_desc bin)
3495 {
3496 return bin.size_bytes;
3497 }
3498
3499 const struct amd_ip_funcs psp_ip_funcs = {
3500 .name = "psp",
3501 .early_init = psp_early_init,
3502 .late_init = NULL,
3503 .sw_init = psp_sw_init,
3504 .sw_fini = psp_sw_fini,
3505 .hw_init = psp_hw_init,
3506 .hw_fini = psp_hw_fini,
3507 .suspend = psp_suspend,
3508 .resume = psp_resume,
3509 .is_idle = NULL,
3510 .check_soft_reset = NULL,
3511 .wait_for_idle = NULL,
3512 .soft_reset = NULL,
3513 .set_clockgating_state = psp_set_clockgating_state,
3514 .set_powergating_state = psp_set_powergating_state,
3515 };
3516
psp_sysfs_init(struct amdgpu_device * adev)3517 static int psp_sysfs_init(struct amdgpu_device *adev)
3518 {
3519 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3520
3521 if (ret)
3522 DRM_ERROR("Failed to create USBC PD FW control file!");
3523
3524 return ret;
3525 }
3526
psp_sysfs_fini(struct amdgpu_device * adev)3527 static void psp_sysfs_fini(struct amdgpu_device *adev)
3528 {
3529 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3530 }
3531
3532 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3533 {
3534 .type = AMD_IP_BLOCK_TYPE_PSP,
3535 .major = 3,
3536 .minor = 1,
3537 .rev = 0,
3538 .funcs = &psp_ip_funcs,
3539 };
3540
3541 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3542 {
3543 .type = AMD_IP_BLOCK_TYPE_PSP,
3544 .major = 10,
3545 .minor = 0,
3546 .rev = 0,
3547 .funcs = &psp_ip_funcs,
3548 };
3549
3550 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3551 {
3552 .type = AMD_IP_BLOCK_TYPE_PSP,
3553 .major = 11,
3554 .minor = 0,
3555 .rev = 0,
3556 .funcs = &psp_ip_funcs,
3557 };
3558
3559 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3560 .type = AMD_IP_BLOCK_TYPE_PSP,
3561 .major = 11,
3562 .minor = 0,
3563 .rev = 8,
3564 .funcs = &psp_ip_funcs,
3565 };
3566
3567 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3568 {
3569 .type = AMD_IP_BLOCK_TYPE_PSP,
3570 .major = 12,
3571 .minor = 0,
3572 .rev = 0,
3573 .funcs = &psp_ip_funcs,
3574 };
3575
3576 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3577 .type = AMD_IP_BLOCK_TYPE_PSP,
3578 .major = 13,
3579 .minor = 0,
3580 .rev = 0,
3581 .funcs = &psp_ip_funcs,
3582 };
3583
