1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
35
36 #include <rdma/ib_verbs.h>
37 #include <rdma/hns-abi.h>
38
39 #define DRV_NAME "hns_roce"
40
41 #define PCI_REVISION_ID_HIP08 0x21
42 #define PCI_REVISION_ID_HIP09 0x30
43
44 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
45
46 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
47
48 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
49
50 #define BA_BYTE_LEN 8
51
52 /* Hardware specification only for v1 engine */
53 #define HNS_ROCE_MIN_CQE_NUM 0x40
54 #define HNS_ROCE_MIN_WQE_NUM 0x20
55 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1
56
57 /* Hardware specification only for v1 engine */
58 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7
59 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000
60
61 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20
62 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \
63 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
64 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
65 #define HNS_ROCE_MIN_CQE_CNT 16
66
67 #define HNS_ROCE_RESERVED_SGE 1
68
69 #define HNS_ROCE_MAX_IRQ_NUM 128
70
71 #define HNS_ROCE_SGE_IN_WQE 2
72 #define HNS_ROCE_SGE_SHIFT 4
73
74 #define EQ_ENABLE 1
75 #define EQ_DISABLE 0
76
77 #define HNS_ROCE_CEQ 0
78 #define HNS_ROCE_AEQ 1
79
80 #define HNS_ROCE_CEQE_SIZE 0x4
81 #define HNS_ROCE_AEQE_SIZE 0x10
82
83 #define HNS_ROCE_V3_EQE_SIZE 0x40
84
85 #define HNS_ROCE_V2_CQE_SIZE 32
86 #define HNS_ROCE_V3_CQE_SIZE 64
87
88 #define HNS_ROCE_V2_QPC_SZ 256
89 #define HNS_ROCE_V3_QPC_SZ 512
90
91 #define HNS_ROCE_MAX_PORTS 6
92 #define HNS_ROCE_GID_SIZE 16
93 #define HNS_ROCE_SGE_SIZE 16
94 #define HNS_ROCE_DWQE_SIZE 65536
95
96 #define HNS_ROCE_HOP_NUM_0 0xff
97
98 #define MR_TYPE_MR 0x00
99 #define MR_TYPE_FRMR 0x01
100 #define MR_TYPE_DMA 0x03
101
102 #define HNS_ROCE_FRMR_MAX_PA 512
103
104 #define PKEY_ID 0xffff
105 #define GUID_LEN 8
106 #define NODE_DESC_SIZE 64
107 #define DB_REG_OFFSET 0x1000
108
109 /* Configure to HW for PAGE_SIZE larger than 4KB */
110 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
111
112 #define PAGES_SHIFT_8 8
113 #define PAGES_SHIFT_16 16
114 #define PAGES_SHIFT_24 24
115 #define PAGES_SHIFT_32 32
116
117 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
118 #define SRQ_DB_REG 0x230
119
120 #define HNS_ROCE_QP_BANK_NUM 8
121 #define HNS_ROCE_CQ_BANK_NUM 4
122
123 #define CQ_BANKID_SHIFT 2
124
125 /* The chip implementation of the consumer index is calculated
126 * according to twice the actual EQ depth
127 */
128 #define EQ_DEPTH_COEFF 2
129
130 enum {
131 SERV_TYPE_RC,
132 SERV_TYPE_UC,
133 SERV_TYPE_RD,
134 SERV_TYPE_UD,
135 SERV_TYPE_XRC = 5,
136 };
137
138 enum hns_roce_qp_state {
139 HNS_ROCE_QP_STATE_RST,
140 HNS_ROCE_QP_STATE_INIT,
141 HNS_ROCE_QP_STATE_RTR,
142 HNS_ROCE_QP_STATE_RTS,
143 HNS_ROCE_QP_STATE_SQD,
144 HNS_ROCE_QP_STATE_ERR,
145 HNS_ROCE_QP_NUM_STATE,
146 };
147
148 enum hns_roce_event {
149 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
150 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
151 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
152 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
153 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
154 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
155 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
156 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
157 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
158 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
159 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
160 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
161 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
162 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
163 /* 0x10 and 0x11 is unused in currently application case */
164 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
165 HNS_ROCE_EVENT_TYPE_MB = 0x13,
166 HNS_ROCE_EVENT_TYPE_FLR = 0x15,
167 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16,
168 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17,
169 };
170
171 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
172
173 enum {
174 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
175 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
176 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
177 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3),
178 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4),
179 HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
180 HNS_ROCE_CAP_FLAG_XRC = BIT(6),
181 HNS_ROCE_CAP_FLAG_MW = BIT(7),
182 HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
183 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9),
184 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
185 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14),
186 HNS_ROCE_CAP_FLAG_STASH = BIT(17),
187 };
188
189 #define HNS_ROCE_DB_TYPE_COUNT 2
190 #define HNS_ROCE_DB_UNIT_SIZE 4
191
192 enum {
193 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
194 };
195
196 enum hns_roce_reset_stage {
197 HNS_ROCE_STATE_NON_RST,
198 HNS_ROCE_STATE_RST_BEF_DOWN,
199 HNS_ROCE_STATE_RST_DOWN,
200 HNS_ROCE_STATE_RST_UNINIT,
201 HNS_ROCE_STATE_RST_INIT,
202 HNS_ROCE_STATE_RST_INITED,
203 };
204
205 enum hns_roce_instance_state {
206 HNS_ROCE_STATE_NON_INIT,
207 HNS_ROCE_STATE_INIT,
208 HNS_ROCE_STATE_INITED,
209 HNS_ROCE_STATE_UNINIT,
210 };
211
212 enum {
213 HNS_ROCE_RST_DIRECT_RETURN = 0,
214 };
215
216 #define HNS_ROCE_CMD_SUCCESS 1
217
218 /* The minimum page size is 4K for hardware */
219 #define HNS_HW_PAGE_SHIFT 12
220 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
221
222 struct hns_roce_uar {
223 u64 pfn;
224 unsigned long index;
225 unsigned long logic_idx;
226 };
227
228 struct hns_roce_ucontext {
229 struct ib_ucontext ibucontext;
230 struct hns_roce_uar uar;
231 struct list_head page_list;
232 struct mutex page_mutex;
233 };
234
235 struct hns_roce_pd {
236 struct ib_pd ibpd;
237 unsigned long pdn;
238 };
239
240 struct hns_roce_xrcd {
241 struct ib_xrcd ibxrcd;
242 u32 xrcdn;
243 };
244
245 struct hns_roce_bitmap {
246 /* Bitmap Traversal last a bit which is 1 */
247 unsigned long last;
248 unsigned long top;
249 unsigned long max;
250 unsigned long reserved_top;
251 unsigned long mask;
252 spinlock_t lock;
253 unsigned long *table;
254 };
255
256 struct hns_roce_ida {
257 struct ida ida;
258 u32 min; /* Lowest ID to allocate. */
259 u32 max; /* Highest ID to allocate. */
260 };
261
262 /* For Hardware Entry Memory */
263 struct hns_roce_hem_table {
264 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
265 u32 type;
266 /* HEM array elment num */
267 unsigned long num_hem;
268 /* Single obj size */
269 unsigned long obj_size;
270 unsigned long table_chunk_size;
271 int lowmem;
272 struct mutex mutex;
273 struct hns_roce_hem **hem;
274 u64 **bt_l1;
275 dma_addr_t *bt_l1_dma_addr;
276 u64 **bt_l0;
277 dma_addr_t *bt_l0_dma_addr;
278 };
279
280 struct hns_roce_buf_region {
281 u32 offset; /* page offset */
282 u32 count; /* page count */
283 int hopnum; /* addressing hop num */
284 };
285
286 #define HNS_ROCE_MAX_BT_REGION 3
287 #define HNS_ROCE_MAX_BT_LEVEL 3
288 struct hns_roce_hem_list {
289 struct list_head root_bt;
290 /* link all bt dma mem by hop config */
291 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
292 struct list_head btm_bt; /* link all bottom bt in @mid_bt */
293 dma_addr_t root_ba; /* pointer to the root ba table */
294 };
295
296 struct hns_roce_buf_attr {
297 struct {
298 size_t size; /* region size */
299 int hopnum; /* multi-hop addressing hop num */
300 } region[HNS_ROCE_MAX_BT_REGION];
301 unsigned int region_count; /* valid region count */
302 unsigned int page_shift; /* buffer page shift */
303 unsigned int user_access; /* umem access flag */
304 bool mtt_only; /* only alloc buffer-required MTT memory */
305 };
306
307 struct hns_roce_hem_cfg {
308 dma_addr_t root_ba; /* root BA table's address */
309 bool is_direct; /* addressing without BA table */
310 unsigned int ba_pg_shift; /* BA table page shift */
311 unsigned int buf_pg_shift; /* buffer page shift */
312 unsigned int buf_pg_count; /* buffer page count */
313 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
314 unsigned int region_count;
315 };
316
317 /* memory translate region */
318 struct hns_roce_mtr {
319 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
320 struct ib_umem *umem; /* user space buffer */
321 struct hns_roce_buf *kmem; /* kernel space buffer */
322 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */
323 };
324
325 struct hns_roce_mw {
326 struct ib_mw ibmw;
327 u32 pdn;
328 u32 rkey;
329 int enabled; /* MW's active status */
330 u32 pbl_hop_num;
331 u32 pbl_ba_pg_sz;
332 u32 pbl_buf_pg_sz;
333 };
334
335 /* Only support 4K page size for mr register */
336 #define MR_SIZE_4K 0
337
338 struct hns_roce_mr {
339 struct ib_mr ibmr;
340 u64 iova; /* MR's virtual original addr */
341 u64 size; /* Address range of MR */
342 u32 key; /* Key of MR */
343 u32 pd; /* PD num of MR */
344 u32 access; /* Access permission of MR */
345 int enabled; /* MR's active status */
346 int type; /* MR's register type */
347 u32 pbl_hop_num; /* multi-hop number */
348 struct hns_roce_mtr pbl_mtr;
349 u32 npages;
350 dma_addr_t *page_list;
351 };
352
353 struct hns_roce_mr_table {
354 struct hns_roce_ida mtpt_ida;
355 struct hns_roce_hem_table mtpt_table;
356 };
357
358 struct hns_roce_wq {
359 u64 *wrid; /* Work request ID */
360 spinlock_t lock;
361 u32 wqe_cnt; /* WQE num */
362 u32 max_gs;
363 u32 rsv_sge;
364 int offset;
365 int wqe_shift; /* WQE size */
366 u32 head;
367 u32 tail;
368 void __iomem *db_reg;
369 };
370
371 struct hns_roce_sge {
372 unsigned int sge_cnt; /* SGE num */
373 int offset;
374 int sge_shift; /* SGE size */
375 };
376
377 struct hns_roce_buf_list {
378 void *buf;
379 dma_addr_t map;
380 };
381
382 /*
383 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
384 * dma address range.
385 *
386 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
387 *
388 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
389 * the allocated size is smaller than the required size.
390 */
391 enum {
392 HNS_ROCE_BUF_DIRECT = BIT(0),
393 HNS_ROCE_BUF_NOSLEEP = BIT(1),
394 HNS_ROCE_BUF_NOFAIL = BIT(2),
395 };
396
397 struct hns_roce_buf {
398 struct hns_roce_buf_list *trunk_list;
399 u32 ntrunks;
400 u32 npages;
401 unsigned int trunk_shift;
402 unsigned int page_shift;
403 };
404
405 struct hns_roce_db_pgdir {
406 struct list_head list;
407 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
408 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
409 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT];
410 u32 *page;
411 dma_addr_t db_dma;
412 };
413
414 struct hns_roce_user_db_page {
415 struct list_head list;
416 struct ib_umem *umem;
417 unsigned long user_virt;
418 refcount_t refcount;
419 };
420
421 struct hns_roce_db {
422 u32 *db_record;
423 union {
424 struct hns_roce_db_pgdir *pgdir;
425 struct hns_roce_user_db_page *user_page;
426 } u;
427 dma_addr_t dma;
428 void *virt_addr;
429 unsigned long index;
430 unsigned long order;
431 };
432
433 struct hns_roce_cq {
434 struct ib_cq ib_cq;
435 struct hns_roce_mtr mtr;
436 struct hns_roce_db db;
437 u32 flags;
438 spinlock_t lock;
439 u32 cq_depth;
440 u32 cons_index;
441 u32 *set_ci_db;
442 void __iomem *db_reg;
443 u16 *tptr_addr;
444 int arm_sn;
445 int cqe_size;
446 unsigned long cqn;
447 u32 vector;
448 refcount_t refcount;
449 struct completion free;
450 struct list_head sq_list; /* all qps on this send cq */
451 struct list_head rq_list; /* all qps on this recv cq */
452 int is_armed; /* cq is armed */
453 struct list_head node; /* all armed cqs are on a list */
454 };
455
456 struct hns_roce_idx_que {
457 struct hns_roce_mtr mtr;
458 int entry_shift;
459 unsigned long *bitmap;
460 u32 head;
461 u32 tail;
462 };
463
464 struct hns_roce_srq {
465 struct ib_srq ibsrq;
466 unsigned long srqn;
467 u32 wqe_cnt;
468 int max_gs;
469 u32 rsv_sge;
470 int wqe_shift;
471 u32 cqn;
472 u32 xrcdn;
473 void __iomem *db_reg;
474
475 refcount_t refcount;
476 struct completion free;
477
478 struct hns_roce_mtr buf_mtr;
479
480 u64 *wrid;
481 struct hns_roce_idx_que idx_que;
482 spinlock_t lock;
483 struct mutex mutex;
484 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
485 };
486
487 struct hns_roce_uar_table {
488 struct hns_roce_bitmap bitmap;
489 };
490
491 struct hns_roce_bank {
492 struct ida ida;
493 u32 inuse; /* Number of IDs allocated */
494 u32 min; /* Lowest ID to allocate. */
495 u32 max; /* Highest ID to allocate. */
496 u32 next; /* Next ID to allocate. */
497 };
498
499 struct hns_roce_idx_table {
500 u32 *spare_idx;
501 u32 head;
502 u32 tail;
503 };
504
505 struct hns_roce_qp_table {
506 struct hns_roce_hem_table qp_table;
507 struct hns_roce_hem_table irrl_table;
508 struct hns_roce_hem_table trrl_table;
509 struct hns_roce_hem_table sccc_table;
510 struct mutex scc_mutex;
511 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
512 struct mutex bank_mutex;
513 struct hns_roce_idx_table idx_table;
514 };
515
516 struct hns_roce_cq_table {
517 struct xarray array;
518 struct hns_roce_hem_table table;
519 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
520 struct mutex bank_mutex;
521 };
522
523 struct hns_roce_srq_table {
524 struct hns_roce_ida srq_ida;
525 struct xarray xa;
526 struct hns_roce_hem_table table;
527 };
528
529 struct hns_roce_raq_table {
530 struct hns_roce_buf_list *e_raq_buf;
531 };
532
533 struct hns_roce_av {
534 u8 port;
535 u8 gid_index;
536 u8 stat_rate;
537 u8 hop_limit;
538 u32 flowlabel;
539 u16 udp_sport;
540 u8 sl;
541 u8 tclass;
542 u8 dgid[HNS_ROCE_GID_SIZE];
543 u8 mac[ETH_ALEN];
544 u16 vlan_id;
545 u8 vlan_en;
546 };
547
548 struct hns_roce_ah {
549 struct ib_ah ibah;
550 struct hns_roce_av av;
551 };
552
553 struct hns_roce_cmd_context {
554 struct completion done;
555 int result;
556 int next;
557 u64 out_param;
558 u16 token;
559 u16 busy;
560 };
561
562 struct hns_roce_cmdq {
563 struct dma_pool *pool;
564 struct semaphore poll_sem;
565 /*
566 * Event mode: cmd register mutex protection,
567 * ensure to not exceed max_cmds and user use limit region
568 */
569 struct semaphore event_sem;
570 int max_cmds;
571 spinlock_t context_lock;
572 int free_head;
573 struct hns_roce_cmd_context *context;
574 /*
575 * Process whether use event mode, init default non-zero
576 * After the event queue of cmd event ready,
577 * can switch into event mode
578 * close device, switch into poll mode(non event mode)
579 */
580 u8 use_events;
581 };
582
583 struct hns_roce_cmd_mailbox {
584 void *buf;
585 dma_addr_t dma;
586 };
587
588 struct hns_roce_dev;
589
590 struct hns_roce_rinl_sge {
591 void *addr;
592 u32 len;
593 };
594
595 struct hns_roce_rinl_wqe {
596 struct hns_roce_rinl_sge *sg_list;
597 u32 sge_cnt;
598 };
599
600 struct hns_roce_rinl_buf {
601 struct hns_roce_rinl_wqe *wqe_list;
602 u32 wqe_cnt;
603 };
604
605 enum {
606 HNS_ROCE_FLUSH_FLAG = 0,
607 };
608
609 struct hns_roce_work {
610 struct hns_roce_dev *hr_dev;
611 struct work_struct work;
612 int event_type;
613 int sub_type;
614 u32 queue_num;
615 };
616
617 enum {
618 HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5),
619 };
620
621 struct hns_roce_qp {
622 struct ib_qp ibqp;
623 struct hns_roce_wq rq;
624 struct hns_roce_db rdb;
625 struct hns_roce_db sdb;
626 unsigned long en_flags;
627 u32 doorbell_qpn;
628 enum ib_sig_type sq_signal_bits;
629 struct hns_roce_wq sq;
630
631 struct hns_roce_mtr mtr;
632
633 u32 buff_size;
634 struct mutex mutex;
635 u8 port;
636 u8 phy_port;
637 u8 sl;
638 u8 resp_depth;
639 u8 state;
640 u32 access_flags;
641 u32 atomic_rd_en;
642 u32 pkey_index;
643 u32 qkey;
644 void (*event)(struct hns_roce_qp *qp,
645 enum hns_roce_event event_type);
646 unsigned long qpn;
647
648 u32 xrcdn;
649
650 refcount_t refcount;
651 struct completion free;
652
653 struct hns_roce_sge sge;
654 u32 next_sge;
655 enum ib_mtu path_mtu;
656 u32 max_inline_data;
657
658 /* 0: flush needed, 1: unneeded */
659 unsigned long flush_flag;
660 struct hns_roce_work flush_work;
661 struct hns_roce_rinl_buf rq_inl_buf;
662 struct list_head node; /* all qps are on a list */
663 struct list_head rq_node; /* all recv qps are on a list */
664 struct list_head sq_node; /* all send qps are on a list */
665 };
666
667 struct hns_roce_ib_iboe {
668 spinlock_t lock;
669 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
670 struct notifier_block nb;
671 u8 phy_port[HNS_ROCE_MAX_PORTS];
672 };
673
674 enum {
675 HNS_ROCE_EQ_STAT_INVALID = 0,
676 HNS_ROCE_EQ_STAT_VALID = 2,
677 };
678
679 struct hns_roce_ceqe {
680 __le32 comp;
681 __le32 rsv[15];
682 };
683
684 struct hns_roce_aeqe {
685 __le32 asyn;
686 union {
687 struct {
688 __le32 num;
689 u32 rsv0;
690 u32 rsv1;
691 } queue_event;
692
693 struct {
694 __le64 out_param;
695 __le16 token;
696 u8 status;
697 u8 rsv0;
698 } __packed cmd;
699 } event;
700 __le32 rsv[12];
701 };
702
703 struct hns_roce_eq {
704 struct hns_roce_dev *hr_dev;
705 void __iomem *db_reg;
706
707 int type_flag; /* Aeq:1 ceq:0 */
708 int eqn;
709 u32 entries;
710 u32 log_entries;
711 int eqe_size;
712 int irq;
713 int log_page_size;
714 u32 cons_index;
715 struct hns_roce_buf_list *buf_list;
716 int over_ignore;
717 int coalesce;
718 int arm_st;
719 int hop_num;
720 struct hns_roce_mtr mtr;
721 u16 eq_max_cnt;
722 u32 eq_period;
723 int shift;
724 int event_type;
725 int sub_type;
726 };
727
728 struct hns_roce_eq_table {
729 struct hns_roce_eq *eq;
730 void __iomem **eqc_base; /* only for hw v1 */
731 };
732
733 enum cong_type {
734 CONG_TYPE_DCQCN,
735 CONG_TYPE_LDCP,
736 CONG_TYPE_HC3,
737 CONG_TYPE_DIP,
738 };
739
740 struct hns_roce_caps {
741 u64 fw_ver;
742 u8 num_ports;
743 int gid_table_len[HNS_ROCE_MAX_PORTS];
744 int pkey_table_len[HNS_ROCE_MAX_PORTS];
745 int local_ca_ack_delay;
746 int num_uars;
747 u32 phy_num_uars;
748 u32 max_sq_sg;
749 u32 max_sq_inline;
750 u32 max_rq_sg;
751 u32 max_extend_sg;
752 u32 num_qps;
753 u32 num_pi_qps;
754 u32 reserved_qps;
755 int num_qpc_timer;
756 int num_cqc_timer;
757 int num_srqs;
758 u32 max_wqes;
759 u32 max_srq_wrs;
760 u32 max_srq_sges;
761 u32 max_sq_desc_sz;
762 u32 max_rq_desc_sz;
763 u32 max_srq_desc_sz;
764 int max_qp_init_rdma;
765 int max_qp_dest_rdma;
766 u32 num_cqs;
767 u32 max_cqes;
768 u32 min_cqes;
769 u32 min_wqes;
770 u32 reserved_cqs;
771 int reserved_srqs;
772 int num_aeq_vectors;
773 int num_comp_vectors;
774 int num_other_vectors;
775 u32 num_mtpts;
776 u32 num_mtt_segs;
777 u32 num_srqwqe_segs;
778 u32 num_idx_segs;
779 int reserved_mrws;
780 int reserved_uars;
781 int num_pds;
782 int reserved_pds;
783 u32 num_xrcds;
784 u32 reserved_xrcds;
785 u32 mtt_entry_sz;
786 u32 cqe_sz;
787 u32 page_size_cap;
788 u32 reserved_lkey;
789 int mtpt_entry_sz;
790 int qpc_sz;
791 int irrl_entry_sz;
792 int trrl_entry_sz;
793 int cqc_entry_sz;
794 int sccc_sz;
795 int qpc_timer_entry_sz;
796 int cqc_timer_entry_sz;
797 int srqc_entry_sz;
798 int idx_entry_sz;
799 u32 pbl_ba_pg_sz;
800 u32 pbl_buf_pg_sz;
801 u32 pbl_hop_num;
802 int aeqe_depth;
803 int ceqe_depth;
804 u32 aeqe_size;
805 u32 ceqe_size;
806 enum ib_mtu max_mtu;
807 u32 qpc_bt_num;
808 u32 qpc_timer_bt_num;
809 u32 srqc_bt_num;
810 u32 cqc_bt_num;
811 u32 cqc_timer_bt_num;
812 u32 mpt_bt_num;
813 u32 eqc_bt_num;
814 u32 smac_bt_num;
815 u32 sgid_bt_num;
816 u32 sccc_bt_num;
817 u32 gmv_bt_num;
818 u32 qpc_ba_pg_sz;
819 u32 qpc_buf_pg_sz;
820 u32 qpc_hop_num;
821 u32 srqc_ba_pg_sz;
822 u32 srqc_buf_pg_sz;
823 u32 srqc_hop_num;
824 u32 cqc_ba_pg_sz;
825 u32 cqc_buf_pg_sz;
826 u32 cqc_hop_num;
827 u32 mpt_ba_pg_sz;
828 u32 mpt_buf_pg_sz;
829 u32 mpt_hop_num;
830 u32 mtt_ba_pg_sz;
831 u32 mtt_buf_pg_sz;
832 u32 mtt_hop_num;
833 u32 wqe_sq_hop_num;
834 u32 wqe_sge_hop_num;
835 u32 wqe_rq_hop_num;
836 u32 sccc_ba_pg_sz;
837 u32 sccc_buf_pg_sz;
838 u32 sccc_hop_num;
839 u32 qpc_timer_ba_pg_sz;
840 u32 qpc_timer_buf_pg_sz;
841 u32 qpc_timer_hop_num;
842 u32 cqc_timer_ba_pg_sz;
843 u32 cqc_timer_buf_pg_sz;
844 u32 cqc_timer_hop_num;
845 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
846 u32 cqe_buf_pg_sz;
847 u32 cqe_hop_num;
848 u32 srqwqe_ba_pg_sz;
849 u32 srqwqe_buf_pg_sz;
850 u32 srqwqe_hop_num;
851 u32 idx_ba_pg_sz;
852 u32 idx_buf_pg_sz;
853 u32 idx_hop_num;
854 u32 eqe_ba_pg_sz;
855 u32 eqe_buf_pg_sz;
856 u32 eqe_hop_num;
857 u32 gmv_entry_num;
858 u32 gmv_entry_sz;
859 u32 gmv_ba_pg_sz;
860 u32 gmv_buf_pg_sz;
861 u32 gmv_hop_num;
862 u32 sl_num;
863 u32 llm_buf_pg_sz;
864 u32 chunk_sz; /* chunk size in non multihop mode */
865 u64 flags;
866 u16 default_ceq_max_cnt;
867 u16 default_ceq_period;
868 u16 default_aeq_max_cnt;
869 u16 default_aeq_period;
870 u16 default_aeq_arm_st;
871 u16 default_ceq_arm_st;
872 enum cong_type cong_type;
873 };
874
875 struct hns_roce_dfx_hw {
876 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
877 int *buffer);
878 };
879
880 enum hns_roce_device_state {
881 HNS_ROCE_DEVICE_STATE_INITED,
882 HNS_ROCE_DEVICE_STATE_RST_DOWN,
883 HNS_ROCE_DEVICE_STATE_UNINIT,
884 };
885
886 struct hns_roce_hw {
887 int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
888 int (*cmq_init)(struct hns_roce_dev *hr_dev);
889 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
890 int (*hw_profile)(struct hns_roce_dev *hr_dev);
891 int (*hw_init)(struct hns_roce_dev *hr_dev);
892 void (*hw_exit)(struct hns_roce_dev *hr_dev);
893 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
894 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
895 u16 token, int event);
896 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev,
897 unsigned int timeout);
898 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
899 int (*set_gid)(struct hns_roce_dev *hr_dev, u32 port, int gid_index,
900 const union ib_gid *gid, const struct ib_gid_attr *attr);
901 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
902 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
903 enum ib_mtu mtu);
904 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
905 struct hns_roce_mr *mr, unsigned long mtpt_idx);
906 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
907 struct hns_roce_mr *mr, int flags,
908 void *mb_buf);
909 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
910 struct hns_roce_mr *mr);
911 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
912 void (*write_cqc)(struct hns_roce_dev *hr_dev,
913 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
914 dma_addr_t dma_handle);
915 int (*set_hem)(struct hns_roce_dev *hr_dev,
916 struct hns_roce_hem_table *table, int obj, int step_idx);
917 int (*clear_hem)(struct hns_roce_dev *hr_dev,
918 struct hns_roce_hem_table *table, int obj,
919 int step_idx);
920 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
921 int attr_mask, enum ib_qp_state cur_state,
922 enum ib_qp_state new_state);
923 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
924 struct hns_roce_qp *hr_qp);
925 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
926 struct ib_udata *udata);
927 int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
928 int (*init_eq)(struct hns_roce_dev *hr_dev);
929 void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
930 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
931 const struct ib_device_ops *hns_roce_dev_ops;
932 const struct ib_device_ops *hns_roce_dev_srq_ops;
933 };
934
935 struct hns_roce_dev {
936 struct ib_device ib_dev;
937 struct platform_device *pdev;
938 struct pci_dev *pci_dev;
939 struct device *dev;
940 struct hns_roce_uar priv_uar;
941 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
942 spinlock_t sm_lock;
943 spinlock_t bt_cmd_lock;
944 bool active;
945 bool is_reset;
946 bool dis_db;
947 unsigned long reset_cnt;
948 struct hns_roce_ib_iboe iboe;
949 enum hns_roce_device_state state;
950 struct list_head qp_list; /* list of all qps on this dev */
951 spinlock_t qp_list_lock; /* protect qp_list */
952 struct list_head dip_list; /* list of all dest ips on this dev */
953 spinlock_t dip_list_lock; /* protect dip_list */
954
955 struct list_head pgdir_list;
956 struct mutex pgdir_mutex;
957 int irq[HNS_ROCE_MAX_IRQ_NUM];
958 u8 __iomem *reg_base;
959 void __iomem *mem_base;
960 struct hns_roce_caps caps;
961 struct xarray qp_table_xa;
962
963 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
964 u64 sys_image_guid;
965 u32 vendor_id;
966 u32 vendor_part_id;
967 u32 hw_rev;
968 void __iomem *priv_addr;
969
970 struct hns_roce_cmdq cmd;
971 struct hns_roce_ida pd_ida;
972 struct hns_roce_ida xrcd_ida;
973 struct hns_roce_ida uar_ida;
974 struct hns_roce_mr_table mr_table;
975 struct hns_roce_cq_table cq_table;
976 struct hns_roce_srq_table srq_table;
977 struct hns_roce_qp_table qp_table;
978 struct hns_roce_eq_table eq_table;
979 struct hns_roce_hem_table qpc_timer_table;
980 struct hns_roce_hem_table cqc_timer_table;
981 /* GMV is the memory area that the driver allocates for the hardware
982 * to store SGID, SMAC and VLAN information.
983 */
984 struct hns_roce_hem_table gmv_table;
985
986 int cmd_mod;
987 int loop_idc;
988 u32 sdb_offset;
989 u32 odb_offset;
990 dma_addr_t tptr_dma_addr; /* only for hw v1 */
991 u32 tptr_size; /* only for hw v1 */
992 const struct hns_roce_hw *hw;
993 void *priv;
994 struct workqueue_struct *irq_workq;
995 const struct hns_roce_dfx_hw *dfx;
996 u32 func_num;
997 u32 is_vf;
998 u32 cong_algo_tmpl_id;
999 };
1000
to_hr_dev(struct ib_device * ib_dev)1001 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1002 {
1003 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1004 }
1005
1006 static inline struct hns_roce_ucontext
to_hr_ucontext(struct ib_ucontext * ibucontext)1007 *to_hr_ucontext(struct ib_ucontext *ibucontext)
1008 {
1009 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1010 }
1011
to_hr_pd(struct ib_pd * ibpd)1012 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1013 {
1014 return container_of(ibpd, struct hns_roce_pd, ibpd);
1015 }
1016
to_hr_xrcd(struct ib_xrcd * ibxrcd)1017 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
1018 {
1019 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
1020 }
1021
to_hr_ah(struct ib_ah * ibah)1022 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1023 {
1024 return container_of(ibah, struct hns_roce_ah, ibah);
1025 }
1026
to_hr_mr(struct ib_mr * ibmr)1027 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1028 {
1029 return container_of(ibmr, struct hns_roce_mr, ibmr);
1030 }
1031
to_hr_mw(struct ib_mw * ibmw)1032 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1033 {
1034 return container_of(ibmw, struct hns_roce_mw, ibmw);
1035 }
1036
to_hr_qp(struct ib_qp * ibqp)1037 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1038 {
1039 return container_of(ibqp, struct hns_roce_qp, ibqp);
1040 }
1041
to_hr_cq(struct ib_cq * ib_cq)1042 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1043 {
1044 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1045 }
1046
to_hr_srq(struct ib_srq * ibsrq)1047 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1048 {
1049 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1050 }
1051
hns_roce_write64_k(__le32 val[2],void __iomem * dest)1052 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1053 {
1054 writeq(*(u64 *)val, dest);
1055 }
1056
1057 static inline struct hns_roce_qp
__hns_roce_qp_lookup(struct hns_roce_dev * hr_dev,u32 qpn)1058 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1059 {
1060 return xa_load(&hr_dev->qp_table_xa, qpn);
1061 }
1062
hns_roce_buf_offset(struct hns_roce_buf * buf,unsigned int offset)1063 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1064 unsigned int offset)
1065 {
1066 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1067 (offset & ((1 << buf->trunk_shift) - 1));
1068 }
1069
hns_roce_buf_dma_addr(struct hns_roce_buf * buf,unsigned int offset)1070 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf,
1071 unsigned int offset)
1072 {
1073 return buf->trunk_list[offset >> buf->trunk_shift].map +
1074 (offset & ((1 << buf->trunk_shift) - 1));
1075 }
1076
hns_roce_buf_page(struct hns_roce_buf * buf,u32 idx)1077 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1078 {
1079 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift);
1080 }
1081
1082 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1083
to_hr_hw_page_addr(u64 addr)1084 static inline u64 to_hr_hw_page_addr(u64 addr)
1085 {
1086 return addr >> HNS_HW_PAGE_SHIFT;
1087 }
1088
to_hr_hw_page_shift(u32 page_shift)1089 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1090 {
1091 return page_shift - HNS_HW_PAGE_SHIFT;
1092 }
1093
to_hr_hem_hopnum(u32 hopnum,u32 count)1094 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1095 {
1096 if (count > 0)
1097 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1098
1099 return 0;
1100 }
1101
to_hr_hem_entries_size(u32 count,u32 buf_shift)1102 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1103 {
1104 return hr_hw_page_align(count << buf_shift);
1105 }
1106
to_hr_hem_entries_count(u32 count,u32 buf_shift)1107 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1108 {
1109 return hr_hw_page_align(count << buf_shift) >> buf_shift;
1110 }
1111
to_hr_hem_entries_shift(u32 count,u32 buf_shift)1112 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1113 {
1114 if (!count)
1115 return 0;
1116
1117 return ilog2(to_hr_hem_entries_count(count, buf_shift));
1118 }
1119
1120 #define DSCP_SHIFT 2
1121
get_tclass(const struct ib_global_route * grh)1122 static inline u8 get_tclass(const struct ib_global_route *grh)
1123 {
1124 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1125 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1126 }
1127
1128 void hns_roce_init_uar_table(struct hns_roce_dev *dev);
1129 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1130
1131 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1132 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1133 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1134 u64 out_param);
1135 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1136 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1137
1138 /* hns roce hw need current block and next block addr from mtt */
1139 #define MTT_MIN_COUNT 2
1140 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1141 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1142 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1143 struct hns_roce_buf_attr *buf_attr,
1144 unsigned int page_shift, struct ib_udata *udata,
1145 unsigned long user_addr);
1146 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1147 struct hns_roce_mtr *mtr);
1148 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1149 dma_addr_t *pages, unsigned int page_cnt);
1150
1151 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1152 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1153 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1154 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1155 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1156 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1157
1158 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1159 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1160 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1161
1162 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1163
1164 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1165 struct ib_udata *udata);
1166 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
hns_roce_destroy_ah(struct ib_ah * ah,u32 flags)1167 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1168 {
1169 return 0;
1170 }
1171
1172 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1173 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1174
1175 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1176 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1177 u64 virt_addr, int access_flags,
1178 struct ib_udata *udata);
1179 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1180 u64 length, u64 virt_addr,
1181 int mr_access_flags, struct ib_pd *pd,
1182 struct ib_udata *udata);
1183 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1184 u32 max_num_sg);
1185 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1186 unsigned int *sg_offset);
1187 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1188 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1189 struct hns_roce_cmd_mailbox *mailbox,
1190 unsigned long mpt_index);
1191 unsigned long key_to_hw_index(u32 key);
1192
1193 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1194 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1195
1196 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1197 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1198 u32 page_shift, u32 flags);
1199
1200 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1201 int buf_cnt, struct hns_roce_buf *buf,
1202 unsigned int page_shift);
1203 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1204 int buf_cnt, struct ib_umem *umem,
1205 unsigned int page_shift);
1206
1207 int hns_roce_create_srq(struct ib_srq *srq,
1208 struct ib_srq_init_attr *srq_init_attr,
1209 struct ib_udata *udata);
1210 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1211 enum ib_srq_attr_mask srq_attr_mask,
1212 struct ib_udata *udata);
1213 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1214
1215 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1216 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1217
1218 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr,
1219 struct ib_udata *udata);
1220 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1221 int attr_mask, struct ib_udata *udata);
1222 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1223 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1224 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1225 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1226 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1227 struct ib_cq *ib_cq);
1228 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1229 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1230 struct hns_roce_cq *recv_cq);
1231 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1232 struct hns_roce_cq *recv_cq);
1233 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1234 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1235 struct ib_udata *udata);
1236 __be32 send_ieth(const struct ib_send_wr *wr);
1237 int to_hr_qp_type(int qp_type);
1238
1239 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1240 struct ib_udata *udata);
1241
1242 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1243 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1244 struct hns_roce_db *db);
1245 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1246 struct hns_roce_db *db);
1247 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1248 int order);
1249 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1250
1251 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1252 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1253 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp);
1254 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1255 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1256 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index);
1257 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1258 int hns_roce_init(struct hns_roce_dev *hr_dev);
1259 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1260 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1261 struct ib_cq *ib_cq);
1262 #endif /* _HNS_ROCE_DEVICE_H */
1263
