1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Support for the interrupt controllers found on Power Macintosh,
4 * currently Apple's "Grand Central" interrupt controller in all
5 * it's incarnations. OpenPIC support used on newer machines is
6 * in a separate file
7 *
8 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
9 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
10 * IBM, Corp.
11 */
12
13 #include <linux/stddef.h>
14 #include <linux/init.h>
15 #include <linux/sched.h>
16 #include <linux/signal.h>
17 #include <linux/pci.h>
18 #include <linux/interrupt.h>
19 #include <linux/syscore_ops.h>
20 #include <linux/adb.h>
21 #include <linux/pmu.h>
22
23 #include <asm/sections.h>
24 #include <asm/io.h>
25 #include <asm/smp.h>
26 #include <asm/prom.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/time.h>
29 #include <asm/pmac_feature.h>
30 #include <asm/mpic.h>
31 #include <asm/xmon.h>
32
33 #include "pmac.h"
34
35 #ifdef CONFIG_PPC32
36 struct pmac_irq_hw {
37 unsigned int event;
38 unsigned int enable;
39 unsigned int ack;
40 unsigned int level;
41 };
42
43 /* Workaround flags for 32bit powermac machines */
44 unsigned int of_irq_workarounds;
45 struct device_node *of_irq_dflt_pic;
46
47 /* Default addresses */
48 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
49
50 static int max_irqs;
51 static int max_real_irqs;
52
53 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
54
55 /* The max irq number this driver deals with is 128; see max_irqs */
56 static DECLARE_BITMAP(ppc_lost_interrupts, 128);
57 static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
58 static int pmac_irq_cascade = -1;
59 static struct irq_domain *pmac_pic_host;
60
__pmac_retrigger(unsigned int irq_nr)61 static void __pmac_retrigger(unsigned int irq_nr)
62 {
63 if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
64 __set_bit(irq_nr, ppc_lost_interrupts);
65 irq_nr = pmac_irq_cascade;
66 mb();
67 }
68 if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
69 atomic_inc(&ppc_n_lost_interrupts);
70 set_dec(1);
71 }
72 }
73
pmac_mask_and_ack_irq(struct irq_data * d)74 static void pmac_mask_and_ack_irq(struct irq_data *d)
75 {
76 unsigned int src = irqd_to_hwirq(d);
77 unsigned long bit = 1UL << (src & 0x1f);
78 int i = src >> 5;
79 unsigned long flags;
80
81 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
82 __clear_bit(src, ppc_cached_irq_mask);
83 if (__test_and_clear_bit(src, ppc_lost_interrupts))
84 atomic_dec(&ppc_n_lost_interrupts);
85 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
86 out_le32(&pmac_irq_hw[i]->ack, bit);
87 do {
88 /* make sure ack gets to controller before we enable
89 interrupts */
90 mb();
91 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
92 != (ppc_cached_irq_mask[i] & bit));
93 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
94 }
95
pmac_ack_irq(struct irq_data * d)96 static void pmac_ack_irq(struct irq_data *d)
97 {
98 unsigned int src = irqd_to_hwirq(d);
99 unsigned long bit = 1UL << (src & 0x1f);
100 int i = src >> 5;
101 unsigned long flags;
102
103 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
104 if (__test_and_clear_bit(src, ppc_lost_interrupts))
105 atomic_dec(&ppc_n_lost_interrupts);
106 out_le32(&pmac_irq_hw[i]->ack, bit);
107 (void)in_le32(&pmac_irq_hw[i]->ack);
108 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
109 }
110
__pmac_set_irq_mask(unsigned int irq_nr,int nokicklost)111 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
112 {
113 unsigned long bit = 1UL << (irq_nr & 0x1f);
114 int i = irq_nr >> 5;
115
116 if ((unsigned)irq_nr >= max_irqs)
117 return;
118
119 /* enable unmasked interrupts */
120 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
121
122 do {
123 /* make sure mask gets to controller before we
124 return to user */
125 mb();
126 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
127 != (ppc_cached_irq_mask[i] & bit));
128
129 /*
130 * Unfortunately, setting the bit in the enable register
131 * when the device interrupt is already on *doesn't* set
132 * the bit in the flag register or request another interrupt.
133 */
134 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
135 __pmac_retrigger(irq_nr);
136 }
137
138 /* When an irq gets requested for the first client, if it's an
139 * edge interrupt, we clear any previous one on the controller
140 */
pmac_startup_irq(struct irq_data * d)141 static unsigned int pmac_startup_irq(struct irq_data *d)
142 {
143 unsigned long flags;
144 unsigned int src = irqd_to_hwirq(d);
145 unsigned long bit = 1UL << (src & 0x1f);
146 int i = src >> 5;
147
148 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
149 if (!irqd_is_level_type(d))
150 out_le32(&pmac_irq_hw[i]->ack, bit);
151 __set_bit(src, ppc_cached_irq_mask);
152 __pmac_set_irq_mask(src, 0);
153 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
154
155 return 0;
156 }
157
pmac_mask_irq(struct irq_data * d)158 static void pmac_mask_irq(struct irq_data *d)
159 {
160 unsigned long flags;
161 unsigned int src = irqd_to_hwirq(d);
162
163 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
164 __clear_bit(src, ppc_cached_irq_mask);
165 __pmac_set_irq_mask(src, 1);
166 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
167 }
168
pmac_unmask_irq(struct irq_data * d)169 static void pmac_unmask_irq(struct irq_data *d)
170 {
171 unsigned long flags;
172 unsigned int src = irqd_to_hwirq(d);
173
174 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
175 __set_bit(src, ppc_cached_irq_mask);
176 __pmac_set_irq_mask(src, 0);
177 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
178 }
179
pmac_retrigger(struct irq_data * d)180 static int pmac_retrigger(struct irq_data *d)
181 {
182 unsigned long flags;
183
184 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
185 __pmac_retrigger(irqd_to_hwirq(d));
186 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
187 return 1;
188 }
189
190 static struct irq_chip pmac_pic = {
191 .name = "PMAC-PIC",
192 .irq_startup = pmac_startup_irq,
193 .irq_mask = pmac_mask_irq,
194 .irq_ack = pmac_ack_irq,
195 .irq_mask_ack = pmac_mask_and_ack_irq,
196 .irq_unmask = pmac_unmask_irq,
197 .irq_retrigger = pmac_retrigger,
198 };
199
gatwick_action(int cpl,void * dev_id)200 static irqreturn_t gatwick_action(int cpl, void *dev_id)
201 {
202 unsigned long flags;
203 int irq, bits;
204 int rc = IRQ_NONE;
205
206 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
207 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
208 int i = irq >> 5;
209 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
210 bits |= in_le32(&pmac_irq_hw[i]->level);
211 bits &= ppc_cached_irq_mask[i];
212 if (bits == 0)
213 continue;
214 irq += __ilog2(bits);
215 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
216 generic_handle_irq(irq);
217 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
218 rc = IRQ_HANDLED;
219 }
220 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
221 return rc;
222 }
223
pmac_pic_get_irq(void)224 static unsigned int pmac_pic_get_irq(void)
225 {
226 int irq;
227 unsigned long bits = 0;
228 unsigned long flags;
229
230 #ifdef CONFIG_PPC_PMAC32_PSURGE
231 /* IPI's are a hack on the powersurge -- Cort */
232 if (smp_processor_id() != 0) {
233 return psurge_secondary_virq;
234 }
235 #endif /* CONFIG_PPC_PMAC32_PSURGE */
236 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
237 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
238 int i = irq >> 5;
239 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
240 bits |= in_le32(&pmac_irq_hw[i]->level);
241 bits &= ppc_cached_irq_mask[i];
242 if (bits == 0)
243 continue;
244 irq += __ilog2(bits);
245 break;
246 }
247 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
248 if (unlikely(irq < 0))
249 return 0;
250 return irq_linear_revmap(pmac_pic_host, irq);
251 }
252
253 #ifdef CONFIG_XMON
254 static struct irqaction xmon_action = {
255 .handler = xmon_irq,
256 .flags = IRQF_NO_THREAD,
257 .name = "NMI - XMON"
258 };
259 #endif
260
261 static struct irqaction gatwick_cascade_action = {
262 .handler = gatwick_action,
263 .flags = IRQF_NO_THREAD,
264 .name = "cascade",
265 };
266
pmac_pic_host_match(struct irq_domain * h,struct device_node * node,enum irq_domain_bus_token bus_token)267 static int pmac_pic_host_match(struct irq_domain *h, struct device_node *node,
268 enum irq_domain_bus_token bus_token)
269 {
270 /* We match all, we don't always have a node anyway */
271 return 1;
272 }
273
pmac_pic_host_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)274 static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq,
275 irq_hw_number_t hw)
276 {
277 if (hw >= max_irqs)
278 return -EINVAL;
279
280 /* Mark level interrupts, set delayed disable for edge ones and set
281 * handlers
282 */
283 irq_set_status_flags(virq, IRQ_LEVEL);
284 irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
285 return 0;
286 }
287
288 static const struct irq_domain_ops pmac_pic_host_ops = {
289 .match = pmac_pic_host_match,
290 .map = pmac_pic_host_map,
291 .xlate = irq_domain_xlate_onecell,
292 };
293
pmac_pic_probe_oldstyle(void)294 static void __init pmac_pic_probe_oldstyle(void)
295 {
296 int i;
297 struct device_node *master = NULL;
298 struct device_node *slave = NULL;
299 u8 __iomem *addr;
300 struct resource r;
301
302 /* Set our get_irq function */
303 ppc_md.get_irq = pmac_pic_get_irq;
304
305 /*
306 * Find the interrupt controller type & node
307 */
308
309 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
310 max_irqs = max_real_irqs = 32;
311 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
312 max_irqs = max_real_irqs = 32;
313 /* We might have a second cascaded ohare */
314 slave = of_find_node_by_name(NULL, "pci106b,7");
315 if (slave)
316 max_irqs = 64;
317 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
318 max_irqs = max_real_irqs = 64;
319
320 /* We might have a second cascaded heathrow */
321
322 /* Compensate for of_node_put() in of_find_node_by_name() */
323 of_node_get(master);
324 slave = of_find_node_by_name(master, "mac-io");
325
326 /* Check ordering of master & slave */
327 if (of_device_is_compatible(master, "gatwick")) {
328 struct device_node *tmp;
329 BUG_ON(slave == NULL);
330 tmp = master;
331 master = slave;
332 slave = tmp;
333 }
334
335 /* We found a slave */
336 if (slave)
337 max_irqs = 128;
338 }
339 BUG_ON(master == NULL);
340
341 /*
342 * Allocate an irq host
343 */
344 pmac_pic_host = irq_domain_add_linear(master, max_irqs,
345 &pmac_pic_host_ops, NULL);
346 BUG_ON(pmac_pic_host == NULL);
347 irq_set_default_host(pmac_pic_host);
348
349 /* Get addresses of first controller if we have a node for it */
350 BUG_ON(of_address_to_resource(master, 0, &r));
351
352 /* Map interrupts of primary controller */
353 addr = (u8 __iomem *) ioremap(r.start, 0x40);
354 i = 0;
355 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
356 (addr + 0x20);
357 if (max_real_irqs > 32)
358 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
359 (addr + 0x10);
360 of_node_put(master);
361
362 printk(KERN_INFO "irq: Found primary Apple PIC %pOF for %d irqs\n",
363 master, max_real_irqs);
364
365 /* Map interrupts of cascaded controller */
366 if (slave && !of_address_to_resource(slave, 0, &r)) {
367 addr = (u8 __iomem *)ioremap(r.start, 0x40);
368 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
369 (addr + 0x20);
370 if (max_irqs > 64)
371 pmac_irq_hw[i++] =
372 (volatile struct pmac_irq_hw __iomem *)
373 (addr + 0x10);
374 pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
375
376 printk(KERN_INFO "irq: Found slave Apple PIC %pOF for %d irqs"
377 " cascade: %d\n", slave,
378 max_irqs - max_real_irqs, pmac_irq_cascade);
379 }
380 of_node_put(slave);
381
382 /* Disable all interrupts in all controllers */
383 for (i = 0; i * 32 < max_irqs; ++i)
384 out_le32(&pmac_irq_hw[i]->enable, 0);
385
386 /* Hookup cascade irq */
387 if (slave && pmac_irq_cascade)
388 setup_irq(pmac_irq_cascade, &gatwick_cascade_action);
389
390 printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
391 #ifdef CONFIG_XMON
392 setup_irq(irq_create_mapping(NULL, 20), &xmon_action);
393 #endif
394 }
395
of_irq_parse_oldworld(struct device_node * device,int index,struct of_phandle_args * out_irq)396 int of_irq_parse_oldworld(struct device_node *device, int index,
397 struct of_phandle_args *out_irq)
398 {
399 const u32 *ints = NULL;
400 int intlen;
401
402 /*
403 * Old machines just have a list of interrupt numbers
404 * and no interrupt-controller nodes. We also have dodgy
405 * cases where the APPL,interrupts property is completely
406 * missing behind pci-pci bridges and we have to get it
407 * from the parent (the bridge itself, as apple just wired
408 * everything together on these)
409 */
410 while (device) {
411 ints = of_get_property(device, "AAPL,interrupts", &intlen);
412 if (ints != NULL)
413 break;
414 device = device->parent;
415 if (!of_node_is_type(device, "pci"))
416 break;
417 }
418 if (ints == NULL)
419 return -EINVAL;
420 intlen /= sizeof(u32);
421
422 if (index >= intlen)
423 return -EINVAL;
424
425 out_irq->np = NULL;
426 out_irq->args[0] = ints[index];
427 out_irq->args_count = 1;
428
429 return 0;
430 }
431 #endif /* CONFIG_PPC32 */
432
pmac_pic_setup_mpic_nmi(struct mpic * mpic)433 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
434 {
435 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
436 struct device_node* pswitch;
437 int nmi_irq;
438
439 pswitch = of_find_node_by_name(NULL, "programmer-switch");
440 if (pswitch) {
441 nmi_irq = irq_of_parse_and_map(pswitch, 0);
442 if (nmi_irq) {
443 mpic_irq_set_priority(nmi_irq, 9);
444 setup_irq(nmi_irq, &xmon_action);
445 }
446 of_node_put(pswitch);
447 }
448 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
449 }
450
pmac_setup_one_mpic(struct device_node * np,int master)451 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
452 int master)
453 {
454 const char *name = master ? " MPIC 1 " : " MPIC 2 ";
455 struct mpic *mpic;
456 unsigned int flags = master ? 0 : MPIC_SECONDARY;
457
458 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
459
460 if (of_get_property(np, "big-endian", NULL))
461 flags |= MPIC_BIG_ENDIAN;
462
463 /* Primary Big Endian means HT interrupts. This is quite dodgy
464 * but works until I find a better way
465 */
466 if (master && (flags & MPIC_BIG_ENDIAN))
467 flags |= MPIC_U3_HT_IRQS;
468
469 mpic = mpic_alloc(np, 0, flags, 0, 0, name);
470 if (mpic == NULL)
471 return NULL;
472
473 mpic_init(mpic);
474
475 return mpic;
476 }
477
pmac_pic_probe_mpic(void)478 static int __init pmac_pic_probe_mpic(void)
479 {
480 struct mpic *mpic1, *mpic2;
481 struct device_node *np, *master = NULL, *slave = NULL;
482
483 /* We can have up to 2 MPICs cascaded */
484 for_each_node_by_type(np, "open-pic") {
485 if (master == NULL &&
486 of_get_property(np, "interrupts", NULL) == NULL)
487 master = of_node_get(np);
488 else if (slave == NULL)
489 slave = of_node_get(np);
490 if (master && slave) {
491 of_node_put(np);
492 break;
493 }
494 }
495
496 /* Check for bogus setups */
497 if (master == NULL && slave != NULL) {
498 master = slave;
499 slave = NULL;
500 }
501
502 /* Not found, default to good old pmac pic */
503 if (master == NULL)
504 return -ENODEV;
505
506 /* Set master handler */
507 ppc_md.get_irq = mpic_get_irq;
508
509 /* Setup master */
510 mpic1 = pmac_setup_one_mpic(master, 1);
511 BUG_ON(mpic1 == NULL);
512
513 /* Install NMI if any */
514 pmac_pic_setup_mpic_nmi(mpic1);
515
516 of_node_put(master);
517
518 /* Set up a cascaded controller, if present */
519 if (slave) {
520 mpic2 = pmac_setup_one_mpic(slave, 0);
521 if (mpic2 == NULL)
522 printk(KERN_ERR "Failed to setup slave MPIC\n");
523 of_node_put(slave);
524 }
525
526 return 0;
527 }
528
529
pmac_pic_init(void)530 void __init pmac_pic_init(void)
531 {
532 /* We configure the OF parsing based on our oldworld vs. newworld
533 * platform type and whether we were booted by BootX.
534 */
535 #ifdef CONFIG_PPC32
536 if (!pmac_newworld)
537 of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
538 if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
539 of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
540
541 /* If we don't have phandles on a newworld, then try to locate a
542 * default interrupt controller (happens when booting with BootX).
543 * We do a first match here, hopefully, that only ever happens on
544 * machines with one controller.
545 */
546 if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
547 struct device_node *np;
548
549 for_each_node_with_property(np, "interrupt-controller") {
550 /* Skip /chosen/interrupt-controller */
551 if (of_node_name_eq(np, "chosen"))
552 continue;
553 /* It seems like at least one person wants
554 * to use BootX on a machine with an AppleKiwi
555 * controller which happens to pretend to be an
556 * interrupt controller too. */
557 if (of_node_name_eq(np, "AppleKiwi"))
558 continue;
559 /* I think we found one ! */
560 of_irq_dflt_pic = np;
561 break;
562 }
563 }
564 #endif /* CONFIG_PPC32 */
565
566 /* We first try to detect Apple's new Core99 chipset, since mac-io
567 * is quite different on those machines and contains an IBM MPIC2.
568 */
569 if (pmac_pic_probe_mpic() == 0)
570 return;
571
572 #ifdef CONFIG_PPC32
573 pmac_pic_probe_oldstyle();
574 #endif
575 }
576
577 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
578 /*
579 * These procedures are used in implementing sleep on the powerbooks.
580 * sleep_save_intrs() saves the states of all interrupt enables
581 * and disables all interrupts except for the nominated one.
582 * sleep_restore_intrs() restores the states of all interrupt enables.
583 */
584 unsigned long sleep_save_mask[2];
585
586 /* This used to be passed by the PMU driver but that link got
587 * broken with the new driver model. We use this tweak for now...
588 * We really want to do things differently though...
589 */
pmacpic_find_viaint(void)590 static int pmacpic_find_viaint(void)
591 {
592 int viaint = -1;
593
594 #ifdef CONFIG_ADB_PMU
595 struct device_node *np;
596
597 if (pmu_get_model() != PMU_OHARE_BASED)
598 goto not_found;
599 np = of_find_node_by_name(NULL, "via-pmu");
600 if (np == NULL)
601 goto not_found;
602 viaint = irq_of_parse_and_map(np, 0);
603 of_node_put(np);
604
605 not_found:
606 #endif /* CONFIG_ADB_PMU */
607 return viaint;
608 }
609
pmacpic_suspend(void)610 static int pmacpic_suspend(void)
611 {
612 int viaint = pmacpic_find_viaint();
613
614 sleep_save_mask[0] = ppc_cached_irq_mask[0];
615 sleep_save_mask[1] = ppc_cached_irq_mask[1];
616 ppc_cached_irq_mask[0] = 0;
617 ppc_cached_irq_mask[1] = 0;
618 if (viaint > 0)
619 set_bit(viaint, ppc_cached_irq_mask);
620 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
621 if (max_real_irqs > 32)
622 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
623 (void)in_le32(&pmac_irq_hw[0]->event);
624 /* make sure mask gets to controller before we return to caller */
625 mb();
626 (void)in_le32(&pmac_irq_hw[0]->enable);
627
628 return 0;
629 }
630
pmacpic_resume(void)631 static void pmacpic_resume(void)
632 {
633 int i;
634
635 out_le32(&pmac_irq_hw[0]->enable, 0);
636 if (max_real_irqs > 32)
637 out_le32(&pmac_irq_hw[1]->enable, 0);
638 mb();
639 for (i = 0; i < max_real_irqs; ++i)
640 if (test_bit(i, sleep_save_mask))
641 pmac_unmask_irq(irq_get_irq_data(i));
642 }
643
644 static struct syscore_ops pmacpic_syscore_ops = {
645 .suspend = pmacpic_suspend,
646 .resume = pmacpic_resume,
647 };
648
init_pmacpic_syscore(void)649 static int __init init_pmacpic_syscore(void)
650 {
651 if (pmac_irq_hw[0])
652 register_syscore_ops(&pmacpic_syscore_ops);
653 return 0;
654 }
655
656 machine_subsys_initcall(powermac, init_pmacpic_syscore);
657
658 #endif /* CONFIG_PM && CONFIG_PPC32 */
659
