1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2019 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13 #ifndef __FIRMWARE_ZYNQMP_H__
14 #define __FIRMWARE_ZYNQMP_H__
15
16 #define ZYNQMP_PM_VERSION_MAJOR 1
17 #define ZYNQMP_PM_VERSION_MINOR 0
18
19 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
20 ZYNQMP_PM_VERSION_MINOR)
21
22 #define ZYNQMP_TZ_VERSION_MAJOR 1
23 #define ZYNQMP_TZ_VERSION_MINOR 0
24
25 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
26 ZYNQMP_TZ_VERSION_MINOR)
27
28 /* SMC SIP service Call Function Identifier Prefix */
29 #define PM_SIP_SVC 0xC2000000
30 #define PM_GET_TRUSTZONE_VERSION 0xa03
31 #define PM_SET_SUSPEND_MODE 0xa02
32 #define GET_CALLBACK_DATA 0xa01
33
34 /* Number of 32bits values in payload */
35 #define PAYLOAD_ARG_CNT 4U
36
37 /* Number of arguments for a callback */
38 #define CB_ARG_CNT 4
39
40 /* Payload size (consists of callback API ID + arguments) */
41 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
42
43 #define ZYNQMP_PM_MAX_QOS 100U
44
45 #define GSS_NUM_REGS (4)
46
47 /* Node capabilities */
48 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
49 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
50 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
51 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
52
53 /*
54 * Firmware FPGA Manager flags
55 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
56 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
57 */
58 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
59 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
60
61 enum pm_api_id {
62 PM_GET_API_VERSION = 1,
63 PM_SYSTEM_SHUTDOWN = 12,
64 PM_REQUEST_NODE = 13,
65 PM_RELEASE_NODE,
66 PM_SET_REQUIREMENT,
67 PM_RESET_ASSERT = 17,
68 PM_RESET_GET_STATUS,
69 PM_PM_INIT_FINALIZE = 21,
70 PM_FPGA_LOAD,
71 PM_FPGA_GET_STATUS,
72 PM_GET_CHIPID = 24,
73 PM_IOCTL = 34,
74 PM_QUERY_DATA,
75 PM_CLOCK_ENABLE,
76 PM_CLOCK_DISABLE,
77 PM_CLOCK_GETSTATE,
78 PM_CLOCK_SETDIVIDER,
79 PM_CLOCK_GETDIVIDER,
80 PM_CLOCK_SETRATE,
81 PM_CLOCK_GETRATE,
82 PM_CLOCK_SETPARENT,
83 PM_CLOCK_GETPARENT,
84 PM_SECURE_AES = 47,
85 PM_FEATURE_CHECK = 63,
86 PM_API_MAX,
87 };
88
89 /* PMU-FW return status codes */
90 enum pm_ret_status {
91 XST_PM_SUCCESS = 0,
92 XST_PM_NO_FEATURE = 19,
93 XST_PM_INTERNAL = 2000,
94 XST_PM_CONFLICT,
95 XST_PM_NO_ACCESS,
96 XST_PM_INVALID_NODE,
97 XST_PM_DOUBLE_REQ,
98 XST_PM_ABORT_SUSPEND,
99 XST_PM_MULT_USER = 2008,
100 };
101
102 enum pm_ioctl_id {
103 IOCTL_SD_DLL_RESET = 6,
104 IOCTL_SET_SD_TAPDELAY,
105 IOCTL_SET_PLL_FRAC_MODE,
106 IOCTL_GET_PLL_FRAC_MODE,
107 IOCTL_SET_PLL_FRAC_DATA,
108 IOCTL_GET_PLL_FRAC_DATA,
109 IOCTL_WRITE_GGS = 12,
110 IOCTL_READ_GGS = 13,
111 IOCTL_WRITE_PGGS = 14,
112 IOCTL_READ_PGGS = 15,
113 /* Set healthy bit value */
114 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
115 };
116
117 enum pm_query_id {
118 PM_QID_INVALID,
119 PM_QID_CLOCK_GET_NAME,
120 PM_QID_CLOCK_GET_TOPOLOGY,
121 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
122 PM_QID_CLOCK_GET_PARENTS,
123 PM_QID_CLOCK_GET_ATTRIBUTES,
124 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
125 PM_QID_CLOCK_GET_MAX_DIVISOR,
126 };
127
128 enum zynqmp_pm_reset_action {
129 PM_RESET_ACTION_RELEASE,
130 PM_RESET_ACTION_ASSERT,
131 PM_RESET_ACTION_PULSE,
132 };
133
134 enum zynqmp_pm_reset {
135 ZYNQMP_PM_RESET_START = 1000,
136 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
137 ZYNQMP_PM_RESET_PCIE_BRIDGE,
138 ZYNQMP_PM_RESET_PCIE_CTRL,
139 ZYNQMP_PM_RESET_DP,
140 ZYNQMP_PM_RESET_SWDT_CRF,
141 ZYNQMP_PM_RESET_AFI_FM5,
142 ZYNQMP_PM_RESET_AFI_FM4,
143 ZYNQMP_PM_RESET_AFI_FM3,
144 ZYNQMP_PM_RESET_AFI_FM2,
145 ZYNQMP_PM_RESET_AFI_FM1,
146 ZYNQMP_PM_RESET_AFI_FM0,
147 ZYNQMP_PM_RESET_GDMA,
148 ZYNQMP_PM_RESET_GPU_PP1,
149 ZYNQMP_PM_RESET_GPU_PP0,
150 ZYNQMP_PM_RESET_GPU,
151 ZYNQMP_PM_RESET_GT,
152 ZYNQMP_PM_RESET_SATA,
153 ZYNQMP_PM_RESET_ACPU3_PWRON,
154 ZYNQMP_PM_RESET_ACPU2_PWRON,
155 ZYNQMP_PM_RESET_ACPU1_PWRON,
156 ZYNQMP_PM_RESET_ACPU0_PWRON,
157 ZYNQMP_PM_RESET_APU_L2,
158 ZYNQMP_PM_RESET_ACPU3,
159 ZYNQMP_PM_RESET_ACPU2,
160 ZYNQMP_PM_RESET_ACPU1,
161 ZYNQMP_PM_RESET_ACPU0,
162 ZYNQMP_PM_RESET_DDR,
163 ZYNQMP_PM_RESET_APM_FPD,
164 ZYNQMP_PM_RESET_SOFT,
165 ZYNQMP_PM_RESET_GEM0,
166 ZYNQMP_PM_RESET_GEM1,
167 ZYNQMP_PM_RESET_GEM2,
168 ZYNQMP_PM_RESET_GEM3,
169 ZYNQMP_PM_RESET_QSPI,
170 ZYNQMP_PM_RESET_UART0,
171 ZYNQMP_PM_RESET_UART1,
172 ZYNQMP_PM_RESET_SPI0,
173 ZYNQMP_PM_RESET_SPI1,
174 ZYNQMP_PM_RESET_SDIO0,
175 ZYNQMP_PM_RESET_SDIO1,
176 ZYNQMP_PM_RESET_CAN0,
177 ZYNQMP_PM_RESET_CAN1,
178 ZYNQMP_PM_RESET_I2C0,
179 ZYNQMP_PM_RESET_I2C1,
180 ZYNQMP_PM_RESET_TTC0,
181 ZYNQMP_PM_RESET_TTC1,
182 ZYNQMP_PM_RESET_TTC2,
183 ZYNQMP_PM_RESET_TTC3,
184 ZYNQMP_PM_RESET_SWDT_CRL,
185 ZYNQMP_PM_RESET_NAND,
186 ZYNQMP_PM_RESET_ADMA,
187 ZYNQMP_PM_RESET_GPIO,
188 ZYNQMP_PM_RESET_IOU_CC,
189 ZYNQMP_PM_RESET_TIMESTAMP,
190 ZYNQMP_PM_RESET_RPU_R50,
191 ZYNQMP_PM_RESET_RPU_R51,
192 ZYNQMP_PM_RESET_RPU_AMBA,
193 ZYNQMP_PM_RESET_OCM,
194 ZYNQMP_PM_RESET_RPU_PGE,
195 ZYNQMP_PM_RESET_USB0_CORERESET,
196 ZYNQMP_PM_RESET_USB1_CORERESET,
197 ZYNQMP_PM_RESET_USB0_HIBERRESET,
198 ZYNQMP_PM_RESET_USB1_HIBERRESET,
199 ZYNQMP_PM_RESET_USB0_APB,
200 ZYNQMP_PM_RESET_USB1_APB,
201 ZYNQMP_PM_RESET_IPI,
202 ZYNQMP_PM_RESET_APM_LPD,
203 ZYNQMP_PM_RESET_RTC,
204 ZYNQMP_PM_RESET_SYSMON,
205 ZYNQMP_PM_RESET_AFI_FM6,
206 ZYNQMP_PM_RESET_LPD_SWDT,
207 ZYNQMP_PM_RESET_FPD,
208 ZYNQMP_PM_RESET_RPU_DBG1,
209 ZYNQMP_PM_RESET_RPU_DBG0,
210 ZYNQMP_PM_RESET_DBG_LPD,
211 ZYNQMP_PM_RESET_DBG_FPD,
212 ZYNQMP_PM_RESET_APLL,
213 ZYNQMP_PM_RESET_DPLL,
214 ZYNQMP_PM_RESET_VPLL,
215 ZYNQMP_PM_RESET_IOPLL,
216 ZYNQMP_PM_RESET_RPLL,
217 ZYNQMP_PM_RESET_GPO3_PL_0,
218 ZYNQMP_PM_RESET_GPO3_PL_1,
219 ZYNQMP_PM_RESET_GPO3_PL_2,
220 ZYNQMP_PM_RESET_GPO3_PL_3,
221 ZYNQMP_PM_RESET_GPO3_PL_4,
222 ZYNQMP_PM_RESET_GPO3_PL_5,
223 ZYNQMP_PM_RESET_GPO3_PL_6,
224 ZYNQMP_PM_RESET_GPO3_PL_7,
225 ZYNQMP_PM_RESET_GPO3_PL_8,
226 ZYNQMP_PM_RESET_GPO3_PL_9,
227 ZYNQMP_PM_RESET_GPO3_PL_10,
228 ZYNQMP_PM_RESET_GPO3_PL_11,
229 ZYNQMP_PM_RESET_GPO3_PL_12,
230 ZYNQMP_PM_RESET_GPO3_PL_13,
231 ZYNQMP_PM_RESET_GPO3_PL_14,
232 ZYNQMP_PM_RESET_GPO3_PL_15,
233 ZYNQMP_PM_RESET_GPO3_PL_16,
234 ZYNQMP_PM_RESET_GPO3_PL_17,
235 ZYNQMP_PM_RESET_GPO3_PL_18,
236 ZYNQMP_PM_RESET_GPO3_PL_19,
237 ZYNQMP_PM_RESET_GPO3_PL_20,
238 ZYNQMP_PM_RESET_GPO3_PL_21,
239 ZYNQMP_PM_RESET_GPO3_PL_22,
240 ZYNQMP_PM_RESET_GPO3_PL_23,
241 ZYNQMP_PM_RESET_GPO3_PL_24,
242 ZYNQMP_PM_RESET_GPO3_PL_25,
243 ZYNQMP_PM_RESET_GPO3_PL_26,
244 ZYNQMP_PM_RESET_GPO3_PL_27,
245 ZYNQMP_PM_RESET_GPO3_PL_28,
246 ZYNQMP_PM_RESET_GPO3_PL_29,
247 ZYNQMP_PM_RESET_GPO3_PL_30,
248 ZYNQMP_PM_RESET_GPO3_PL_31,
249 ZYNQMP_PM_RESET_RPU_LS,
250 ZYNQMP_PM_RESET_PS_ONLY,
251 ZYNQMP_PM_RESET_PL,
252 ZYNQMP_PM_RESET_PS_PL0,
253 ZYNQMP_PM_RESET_PS_PL1,
254 ZYNQMP_PM_RESET_PS_PL2,
255 ZYNQMP_PM_RESET_PS_PL3,
256 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
257 };
258
259 enum zynqmp_pm_suspend_reason {
260 SUSPEND_POWER_REQUEST = 201,
261 SUSPEND_ALERT,
262 SUSPEND_SYSTEM_SHUTDOWN,
263 };
264
265 enum zynqmp_pm_request_ack {
266 ZYNQMP_PM_REQUEST_ACK_NO = 1,
267 ZYNQMP_PM_REQUEST_ACK_BLOCKING,
268 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
269 };
270
271 enum pm_node_id {
272 NODE_SD_0 = 39,
273 NODE_SD_1,
274 };
275
276 enum tap_delay_type {
277 PM_TAPDELAY_INPUT = 0,
278 PM_TAPDELAY_OUTPUT,
279 };
280
281 enum dll_reset_type {
282 PM_DLL_RESET_ASSERT,
283 PM_DLL_RESET_RELEASE,
284 PM_DLL_RESET_PULSE,
285 };
286
287 enum zynqmp_pm_shutdown_type {
288 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN,
289 ZYNQMP_PM_SHUTDOWN_TYPE_RESET,
290 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
291 };
292
293 enum zynqmp_pm_shutdown_subtype {
294 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM,
295 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY,
296 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM,
297 };
298
299 /**
300 * struct zynqmp_pm_query_data - PM query data
301 * @qid: query ID
302 * @arg1: Argument 1 of query data
303 * @arg2: Argument 2 of query data
304 * @arg3: Argument 3 of query data
305 */
306 struct zynqmp_pm_query_data {
307 u32 qid;
308 u32 arg1;
309 u32 arg2;
310 u32 arg3;
311 };
312
313
314 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
315 u32 arg2, u32 arg3, u32 *ret_payload);
316
317 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
318 int zynqmp_pm_get_api_version(u32 *version);
319 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
320 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
321 int zynqmp_pm_clock_enable(u32 clock_id);
322 int zynqmp_pm_clock_disable(u32 clock_id);
323 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
324 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
325 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
326 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
327 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
328 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
329 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
330 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
331 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
332 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
333 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
334 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
335 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
336 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
337 const enum zynqmp_pm_reset_action assert_flag);
338 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
339 int zynqmp_pm_init_finalize(void);
340 int zynqmp_pm_set_suspend_mode(u32 mode);
341 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
342 const u32 qos, const enum zynqmp_pm_request_ack ack);
343 int zynqmp_pm_release_node(const u32 node);
344 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
345 const u32 qos,
346 const enum zynqmp_pm_request_ack ack);
347 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
348 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
349 int zynqmp_pm_fpga_get_status(u32 *value);
350 int zynqmp_pm_write_ggs(u32 index, u32 value);
351 int zynqmp_pm_read_ggs(u32 index, u32 *value);
352 int zynqmp_pm_write_pggs(u32 index, u32 value);
353 int zynqmp_pm_read_pggs(u32 index, u32 *value);
354 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
355 int zynqmp_pm_set_boot_health_status(u32 value);
356 #else
zynqmp_pm_get_eemi_ops(void)357 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
358 {
359 return ERR_PTR(-ENODEV);
360 }
zynqmp_pm_get_api_version(u32 * version)361 static inline int zynqmp_pm_get_api_version(u32 *version)
362 {
363 return -ENODEV;
364 }
zynqmp_pm_get_chipid(u32 * idcode,u32 * version)365 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
366 {
367 return -ENODEV;
368 }
zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,u32 * out)369 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
370 u32 *out)
371 {
372 return -ENODEV;
373 }
zynqmp_pm_clock_enable(u32 clock_id)374 static inline int zynqmp_pm_clock_enable(u32 clock_id)
375 {
376 return -ENODEV;
377 }
zynqmp_pm_clock_disable(u32 clock_id)378 static inline int zynqmp_pm_clock_disable(u32 clock_id)
379 {
380 return -ENODEV;
381 }
zynqmp_pm_clock_getstate(u32 clock_id,u32 * state)382 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
383 {
384 return -ENODEV;
385 }
zynqmp_pm_clock_setdivider(u32 clock_id,u32 divider)386 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
387 {
388 return -ENODEV;
389 }
zynqmp_pm_clock_getdivider(u32 clock_id,u32 * divider)390 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
391 {
392 return -ENODEV;
393 }
zynqmp_pm_clock_setrate(u32 clock_id,u64 rate)394 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
395 {
396 return -ENODEV;
397 }
zynqmp_pm_clock_getrate(u32 clock_id,u64 * rate)398 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
399 {
400 return -ENODEV;
401 }
zynqmp_pm_clock_setparent(u32 clock_id,u32 parent_id)402 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
403 {
404 return -ENODEV;
405 }
zynqmp_pm_clock_getparent(u32 clock_id,u32 * parent_id)406 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
407 {
408 return -ENODEV;
409 }
zynqmp_pm_set_pll_frac_mode(u32 clk_id,u32 mode)410 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
411 {
412 return -ENODEV;
413 }
zynqmp_pm_get_pll_frac_mode(u32 clk_id,u32 * mode)414 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
415 {
416 return -ENODEV;
417 }
zynqmp_pm_set_pll_frac_data(u32 clk_id,u32 data)418 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
419 {
420 return -ENODEV;
421 }
zynqmp_pm_get_pll_frac_data(u32 clk_id,u32 * data)422 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
423 {
424 return -ENODEV;
425 }
zynqmp_pm_set_sd_tapdelay(u32 node_id,u32 type,u32 value)426 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
427 {
428 return -ENODEV;
429 }
zynqmp_pm_sd_dll_reset(u32 node_id,u32 type)430 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
431 {
432 return -ENODEV;
433 }
zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,const enum zynqmp_pm_reset_action assert_flag)434 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
435 const enum zynqmp_pm_reset_action assert_flag)
436 {
437 return -ENODEV;
438 }
zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,u32 * status)439 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
440 u32 *status)
441 {
442 return -ENODEV;
443 }
zynqmp_pm_init_finalize(void)444 static inline int zynqmp_pm_init_finalize(void)
445 {
446 return -ENODEV;
447 }
zynqmp_pm_set_suspend_mode(u32 mode)448 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
449 {
450 return -ENODEV;
451 }
zynqmp_pm_request_node(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)452 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
453 const u32 qos,
454 const enum zynqmp_pm_request_ack ack)
455 {
456 return -ENODEV;
457 }
zynqmp_pm_release_node(const u32 node)458 static inline int zynqmp_pm_release_node(const u32 node)
459 {
460 return -ENODEV;
461 }
zynqmp_pm_set_requirement(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)462 static inline int zynqmp_pm_set_requirement(const u32 node,
463 const u32 capabilities,
464 const u32 qos,
465 const enum zynqmp_pm_request_ack ack)
466 {
467 return -ENODEV;
468 }
zynqmp_pm_aes_engine(const u64 address,u32 * out)469 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
470 {
471 return -ENODEV;
472 }
zynqmp_pm_fpga_load(const u64 address,const u32 size,const u32 flags)473 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
474 const u32 flags)
475 {
476 return -ENODEV;
477 }
zynqmp_pm_fpga_get_status(u32 * value)478 static inline int zynqmp_pm_fpga_get_status(u32 *value)
479 {
480 return -ENODEV;
481 }
zynqmp_pm_write_ggs(u32 index,u32 value)482 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
483 {
484 return -ENODEV;
485 }
zynqmp_pm_read_ggs(u32 index,u32 * value)486 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
487 {
488 return -ENODEV;
489 }
zynqmp_pm_write_pggs(u32 index,u32 value)490 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
491 {
492 return -ENODEV;
493 }
zynqmp_pm_read_pggs(u32 index,u32 * value)494 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
495 {
496 return -ENODEV;
497 }
zynqmp_pm_system_shutdown(const u32 type,const u32 subtype)498 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
499 {
500 return -ENODEV;
501 }
zynqmp_pm_set_boot_health_status(u32 value)502 static inline int zynqmp_pm_set_boot_health_status(u32 value)
503 {
504 return -ENODEV;
505 }
506 #endif
507
508 #endif /* __FIRMWARE_ZYNQMP_H__ */
509
