1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_ADMINQ_CMD_H_ 5 #define _I40E_ADMINQ_CMD_H_ 6 7 /* This header file defines the i40e Admin Queue commands and is shared between 8 * i40e Firmware and Software. 9 * 10 * This file needs to comply with the Linux Kernel coding style. 11 */ 12 13 #define I40E_FW_API_VERSION_MAJOR 0x0001 14 #define I40E_FW_API_VERSION_MINOR_X722 0x0009 15 #define I40E_FW_API_VERSION_MINOR_X710 0x0009 16 17 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 18 I40E_FW_API_VERSION_MINOR_X710 : \ 19 I40E_FW_API_VERSION_MINOR_X722) 20 21 /* API version 1.7 implements additional link and PHY-specific APIs */ 22 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 23 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */ 24 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009 25 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */ 26 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 27 28 struct i40e_aq_desc { 29 __le16 flags; 30 __le16 opcode; 31 __le16 datalen; 32 __le16 retval; 33 __le32 cookie_high; 34 __le32 cookie_low; 35 union { 36 struct { 37 __le32 param0; 38 __le32 param1; 39 __le32 param2; 40 __le32 param3; 41 } internal; 42 struct { 43 __le32 param0; 44 __le32 param1; 45 __le32 addr_high; 46 __le32 addr_low; 47 } external; 48 u8 raw[16]; 49 } params; 50 }; 51 52 /* Flags sub-structure 53 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 54 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 55 */ 56 57 /* command flags and offsets*/ 58 #define I40E_AQ_FLAG_DD_SHIFT 0 59 #define I40E_AQ_FLAG_CMP_SHIFT 1 60 #define I40E_AQ_FLAG_ERR_SHIFT 2 61 #define I40E_AQ_FLAG_VFE_SHIFT 3 62 #define I40E_AQ_FLAG_LB_SHIFT 9 63 #define I40E_AQ_FLAG_RD_SHIFT 10 64 #define I40E_AQ_FLAG_VFC_SHIFT 11 65 #define I40E_AQ_FLAG_BUF_SHIFT 12 66 #define I40E_AQ_FLAG_SI_SHIFT 13 67 #define I40E_AQ_FLAG_EI_SHIFT 14 68 #define I40E_AQ_FLAG_FE_SHIFT 15 69 70 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 71 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 72 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 73 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 74 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 75 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 76 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 77 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 78 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 79 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 80 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 81 82 /* error codes */ 83 enum i40e_admin_queue_err { 84 I40E_AQ_RC_OK = 0, /* success */ 85 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 86 I40E_AQ_RC_ENOENT = 2, /* No such element */ 87 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 88 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 89 I40E_AQ_RC_EIO = 5, /* I/O error */ 90 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 91 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 92 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 93 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 94 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 95 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 96 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 97 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 98 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 99 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 100 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 101 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 102 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 103 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 104 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 105 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 106 I40E_AQ_RC_EFBIG = 22, /* File too large */ 107 }; 108 109 /* Admin Queue command opcodes */ 110 enum i40e_admin_queue_opc { 111 /* aq commands */ 112 i40e_aqc_opc_get_version = 0x0001, 113 i40e_aqc_opc_driver_version = 0x0002, 114 i40e_aqc_opc_queue_shutdown = 0x0003, 115 i40e_aqc_opc_set_pf_context = 0x0004, 116 117 /* resource ownership */ 118 i40e_aqc_opc_request_resource = 0x0008, 119 i40e_aqc_opc_release_resource = 0x0009, 120 121 i40e_aqc_opc_list_func_capabilities = 0x000A, 122 i40e_aqc_opc_list_dev_capabilities = 0x000B, 123 124 /* Proxy commands */ 125 i40e_aqc_opc_set_proxy_config = 0x0104, 126 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 127 128 /* LAA */ 129 i40e_aqc_opc_mac_address_read = 0x0107, 130 i40e_aqc_opc_mac_address_write = 0x0108, 131 132 /* PXE */ 133 i40e_aqc_opc_clear_pxe_mode = 0x0110, 134 135 /* WoL commands */ 136 i40e_aqc_opc_set_wol_filter = 0x0120, 137 i40e_aqc_opc_get_wake_reason = 0x0121, 138 139 /* internal switch commands */ 140 i40e_aqc_opc_get_switch_config = 0x0200, 141 i40e_aqc_opc_add_statistics = 0x0201, 142 i40e_aqc_opc_remove_statistics = 0x0202, 143 i40e_aqc_opc_set_port_parameters = 0x0203, 144 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 145 i40e_aqc_opc_set_switch_config = 0x0205, 146 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 147 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 148 149 i40e_aqc_opc_add_vsi = 0x0210, 150 i40e_aqc_opc_update_vsi_parameters = 0x0211, 151 i40e_aqc_opc_get_vsi_parameters = 0x0212, 152 153 i40e_aqc_opc_add_pv = 0x0220, 154 i40e_aqc_opc_update_pv_parameters = 0x0221, 155 i40e_aqc_opc_get_pv_parameters = 0x0222, 156 157 i40e_aqc_opc_add_veb = 0x0230, 158 i40e_aqc_opc_update_veb_parameters = 0x0231, 159 i40e_aqc_opc_get_veb_parameters = 0x0232, 160 161 i40e_aqc_opc_delete_element = 0x0243, 162 163 i40e_aqc_opc_add_macvlan = 0x0250, 164 i40e_aqc_opc_remove_macvlan = 0x0251, 165 i40e_aqc_opc_add_vlan = 0x0252, 166 i40e_aqc_opc_remove_vlan = 0x0253, 167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 168 i40e_aqc_opc_add_tag = 0x0255, 169 i40e_aqc_opc_remove_tag = 0x0256, 170 i40e_aqc_opc_add_multicast_etag = 0x0257, 171 i40e_aqc_opc_remove_multicast_etag = 0x0258, 172 i40e_aqc_opc_update_tag = 0x0259, 173 i40e_aqc_opc_add_control_packet_filter = 0x025A, 174 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 175 i40e_aqc_opc_add_cloud_filters = 0x025C, 176 i40e_aqc_opc_remove_cloud_filters = 0x025D, 177 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 178 179 i40e_aqc_opc_add_mirror_rule = 0x0260, 180 i40e_aqc_opc_delete_mirror_rule = 0x0261, 181 182 /* Dynamic Device Personalization */ 183 i40e_aqc_opc_write_personalization_profile = 0x0270, 184 i40e_aqc_opc_get_personalization_profile_list = 0x0271, 185 186 /* DCB commands */ 187 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 188 i40e_aqc_opc_dcb_updated = 0x0302, 189 i40e_aqc_opc_set_dcb_parameters = 0x0303, 190 191 /* TX scheduler */ 192 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 193 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 194 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 195 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 196 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 197 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 198 199 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 200 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 201 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 202 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 203 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 204 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 205 i40e_aqc_opc_query_port_ets_config = 0x0419, 206 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 207 i40e_aqc_opc_suspend_port_tx = 0x041B, 208 i40e_aqc_opc_resume_port_tx = 0x041C, 209 i40e_aqc_opc_configure_partition_bw = 0x041D, 210 /* hmc */ 211 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 212 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 213 214 /* phy commands*/ 215 i40e_aqc_opc_get_phy_abilities = 0x0600, 216 i40e_aqc_opc_set_phy_config = 0x0601, 217 i40e_aqc_opc_set_mac_config = 0x0603, 218 i40e_aqc_opc_set_link_restart_an = 0x0605, 219 i40e_aqc_opc_get_link_status = 0x0607, 220 i40e_aqc_opc_set_phy_int_mask = 0x0613, 221 i40e_aqc_opc_get_local_advt_reg = 0x0614, 222 i40e_aqc_opc_set_local_advt_reg = 0x0615, 223 i40e_aqc_opc_get_partner_advt = 0x0616, 224 i40e_aqc_opc_set_lb_modes = 0x0618, 225 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 226 i40e_aqc_opc_set_phy_debug = 0x0622, 227 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 228 i40e_aqc_opc_run_phy_activity = 0x0626, 229 i40e_aqc_opc_set_phy_register = 0x0628, 230 i40e_aqc_opc_get_phy_register = 0x0629, 231 232 /* NVM commands */ 233 i40e_aqc_opc_nvm_read = 0x0701, 234 i40e_aqc_opc_nvm_erase = 0x0702, 235 i40e_aqc_opc_nvm_update = 0x0703, 236 i40e_aqc_opc_nvm_config_read = 0x0704, 237 i40e_aqc_opc_nvm_config_write = 0x0705, 238 i40e_aqc_opc_oem_post_update = 0x0720, 239 i40e_aqc_opc_thermal_sensor = 0x0721, 240 241 /* virtualization commands */ 242 i40e_aqc_opc_send_msg_to_pf = 0x0801, 243 i40e_aqc_opc_send_msg_to_vf = 0x0802, 244 i40e_aqc_opc_send_msg_to_peer = 0x0803, 245 246 /* alternate structure */ 247 i40e_aqc_opc_alternate_write = 0x0900, 248 i40e_aqc_opc_alternate_write_indirect = 0x0901, 249 i40e_aqc_opc_alternate_read = 0x0902, 250 i40e_aqc_opc_alternate_read_indirect = 0x0903, 251 i40e_aqc_opc_alternate_write_done = 0x0904, 252 i40e_aqc_opc_alternate_set_mode = 0x0905, 253 i40e_aqc_opc_alternate_clear_port = 0x0906, 254 255 /* LLDP commands */ 256 i40e_aqc_opc_lldp_get_mib = 0x0A00, 257 i40e_aqc_opc_lldp_update_mib = 0x0A01, 258 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 259 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 260 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 261 i40e_aqc_opc_lldp_stop = 0x0A05, 262 i40e_aqc_opc_lldp_start = 0x0A06, 263 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 264 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 265 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 266 i40e_aqc_opc_lldp_restore = 0x0A0A, 267 268 /* Tunnel commands */ 269 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 270 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 271 i40e_aqc_opc_set_rss_key = 0x0B02, 272 i40e_aqc_opc_set_rss_lut = 0x0B03, 273 i40e_aqc_opc_get_rss_key = 0x0B04, 274 i40e_aqc_opc_get_rss_lut = 0x0B05, 275 276 /* Async Events */ 277 i40e_aqc_opc_event_lan_overflow = 0x1001, 278 279 /* OEM commands */ 280 i40e_aqc_opc_oem_parameter_change = 0xFE00, 281 i40e_aqc_opc_oem_device_status_change = 0xFE01, 282 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 283 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 284 285 /* debug commands */ 286 i40e_aqc_opc_debug_read_reg = 0xFF03, 287 i40e_aqc_opc_debug_write_reg = 0xFF04, 288 i40e_aqc_opc_debug_modify_reg = 0xFF07, 289 i40e_aqc_opc_debug_dump_internals = 0xFF08, 290 }; 291 292 /* command structures and indirect data structures */ 293 294 /* Structure naming conventions: 295 * - no suffix for direct command descriptor structures 296 * - _data for indirect sent data 297 * - _resp for indirect return data (data which is both will use _data) 298 * - _completion for direct return data 299 * - _element_ for repeated elements (may also be _data or _resp) 300 * 301 * Command structures are expected to overlay the params.raw member of the basic 302 * descriptor, and as such cannot exceed 16 bytes in length. 303 */ 304 305 /* This macro is used to generate a compilation error if a structure 306 * is not exactly the correct length. It gives a divide by zero error if the 307 * structure is not of the correct size, otherwise it creates an enum that is 308 * never used. 309 */ 310 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 311 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 312 313 /* This macro is used extensively to ensure that command structures are 16 314 * bytes in length as they have to map to the raw array of that size. 315 */ 316 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 317 318 /* internal (0x00XX) commands */ 319 320 /* Get version (direct 0x0001) */ 321 struct i40e_aqc_get_version { 322 __le32 rom_ver; 323 __le32 fw_build; 324 __le16 fw_major; 325 __le16 fw_minor; 326 __le16 api_major; 327 __le16 api_minor; 328 }; 329 330 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 331 332 /* Send driver version (indirect 0x0002) */ 333 struct i40e_aqc_driver_version { 334 u8 driver_major_ver; 335 u8 driver_minor_ver; 336 u8 driver_build_ver; 337 u8 driver_subbuild_ver; 338 u8 reserved[4]; 339 __le32 address_high; 340 __le32 address_low; 341 }; 342 343 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 344 345 /* Queue Shutdown (direct 0x0003) */ 346 struct i40e_aqc_queue_shutdown { 347 __le32 driver_unloading; 348 #define I40E_AQ_DRIVER_UNLOADING 0x1 349 u8 reserved[12]; 350 }; 351 352 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 353 354 /* Set PF context (0x0004, direct) */ 355 struct i40e_aqc_set_pf_context { 356 u8 pf_id; 357 u8 reserved[15]; 358 }; 359 360 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 361 362 /* Request resource ownership (direct 0x0008) 363 * Release resource ownership (direct 0x0009) 364 */ 365 #define I40E_AQ_RESOURCE_NVM 1 366 #define I40E_AQ_RESOURCE_SDP 2 367 #define I40E_AQ_RESOURCE_ACCESS_READ 1 368 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 369 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 370 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 371 372 struct i40e_aqc_request_resource { 373 __le16 resource_id; 374 __le16 access_type; 375 __le32 timeout; 376 __le32 resource_number; 377 u8 reserved[4]; 378 }; 379 380 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 381 382 /* Get function capabilities (indirect 0x000A) 383 * Get device capabilities (indirect 0x000B) 384 */ 385 struct i40e_aqc_list_capabilites { 386 u8 command_flags; 387 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 388 u8 pf_index; 389 u8 reserved[2]; 390 __le32 count; 391 __le32 addr_high; 392 __le32 addr_low; 393 }; 394 395 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 396 397 struct i40e_aqc_list_capabilities_element_resp { 398 __le16 id; 399 u8 major_rev; 400 u8 minor_rev; 401 __le32 number; 402 __le32 logical_id; 403 __le32 phys_id; 404 u8 reserved[16]; 405 }; 406 407 /* list of caps */ 408 409 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 410 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 411 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 412 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 413 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 414 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 415 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 416 #define I40E_AQ_CAP_ID_SRIOV 0x0012 417 #define I40E_AQ_CAP_ID_VF 0x0013 418 #define I40E_AQ_CAP_ID_VMDQ 0x0014 419 #define I40E_AQ_CAP_ID_8021QBG 0x0015 420 #define I40E_AQ_CAP_ID_8021QBR 0x0016 421 #define I40E_AQ_CAP_ID_VSI 0x0017 422 #define I40E_AQ_CAP_ID_DCB 0x0018 423 #define I40E_AQ_CAP_ID_FCOE 0x0021 424 #define I40E_AQ_CAP_ID_ISCSI 0x0022 425 #define I40E_AQ_CAP_ID_RSS 0x0040 426 #define I40E_AQ_CAP_ID_RXQ 0x0041 427 #define I40E_AQ_CAP_ID_TXQ 0x0042 428 #define I40E_AQ_CAP_ID_MSIX 0x0043 429 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 430 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 431 #define I40E_AQ_CAP_ID_1588 0x0046 432 #define I40E_AQ_CAP_ID_IWARP 0x0051 433 #define I40E_AQ_CAP_ID_LED 0x0061 434 #define I40E_AQ_CAP_ID_SDP 0x0062 435 #define I40E_AQ_CAP_ID_MDIO 0x0063 436 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 437 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 438 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 439 #define I40E_AQ_CAP_ID_CEM 0x00F2 440 441 /* Set CPPM Configuration (direct 0x0103) */ 442 struct i40e_aqc_cppm_configuration { 443 __le16 command_flags; 444 #define I40E_AQ_CPPM_EN_LTRC 0x0800 445 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 446 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 447 #define I40E_AQ_CPPM_EN_HPTC 0x4000 448 #define I40E_AQ_CPPM_EN_DMARC 0x8000 449 __le16 ttlx; 450 __le32 dmacr; 451 __le16 dmcth; 452 u8 hptc; 453 u8 reserved; 454 __le32 pfltrc; 455 }; 456 457 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 458 459 /* Set ARP Proxy command / response (indirect 0x0104) */ 460 struct i40e_aqc_arp_proxy_data { 461 __le16 command_flags; 462 #define I40E_AQ_ARP_INIT_IPV4 0x0800 463 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 464 #define I40E_AQ_ARP_ENA 0x2000 465 #define I40E_AQ_ARP_ADD_IPV4 0x4000 466 #define I40E_AQ_ARP_DEL_IPV4 0x8000 467 __le16 table_id; 468 __le32 enabled_offloads; 469 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 470 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 471 __le32 ip_addr; 472 u8 mac_addr[6]; 473 u8 reserved[2]; 474 }; 475 476 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 477 478 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 479 struct i40e_aqc_ns_proxy_data { 480 __le16 table_idx_mac_addr_0; 481 __le16 table_idx_mac_addr_1; 482 __le16 table_idx_ipv6_0; 483 __le16 table_idx_ipv6_1; 484 __le16 control; 485 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 486 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 487 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 488 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 489 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 490 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 491 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 492 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 493 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 494 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 495 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 496 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 497 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 498 u8 mac_addr_0[6]; 499 u8 mac_addr_1[6]; 500 u8 local_mac_addr[6]; 501 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 502 u8 ipv6_addr_1[16]; 503 }; 504 505 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 506 507 /* Manage LAA Command (0x0106) - obsolete */ 508 struct i40e_aqc_mng_laa { 509 __le16 command_flags; 510 #define I40E_AQ_LAA_FLAG_WR 0x8000 511 u8 reserved[2]; 512 __le32 sal; 513 __le16 sah; 514 u8 reserved2[6]; 515 }; 516 517 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 518 519 /* Manage MAC Address Read Command (indirect 0x0107) */ 520 struct i40e_aqc_mac_address_read { 521 __le16 command_flags; 522 #define I40E_AQC_LAN_ADDR_VALID 0x10 523 #define I40E_AQC_SAN_ADDR_VALID 0x20 524 #define I40E_AQC_PORT_ADDR_VALID 0x40 525 #define I40E_AQC_WOL_ADDR_VALID 0x80 526 #define I40E_AQC_MC_MAG_EN_VALID 0x100 527 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 528 u8 reserved[6]; 529 __le32 addr_high; 530 __le32 addr_low; 531 }; 532 533 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 534 535 struct i40e_aqc_mac_address_read_data { 536 u8 pf_lan_mac[6]; 537 u8 pf_san_mac[6]; 538 u8 port_mac[6]; 539 u8 pf_wol_mac[6]; 540 }; 541 542 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 543 544 /* Manage MAC Address Write Command (0x0108) */ 545 struct i40e_aqc_mac_address_write { 546 __le16 command_flags; 547 #define I40E_AQC_MC_MAG_EN 0x0100 548 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 549 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 550 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 551 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 552 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 553 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 554 555 __le16 mac_sah; 556 __le32 mac_sal; 557 u8 reserved[8]; 558 }; 559 560 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 561 562 /* PXE commands (0x011x) */ 563 564 /* Clear PXE Command and response (direct 0x0110) */ 565 struct i40e_aqc_clear_pxe { 566 u8 rx_cnt; 567 u8 reserved[15]; 568 }; 569 570 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 571 572 /* Set WoL Filter (0x0120) */ 573 574 struct i40e_aqc_set_wol_filter { 575 __le16 filter_index; 576 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 577 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 578 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 579 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 580 581 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 582 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 583 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 584 __le16 cmd_flags; 585 #define I40E_AQC_SET_WOL_FILTER 0x8000 586 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 587 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 588 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 589 __le16 valid_flags; 590 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 591 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 592 u8 reserved[2]; 593 __le32 address_high; 594 __le32 address_low; 595 }; 596 597 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 598 599 struct i40e_aqc_set_wol_filter_data { 600 u8 filter[128]; 601 u8 mask[16]; 602 }; 603 604 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 605 606 /* Get Wake Reason (0x0121) */ 607 608 struct i40e_aqc_get_wake_reason_completion { 609 u8 reserved_1[2]; 610 __le16 wake_reason; 611 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 612 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 613 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 614 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 615 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 616 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 617 u8 reserved_2[12]; 618 }; 619 620 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 621 622 /* Switch configuration commands (0x02xx) */ 623 624 /* Used by many indirect commands that only pass an seid and a buffer in the 625 * command 626 */ 627 struct i40e_aqc_switch_seid { 628 __le16 seid; 629 u8 reserved[6]; 630 __le32 addr_high; 631 __le32 addr_low; 632 }; 633 634 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 635 636 /* Get Switch Configuration command (indirect 0x0200) 637 * uses i40e_aqc_switch_seid for the descriptor 638 */ 639 struct i40e_aqc_get_switch_config_header_resp { 640 __le16 num_reported; 641 __le16 num_total; 642 u8 reserved[12]; 643 }; 644 645 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 646 647 struct i40e_aqc_switch_config_element_resp { 648 u8 element_type; 649 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 650 #define I40E_AQ_SW_ELEM_TYPE_PF 2 651 #define I40E_AQ_SW_ELEM_TYPE_VF 3 652 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 653 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 654 #define I40E_AQ_SW_ELEM_TYPE_PV 16 655 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 656 #define I40E_AQ_SW_ELEM_TYPE_PA 18 657 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 658 u8 revision; 659 #define I40E_AQ_SW_ELEM_REV_1 1 660 __le16 seid; 661 __le16 uplink_seid; 662 __le16 downlink_seid; 663 u8 reserved[3]; 664 u8 connection_type; 665 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 666 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 667 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 668 __le16 scheduler_id; 669 __le16 element_info; 670 }; 671 672 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 673 674 /* Get Switch Configuration (indirect 0x0200) 675 * an array of elements are returned in the response buffer 676 * the first in the array is the header, remainder are elements 677 */ 678 struct i40e_aqc_get_switch_config_resp { 679 struct i40e_aqc_get_switch_config_header_resp header; 680 struct i40e_aqc_switch_config_element_resp element[1]; 681 }; 682 683 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 684 685 /* Add Statistics (direct 0x0201) 686 * Remove Statistics (direct 0x0202) 687 */ 688 struct i40e_aqc_add_remove_statistics { 689 __le16 seid; 690 __le16 vlan; 691 __le16 stat_index; 692 u8 reserved[10]; 693 }; 694 695 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 696 697 /* Set Port Parameters command (direct 0x0203) */ 698 struct i40e_aqc_set_port_parameters { 699 __le16 command_flags; 700 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 701 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 702 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 703 __le16 bad_frame_vsi; 704 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 705 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 706 __le16 default_seid; /* reserved for command */ 707 u8 reserved[10]; 708 }; 709 710 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 711 712 /* Get Switch Resource Allocation (indirect 0x0204) */ 713 struct i40e_aqc_get_switch_resource_alloc { 714 u8 num_entries; /* reserved for command */ 715 u8 reserved[7]; 716 __le32 addr_high; 717 __le32 addr_low; 718 }; 719 720 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 721 722 /* expect an array of these structs in the response buffer */ 723 struct i40e_aqc_switch_resource_alloc_element_resp { 724 u8 resource_type; 725 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 726 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 727 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 728 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 729 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 730 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 731 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 732 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 733 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 734 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 735 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 736 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 737 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 738 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 739 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 740 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 741 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 742 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 743 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 744 u8 reserved1; 745 __le16 guaranteed; 746 __le16 total; 747 __le16 used; 748 __le16 total_unalloced; 749 u8 reserved2[6]; 750 }; 751 752 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 753 754 /* Set Switch Configuration (direct 0x0205) */ 755 struct i40e_aqc_set_switch_config { 756 __le16 flags; 757 /* flags used for both fields below */ 758 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 759 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 760 __le16 valid_flags; 761 /* The ethertype in switch_tag is dropped on ingress and used 762 * internally by the switch. Set this to zero for the default 763 * of 0x88a8 (802.1ad). Should be zero for firmware API 764 * versions lower than 1.7. 765 */ 766 __le16 switch_tag; 767 /* The ethertypes in first_tag and second_tag are used to 768 * match the outer and inner VLAN tags (respectively) when HW 769 * double VLAN tagging is enabled via the set port parameters 770 * AQ command. Otherwise these are both ignored. Set them to 771 * zero for their defaults of 0x8100 (802.1Q). Should be zero 772 * for firmware API versions lower than 1.7. 773 */ 774 __le16 first_tag; 775 __le16 second_tag; 776 /* Next byte is split into following: 777 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 778 * Bit 6 : 0 : Destination Port, 1: source port 779 * Bit 5..4 : L4 type 780 * 0: rsvd 781 * 1: TCP 782 * 2: UDP 783 * 3: Both TCP and UDP 784 * Bits 3:0 Mode 785 * 0: default mode 786 * 1: L4 port only mode 787 * 2: non-tunneled mode 788 * 3: tunneled mode 789 */ 790 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 791 792 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 793 794 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 795 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 796 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 797 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 798 799 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 800 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 801 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 802 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 803 u8 mode; 804 u8 rsvd5[5]; 805 }; 806 807 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 808 809 /* Read Receive control registers (direct 0x0206) 810 * Write Receive control registers (direct 0x0207) 811 * used for accessing Rx control registers that can be 812 * slow and need special handling when under high Rx load 813 */ 814 struct i40e_aqc_rx_ctl_reg_read_write { 815 __le32 reserved1; 816 __le32 address; 817 __le32 reserved2; 818 __le32 value; 819 }; 820 821 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 822 823 /* Add VSI (indirect 0x0210) 824 * this indirect command uses struct i40e_aqc_vsi_properties_data 825 * as the indirect buffer (128 bytes) 826 * 827 * Update VSI (indirect 0x211) 828 * uses the same data structure as Add VSI 829 * 830 * Get VSI (indirect 0x0212) 831 * uses the same completion and data structure as Add VSI 832 */ 833 struct i40e_aqc_add_get_update_vsi { 834 __le16 uplink_seid; 835 u8 connection_type; 836 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 837 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 838 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 839 u8 reserved1; 840 u8 vf_id; 841 u8 reserved2; 842 __le16 vsi_flags; 843 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 844 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 845 #define I40E_AQ_VSI_TYPE_VF 0x0 846 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 847 #define I40E_AQ_VSI_TYPE_PF 0x2 848 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 849 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 850 __le32 addr_high; 851 __le32 addr_low; 852 }; 853 854 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 855 856 struct i40e_aqc_add_get_update_vsi_completion { 857 __le16 seid; 858 __le16 vsi_number; 859 __le16 vsi_used; 860 __le16 vsi_free; 861 __le32 addr_high; 862 __le32 addr_low; 863 }; 864 865 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 866 867 struct i40e_aqc_vsi_properties_data { 868 /* first 96 byte are written by SW */ 869 __le16 valid_sections; 870 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 871 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 872 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 873 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 874 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 875 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 876 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 877 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 878 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 879 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 880 /* switch section */ 881 __le16 switch_id; /* 12bit id combined with flags below */ 882 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 883 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 884 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 885 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 886 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 887 u8 sw_reserved[2]; 888 /* security section */ 889 u8 sec_flags; 890 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 891 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 892 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 893 u8 sec_reserved; 894 /* VLAN section */ 895 __le16 pvid; /* VLANS include priority bits */ 896 __le16 fcoe_pvid; 897 u8 port_vlan_flags; 898 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 899 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 900 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 901 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 902 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 903 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 904 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 905 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 906 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 907 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 908 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 909 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 910 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 911 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 912 u8 pvlan_reserved[3]; 913 /* ingress egress up sections */ 914 __le32 ingress_table; /* bitmap, 3 bits per up */ 915 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 916 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 917 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 918 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 919 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 920 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 921 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 922 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 923 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 924 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 925 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 926 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 927 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 928 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 929 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 930 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 931 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 932 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 933 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 934 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 935 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 936 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 937 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 938 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 939 __le32 egress_table; /* same defines as for ingress table */ 940 /* cascaded PV section */ 941 __le16 cas_pv_tag; 942 u8 cas_pv_flags; 943 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 944 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 945 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 946 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 947 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 948 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 949 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 950 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 951 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 952 u8 cas_pv_reserved; 953 /* queue mapping section */ 954 __le16 mapping_flags; 955 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 956 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 957 __le16 queue_mapping[16]; 958 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 959 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 960 __le16 tc_mapping[8]; 961 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 962 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 963 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 964 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 965 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 966 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 967 /* queueing option section */ 968 u8 queueing_opt_flags; 969 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 970 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 971 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 972 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 973 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 974 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 975 u8 queueing_opt_reserved[3]; 976 /* scheduler section */ 977 u8 up_enable_bits; 978 u8 sched_reserved; 979 /* outer up section */ 980 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 981 u8 cmd_reserved[8]; 982 /* last 32 bytes are written by FW */ 983 __le16 qs_handle[8]; 984 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 985 __le16 stat_counter_idx; 986 __le16 sched_id; 987 u8 resp_reserved[12]; 988 }; 989 990 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 991 992 /* Add Port Virtualizer (direct 0x0220) 993 * also used for update PV (direct 0x0221) but only flags are used 994 * (IS_CTRL_PORT only works on add PV) 995 */ 996 struct i40e_aqc_add_update_pv { 997 __le16 command_flags; 998 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 999 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1000 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1001 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1002 __le16 uplink_seid; 1003 __le16 connected_seid; 1004 u8 reserved[10]; 1005 }; 1006 1007 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1008 1009 struct i40e_aqc_add_update_pv_completion { 1010 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1011 __le16 pv_seid; 1012 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1013 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1014 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1015 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1016 u8 reserved[14]; 1017 }; 1018 1019 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1020 1021 /* Get PV Params (direct 0x0222) 1022 * uses i40e_aqc_switch_seid for the descriptor 1023 */ 1024 1025 struct i40e_aqc_get_pv_params_completion { 1026 __le16 seid; 1027 __le16 default_stag; 1028 __le16 pv_flags; /* same flags as add_pv */ 1029 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1030 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1031 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1032 u8 reserved[8]; 1033 __le16 default_port_seid; 1034 }; 1035 1036 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1037 1038 /* Add VEB (direct 0x0230) */ 1039 struct i40e_aqc_add_veb { 1040 __le16 uplink_seid; 1041 __le16 downlink_seid; 1042 __le16 veb_flags; 1043 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1044 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1045 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1046 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1047 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1048 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1049 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1050 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1051 u8 enable_tcs; 1052 u8 reserved[9]; 1053 }; 1054 1055 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1056 1057 struct i40e_aqc_add_veb_completion { 1058 u8 reserved[6]; 1059 __le16 switch_seid; 1060 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1061 __le16 veb_seid; 1062 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1063 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1064 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1065 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1066 __le16 statistic_index; 1067 __le16 vebs_used; 1068 __le16 vebs_free; 1069 }; 1070 1071 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1072 1073 /* Get VEB Parameters (direct 0x0232) 1074 * uses i40e_aqc_switch_seid for the descriptor 1075 */ 1076 struct i40e_aqc_get_veb_parameters_completion { 1077 __le16 seid; 1078 __le16 switch_id; 1079 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1080 __le16 statistic_index; 1081 __le16 vebs_used; 1082 __le16 vebs_free; 1083 u8 reserved[4]; 1084 }; 1085 1086 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1087 1088 /* Delete Element (direct 0x0243) 1089 * uses the generic i40e_aqc_switch_seid 1090 */ 1091 1092 /* Add MAC-VLAN (indirect 0x0250) */ 1093 1094 /* used for the command for most vlan commands */ 1095 struct i40e_aqc_macvlan { 1096 __le16 num_addresses; 1097 __le16 seid[3]; 1098 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1099 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1100 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1101 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1102 __le32 addr_high; 1103 __le32 addr_low; 1104 }; 1105 1106 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1107 1108 /* indirect data for command and response */ 1109 struct i40e_aqc_add_macvlan_element_data { 1110 u8 mac_addr[6]; 1111 __le16 vlan_tag; 1112 __le16 flags; 1113 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1114 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1115 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1116 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1117 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1118 __le16 queue_number; 1119 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1120 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1121 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1122 /* response section */ 1123 u8 match_method; 1124 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1125 #define I40E_AQC_MM_HASH_MATCH 0x02 1126 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1127 u8 reserved1[3]; 1128 }; 1129 1130 struct i40e_aqc_add_remove_macvlan_completion { 1131 __le16 perfect_mac_used; 1132 __le16 perfect_mac_free; 1133 __le16 unicast_hash_free; 1134 __le16 multicast_hash_free; 1135 __le32 addr_high; 1136 __le32 addr_low; 1137 }; 1138 1139 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1140 1141 /* Remove MAC-VLAN (indirect 0x0251) 1142 * uses i40e_aqc_macvlan for the descriptor 1143 * data points to an array of num_addresses of elements 1144 */ 1145 1146 struct i40e_aqc_remove_macvlan_element_data { 1147 u8 mac_addr[6]; 1148 __le16 vlan_tag; 1149 u8 flags; 1150 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1151 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1152 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1153 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1154 u8 reserved[3]; 1155 /* reply section */ 1156 u8 error_code; 1157 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1158 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1159 u8 reply_reserved[3]; 1160 }; 1161 1162 /* Add VLAN (indirect 0x0252) 1163 * Remove VLAN (indirect 0x0253) 1164 * use the generic i40e_aqc_macvlan for the command 1165 */ 1166 struct i40e_aqc_add_remove_vlan_element_data { 1167 __le16 vlan_tag; 1168 u8 vlan_flags; 1169 /* flags for add VLAN */ 1170 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1171 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1172 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1173 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1174 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1175 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1176 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1177 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1178 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1179 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1180 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1181 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1182 /* flags for remove VLAN */ 1183 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1184 u8 reserved; 1185 u8 result; 1186 /* flags for add VLAN */ 1187 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1188 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1189 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1190 /* flags for remove VLAN */ 1191 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1192 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1193 u8 reserved1[3]; 1194 }; 1195 1196 struct i40e_aqc_add_remove_vlan_completion { 1197 u8 reserved[4]; 1198 __le16 vlans_used; 1199 __le16 vlans_free; 1200 __le32 addr_high; 1201 __le32 addr_low; 1202 }; 1203 1204 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1205 struct i40e_aqc_set_vsi_promiscuous_modes { 1206 __le16 promiscuous_flags; 1207 __le16 valid_flags; 1208 /* flags used for both fields above */ 1209 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1210 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1211 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1212 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1213 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1214 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1215 __le16 seid; 1216 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1217 __le16 vlan_tag; 1218 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1219 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1220 u8 reserved[8]; 1221 }; 1222 1223 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1224 1225 /* Add S/E-tag command (direct 0x0255) 1226 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1227 */ 1228 struct i40e_aqc_add_tag { 1229 __le16 flags; 1230 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1231 __le16 seid; 1232 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1233 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1234 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1235 __le16 tag; 1236 __le16 queue_number; 1237 u8 reserved[8]; 1238 }; 1239 1240 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1241 1242 struct i40e_aqc_add_remove_tag_completion { 1243 u8 reserved[12]; 1244 __le16 tags_used; 1245 __le16 tags_free; 1246 }; 1247 1248 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1249 1250 /* Remove S/E-tag command (direct 0x0256) 1251 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1252 */ 1253 struct i40e_aqc_remove_tag { 1254 __le16 seid; 1255 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1256 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1257 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1258 __le16 tag; 1259 u8 reserved[12]; 1260 }; 1261 1262 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1263 1264 /* Add multicast E-Tag (direct 0x0257) 1265 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1266 * and no external data 1267 */ 1268 struct i40e_aqc_add_remove_mcast_etag { 1269 __le16 pv_seid; 1270 __le16 etag; 1271 u8 num_unicast_etags; 1272 u8 reserved[3]; 1273 __le32 addr_high; /* address of array of 2-byte s-tags */ 1274 __le32 addr_low; 1275 }; 1276 1277 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1278 1279 struct i40e_aqc_add_remove_mcast_etag_completion { 1280 u8 reserved[4]; 1281 __le16 mcast_etags_used; 1282 __le16 mcast_etags_free; 1283 __le32 addr_high; 1284 __le32 addr_low; 1285 1286 }; 1287 1288 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1289 1290 /* Update S/E-Tag (direct 0x0259) */ 1291 struct i40e_aqc_update_tag { 1292 __le16 seid; 1293 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1294 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1295 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1296 __le16 old_tag; 1297 __le16 new_tag; 1298 u8 reserved[10]; 1299 }; 1300 1301 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1302 1303 struct i40e_aqc_update_tag_completion { 1304 u8 reserved[12]; 1305 __le16 tags_used; 1306 __le16 tags_free; 1307 }; 1308 1309 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1310 1311 /* Add Control Packet filter (direct 0x025A) 1312 * Remove Control Packet filter (direct 0x025B) 1313 * uses the i40e_aqc_add_oveb_cloud, 1314 * and the generic direct completion structure 1315 */ 1316 struct i40e_aqc_add_remove_control_packet_filter { 1317 u8 mac[6]; 1318 __le16 etype; 1319 __le16 flags; 1320 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1321 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1322 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1323 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1324 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1325 __le16 seid; 1326 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1327 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1328 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1329 __le16 queue; 1330 u8 reserved[2]; 1331 }; 1332 1333 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1334 1335 struct i40e_aqc_add_remove_control_packet_filter_completion { 1336 __le16 mac_etype_used; 1337 __le16 etype_used; 1338 __le16 mac_etype_free; 1339 __le16 etype_free; 1340 u8 reserved[8]; 1341 }; 1342 1343 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1344 1345 /* Add Cloud filters (indirect 0x025C) 1346 * Remove Cloud filters (indirect 0x025D) 1347 * uses the i40e_aqc_add_remove_cloud_filters, 1348 * and the generic indirect completion structure 1349 */ 1350 struct i40e_aqc_add_remove_cloud_filters { 1351 u8 num_filters; 1352 u8 reserved; 1353 __le16 seid; 1354 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1355 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1356 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1357 u8 big_buffer_flag; 1358 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1359 u8 reserved2[3]; 1360 __le32 addr_high; 1361 __le32 addr_low; 1362 }; 1363 1364 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1365 1366 struct i40e_aqc_cloud_filters_element_data { 1367 u8 outer_mac[6]; 1368 u8 inner_mac[6]; 1369 __le16 inner_vlan; 1370 union { 1371 struct { 1372 u8 reserved[12]; 1373 u8 data[4]; 1374 } v4; 1375 struct { 1376 u8 data[16]; 1377 } v6; 1378 struct { 1379 __le16 data[8]; 1380 } raw_v6; 1381 } ipaddr; 1382 __le16 flags; 1383 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1384 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1385 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1386 /* 0x0000 reserved */ 1387 /* 0x0001 reserved */ 1388 /* 0x0002 reserved */ 1389 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1390 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1391 /* 0x0005 reserved */ 1392 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1393 /* 0x0007 reserved */ 1394 /* 0x0008 reserved */ 1395 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1396 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1397 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1398 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1399 /* 0x000D reserved */ 1400 /* 0x000E reserved */ 1401 /* 0x000F reserved */ 1402 /* 0x0010 to 0x0017 is for custom filters */ 1403 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1404 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1405 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1406 1407 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1408 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1409 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1410 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1411 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1412 1413 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1414 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1415 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1416 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1417 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1418 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1419 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1420 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1421 1422 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1423 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1424 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1425 1426 __le32 tenant_id; 1427 u8 reserved[4]; 1428 __le16 queue_number; 1429 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1430 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1431 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1432 u8 reserved2[14]; 1433 /* response section */ 1434 u8 allocation_result; 1435 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1436 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1437 u8 response_reserved[7]; 1438 }; 1439 1440 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1441 1442 /* i40e_aqc_cloud_filters_element_bb is used when 1443 * I40E_AQC_CLOUD_CMD_BB flag is set. 1444 */ 1445 struct i40e_aqc_cloud_filters_element_bb { 1446 struct i40e_aqc_cloud_filters_element_data element; 1447 u16 general_fields[32]; 1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1449 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1450 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1451 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1452 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1453 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1454 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1455 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1473 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1474 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1475 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1476 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1477 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1478 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1479 }; 1480 1481 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1482 1483 struct i40e_aqc_remove_cloud_filters_completion { 1484 __le16 perfect_ovlan_used; 1485 __le16 perfect_ovlan_free; 1486 __le16 vlan_used; 1487 __le16 vlan_free; 1488 __le32 addr_high; 1489 __le32 addr_low; 1490 }; 1491 1492 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1493 1494 /* Replace filter Command 0x025F 1495 * uses the i40e_aqc_replace_cloud_filters, 1496 * and the generic indirect completion structure 1497 */ 1498 struct i40e_filter_data { 1499 u8 filter_type; 1500 u8 input[3]; 1501 }; 1502 1503 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1504 1505 struct i40e_aqc_replace_cloud_filters_cmd { 1506 u8 valid_flags; 1507 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1508 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1509 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1510 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1511 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1512 u8 old_filter_type; 1513 u8 new_filter_type; 1514 u8 tr_bit; 1515 u8 reserved[4]; 1516 __le32 addr_high; 1517 __le32 addr_low; 1518 }; 1519 1520 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1521 1522 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1523 u8 data[32]; 1524 /* Filter type INPUT codes*/ 1525 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1526 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) 1527 1528 /* Field Vector offsets */ 1529 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1530 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1531 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1532 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1533 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1534 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1535 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1536 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1537 /* big FLU */ 1538 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1539 /* big FLU */ 1540 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1541 1542 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1543 struct i40e_filter_data filters[8]; 1544 }; 1545 1546 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1547 1548 /* Add Mirror Rule (indirect or direct 0x0260) 1549 * Delete Mirror Rule (indirect or direct 0x0261) 1550 * note: some rule types (4,5) do not use an external buffer. 1551 * take care to set the flags correctly. 1552 */ 1553 struct i40e_aqc_add_delete_mirror_rule { 1554 __le16 seid; 1555 __le16 rule_type; 1556 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1557 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1558 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1559 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1560 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1561 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1562 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1563 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1564 __le16 num_entries; 1565 __le16 destination; /* VSI for add, rule id for delete */ 1566 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1567 __le32 addr_low; 1568 }; 1569 1570 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1571 1572 struct i40e_aqc_add_delete_mirror_rule_completion { 1573 u8 reserved[2]; 1574 __le16 rule_id; /* only used on add */ 1575 __le16 mirror_rules_used; 1576 __le16 mirror_rules_free; 1577 __le32 addr_high; 1578 __le32 addr_low; 1579 }; 1580 1581 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1582 1583 /* Dynamic Device Personalization */ 1584 struct i40e_aqc_write_personalization_profile { 1585 u8 flags; 1586 u8 reserved[3]; 1587 __le32 profile_track_id; 1588 __le32 addr_high; 1589 __le32 addr_low; 1590 }; 1591 1592 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); 1593 1594 struct i40e_aqc_write_ddp_resp { 1595 __le32 error_offset; 1596 __le32 error_info; 1597 __le32 addr_high; 1598 __le32 addr_low; 1599 }; 1600 1601 struct i40e_aqc_get_applied_profiles { 1602 u8 flags; 1603 #define I40E_AQC_GET_DDP_GET_CONF 0x1 1604 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 1605 u8 rsv[3]; 1606 __le32 reserved; 1607 __le32 addr_high; 1608 __le32 addr_low; 1609 }; 1610 1611 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); 1612 1613 /* DCB 0x03xx*/ 1614 1615 /* PFC Ignore (direct 0x0301) 1616 * the command and response use the same descriptor structure 1617 */ 1618 struct i40e_aqc_pfc_ignore { 1619 u8 tc_bitmap; 1620 u8 command_flags; /* unused on response */ 1621 #define I40E_AQC_PFC_IGNORE_SET 0x80 1622 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1623 u8 reserved[14]; 1624 }; 1625 1626 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1627 1628 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1629 * with no parameters 1630 */ 1631 1632 /* TX scheduler 0x04xx */ 1633 1634 /* Almost all the indirect commands use 1635 * this generic struct to pass the SEID in param0 1636 */ 1637 struct i40e_aqc_tx_sched_ind { 1638 __le16 vsi_seid; 1639 u8 reserved[6]; 1640 __le32 addr_high; 1641 __le32 addr_low; 1642 }; 1643 1644 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1645 1646 /* Several commands respond with a set of queue set handles */ 1647 struct i40e_aqc_qs_handles_resp { 1648 __le16 qs_handles[8]; 1649 }; 1650 1651 /* Configure VSI BW limits (direct 0x0400) */ 1652 struct i40e_aqc_configure_vsi_bw_limit { 1653 __le16 vsi_seid; 1654 u8 reserved[2]; 1655 __le16 credit; 1656 u8 reserved1[2]; 1657 u8 max_credit; /* 0-3, limit = 2^max */ 1658 u8 reserved2[7]; 1659 }; 1660 1661 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1662 1663 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1664 * responds with i40e_aqc_qs_handles_resp 1665 */ 1666 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1667 u8 tc_valid_bits; 1668 u8 reserved[15]; 1669 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1670 1671 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1672 __le16 tc_bw_max[2]; 1673 u8 reserved1[28]; 1674 }; 1675 1676 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1677 1678 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1679 * responds with i40e_aqc_qs_handles_resp 1680 */ 1681 struct i40e_aqc_configure_vsi_tc_bw_data { 1682 u8 tc_valid_bits; 1683 u8 reserved[3]; 1684 u8 tc_bw_credits[8]; 1685 u8 reserved1[4]; 1686 __le16 qs_handles[8]; 1687 }; 1688 1689 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1690 1691 /* Query vsi bw configuration (indirect 0x0408) */ 1692 struct i40e_aqc_query_vsi_bw_config_resp { 1693 u8 tc_valid_bits; 1694 u8 tc_suspended_bits; 1695 u8 reserved[14]; 1696 __le16 qs_handles[8]; 1697 u8 reserved1[4]; 1698 __le16 port_bw_limit; 1699 u8 reserved2[2]; 1700 u8 max_bw; /* 0-3, limit = 2^max */ 1701 u8 reserved3[23]; 1702 }; 1703 1704 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1705 1706 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1707 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1708 u8 tc_valid_bits; 1709 u8 reserved[3]; 1710 u8 share_credits[8]; 1711 __le16 credits[8]; 1712 1713 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1714 __le16 tc_bw_max[2]; 1715 }; 1716 1717 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1718 1719 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1720 struct i40e_aqc_configure_switching_comp_bw_limit { 1721 __le16 seid; 1722 u8 reserved[2]; 1723 __le16 credit; 1724 u8 reserved1[2]; 1725 u8 max_bw; /* 0-3, limit = 2^max */ 1726 u8 reserved2[7]; 1727 }; 1728 1729 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1730 1731 /* Enable Physical Port ETS (indirect 0x0413) 1732 * Modify Physical Port ETS (indirect 0x0414) 1733 * Disable Physical Port ETS (indirect 0x0415) 1734 */ 1735 struct i40e_aqc_configure_switching_comp_ets_data { 1736 u8 reserved[4]; 1737 u8 tc_valid_bits; 1738 u8 seepage; 1739 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1740 u8 tc_strict_priority_flags; 1741 u8 reserved1[17]; 1742 u8 tc_bw_share_credits[8]; 1743 u8 reserved2[96]; 1744 }; 1745 1746 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1747 1748 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1749 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1750 u8 tc_valid_bits; 1751 u8 reserved[15]; 1752 __le16 tc_bw_credit[8]; 1753 1754 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1755 __le16 tc_bw_max[2]; 1756 u8 reserved1[28]; 1757 }; 1758 1759 I40E_CHECK_STRUCT_LEN(0x40, 1760 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1761 1762 /* Configure Switching Component Bandwidth Allocation per Tc 1763 * (indirect 0x0417) 1764 */ 1765 struct i40e_aqc_configure_switching_comp_bw_config_data { 1766 u8 tc_valid_bits; 1767 u8 reserved[2]; 1768 u8 absolute_credits; /* bool */ 1769 u8 tc_bw_share_credits[8]; 1770 u8 reserved1[20]; 1771 }; 1772 1773 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1774 1775 /* Query Switching Component Configuration (indirect 0x0418) */ 1776 struct i40e_aqc_query_switching_comp_ets_config_resp { 1777 u8 tc_valid_bits; 1778 u8 reserved[35]; 1779 __le16 port_bw_limit; 1780 u8 reserved1[2]; 1781 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1782 u8 reserved2[23]; 1783 }; 1784 1785 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1786 1787 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1788 struct i40e_aqc_query_port_ets_config_resp { 1789 u8 reserved[4]; 1790 u8 tc_valid_bits; 1791 u8 reserved1; 1792 u8 tc_strict_priority_bits; 1793 u8 reserved2; 1794 u8 tc_bw_share_credits[8]; 1795 __le16 tc_bw_limits[8]; 1796 1797 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1798 __le16 tc_bw_max[2]; 1799 u8 reserved3[32]; 1800 }; 1801 1802 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1803 1804 /* Query Switching Component Bandwidth Allocation per Traffic Type 1805 * (indirect 0x041A) 1806 */ 1807 struct i40e_aqc_query_switching_comp_bw_config_resp { 1808 u8 tc_valid_bits; 1809 u8 reserved[2]; 1810 u8 absolute_credits_enable; /* bool */ 1811 u8 tc_bw_share_credits[8]; 1812 __le16 tc_bw_limits[8]; 1813 1814 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1815 __le16 tc_bw_max[2]; 1816 }; 1817 1818 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1819 1820 /* Suspend/resume port TX traffic 1821 * (direct 0x041B and 0x041C) uses the generic SEID struct 1822 */ 1823 1824 /* Configure partition BW 1825 * (indirect 0x041D) 1826 */ 1827 struct i40e_aqc_configure_partition_bw_data { 1828 __le16 pf_valid_bits; 1829 u8 min_bw[16]; /* guaranteed bandwidth */ 1830 u8 max_bw[16]; /* bandwidth limit */ 1831 }; 1832 1833 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1834 1835 /* Get and set the active HMC resource profile and status. 1836 * (direct 0x0500) and (direct 0x0501) 1837 */ 1838 struct i40e_aq_get_set_hmc_resource_profile { 1839 u8 pm_profile; 1840 u8 pe_vf_enabled; 1841 u8 reserved[14]; 1842 }; 1843 1844 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1845 1846 enum i40e_aq_hmc_profile { 1847 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1848 I40E_HMC_PROFILE_DEFAULT = 1, 1849 I40E_HMC_PROFILE_FAVOR_VF = 2, 1850 I40E_HMC_PROFILE_EQUAL = 3, 1851 }; 1852 1853 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1854 1855 /* set in param0 for get phy abilities to report qualified modules */ 1856 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1857 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1858 1859 enum i40e_aq_phy_type { 1860 I40E_PHY_TYPE_SGMII = 0x0, 1861 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1862 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1863 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1864 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1865 I40E_PHY_TYPE_XAUI = 0x5, 1866 I40E_PHY_TYPE_XFI = 0x6, 1867 I40E_PHY_TYPE_SFI = 0x7, 1868 I40E_PHY_TYPE_XLAUI = 0x8, 1869 I40E_PHY_TYPE_XLPPI = 0x9, 1870 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1871 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1872 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1873 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1874 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1875 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1876 I40E_PHY_TYPE_100BASE_TX = 0x11, 1877 I40E_PHY_TYPE_1000BASE_T = 0x12, 1878 I40E_PHY_TYPE_10GBASE_T = 0x13, 1879 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1880 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1881 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1882 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1883 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1884 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1885 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1886 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1887 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1888 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1889 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1890 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1891 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1892 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1893 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1894 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1895 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1896 I40E_PHY_TYPE_2_5GBASE_T = 0x30, 1897 I40E_PHY_TYPE_5GBASE_T = 0x31, 1898 I40E_PHY_TYPE_MAX, 1899 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1900 I40E_PHY_TYPE_EMPTY = 0xFE, 1901 I40E_PHY_TYPE_DEFAULT = 0xFF, 1902 }; 1903 1904 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1905 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1906 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1907 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1908 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1909 BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1910 BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1911 BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1912 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1913 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1914 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1915 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1916 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1917 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1918 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1919 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1920 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1921 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1922 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1923 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1924 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1925 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1926 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1927 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1928 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 1929 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 1930 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 1931 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 1932 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 1933 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 1934 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 1935 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 1936 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 1937 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 1938 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 1939 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ 1940 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ 1941 BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) 1942 1943 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 1944 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1945 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1946 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1947 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1948 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1949 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1950 #define I40E_LINK_SPEED_5GB_SHIFT 0x7 1951 1952 enum i40e_aq_link_speed { 1953 I40E_LINK_SPEED_UNKNOWN = 0, 1954 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), 1955 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), 1956 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), 1957 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), 1958 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), 1959 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), 1960 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), 1961 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), 1962 }; 1963 1964 struct i40e_aqc_module_desc { 1965 u8 oui[3]; 1966 u8 reserved1; 1967 u8 part_number[16]; 1968 u8 revision[4]; 1969 u8 reserved2[8]; 1970 }; 1971 1972 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1973 1974 struct i40e_aq_get_phy_abilities_resp { 1975 __le32 phy_type; /* bitmap using the above enum for offsets */ 1976 u8 link_speed; /* bitmap using the above enum bit patterns */ 1977 u8 abilities; 1978 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1979 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1980 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1981 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1982 #define I40E_AQ_PHY_AN_ENABLED 0x10 1983 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1984 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1985 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1986 __le16 eee_capability; 1987 #define I40E_AQ_EEE_100BASE_TX 0x0002 1988 #define I40E_AQ_EEE_1000BASE_T 0x0004 1989 #define I40E_AQ_EEE_10GBASE_T 0x0008 1990 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1991 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1992 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1993 __le32 eeer_val; 1994 u8 d3_lpan; 1995 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1996 u8 phy_type_ext; 1997 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1998 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1999 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2000 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2001 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 2002 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 2003 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 2004 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 2005 u8 fec_cfg_curr_mod_ext_info; 2006 #define I40E_AQ_ENABLE_FEC_KR 0x01 2007 #define I40E_AQ_ENABLE_FEC_RS 0x02 2008 #define I40E_AQ_REQUEST_FEC_KR 0x04 2009 #define I40E_AQ_REQUEST_FEC_RS 0x08 2010 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 2011 #define I40E_AQ_FEC 2012 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 2013 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 2014 2015 u8 ext_comp_code; 2016 u8 phy_id[4]; 2017 u8 module_type[3]; 2018 u8 qualified_module_count; 2019 #define I40E_AQ_PHY_MAX_QMS 16 2020 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 2021 }; 2022 2023 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 2024 2025 /* Set PHY Config (direct 0x0601) */ 2026 struct i40e_aq_set_phy_config { /* same bits as above in all */ 2027 __le32 phy_type; 2028 u8 link_speed; 2029 u8 abilities; 2030 /* bits 0-2 use the values from get_phy_abilities_resp */ 2031 #define I40E_AQ_PHY_ENABLE_LINK 0x08 2032 #define I40E_AQ_PHY_ENABLE_AN 0x10 2033 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 2034 __le16 eee_capability; 2035 __le32 eeer; 2036 u8 low_power_ctrl; 2037 u8 phy_type_ext; 2038 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 2039 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 2040 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2041 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2042 u8 fec_config; 2043 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2044 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2045 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2046 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2047 #define I40E_AQ_SET_FEC_AUTO BIT(4) 2048 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 2049 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 2050 u8 reserved; 2051 }; 2052 2053 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 2054 2055 /* Set MAC Config command data structure (direct 0x0603) */ 2056 struct i40e_aq_set_mac_config { 2057 __le16 max_frame_size; 2058 u8 params; 2059 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2060 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2061 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2062 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2063 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2064 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2065 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2066 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2067 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2068 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2069 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2070 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2071 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2072 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2073 #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80 2074 u8 tx_timer_priority; /* bitmap */ 2075 __le16 tx_timer_value; 2076 __le16 fc_refresh_threshold; 2077 u8 reserved[8]; 2078 }; 2079 2080 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2081 2082 /* Restart Auto-Negotiation (direct 0x605) */ 2083 struct i40e_aqc_set_link_restart_an { 2084 u8 command; 2085 #define I40E_AQ_PHY_RESTART_AN 0x02 2086 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2087 u8 reserved[15]; 2088 }; 2089 2090 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2091 2092 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2093 struct i40e_aqc_get_link_status { 2094 __le16 command_flags; /* only field set on command */ 2095 #define I40E_AQ_LSE_MASK 0x3 2096 #define I40E_AQ_LSE_NOP 0x0 2097 #define I40E_AQ_LSE_DISABLE 0x2 2098 #define I40E_AQ_LSE_ENABLE 0x3 2099 /* only response uses this flag */ 2100 #define I40E_AQ_LSE_IS_ENABLED 0x1 2101 u8 phy_type; /* i40e_aq_phy_type */ 2102 u8 link_speed; /* i40e_aq_link_speed */ 2103 u8 link_info; 2104 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2105 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2106 #define I40E_AQ_LINK_FAULT 0x02 2107 #define I40E_AQ_LINK_FAULT_TX 0x04 2108 #define I40E_AQ_LINK_FAULT_RX 0x08 2109 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2110 #define I40E_AQ_LINK_UP_PORT 0x20 2111 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2112 #define I40E_AQ_SIGNAL_DETECT 0x80 2113 u8 an_info; 2114 #define I40E_AQ_AN_COMPLETED 0x01 2115 #define I40E_AQ_LP_AN_ABILITY 0x02 2116 #define I40E_AQ_PD_FAULT 0x04 2117 #define I40E_AQ_FEC_EN 0x08 2118 #define I40E_AQ_PHY_LOW_POWER 0x10 2119 #define I40E_AQ_LINK_PAUSE_TX 0x20 2120 #define I40E_AQ_LINK_PAUSE_RX 0x40 2121 #define I40E_AQ_QUALIFIED_MODULE 0x80 2122 u8 ext_info; 2123 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2124 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2125 #define I40E_AQ_LINK_TX_SHIFT 0x02 2126 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2127 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2128 #define I40E_AQ_LINK_TX_DRAINED 0x01 2129 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2130 #define I40E_AQ_LINK_FORCED_40G 0x10 2131 /* 25G Error Codes */ 2132 #define I40E_AQ_25G_NO_ERR 0X00 2133 #define I40E_AQ_25G_NOT_PRESENT 0X01 2134 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2135 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2136 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2137 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2138 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2139 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2140 #define I40E_AQ_LOOPBACK_MASK 0x07 2141 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2142 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2143 __le16 max_frame_size; 2144 u8 config; 2145 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2146 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2147 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2148 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2149 union { 2150 struct { 2151 u8 power_desc; 2152 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2153 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2154 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2155 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2156 #define I40E_AQ_PWR_CLASS_MASK 0x03 2157 u8 reserved[4]; 2158 }; 2159 struct { 2160 u8 link_type[4]; 2161 u8 link_type_ext; 2162 }; 2163 }; 2164 }; 2165 2166 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2167 2168 /* Set event mask command (direct 0x613) */ 2169 struct i40e_aqc_set_phy_int_mask { 2170 u8 reserved[8]; 2171 __le16 event_mask; 2172 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2173 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2174 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2175 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2176 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2177 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2178 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2179 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2180 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2181 u8 reserved1[6]; 2182 }; 2183 2184 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2185 2186 /* Get Local AN advt register (direct 0x0614) 2187 * Set Local AN advt register (direct 0x0615) 2188 * Get Link Partner AN advt register (direct 0x0616) 2189 */ 2190 struct i40e_aqc_an_advt_reg { 2191 __le32 local_an_reg0; 2192 __le16 local_an_reg1; 2193 u8 reserved[10]; 2194 }; 2195 2196 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2197 2198 /* Set Loopback mode (0x0618) */ 2199 struct i40e_aqc_set_lb_mode { 2200 __le16 lb_mode; 2201 #define I40E_AQ_LB_PHY_LOCAL 0x01 2202 #define I40E_AQ_LB_PHY_REMOTE 0x02 2203 #define I40E_AQ_LB_MAC_LOCAL 0x04 2204 u8 reserved[14]; 2205 }; 2206 2207 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2208 2209 /* Set PHY Debug command (0x0622) */ 2210 struct i40e_aqc_set_phy_debug { 2211 u8 command_flags; 2212 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2213 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2214 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2215 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2216 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2217 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2218 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2219 /* Disable link manageability on a single port */ 2220 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2221 /* Disable link manageability on all ports */ 2222 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2223 u8 reserved[15]; 2224 }; 2225 2226 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2227 2228 enum i40e_aq_phy_reg_type { 2229 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2230 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2231 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2232 }; 2233 2234 /* Run PHY Activity (0x0626) */ 2235 struct i40e_aqc_run_phy_activity { 2236 __le16 activity_id; 2237 u8 flags; 2238 u8 reserved1; 2239 __le32 control; 2240 __le32 data; 2241 u8 reserved2[4]; 2242 }; 2243 2244 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2245 2246 /* Set PHY Register command (0x0628) */ 2247 /* Get PHY Register command (0x0629) */ 2248 struct i40e_aqc_phy_register_access { 2249 u8 phy_interface; 2250 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2251 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2252 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2253 u8 dev_address; 2254 u8 reserved1[2]; 2255 __le32 reg_address; 2256 __le32 reg_value; 2257 u8 reserved2[4]; 2258 }; 2259 2260 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2261 2262 /* NVM Read command (indirect 0x0701) 2263 * NVM Erase commands (direct 0x0702) 2264 * NVM Update commands (indirect 0x0703) 2265 */ 2266 struct i40e_aqc_nvm_update { 2267 u8 command_flags; 2268 #define I40E_AQ_NVM_LAST_CMD 0x01 2269 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 2270 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 2271 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2272 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2273 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2274 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2275 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2276 u8 module_pointer; 2277 __le16 length; 2278 __le32 offset; 2279 __le32 addr_high; 2280 __le32 addr_low; 2281 }; 2282 2283 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2284 2285 /* NVM Config Read (indirect 0x0704) */ 2286 struct i40e_aqc_nvm_config_read { 2287 __le16 cmd_flags; 2288 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2289 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2290 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2291 __le16 element_count; 2292 __le16 element_id; /* Feature/field ID */ 2293 __le16 element_id_msw; /* MSWord of field ID */ 2294 __le32 address_high; 2295 __le32 address_low; 2296 }; 2297 2298 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2299 2300 /* NVM Config Write (indirect 0x0705) */ 2301 struct i40e_aqc_nvm_config_write { 2302 __le16 cmd_flags; 2303 __le16 element_count; 2304 u8 reserved[4]; 2305 __le32 address_high; 2306 __le32 address_low; 2307 }; 2308 2309 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2310 2311 /* Used for 0x0704 as well as for 0x0705 commands */ 2312 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2313 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2314 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2315 #define I40E_AQ_ANVM_FEATURE 0 2316 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) 2317 struct i40e_aqc_nvm_config_data_feature { 2318 __le16 feature_id; 2319 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2320 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2321 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2322 __le16 feature_options; 2323 __le16 feature_selection; 2324 }; 2325 2326 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2327 2328 struct i40e_aqc_nvm_config_data_immediate_field { 2329 __le32 field_id; 2330 __le32 field_value; 2331 __le16 field_options; 2332 __le16 reserved; 2333 }; 2334 2335 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2336 2337 /* OEM Post Update (indirect 0x0720) 2338 * no command data struct used 2339 */ 2340 struct i40e_aqc_nvm_oem_post_update { 2341 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2342 u8 sel_data; 2343 u8 reserved[7]; 2344 }; 2345 2346 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2347 2348 struct i40e_aqc_nvm_oem_post_update_buffer { 2349 u8 str_len; 2350 u8 dev_addr; 2351 __le16 eeprom_addr; 2352 u8 data[36]; 2353 }; 2354 2355 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2356 2357 /* Thermal Sensor (indirect 0x0721) 2358 * read or set thermal sensor configs and values 2359 * takes a sensor and command specific data buffer, not detailed here 2360 */ 2361 struct i40e_aqc_thermal_sensor { 2362 u8 sensor_action; 2363 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2364 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2365 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2366 u8 reserved[7]; 2367 __le32 addr_high; 2368 __le32 addr_low; 2369 }; 2370 2371 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2372 2373 /* Send to PF command (indirect 0x0801) id is only used by PF 2374 * Send to VF command (indirect 0x0802) id is only used by PF 2375 * Send to Peer PF command (indirect 0x0803) 2376 */ 2377 struct i40e_aqc_pf_vf_message { 2378 __le32 id; 2379 u8 reserved[4]; 2380 __le32 addr_high; 2381 __le32 addr_low; 2382 }; 2383 2384 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2385 2386 /* Alternate structure */ 2387 2388 /* Direct write (direct 0x0900) 2389 * Direct read (direct 0x0902) 2390 */ 2391 struct i40e_aqc_alternate_write { 2392 __le32 address0; 2393 __le32 data0; 2394 __le32 address1; 2395 __le32 data1; 2396 }; 2397 2398 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2399 2400 /* Indirect write (indirect 0x0901) 2401 * Indirect read (indirect 0x0903) 2402 */ 2403 2404 struct i40e_aqc_alternate_ind_write { 2405 __le32 address; 2406 __le32 length; 2407 __le32 addr_high; 2408 __le32 addr_low; 2409 }; 2410 2411 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2412 2413 /* Done alternate write (direct 0x0904) 2414 * uses i40e_aq_desc 2415 */ 2416 struct i40e_aqc_alternate_write_done { 2417 __le16 cmd_flags; 2418 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2419 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2420 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2421 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2422 u8 reserved[14]; 2423 }; 2424 2425 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2426 2427 /* Set OEM mode (direct 0x0905) */ 2428 struct i40e_aqc_alternate_set_mode { 2429 __le32 mode; 2430 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2431 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2432 u8 reserved[12]; 2433 }; 2434 2435 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2436 2437 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2438 2439 /* async events 0x10xx */ 2440 2441 /* Lan Queue Overflow Event (direct, 0x1001) */ 2442 struct i40e_aqc_lan_overflow { 2443 __le32 prtdcb_rupto; 2444 __le32 otx_ctl; 2445 u8 reserved[8]; 2446 }; 2447 2448 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2449 2450 /* Get LLDP MIB (indirect 0x0A00) */ 2451 struct i40e_aqc_lldp_get_mib { 2452 u8 type; 2453 u8 reserved1; 2454 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2455 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2456 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2457 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2458 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2459 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2460 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2461 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2462 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2463 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2464 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2465 __le16 local_len; 2466 __le16 remote_len; 2467 u8 reserved2[2]; 2468 __le32 addr_high; 2469 __le32 addr_low; 2470 }; 2471 2472 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2473 2474 /* Configure LLDP MIB Change Event (direct 0x0A01) 2475 * also used for the event (with type in the command field) 2476 */ 2477 struct i40e_aqc_lldp_update_mib { 2478 u8 command; 2479 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2480 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2481 u8 reserved[7]; 2482 __le32 addr_high; 2483 __le32 addr_low; 2484 }; 2485 2486 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2487 2488 /* Add LLDP TLV (indirect 0x0A02) 2489 * Delete LLDP TLV (indirect 0x0A04) 2490 */ 2491 struct i40e_aqc_lldp_add_tlv { 2492 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2493 u8 reserved1[1]; 2494 __le16 len; 2495 u8 reserved2[4]; 2496 __le32 addr_high; 2497 __le32 addr_low; 2498 }; 2499 2500 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2501 2502 /* Update LLDP TLV (indirect 0x0A03) */ 2503 struct i40e_aqc_lldp_update_tlv { 2504 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2505 u8 reserved; 2506 __le16 old_len; 2507 __le16 new_offset; 2508 __le16 new_len; 2509 __le32 addr_high; 2510 __le32 addr_low; 2511 }; 2512 2513 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2514 2515 /* Stop LLDP (direct 0x0A05) */ 2516 struct i40e_aqc_lldp_stop { 2517 u8 command; 2518 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2519 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2520 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2 2521 u8 reserved[15]; 2522 }; 2523 2524 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2525 2526 /* Start LLDP (direct 0x0A06) */ 2527 struct i40e_aqc_lldp_start { 2528 u8 command; 2529 #define I40E_AQ_LLDP_AGENT_START 0x1 2530 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2 2531 u8 reserved[15]; 2532 }; 2533 2534 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2535 2536 /* Set DCB (direct 0x0303) */ 2537 struct i40e_aqc_set_dcb_parameters { 2538 u8 command; 2539 #define I40E_AQ_DCB_SET_AGENT 0x1 2540 #define I40E_DCB_VALID 0x1 2541 u8 valid_flags; 2542 u8 reserved[14]; 2543 }; 2544 2545 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2546 2547 /* Get CEE DCBX Oper Config (0x0A07) 2548 * uses the generic descriptor struct 2549 * returns below as indirect response 2550 */ 2551 2552 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2553 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2554 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2555 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2556 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2557 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2558 2559 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2560 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2561 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2562 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2563 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2564 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2565 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2566 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2567 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2568 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2569 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2570 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2571 2572 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2573 * word boundary layout issues, which the Linux compilers silently deal 2574 * with by adding padding, making the actual struct larger than designed. 2575 * However, the FW compiler for the NIC is less lenient and complains 2576 * about the struct. Hence, the struct defined here has an extra byte in 2577 * fields reserved3 and reserved4 to directly acknowledge that padding, 2578 * and the new length is used in the length check macro. 2579 */ 2580 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2581 u8 reserved1; 2582 u8 oper_num_tc; 2583 u8 oper_prio_tc[4]; 2584 u8 reserved2; 2585 u8 oper_tc_bw[8]; 2586 u8 oper_pfc_en; 2587 u8 reserved3[2]; 2588 __le16 oper_app_prio; 2589 u8 reserved4[2]; 2590 __le16 tlv_status; 2591 }; 2592 2593 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2594 2595 struct i40e_aqc_get_cee_dcb_cfg_resp { 2596 u8 oper_num_tc; 2597 u8 oper_prio_tc[4]; 2598 u8 oper_tc_bw[8]; 2599 u8 oper_pfc_en; 2600 __le16 oper_app_prio; 2601 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2602 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2603 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2604 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2605 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2606 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2607 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2608 __le32 tlv_status; 2609 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2610 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2611 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2612 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2613 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2614 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2615 u8 reserved[12]; 2616 }; 2617 2618 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2619 2620 /* Set Local LLDP MIB (indirect 0x0A08) 2621 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2622 */ 2623 struct i40e_aqc_lldp_set_local_mib { 2624 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2625 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2626 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2627 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2628 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \ 2629 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2630 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2631 u8 type; 2632 u8 reserved0; 2633 __le16 length; 2634 u8 reserved1[4]; 2635 __le32 address_high; 2636 __le32 address_low; 2637 }; 2638 2639 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2640 2641 /* Stop/Start LLDP Agent (direct 0x0A09) 2642 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2643 */ 2644 struct i40e_aqc_lldp_stop_start_specific_agent { 2645 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2646 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2647 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2648 u8 command; 2649 u8 reserved[15]; 2650 }; 2651 2652 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2653 2654 /* Restore LLDP Agent factory settings (direct 0x0A0A) */ 2655 struct i40e_aqc_lldp_restore { 2656 u8 command; 2657 #define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0 2658 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1 2659 u8 reserved[15]; 2660 }; 2661 2662 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore); 2663 2664 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2665 struct i40e_aqc_add_udp_tunnel { 2666 __le16 udp_port; 2667 u8 reserved0[3]; 2668 u8 protocol_type; 2669 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2670 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2671 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2672 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2673 u8 reserved1[10]; 2674 }; 2675 2676 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2677 2678 struct i40e_aqc_add_udp_tunnel_completion { 2679 __le16 udp_port; 2680 u8 filter_entry_index; 2681 u8 multiple_pfs; 2682 #define I40E_AQC_SINGLE_PF 0x0 2683 #define I40E_AQC_MULTIPLE_PFS 0x1 2684 u8 total_filters; 2685 u8 reserved[11]; 2686 }; 2687 2688 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2689 2690 /* remove UDP Tunnel command (0x0B01) */ 2691 struct i40e_aqc_remove_udp_tunnel { 2692 u8 reserved[2]; 2693 u8 index; /* 0 to 15 */ 2694 u8 reserved2[13]; 2695 }; 2696 2697 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2698 2699 struct i40e_aqc_del_udp_tunnel_completion { 2700 __le16 udp_port; 2701 u8 index; /* 0 to 15 */ 2702 u8 multiple_pfs; 2703 u8 total_filters_used; 2704 u8 reserved1[11]; 2705 }; 2706 2707 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2708 2709 struct i40e_aqc_get_set_rss_key { 2710 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) 2711 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2712 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2713 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2714 __le16 vsi_id; 2715 u8 reserved[6]; 2716 __le32 addr_high; 2717 __le32 addr_low; 2718 }; 2719 2720 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2721 2722 struct i40e_aqc_get_set_rss_key_data { 2723 u8 standard_rss_key[0x28]; 2724 u8 extended_hash_key[0xc]; 2725 }; 2726 2727 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2728 2729 struct i40e_aqc_get_set_rss_lut { 2730 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) 2731 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2732 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2733 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2734 __le16 vsi_id; 2735 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2736 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2737 2738 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2739 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2740 __le16 flags; 2741 u8 reserved[4]; 2742 __le32 addr_high; 2743 __le32 addr_low; 2744 }; 2745 2746 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2747 2748 /* tunnel key structure 0x0B10 */ 2749 2750 struct i40e_aqc_tunnel_key_structure { 2751 u8 key1_off; 2752 u8 key2_off; 2753 u8 key1_len; /* 0 to 15 */ 2754 u8 key2_len; /* 0 to 15 */ 2755 u8 flags; 2756 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2757 /* response flags */ 2758 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2759 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2760 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2761 u8 network_key_index; 2762 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2763 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2764 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2765 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2766 u8 reserved[10]; 2767 }; 2768 2769 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2770 2771 /* OEM mode commands (direct 0xFE0x) */ 2772 struct i40e_aqc_oem_param_change { 2773 __le32 param_type; 2774 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2775 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2776 #define I40E_AQ_OEM_PARAM_MAC 2 2777 __le32 param_value1; 2778 __le16 param_value2; 2779 u8 reserved[6]; 2780 }; 2781 2782 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2783 2784 struct i40e_aqc_oem_state_change { 2785 __le32 state; 2786 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2787 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2788 u8 reserved[12]; 2789 }; 2790 2791 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2792 2793 /* Initialize OCSD (0xFE02, direct) */ 2794 struct i40e_aqc_opc_oem_ocsd_initialize { 2795 u8 type_status; 2796 u8 reserved1[3]; 2797 __le32 ocsd_memory_block_addr_high; 2798 __le32 ocsd_memory_block_addr_low; 2799 __le32 requested_update_interval; 2800 }; 2801 2802 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2803 2804 /* Initialize OCBB (0xFE03, direct) */ 2805 struct i40e_aqc_opc_oem_ocbb_initialize { 2806 u8 type_status; 2807 u8 reserved1[3]; 2808 __le32 ocbb_memory_block_addr_high; 2809 __le32 ocbb_memory_block_addr_low; 2810 u8 reserved2[4]; 2811 }; 2812 2813 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2814 2815 /* debug commands */ 2816 2817 /* get device id (0xFF00) uses the generic structure */ 2818 2819 /* set test more (0xFF01, internal) */ 2820 2821 struct i40e_acq_set_test_mode { 2822 u8 mode; 2823 #define I40E_AQ_TEST_PARTIAL 0 2824 #define I40E_AQ_TEST_FULL 1 2825 #define I40E_AQ_TEST_NVM 2 2826 u8 reserved[3]; 2827 u8 command; 2828 #define I40E_AQ_TEST_OPEN 0 2829 #define I40E_AQ_TEST_CLOSE 1 2830 #define I40E_AQ_TEST_INC 2 2831 u8 reserved2[3]; 2832 __le32 address_high; 2833 __le32 address_low; 2834 }; 2835 2836 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2837 2838 /* Debug Read Register command (0xFF03) 2839 * Debug Write Register command (0xFF04) 2840 */ 2841 struct i40e_aqc_debug_reg_read_write { 2842 __le32 reserved; 2843 __le32 address; 2844 __le32 value_high; 2845 __le32 value_low; 2846 }; 2847 2848 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2849 2850 /* Scatter/gather Reg Read (indirect 0xFF05) 2851 * Scatter/gather Reg Write (indirect 0xFF06) 2852 */ 2853 2854 /* i40e_aq_desc is used for the command */ 2855 struct i40e_aqc_debug_reg_sg_element_data { 2856 __le32 address; 2857 __le32 value; 2858 }; 2859 2860 /* Debug Modify register (direct 0xFF07) */ 2861 struct i40e_aqc_debug_modify_reg { 2862 __le32 address; 2863 __le32 value; 2864 __le32 clear_mask; 2865 __le32 set_mask; 2866 }; 2867 2868 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2869 2870 /* dump internal data (0xFF08, indirect) */ 2871 2872 #define I40E_AQ_CLUSTER_ID_AUX 0 2873 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2874 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2875 #define I40E_AQ_CLUSTER_ID_HMC 3 2876 #define I40E_AQ_CLUSTER_ID_MAC0 4 2877 #define I40E_AQ_CLUSTER_ID_MAC1 5 2878 #define I40E_AQ_CLUSTER_ID_MAC2 6 2879 #define I40E_AQ_CLUSTER_ID_MAC3 7 2880 #define I40E_AQ_CLUSTER_ID_DCB 8 2881 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2882 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2883 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2884 2885 struct i40e_aqc_debug_dump_internals { 2886 u8 cluster_id; 2887 u8 table_id; 2888 __le16 data_size; 2889 __le32 idx; 2890 __le32 address_high; 2891 __le32 address_low; 2892 }; 2893 2894 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2895 2896 struct i40e_aqc_debug_modify_internals { 2897 u8 cluster_id; 2898 u8 cluster_specific_params[7]; 2899 __le32 address_high; 2900 __le32 address_low; 2901 }; 2902 2903 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2904 2905 #endif /* _I40E_ADMINQ_CMD_H_ */ 2906
