1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_DPM_H__ 24 #define __AMDGPU_DPM_H__ 25 26 enum amdgpu_int_thermal_type { 27 THERMAL_TYPE_NONE, 28 THERMAL_TYPE_EXTERNAL, 29 THERMAL_TYPE_EXTERNAL_GPIO, 30 THERMAL_TYPE_RV6XX, 31 THERMAL_TYPE_RV770, 32 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 33 THERMAL_TYPE_EVERGREEN, 34 THERMAL_TYPE_SUMO, 35 THERMAL_TYPE_NI, 36 THERMAL_TYPE_SI, 37 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 38 THERMAL_TYPE_CI, 39 THERMAL_TYPE_KV, 40 }; 41 42 enum amdgpu_dpm_auto_throttle_src { 43 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 44 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 45 }; 46 47 enum amdgpu_dpm_event_src { 48 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 49 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 50 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 51 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 52 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 53 }; 54 55 struct amdgpu_ps { 56 u32 caps; /* vbios flags */ 57 u32 class; /* vbios flags */ 58 u32 class2; /* vbios flags */ 59 /* UVD clocks */ 60 u32 vclk; 61 u32 dclk; 62 /* VCE clocks */ 63 u32 evclk; 64 u32 ecclk; 65 bool vce_active; 66 enum amd_vce_level vce_level; 67 /* asic priv */ 68 void *ps_priv; 69 }; 70 71 struct amdgpu_dpm_thermal { 72 /* thermal interrupt work */ 73 struct work_struct work; 74 /* low temperature threshold */ 75 int min_temp; 76 /* high temperature threshold */ 77 int max_temp; 78 /* was last interrupt low to high or high to low */ 79 bool high_to_low; 80 /* interrupt source */ 81 struct amdgpu_irq_src irq; 82 }; 83 84 enum amdgpu_clk_action 85 { 86 AMDGPU_SCLK_UP = 1, 87 AMDGPU_SCLK_DOWN 88 }; 89 90 struct amdgpu_blacklist_clocks 91 { 92 u32 sclk; 93 u32 mclk; 94 enum amdgpu_clk_action action; 95 }; 96 97 struct amdgpu_clock_and_voltage_limits { 98 u32 sclk; 99 u32 mclk; 100 u16 vddc; 101 u16 vddci; 102 }; 103 104 struct amdgpu_clock_array { 105 u32 count; 106 u32 *values; 107 }; 108 109 struct amdgpu_clock_voltage_dependency_entry { 110 u32 clk; 111 u16 v; 112 }; 113 114 struct amdgpu_clock_voltage_dependency_table { 115 u32 count; 116 struct amdgpu_clock_voltage_dependency_entry *entries; 117 }; 118 119 union amdgpu_cac_leakage_entry { 120 struct { 121 u16 vddc; 122 u32 leakage; 123 }; 124 struct { 125 u16 vddc1; 126 u16 vddc2; 127 u16 vddc3; 128 }; 129 }; 130 131 struct amdgpu_cac_leakage_table { 132 u32 count; 133 union amdgpu_cac_leakage_entry *entries; 134 }; 135 136 struct amdgpu_phase_shedding_limits_entry { 137 u16 voltage; 138 u32 sclk; 139 u32 mclk; 140 }; 141 142 struct amdgpu_phase_shedding_limits_table { 143 u32 count; 144 struct amdgpu_phase_shedding_limits_entry *entries; 145 }; 146 147 struct amdgpu_uvd_clock_voltage_dependency_entry { 148 u32 vclk; 149 u32 dclk; 150 u16 v; 151 }; 152 153 struct amdgpu_uvd_clock_voltage_dependency_table { 154 u8 count; 155 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 156 }; 157 158 struct amdgpu_vce_clock_voltage_dependency_entry { 159 u32 ecclk; 160 u32 evclk; 161 u16 v; 162 }; 163 164 struct amdgpu_vce_clock_voltage_dependency_table { 165 u8 count; 166 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 167 }; 168 169 struct amdgpu_ppm_table { 170 u8 ppm_design; 171 u16 cpu_core_number; 172 u32 platform_tdp; 173 u32 small_ac_platform_tdp; 174 u32 platform_tdc; 175 u32 small_ac_platform_tdc; 176 u32 apu_tdp; 177 u32 dgpu_tdp; 178 u32 dgpu_ulv_power; 179 u32 tj_max; 180 }; 181 182 struct amdgpu_cac_tdp_table { 183 u16 tdp; 184 u16 configurable_tdp; 185 u16 tdc; 186 u16 battery_power_limit; 187 u16 small_power_limit; 188 u16 low_cac_leakage; 189 u16 high_cac_leakage; 190 u16 maximum_power_delivery_limit; 191 }; 192 193 struct amdgpu_dpm_dynamic_state { 194 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 195 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 196 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 197 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 198 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 199 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 200 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 201 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 202 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 203 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 204 struct amdgpu_clock_array valid_sclk_values; 205 struct amdgpu_clock_array valid_mclk_values; 206 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 207 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 208 u32 mclk_sclk_ratio; 209 u32 sclk_mclk_delta; 210 u16 vddc_vddci_delta; 211 u16 min_vddc_for_pcie_gen2; 212 struct amdgpu_cac_leakage_table cac_leakage_table; 213 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 214 struct amdgpu_ppm_table *ppm_table; 215 struct amdgpu_cac_tdp_table *cac_tdp_table; 216 }; 217 218 struct amdgpu_dpm_fan { 219 u16 t_min; 220 u16 t_med; 221 u16 t_high; 222 u16 pwm_min; 223 u16 pwm_med; 224 u16 pwm_high; 225 u8 t_hyst; 226 u32 cycle_delay; 227 u16 t_max; 228 u8 control_mode; 229 u16 default_max_fan_pwm; 230 u16 default_fan_output_sensitivity; 231 u16 fan_output_sensitivity; 232 bool ucode_fan_control; 233 }; 234 235 enum amdgpu_pcie_gen { 236 AMDGPU_PCIE_GEN1 = 0, 237 AMDGPU_PCIE_GEN2 = 1, 238 AMDGPU_PCIE_GEN3 = 2, 239 AMDGPU_PCIE_GEN_INVALID = 0xffff 240 }; 241 242 #define amdgpu_dpm_pre_set_power_state(adev) \ 243 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle)) 244 245 #define amdgpu_dpm_set_power_state(adev) \ 246 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle)) 247 248 #define amdgpu_dpm_post_set_power_state(adev) \ 249 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle)) 250 251 #define amdgpu_dpm_display_configuration_changed(adev) \ 252 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle)) 253 254 #define amdgpu_dpm_print_power_state(adev, ps) \ 255 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps))) 256 257 #define amdgpu_dpm_vblank_too_short(adev) \ 258 ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle)) 259 260 #define amdgpu_dpm_enable_bapm(adev, e) \ 261 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 262 263 #define amdgpu_dpm_read_sensor(adev, idx, value, size) \ 264 ((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size))) 265 266 #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 267 ((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m))) 268 269 #define amdgpu_dpm_get_fan_control_mode(adev) \ 270 ((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle)) 271 272 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 273 ((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s))) 274 275 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 276 ((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s))) 277 278 #define amdgpu_dpm_get_fan_speed_rpm(adev, s) \ 279 ((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s)) 280 281 #define amdgpu_dpm_get_sclk(adev, l) \ 282 ((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l))) 283 284 #define amdgpu_dpm_get_mclk(adev, l) \ 285 ((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l))) 286 287 #define amdgpu_dpm_force_performance_level(adev, l) \ 288 ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l))) 289 290 #define amdgpu_dpm_get_current_power_state(adev) \ 291 ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)) 292 293 #define amdgpu_dpm_get_pp_num_states(adev, data) \ 294 ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)) 295 296 #define amdgpu_dpm_get_pp_table(adev, table) \ 297 ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)) 298 299 #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 300 ((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)) 301 302 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 303 ((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)) 304 305 #define amdgpu_dpm_force_clock_level(adev, type, level) \ 306 ((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)) 307 308 #define amdgpu_dpm_get_sclk_od(adev) \ 309 ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)) 310 311 #define amdgpu_dpm_set_sclk_od(adev, value) \ 312 ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)) 313 314 #define amdgpu_dpm_get_mclk_od(adev) \ 315 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) 316 317 #define amdgpu_dpm_set_mclk_od(adev, value) \ 318 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) 319 320 #define amdgpu_dpm_dispatch_task(adev, task_id, user_state) \ 321 ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (user_state)) 322 323 #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \ 324 ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal))) 325 326 #define amdgpu_dpm_get_vce_clock_state(adev, i) \ 327 ((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i))) 328 329 #define amdgpu_dpm_get_performance_level(adev) \ 330 ((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)) 331 332 #define amdgpu_dpm_reset_power_profile_state(adev, request) \ 333 ((adev)->powerplay.pp_funcs->reset_power_profile_state(\ 334 (adev)->powerplay.pp_handle, request)) 335 336 #define amdgpu_dpm_switch_power_profile(adev, type, en) \ 337 ((adev)->powerplay.pp_funcs->switch_power_profile(\ 338 (adev)->powerplay.pp_handle, type, en)) 339 340 #define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \ 341 ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\ 342 (adev)->powerplay.pp_handle, msg_id)) 343 344 #define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \ 345 ((adev)->powerplay.pp_funcs->set_powergating_by_smu(\ 346 (adev)->powerplay.pp_handle, block_type, gate)) 347 348 #define amdgpu_dpm_get_power_profile_mode(adev, buf) \ 349 ((adev)->powerplay.pp_funcs->get_power_profile_mode(\ 350 (adev)->powerplay.pp_handle, buf)) 351 352 #define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \ 353 ((adev)->powerplay.pp_funcs->set_power_profile_mode(\ 354 (adev)->powerplay.pp_handle, parameter, size)) 355 356 #define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \ 357 ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\ 358 (adev)->powerplay.pp_handle, type, parameter, size)) 359 360 struct amdgpu_dpm { 361 struct amdgpu_ps *ps; 362 /* number of valid power states */ 363 int num_ps; 364 /* current power state that is active */ 365 struct amdgpu_ps *current_ps; 366 /* requested power state */ 367 struct amdgpu_ps *requested_ps; 368 /* boot up power state */ 369 struct amdgpu_ps *boot_ps; 370 /* default uvd power state */ 371 struct amdgpu_ps *uvd_ps; 372 /* vce requirements */ 373 u32 num_of_vce_states; 374 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 375 enum amd_vce_level vce_level; 376 enum amd_pm_state_type state; 377 enum amd_pm_state_type user_state; 378 enum amd_pm_state_type last_state; 379 enum amd_pm_state_type last_user_state; 380 u32 platform_caps; 381 u32 voltage_response_time; 382 u32 backbias_response_time; 383 void *priv; 384 u32 new_active_crtcs; 385 int new_active_crtc_count; 386 u32 current_active_crtcs; 387 int current_active_crtc_count; 388 struct amdgpu_dpm_dynamic_state dyn_state; 389 struct amdgpu_dpm_fan fan; 390 u32 tdp_limit; 391 u32 near_tdp_limit; 392 u32 near_tdp_limit_adjusted; 393 u32 sq_ramping_threshold; 394 u32 cac_leakage; 395 u16 tdp_od_limit; 396 u32 tdp_adjustment; 397 u16 load_line_slope; 398 bool power_control; 399 /* special states active */ 400 bool thermal_active; 401 bool uvd_active; 402 bool vce_active; 403 /* thermal handling */ 404 struct amdgpu_dpm_thermal thermal; 405 /* forced levels */ 406 enum amd_dpm_forced_level forced_level; 407 }; 408 409 struct amdgpu_pm { 410 struct mutex mutex; 411 u32 current_sclk; 412 u32 current_mclk; 413 u32 default_sclk; 414 u32 default_mclk; 415 struct amdgpu_i2c_chan *i2c_bus; 416 /* internal thermal controller on rv6xx+ */ 417 enum amdgpu_int_thermal_type int_thermal_type; 418 struct device *int_hwmon_dev; 419 /* fan control parameters */ 420 bool no_fan; 421 u8 fan_pulses_per_revolution; 422 u8 fan_min_rpm; 423 u8 fan_max_rpm; 424 /* dpm */ 425 bool dpm_enabled; 426 bool sysfs_initialized; 427 struct amdgpu_dpm dpm; 428 const struct firmware *fw; /* SMC firmware */ 429 uint32_t fw_version; 430 uint32_t pcie_gen_mask; 431 uint32_t pcie_mlw_mask; 432 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ 433 uint32_t smu_prv_buffer_size; 434 struct amdgpu_bo *smu_prv_buffer; 435 bool ac_power; 436 }; 437 438 #define R600_SSTU_DFLT 0 439 #define R600_SST_DFLT 0x00C8 440 441 /* XXX are these ok? */ 442 #define R600_TEMP_RANGE_MIN (90 * 1000) 443 #define R600_TEMP_RANGE_MAX (120 * 1000) 444 445 #define FDO_PWM_MODE_STATIC 1 446 #define FDO_PWM_MODE_STATIC_RPM 5 447 448 enum amdgpu_td { 449 AMDGPU_TD_AUTO, 450 AMDGPU_TD_UP, 451 AMDGPU_TD_DOWN, 452 }; 453 454 enum amdgpu_display_watermark { 455 AMDGPU_DISPLAY_WATERMARK_LOW = 0, 456 AMDGPU_DISPLAY_WATERMARK_HIGH = 1, 457 }; 458 459 enum amdgpu_display_gap 460 { 461 AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 462 AMDGPU_PM_DISPLAY_GAP_VBLANK = 1, 463 AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2, 464 AMDGPU_PM_DISPLAY_GAP_IGNORE = 3, 465 }; 466 467 void amdgpu_dpm_print_class_info(u32 class, u32 class2); 468 void amdgpu_dpm_print_cap_info(u32 caps); 469 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, 470 struct amdgpu_ps *rps); 471 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); 472 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev); 473 void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev); 474 bool amdgpu_is_uvd_state(u32 class, u32 class2); 475 void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 476 u32 *p, u32 *u); 477 int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th); 478 479 bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor); 480 481 int amdgpu_get_platform_caps(struct amdgpu_device *adev); 482 483 int amdgpu_parse_extended_power_table(struct amdgpu_device *adev); 484 void amdgpu_free_extended_power_table(struct amdgpu_device *adev); 485 486 void amdgpu_add_thermal_controller(struct amdgpu_device *adev); 487 488 enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev, 489 u32 sys_mask, 490 enum amdgpu_pcie_gen asic_gen, 491 enum amdgpu_pcie_gen default_gen); 492 493 u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev, 494 u16 asic_lanes, 495 u16 default_lanes); 496 u8 amdgpu_encode_pci_lane_width(u32 lanes); 497 498 struct amd_vce_state* 499 amdgpu_get_vce_clock_state(void *handle, u32 idx); 500 501 #endif 502
