1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #if defined(CONFIG_DRM_AMD_DC_DCN) 37 #include "mpc.h" 38 #endif 39 #include "dwb.h" 40 #include "mcif_wb.h" 41 #include "panel_cntl.h" 42 43 #define MAX_CLOCK_SOURCES 7 44 45 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 46 uint32_t controller_id); 47 48 #include "grph_object_id.h" 49 #include "link_encoder.h" 50 #include "stream_encoder.h" 51 #include "clock_source.h" 52 #include "audio.h" 53 #include "dm_pp_smu.h" 54 #ifdef CONFIG_DRM_AMD_DC_HDCP 55 #include "dm_cp_psp.h" 56 #endif 57 58 /************ link *****************/ 59 struct link_init_data { 60 const struct dc *dc; 61 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 62 uint32_t connector_index; /* this will be mapped to the HPD pins */ 63 uint32_t link_index; /* this is mapped to DAL display_index 64 TODO: remove it when DC is complete. */ 65 }; 66 67 struct dc_link *link_create(const struct link_init_data *init_params); 68 void link_destroy(struct dc_link **link); 69 70 enum dc_status dc_link_validate_mode_timing( 71 const struct dc_stream_state *stream, 72 struct dc_link *link, 73 const struct dc_crtc_timing *timing); 74 75 void core_link_resume(struct dc_link *link); 76 77 void core_link_enable_stream( 78 struct dc_state *state, 79 struct pipe_ctx *pipe_ctx); 80 81 void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 82 83 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 84 /********** DAL Core*********************/ 85 #include "transform.h" 86 #include "dpp.h" 87 88 struct resource_pool; 89 struct dc_state; 90 struct resource_context; 91 struct clk_bw_params; 92 93 struct resource_funcs { 94 void (*destroy)(struct resource_pool **pool); 95 void (*link_init)(struct dc_link *link); 96 struct panel_cntl*(*panel_cntl_create)( 97 const struct panel_cntl_init_data *panel_cntl_init_data); 98 struct link_encoder *(*link_enc_create)( 99 const struct encoder_init_data *init); 100 /* Create a minimal link encoder object with no dc_link object 101 * associated with it. */ 102 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 103 104 bool (*validate_bandwidth)( 105 struct dc *dc, 106 struct dc_state *context, 107 bool fast_validate); 108 void (*calculate_wm_and_dlg)( 109 struct dc *dc, struct dc_state *context, 110 display_e2e_pipe_params_st *pipes, 111 int pipe_cnt, 112 int vlevel); 113 void (*update_soc_for_wm_a)( 114 struct dc *dc, struct dc_state *context); 115 int (*populate_dml_pipes)( 116 struct dc *dc, 117 struct dc_state *context, 118 display_e2e_pipe_params_st *pipes, 119 bool fast_validate); 120 121 /* 122 * Algorithm for assigning available link encoders to links. 123 * 124 * Update link_enc_assignments table and link_enc_avail list accordingly in 125 * struct resource_context. 126 */ 127 void (*link_encs_assign)( 128 struct dc *dc, 129 struct dc_state *state, 130 struct dc_stream_state *streams[], 131 uint8_t stream_count); 132 /* 133 * Unassign a link encoder from a stream. 134 * 135 * Update link_enc_assignments table and link_enc_avail list accordingly in 136 * struct resource_context. 137 */ 138 void (*link_enc_unassign)( 139 struct dc_state *state, 140 struct dc_stream_state *stream); 141 142 enum dc_status (*validate_global)( 143 struct dc *dc, 144 struct dc_state *context); 145 146 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 147 struct dc_state *context, 148 const struct resource_pool *pool, 149 struct dc_stream_state *stream); 150 151 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 152 153 enum dc_status (*add_stream_to_ctx)( 154 struct dc *dc, 155 struct dc_state *new_ctx, 156 struct dc_stream_state *dc_stream); 157 158 enum dc_status (*remove_stream_from_ctx)( 159 struct dc *dc, 160 struct dc_state *new_ctx, 161 struct dc_stream_state *stream); 162 enum dc_status (*patch_unknown_plane_state)( 163 struct dc_plane_state *plane_state); 164 165 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 166 struct resource_context *res_ctx, 167 const struct resource_pool *pool, 168 struct dc_stream_state *stream); 169 void (*populate_dml_writeback_from_context)( 170 struct dc *dc, 171 struct resource_context *res_ctx, 172 display_e2e_pipe_params_st *pipes); 173 174 void (*set_mcif_arb_params)( 175 struct dc *dc, 176 struct dc_state *context, 177 display_e2e_pipe_params_st *pipes, 178 int pipe_cnt); 179 void (*update_bw_bounding_box)( 180 struct dc *dc, 181 struct clk_bw_params *bw_params); 182 #if defined(CONFIG_DRM_AMD_DC_DCN) 183 bool (*acquire_post_bldn_3dlut)( 184 struct resource_context *res_ctx, 185 const struct resource_pool *pool, 186 int mpcc_id, 187 struct dc_3dlut **lut, 188 struct dc_transfer_func **shaper); 189 190 bool (*release_post_bldn_3dlut)( 191 struct resource_context *res_ctx, 192 const struct resource_pool *pool, 193 struct dc_3dlut **lut, 194 struct dc_transfer_func **shaper); 195 #endif 196 enum dc_status (*add_dsc_to_stream_resource)( 197 struct dc *dc, struct dc_state *state, 198 struct dc_stream_state *stream); 199 }; 200 201 struct audio_support{ 202 bool dp_audio; 203 bool hdmi_audio_on_dongle; 204 bool hdmi_audio_native; 205 }; 206 207 #define NO_UNDERLAY_PIPE -1 208 209 struct resource_pool { 210 struct mem_input *mis[MAX_PIPES]; 211 struct hubp *hubps[MAX_PIPES]; 212 struct input_pixel_processor *ipps[MAX_PIPES]; 213 struct transform *transforms[MAX_PIPES]; 214 struct dpp *dpps[MAX_PIPES]; 215 struct output_pixel_processor *opps[MAX_PIPES]; 216 struct timing_generator *timing_generators[MAX_PIPES]; 217 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 218 struct hubbub *hubbub; 219 struct mpc *mpc; 220 struct pp_smu_funcs *pp_smu; 221 struct dce_aux *engines[MAX_PIPES]; 222 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 223 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 224 bool i2c_hw_buffer_in_use; 225 226 struct dwbc *dwbc[MAX_DWB_PIPES]; 227 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 228 struct { 229 unsigned int gsl_0:1; 230 unsigned int gsl_1:1; 231 unsigned int gsl_2:1; 232 } gsl_groups; 233 234 struct display_stream_compressor *dscs[MAX_PIPES]; 235 236 unsigned int pipe_count; 237 unsigned int underlay_pipe_index; 238 unsigned int stream_enc_count; 239 240 /* An array for accessing the link encoder objects that have been created. 241 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 242 */ 243 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 244 /* Number of DIG link encoder objects created - i.e. number of valid 245 * entries in link_encoders array. 246 */ 247 unsigned int dig_link_enc_count; 248 249 #if defined(CONFIG_DRM_AMD_DC_DCN) 250 struct dc_3dlut *mpc_lut[MAX_PIPES]; 251 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 252 #endif 253 struct { 254 unsigned int xtalin_clock_inKhz; 255 unsigned int dccg_ref_clock_inKhz; 256 unsigned int dchub_ref_clock_inKhz; 257 } ref_clocks; 258 unsigned int timing_generator_count; 259 unsigned int mpcc_count; 260 261 unsigned int writeback_pipe_count; 262 /* 263 * reserved clock source for DP 264 */ 265 struct clock_source *dp_clock_source; 266 267 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 268 unsigned int clk_src_count; 269 270 struct audio *audios[MAX_AUDIOS]; 271 unsigned int audio_count; 272 struct audio_support audio_support; 273 274 struct dccg *dccg; 275 struct irq_service *irqs; 276 277 struct abm *abm; 278 struct dmcu *dmcu; 279 struct dmub_psr *psr; 280 281 #if defined(CONFIG_DRM_AMD_DC_DCN) 282 struct abm *multiple_abms[MAX_PIPES]; 283 #endif 284 285 const struct resource_funcs *funcs; 286 const struct resource_caps *res_cap; 287 288 struct ddc_service *oem_device; 289 }; 290 291 struct dcn_fe_bandwidth { 292 int dppclk_khz; 293 294 }; 295 296 struct stream_resource { 297 struct output_pixel_processor *opp; 298 struct display_stream_compressor *dsc; 299 struct timing_generator *tg; 300 struct stream_encoder *stream_enc; 301 struct audio *audio; 302 303 struct pixel_clk_params pix_clk_params; 304 struct encoder_info_frame encoder_info_frame; 305 306 struct abm *abm; 307 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 308 * otherwise it's using group number 'gsl_group-1' 309 */ 310 uint8_t gsl_group; 311 }; 312 313 struct plane_resource { 314 struct scaler_data scl_data; 315 struct hubp *hubp; 316 struct mem_input *mi; 317 struct input_pixel_processor *ipp; 318 struct transform *xfm; 319 struct dpp *dpp; 320 uint8_t mpcc_inst; 321 322 struct dcn_fe_bandwidth bw; 323 }; 324 325 union pipe_update_flags { 326 struct { 327 uint32_t enable : 1; 328 uint32_t disable : 1; 329 uint32_t odm : 1; 330 uint32_t global_sync : 1; 331 uint32_t opp_changed : 1; 332 uint32_t tg_changed : 1; 333 uint32_t mpcc : 1; 334 uint32_t dppclk : 1; 335 uint32_t hubp_interdependent : 1; 336 uint32_t hubp_rq_dlg_ttu : 1; 337 uint32_t gamut_remap : 1; 338 uint32_t scaler : 1; 339 uint32_t viewport : 1; 340 uint32_t plane_changed : 1; 341 uint32_t det_size : 1; 342 } bits; 343 uint32_t raw; 344 }; 345 346 struct pipe_ctx { 347 struct dc_plane_state *plane_state; 348 struct dc_stream_state *stream; 349 350 struct plane_resource plane_res; 351 struct stream_resource stream_res; 352 353 struct clock_source *clock_source; 354 355 struct pll_settings pll_settings; 356 357 uint8_t pipe_idx; 358 359 struct pipe_ctx *top_pipe; 360 struct pipe_ctx *bottom_pipe; 361 struct pipe_ctx *next_odm_pipe; 362 struct pipe_ctx *prev_odm_pipe; 363 364 #ifdef CONFIG_DRM_AMD_DC_DCN 365 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 366 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 367 struct _vcs_dpi_display_rq_regs_st rq_regs; 368 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 369 int det_buffer_size_kb; 370 bool unbounded_req; 371 #endif 372 union pipe_update_flags update_flags; 373 struct dwbc *dwbc; 374 struct mcif_wb *mcif_wb; 375 bool vtp_locked; 376 }; 377 378 struct resource_context { 379 struct pipe_ctx pipe_ctx[MAX_PIPES]; 380 bool is_stream_enc_acquired[MAX_PIPES * 2]; 381 bool is_audio_acquired[MAX_PIPES]; 382 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 383 uint8_t dp_clock_source_ref_count; 384 bool is_dsc_acquired[MAX_PIPES]; 385 /* A table/array of encoder-to-link assignments. One entry per stream. 386 * Indexed by stream index in dc_state. 387 */ 388 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 389 /* List of available link encoders. Uses engine ID as encoder identifier. */ 390 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 391 #if defined(CONFIG_DRM_AMD_DC_DCN) 392 bool is_mpc_3dlut_acquired[MAX_PIPES]; 393 #endif 394 }; 395 396 struct dce_bw_output { 397 bool cpuc_state_change_enable; 398 bool cpup_state_change_enable; 399 bool stutter_mode_enable; 400 bool nbp_state_change_enable; 401 bool all_displays_in_sync; 402 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 403 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 404 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 405 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 406 int sclk_khz; 407 int sclk_deep_sleep_khz; 408 int yclk_khz; 409 int dispclk_khz; 410 int blackout_recovery_time_us; 411 }; 412 413 struct dcn_bw_writeback { 414 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 415 }; 416 417 struct dcn_bw_output { 418 struct dc_clocks clk; 419 struct dcn_watermark_set watermarks; 420 struct dcn_bw_writeback bw_writeback; 421 int compbuf_size_kb; 422 }; 423 424 union bw_output { 425 struct dcn_bw_output dcn; 426 struct dce_bw_output dce; 427 }; 428 429 struct bw_context { 430 union bw_output bw; 431 struct display_mode_lib dml; 432 }; 433 /** 434 * struct dc_state - The full description of a state requested by a user 435 * 436 * @streams: Stream properties 437 * @stream_status: The planes on a given stream 438 * @res_ctx: Persistent state of resources 439 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 440 * @pp_display_cfg: PowerPlay clocks and settings 441 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 442 * 443 */ 444 struct dc_state { 445 struct dc_stream_state *streams[MAX_PIPES]; 446 struct dc_stream_status stream_status[MAX_PIPES]; 447 uint8_t stream_count; 448 uint8_t stream_mask; 449 450 struct resource_context res_ctx; 451 452 struct bw_context bw_ctx; 453 454 /* Note: these are big structures, do *not* put on stack! */ 455 struct dm_pp_display_configuration pp_display_cfg; 456 #ifdef CONFIG_DRM_AMD_DC_DCN 457 struct dcn_bw_internal_vars dcn_bw_vars; 458 #endif 459 460 struct clk_mgr *clk_mgr; 461 462 struct kref refcount; 463 464 struct { 465 unsigned int stutter_period_us; 466 } perf_params; 467 }; 468 469 #endif /* _CORE_TYPES_H_ */ 470
