1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
46 #endif
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
49 #include <net/xdp.h>
50
51 #include <linux/mlx4/device.h>
52 #include <linux/mlx4/qp.h>
53 #include <linux/mlx4/cq.h>
54 #include <linux/mlx4/srq.h>
55 #include <linux/mlx4/doorbell.h>
56 #include <linux/mlx4/cmd.h>
57
58 #include "en_port.h"
59 #include "mlx4_stats.h"
60
61 #define DRV_NAME "mlx4_en"
62 #define DRV_VERSION "4.0-0"
63
64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
65
66 /*
67 * Device constants
68 */
69
70
71 #define MLX4_EN_PAGE_SHIFT 12
72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
73 #define DEF_RX_RINGS 16
74 #define MAX_RX_RINGS 128
75 #define MIN_RX_RINGS 4
76 #define LOG_TXBB_SIZE 6
77 #define TXBB_SIZE BIT(LOG_TXBB_SIZE)
78 #define HEADROOM (2048 / TXBB_SIZE + 1)
79 #define STAMP_STRIDE 64
80 #define STAMP_DWORDS (STAMP_STRIDE / 4)
81 #define STAMP_SHIFT 31
82 #define STAMP_VAL 0x7fffffff
83 #define STATS_DELAY (HZ / 4)
84 #define SERVICE_TASK_DELAY (HZ / 4)
85 #define MAX_NUM_OF_FS_RULES 256
86
87 #define MLX4_EN_FILTER_HASH_SHIFT 4
88 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
89
90 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
91 #define MAX_DESC_SIZE 512
92 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
93
94 /*
95 * OS related constants and tunables
96 */
97
98 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
99 #define MLX4_EN_PRIV_FLAGS_PHV 2
100
101 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
102
103 /* Use the maximum between 16384 and a single page */
104 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
105
106 #define MLX4_EN_MAX_RX_FRAGS 4
107
108 /* Maximum ring sizes */
109 #define MLX4_EN_MAX_TX_SIZE 8192
110 #define MLX4_EN_MAX_RX_SIZE 8192
111
112 /* Minimum ring size for our page-allocation scheme to work */
113 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
114 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
115
116 #define MLX4_EN_SMALL_PKT_SIZE 64
117 #define MLX4_EN_MIN_TX_RING_P_UP 1
118 #define MLX4_EN_MAX_TX_RING_P_UP 32
119 #define MLX4_EN_NUM_UP_LOW 1
120 #define MLX4_EN_NUM_UP_HIGH 8
121 #define MLX4_EN_DEF_RX_RING_SIZE 1024
122 #define MLX4_EN_DEF_TX_RING_SIZE MLX4_EN_DEF_RX_RING_SIZE
123 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
124 MLX4_EN_NUM_UP_HIGH)
125
126 #define MLX4_EN_DEFAULT_TX_WORK 256
127
128 /* Target number of packets to coalesce with interrupt moderation */
129 #define MLX4_EN_RX_COAL_TARGET 44
130 #define MLX4_EN_RX_COAL_TIME 0x10
131
132 #define MLX4_EN_TX_COAL_PKTS 16
133 #define MLX4_EN_TX_COAL_TIME 0x10
134
135 #define MLX4_EN_MAX_COAL_PKTS U16_MAX
136 #define MLX4_EN_MAX_COAL_TIME U16_MAX
137
138 #define MLX4_EN_RX_RATE_LOW 400000
139 #define MLX4_EN_RX_COAL_TIME_LOW 0
140 #define MLX4_EN_RX_RATE_HIGH 450000
141 #define MLX4_EN_RX_COAL_TIME_HIGH 128
142 #define MLX4_EN_RX_SIZE_THRESH 1024
143 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
144 #define MLX4_EN_SAMPLE_INTERVAL 0
145 #define MLX4_EN_AVG_PKT_SMALL 256
146
147 #define MLX4_EN_AUTO_CONF 0xffff
148
149 #define MLX4_EN_DEF_RX_PAUSE 1
150 #define MLX4_EN_DEF_TX_PAUSE 1
151
152 /* Interval between successive polls in the Tx routine when polling is used
153 instead of interrupts (in per-core Tx rings) - should be power of 2 */
154 #define MLX4_EN_TX_POLL_MODER 16
155 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
156
157 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
158 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
159 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
160 #define PREAMBLE_LEN 8
161 #define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \
162 ETH_HLEN + PREAMBLE_LEN)
163
164 #define MLX4_EN_MIN_MTU 46
165 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
166 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
167 */
168 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
169 #define ETH_BCAST 0xffffffffffffULL
170
171 #define MLX4_EN_LOOPBACK_RETRIES 5
172 #define MLX4_EN_LOOPBACK_TIMEOUT 100
173
174 #ifdef MLX4_EN_PERF_STAT
175 /* Number of samples to 'average' */
176 #define AVG_SIZE 128
177 #define AVG_FACTOR 1024
178
179 #define INC_PERF_COUNTER(cnt) (++(cnt))
180 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
181 #define AVG_PERF_COUNTER(cnt, sample) \
182 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
183 #define GET_PERF_COUNTER(cnt) (cnt)
184 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
185
186 #else
187
188 #define INC_PERF_COUNTER(cnt) do {} while (0)
189 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
190 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
191 #define GET_PERF_COUNTER(cnt) (0)
192 #define GET_AVG_PERF_COUNTER(cnt) (0)
193 #endif /* MLX4_EN_PERF_STAT */
194
195 /* Constants for TX flow */
196 enum {
197 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
198 MAX_BF = 256,
199 MIN_PKT_LEN = 17,
200 };
201
202 /*
203 * Configurables
204 */
205
206 enum cq_type {
207 /* keep tx types first */
208 TX,
209 TX_XDP,
210 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
211 RX,
212 };
213
214
215 /*
216 * Useful macros
217 */
218 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
219 #define XNOR(x, y) (!(x) == !(y))
220
221
222 struct mlx4_en_tx_info {
223 union {
224 struct sk_buff *skb;
225 struct page *page;
226 };
227 dma_addr_t map0_dma;
228 u32 map0_byte_count;
229 u32 nr_txbb;
230 u32 nr_bytes;
231 u8 linear;
232 u8 data_offset;
233 u8 inl;
234 u8 ts_requested;
235 u8 nr_maps;
236 } ____cacheline_aligned_in_smp;
237
238
239 #define MLX4_EN_BIT_DESC_OWN 0x80000000
240 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
241 #define MLX4_EN_MEMTYPE_PAD 0x100
242 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
243
244
245 struct mlx4_en_tx_desc {
246 struct mlx4_wqe_ctrl_seg ctrl;
247 union {
248 struct mlx4_wqe_data_seg data; /* at least one data segment */
249 struct mlx4_wqe_lso_seg lso;
250 struct mlx4_wqe_inline_seg inl;
251 };
252 };
253
254 #define MLX4_EN_USE_SRQ 0x01000000
255
256 #define MLX4_EN_CX3_LOW_ID 0x1000
257 #define MLX4_EN_CX3_HIGH_ID 0x1005
258
259 struct mlx4_en_rx_alloc {
260 struct page *page;
261 dma_addr_t dma;
262 u32 page_offset;
263 };
264
265 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
266
267 struct mlx4_en_page_cache {
268 u32 index;
269 struct {
270 struct page *page;
271 dma_addr_t dma;
272 } buf[MLX4_EN_CACHE_SIZE];
273 };
274
275 struct mlx4_en_priv;
276
277 struct mlx4_en_tx_ring {
278 /* cache line used and dirtied in tx completion
279 * (mlx4_en_free_tx_buf())
280 */
281 u32 last_nr_txbb;
282 u32 cons;
283 unsigned long wake_queue;
284 struct netdev_queue *tx_queue;
285 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
286 struct mlx4_en_tx_ring *ring,
287 int index,
288 u64 timestamp, int napi_mode);
289 struct mlx4_en_rx_ring *recycle_ring;
290
291 /* cache line used and dirtied in mlx4_en_xmit() */
292 u32 prod ____cacheline_aligned_in_smp;
293 unsigned int tx_dropped;
294 unsigned long bytes;
295 unsigned long packets;
296 unsigned long tx_csum;
297 unsigned long tso_packets;
298 unsigned long xmit_more;
299 struct mlx4_bf bf;
300
301 /* Following part should be mostly read */
302 __be32 doorbell_qpn;
303 __be32 mr_key;
304 u32 size; /* number of TXBBs */
305 u32 size_mask;
306 u32 full_size;
307 u32 buf_size;
308 void *buf;
309 struct mlx4_en_tx_info *tx_info;
310 int qpn;
311 u8 queue_index;
312 bool bf_enabled;
313 bool bf_alloced;
314 u8 hwtstamp_tx_type;
315 u8 *bounce_buf;
316
317 /* Not used in fast path
318 * Only queue_stopped might be used if BQL is not properly working.
319 */
320 unsigned long queue_stopped;
321 struct mlx4_hwq_resources sp_wqres;
322 struct mlx4_qp sp_qp;
323 struct mlx4_qp_context sp_context;
324 cpumask_t sp_affinity_mask;
325 enum mlx4_qp_state sp_qp_state;
326 u16 sp_stride;
327 u16 sp_cqn; /* index of port CQ associated with this ring */
328 } ____cacheline_aligned_in_smp;
329
330 struct mlx4_en_rx_desc {
331 /* actual number of entries depends on rx ring stride */
332 struct mlx4_wqe_data_seg data[0];
333 };
334
335 struct mlx4_en_rx_ring {
336 struct mlx4_hwq_resources wqres;
337 u32 size ; /* number of Rx descs*/
338 u32 actual_size;
339 u32 size_mask;
340 u16 stride;
341 u16 log_stride;
342 u16 cqn; /* index of port CQ associated with this ring */
343 u32 prod;
344 u32 cons;
345 u32 buf_size;
346 u8 fcs_del;
347 void *buf;
348 void *rx_info;
349 struct bpf_prog __rcu *xdp_prog;
350 struct mlx4_en_page_cache page_cache;
351 unsigned long bytes;
352 unsigned long packets;
353 unsigned long csum_ok;
354 unsigned long csum_none;
355 unsigned long csum_complete;
356 unsigned long rx_alloc_pages;
357 unsigned long xdp_drop;
358 unsigned long xdp_tx;
359 unsigned long xdp_tx_full;
360 unsigned long dropped;
361 int hwtstamp_rx_filter;
362 cpumask_var_t affinity_mask;
363 struct xdp_rxq_info xdp_rxq;
364 };
365
366 struct mlx4_en_cq {
367 struct mlx4_cq mcq;
368 struct mlx4_hwq_resources wqres;
369 int ring;
370 struct net_device *dev;
371 union {
372 struct napi_struct napi;
373 bool xdp_busy;
374 };
375 int size;
376 int buf_size;
377 int vector;
378 enum cq_type type;
379 u16 moder_time;
380 u16 moder_cnt;
381 struct mlx4_cqe *buf;
382 #define MLX4_EN_OPCODE_ERROR 0x1e
383
384 struct irq_desc *irq_desc;
385 };
386
387 struct mlx4_en_port_profile {
388 u32 flags;
389 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
390 u32 rx_ring_num;
391 u32 tx_ring_size;
392 u32 rx_ring_size;
393 u8 num_tx_rings_p_up;
394 u8 rx_pause;
395 u8 rx_ppp;
396 u8 tx_pause;
397 u8 tx_ppp;
398 u8 num_up;
399 int rss_rings;
400 int inline_thold;
401 struct hwtstamp_config hwtstamp_config;
402 };
403
404 struct mlx4_en_profile {
405 int udp_rss;
406 u8 rss_mask;
407 u32 active_ports;
408 u32 small_pkt_int;
409 u8 no_reset;
410 u8 max_num_tx_rings_p_up;
411 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
412 };
413
414 struct mlx4_en_dev {
415 struct mlx4_dev *dev;
416 struct pci_dev *pdev;
417 struct mutex state_lock;
418 struct net_device *pndev[MLX4_MAX_PORTS + 1];
419 struct net_device *upper[MLX4_MAX_PORTS + 1];
420 u32 port_cnt;
421 bool device_up;
422 struct mlx4_en_profile profile;
423 u32 LSO_support;
424 struct workqueue_struct *workqueue;
425 struct device *dma_device;
426 void __iomem *uar_map;
427 struct mlx4_uar priv_uar;
428 struct mlx4_mr mr;
429 u32 priv_pdn;
430 spinlock_t uar_lock;
431 u8 mac_removed[MLX4_MAX_PORTS + 1];
432 u32 nominal_c_mult;
433 struct cyclecounter cycles;
434 seqlock_t clock_lock;
435 struct timecounter clock;
436 unsigned long last_overflow_check;
437 struct ptp_clock *ptp_clock;
438 struct ptp_clock_info ptp_clock_info;
439 struct notifier_block nb;
440 };
441
442
443 struct mlx4_en_rss_map {
444 int base_qpn;
445 struct mlx4_qp qps[MAX_RX_RINGS];
446 enum mlx4_qp_state state[MAX_RX_RINGS];
447 struct mlx4_qp *indir_qp;
448 enum mlx4_qp_state indir_state;
449 };
450
451 enum mlx4_en_port_flag {
452 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
453 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
454 };
455
456 struct mlx4_en_port_state {
457 int link_state;
458 int link_speed;
459 int transceiver;
460 u32 flags;
461 };
462
463 enum mlx4_en_mclist_act {
464 MCLIST_NONE,
465 MCLIST_REM,
466 MCLIST_ADD,
467 };
468
469 struct mlx4_en_mc_list {
470 struct list_head list;
471 enum mlx4_en_mclist_act action;
472 u8 addr[ETH_ALEN];
473 u64 reg_id;
474 u64 tunnel_reg_id;
475 };
476
477 struct mlx4_en_frag_info {
478 u16 frag_size;
479 u32 frag_stride;
480 };
481
482 #ifdef CONFIG_MLX4_EN_DCB
483 /* Minimal TC BW - setting to 0 will block traffic */
484 #define MLX4_EN_BW_MIN 1
485 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
486
487 #define MLX4_EN_TC_VENDOR 0
488 #define MLX4_EN_TC_ETS 7
489
490 enum dcb_pfc_type {
491 pfc_disabled = 0,
492 pfc_enabled_full,
493 pfc_enabled_tx,
494 pfc_enabled_rx
495 };
496
497 struct mlx4_en_cee_config {
498 bool pfc_state;
499 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];
500 };
501 #endif
502
503 struct ethtool_flow_id {
504 struct list_head list;
505 struct ethtool_rx_flow_spec flow_spec;
506 u64 id;
507 };
508
509 enum {
510 MLX4_EN_FLAG_PROMISC = (1 << 0),
511 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
512 /* whether we need to enable hardware loopback by putting dmac
513 * in Tx WQE
514 */
515 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
516 /* whether we need to drop packets that hardware loopback-ed */
517 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
518 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
519 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
520 #ifdef CONFIG_MLX4_EN_DCB
521 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
522 #endif
523 };
524
525 #define PORT_BEACON_MAX_LIMIT (65535)
526 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
527 #define MLX4_EN_MAC_HASH_IDX 5
528
529 struct mlx4_en_stats_bitmap {
530 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
531 struct mutex mutex; /* for mutual access to stats bitmap */
532 };
533
534 struct mlx4_en_priv {
535 struct mlx4_en_dev *mdev;
536 struct mlx4_en_port_profile *prof;
537 struct net_device *dev;
538 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
539 struct mlx4_en_port_state port_state;
540 spinlock_t stats_lock;
541 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
542 /* To allow rules removal while port is going down */
543 struct list_head ethtool_list;
544
545 unsigned long last_moder_packets[MAX_RX_RINGS];
546 unsigned long last_moder_tx_packets;
547 unsigned long last_moder_bytes[MAX_RX_RINGS];
548 unsigned long last_moder_jiffies;
549 int last_moder_time[MAX_RX_RINGS];
550 u16 rx_usecs;
551 u16 rx_frames;
552 u16 tx_usecs;
553 u16 tx_frames;
554 u32 pkt_rate_low;
555 u16 rx_usecs_low;
556 u32 pkt_rate_high;
557 u16 rx_usecs_high;
558 u32 sample_interval;
559 u32 adaptive_rx_coal;
560 u32 msg_enable;
561 u32 loopback_ok;
562 u32 validate_loopback;
563
564 struct mlx4_hwq_resources res;
565 int link_state;
566 int last_link_state;
567 bool port_up;
568 int port;
569 int registered;
570 int allocated;
571 int stride;
572 unsigned char current_mac[ETH_ALEN + 2];
573 int mac_index;
574 unsigned max_mtu;
575 int base_qpn;
576 int cqe_factor;
577 int cqe_size;
578
579 struct mlx4_en_rss_map rss_map;
580 __be32 ctrl_flags;
581 u32 flags;
582 u8 num_tx_rings_p_up;
583 u32 tx_work_limit;
584 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
585 u32 rx_ring_num;
586 u32 rx_skb_size;
587 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
588 u8 num_frags;
589 u8 log_rx_info;
590 u8 dma_dir;
591 u16 rx_headroom;
592
593 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
594 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
595 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
596 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
597 struct mlx4_qp drop_qp;
598 struct work_struct rx_mode_task;
599 struct work_struct watchdog_task;
600 struct work_struct linkstate_task;
601 struct delayed_work stats_task;
602 struct delayed_work service_task;
603 struct work_struct vxlan_add_task;
604 struct work_struct vxlan_del_task;
605 struct mlx4_en_perf_stats pstats;
606 struct mlx4_en_pkt_stats pkstats;
607 struct mlx4_en_counter_stats pf_stats;
608 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
609 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
610 struct mlx4_en_flow_stats_rx rx_flowstats;
611 struct mlx4_en_flow_stats_tx tx_flowstats;
612 struct mlx4_en_port_stats port_stats;
613 struct mlx4_en_xdp_stats xdp_stats;
614 struct mlx4_en_phy_stats phy_stats;
615 struct mlx4_en_stats_bitmap stats_bitmap;
616 struct list_head mc_list;
617 struct list_head curr_list;
618 u64 broadcast_id;
619 struct mlx4_en_stat_out_mbox hw_stats;
620 int vids[128];
621 bool wol;
622 struct device *ddev;
623 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
624 struct hwtstamp_config hwtstamp_config;
625 u32 counter_index;
626
627 #ifdef CONFIG_MLX4_EN_DCB
628 #define MLX4_EN_DCB_ENABLED 0x3
629 struct ieee_ets ets;
630 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
631 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
632 struct mlx4_en_cee_config cee_config;
633 u8 dcbx_cap;
634 #endif
635 #ifdef CONFIG_RFS_ACCEL
636 spinlock_t filters_lock;
637 int last_filter_id;
638 struct list_head filters;
639 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
640 #endif
641 u64 tunnel_reg_id;
642 __be16 vxlan_port;
643
644 u32 pflags;
645 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
646 u8 rss_hash_fn;
647 };
648
649 enum mlx4_en_wol {
650 MLX4_EN_WOL_MAGIC = (1ULL << 61),
651 MLX4_EN_WOL_ENABLED = (1ULL << 62),
652 };
653
654 struct mlx4_mac_entry {
655 struct hlist_node hlist;
656 unsigned char mac[ETH_ALEN + 2];
657 u64 reg_id;
658 struct rcu_head rcu;
659 };
660
mlx4_en_get_cqe(void * buf,int idx,int cqe_sz)661 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
662 {
663 return buf + idx * cqe_sz;
664 }
665
666 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
667
668 void mlx4_en_init_ptys2ethtool_map(void);
669 void mlx4_en_update_loopback_state(struct net_device *dev,
670 netdev_features_t features);
671
672 void mlx4_en_destroy_netdev(struct net_device *dev);
673 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
674 struct mlx4_en_port_profile *prof);
675
676 int mlx4_en_start_port(struct net_device *dev);
677 void mlx4_en_stop_port(struct net_device *dev, int detach);
678
679 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
680 struct mlx4_en_stats_bitmap *stats_bitmap,
681 u8 rx_ppp, u8 rx_pause,
682 u8 tx_ppp, u8 tx_pause);
683
684 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
685 struct mlx4_en_priv *tmp,
686 struct mlx4_en_port_profile *prof,
687 bool carry_xdp_prog);
688 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
689 struct mlx4_en_priv *tmp);
690
691 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
692 int entries, int ring, enum cq_type mode, int node);
693 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
694 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
695 int cq_idx);
696 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
697 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
698 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
699
700 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
701 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
702 struct net_device *sb_dev,
703 select_queue_fallback_t fallback);
704 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
705 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
706 struct mlx4_en_rx_alloc *frame,
707 struct mlx4_en_priv *priv, unsigned int length,
708 int tx_ind, bool *doorbell_pending);
709 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
710 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
711 struct mlx4_en_rx_alloc *frame);
712
713 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
714 struct mlx4_en_tx_ring **pring,
715 u32 size, u16 stride,
716 int node, int queue_index);
717 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
718 struct mlx4_en_tx_ring **pring);
719 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
720 struct mlx4_en_tx_ring *ring);
721 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
722 struct mlx4_en_tx_ring *ring,
723 int cq, int user_prio);
724 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
725 struct mlx4_en_tx_ring *ring);
726 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
727 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
728 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
729 struct mlx4_en_rx_ring **pring,
730 u32 size, u16 stride, int node, int queue_index);
731 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
732 struct mlx4_en_rx_ring **pring,
733 u32 size, u16 stride);
734 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
735 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
736 struct mlx4_en_rx_ring *ring);
737 int mlx4_en_process_rx_cq(struct net_device *dev,
738 struct mlx4_en_cq *cq,
739 int budget);
740 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
741 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
742 bool mlx4_en_process_tx_cq(struct net_device *dev,
743 struct mlx4_en_cq *cq, int napi_budget);
744 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
745 struct mlx4_en_tx_ring *ring,
746 int index, u64 timestamp,
747 int napi_mode);
748 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
749 struct mlx4_en_tx_ring *ring,
750 int index, u64 timestamp,
751 int napi_mode);
752 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
753 int is_tx, int rss, int qpn, int cqn, int user_prio,
754 struct mlx4_qp_context *context);
755 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
756 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
757 int loopback);
758 void mlx4_en_calc_rx_buf(struct net_device *dev);
759 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
760 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
761 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
762 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
763 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
764 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
765
766 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
767 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
768
769 void mlx4_en_fold_software_stats(struct net_device *dev);
770 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
771 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
772
773 #ifdef CONFIG_MLX4_EN_DCB
774 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
775 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
776 #endif
777
778 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
779 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc);
780
781 #ifdef CONFIG_RFS_ACCEL
782 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
783 #endif
784
785 #define MLX4_EN_NUM_SELF_TEST 5
786 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
787 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
788
789 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
790 ((dev->features & feature) ^ (new_features & feature))
791
792 int mlx4_en_reset_config(struct net_device *dev,
793 struct hwtstamp_config ts_config,
794 netdev_features_t new_features);
795 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
796 struct mlx4_en_stats_bitmap *stats_bitmap,
797 u8 rx_ppp, u8 rx_pause,
798 u8 tx_ppp, u8 tx_pause);
799 int mlx4_en_netdev_event(struct notifier_block *this,
800 unsigned long event, void *ptr);
801
802 /*
803 * Functions for time stamping
804 */
805 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
806 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
807 struct skb_shared_hwtstamps *hwts,
808 u64 timestamp);
809 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
810 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
811
812 /* Globals
813 */
814 extern const struct ethtool_ops mlx4_en_ethtool_ops;
815
816
817
818 /*
819 * printk / logging functions
820 */
821
822 __printf(3, 4)
823 void en_print(const char *level, const struct mlx4_en_priv *priv,
824 const char *format, ...);
825
826 #define en_dbg(mlevel, priv, format, ...) \
827 do { \
828 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
829 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
830 } while (0)
831 #define en_warn(priv, format, ...) \
832 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
833 #define en_err(priv, format, ...) \
834 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
835 #define en_info(priv, format, ...) \
836 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
837
838 #define mlx4_err(mdev, format, ...) \
839 pr_err(DRV_NAME " %s: " format, \
840 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
841 #define mlx4_info(mdev, format, ...) \
842 pr_info(DRV_NAME " %s: " format, \
843 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
844 #define mlx4_warn(mdev, format, ...) \
845 pr_warn(DRV_NAME " %s: " format, \
846 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
847
848 #endif
849
