1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2016 Realtek Corporation.
5 *
6 * Contact Information:
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
9 * Hsinchu 300, Taiwan.
10 *
11 * Larry Finger <Larry.Finger@lwfinger.net>
12 *
13 *****************************************************************************/
14 #include "mp_precomp.h"
15 #include "phydm_precomp.h"
16
phydm_la_buffer_allocate(void * dm_void)17 static bool phydm_la_buffer_allocate(void *dm_void)
18 {
19 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
20 struct rt_adcsmp *adc_smp = &dm->adcsmp;
21 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
22 bool ret = false;
23
24 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "[LA mode BufferAllocate]\n");
25
26 if (adc_smp_buf->length == 0) {
27 odm_allocate_memory(dm, (void **)&adc_smp_buf->octet,
28 adc_smp_buf->buffer_size);
29 if (!adc_smp_buf->octet) {
30 ret = false;
31 } else {
32 adc_smp_buf->length = adc_smp_buf->buffer_size;
33 ret = true;
34 }
35 }
36
37 return ret;
38 }
39
phydm_la_get_tx_pkt_buf(void * dm_void)40 static void phydm_la_get_tx_pkt_buf(void *dm_void)
41 {
42 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
43 struct rt_adcsmp *adc_smp = &dm->adcsmp;
44 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
45 u32 i = 0, value32, data_l = 0, data_h = 0;
46 u32 addr, finish_addr;
47 u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) -
48 1; /*end_addr = 0x3ffff;*/
49 bool is_round_up;
50 static u32 page = 0xFF;
51 u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0;
52
53 odm_memory_set(dm, adc_smp_buf->octet, 0, adc_smp_buf->length);
54 odm_write_1byte(dm, 0x0106, 0x69);
55
56 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "GetTxPktBuf\n");
57
58 value32 = odm_read_4byte(dm, 0x7c0);
59 is_round_up = (bool)((value32 & BIT(31)) >> 31);
60 /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
61 finish_addr = (value32 & 0x7FFF0000) >> 16;
62
63 if (is_round_up) {
64 addr = (finish_addr + 1) << 3;
65 ODM_RT_TRACE(
66 dm, ODM_COMP_UNCOND,
67 "is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n",
68 is_round_up, finish_addr, value32);
69 /*Byte to 64Byte*/
70 smp_number = ((adc_smp_buf->buffer_size) >> 3);
71 } else {
72 addr = adc_smp_buf->start_pos;
73
74 addr_8byte = addr >> 3;
75 if (addr_8byte > finish_addr)
76 smp_number = addr_8byte - finish_addr;
77 else
78 smp_number = finish_addr - addr_8byte;
79
80 ODM_RT_TRACE(
81 dm, ODM_COMP_UNCOND,
82 "is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n",
83 is_round_up, finish_addr, addr_8byte, smp_number);
84 }
85
86 if (dm->support_ic_type & ODM_RTL8197F) {
87 /*64K byte*/
88 for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) {
89 if ((addr & 0xfff) == 0)
90 odm_set_bb_reg(dm, 0x0140, MASKLWORD,
91 0x780 + (addr >> 12));
92 data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
93 MASKDWORD);
94 data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4,
95 MASKDWORD);
96
97 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%08x%08x\n", data_h,
98 data_l);
99 }
100 } else {
101 while (addr != (finish_addr << 3)) {
102 if (page != (addr >> 12)) {
103 /*Reg140=0x780+(addr>>12),
104 *addr=0x30~0x3F, total 16 pages
105 */
106 page = (addr >> 12);
107 }
108 odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + page);
109
110 /*pDataL = 0x8000+(addr&0xfff);*/
111 data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
112 MASKDWORD);
113 data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4,
114 MASKDWORD);
115
116 adc_smp_buf->octet[i] = data_h;
117 adc_smp_buf->octet[i + 1] = data_l;
118
119 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%08x%08x\n", data_h,
120 data_l);
121
122 i = i + 2;
123
124 if ((addr + 8) >= end_addr)
125 addr = adc_smp_buf->start_pos;
126 else
127 addr = addr + 8;
128
129 smp_cnt++;
130 if (smp_cnt >= (smp_number - 1))
131 break;
132 }
133 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "smp_cnt = ((%d))\n",
134 smp_cnt);
135 }
136 }
137
phydm_la_mode_set_mac_iq_dump(void * dm_void)138 static void phydm_la_mode_set_mac_iq_dump(void *dm_void)
139 {
140 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
141 struct rt_adcsmp *adc_smp = &dm->adcsmp;
142 u32 reg_value;
143
144 odm_write_1byte(dm, 0x7c0, 0); /*clear all 0x7c0*/
145 odm_set_mac_reg(dm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/
146
147 if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) {
148 adc_smp->is_bb_trigger = 0;
149 odm_set_mac_reg(dm, 0x7c0, BIT(2),
150 1); /*polling bit for MAC mode*/
151 odm_set_mac_reg(
152 dm, 0x7c0, BIT(4) | BIT(3),
153 adc_smp->la_trigger_edge); /*trigger mode for MAC*/
154
155 ODM_RT_TRACE(
156 dm, ODM_COMP_UNCOND,
157 "[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n",
158 adc_smp->la_mac_ref_mask, adc_smp->la_trig_sig_sel,
159 adc_smp->la_dbg_port);
160 /*[Set MAC Debug Port]*/
161 odm_set_mac_reg(dm, 0xF4, BIT(16), 1);
162 odm_set_mac_reg(dm, 0x38, 0xff0000, adc_smp->la_dbg_port);
163 odm_set_mac_reg(dm, 0x7c4, MASKDWORD, adc_smp->la_mac_ref_mask);
164 odm_set_mac_reg(dm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel);
165
166 } else {
167 adc_smp->is_bb_trigger = 1;
168 odm_set_mac_reg(dm, 0x7c0, BIT(1),
169 1); /*polling bit for BB ADC mode*/
170
171 if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
172 odm_set_mac_reg(
173 dm, 0x7c0, BIT(3),
174 1); /*polling bit for MAC trigger event*/
175 odm_set_mac_reg(dm, 0x7c0, BIT(7) | BIT(6),
176 adc_smp->la_trig_sig_sel);
177
178 if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
179 odm_set_mac_reg(
180 dm, 0x7c0, BIT(5),
181 1); /* manual trigger 0x7C0[5] = 0->1*/
182 }
183 }
184
185 reg_value = odm_get_bb_reg(dm, 0x7c0, 0xff);
186 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
187 "4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value);
188 }
189
phydm_la_mode_set_dma_type(void * dm_void,u8 la_dma_type)190 static void phydm_la_mode_set_dma_type(void *dm_void, u8 la_dma_type)
191 {
192 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
193
194 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
195 "2. [LA mode DMA setting] Dma_type = ((%d))\n",
196 la_dma_type);
197
198 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
199 odm_set_bb_reg(dm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/
200 else
201 odm_set_bb_reg(dm, odm_adc_trigger_jaguar2, 0xf00,
202 la_dma_type); /*0x95C[11:8]*/
203 }
204
phydm_adc_smp_start(void * dm_void)205 static void phydm_adc_smp_start(void *dm_void)
206 {
207 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
208 struct rt_adcsmp *adc_smp = &dm->adcsmp;
209 u8 tmp_u1b;
210 u8 while_cnt = 0;
211 u8 polling_ok = false, target_polling_bit;
212
213 phydm_la_mode_bb_setting(dm);
214 phydm_la_mode_set_dma_type(dm, adc_smp->la_dma_type);
215 phydm_la_mode_set_trigger_time(dm, adc_smp->la_trigger_time);
216
217 if (dm->support_ic_type & ODM_RTL8197F) {
218 odm_set_bb_reg(dm, 0xd00, BIT(26), 0x1);
219 } else { /*for 8814A and 8822B?*/
220 odm_write_1byte(dm, 0x198c, 0x7);
221 odm_write_1byte(dm, 0x8b4, 0x80);
222 /* odm_set_bb_reg(dm, 0x8b4, BIT(7), 1); */
223 }
224
225 phydm_la_mode_set_mac_iq_dump(dm);
226 /* return; */
227
228 target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2);
229 do { /*Poll time always use 100ms, when it exceed 2s, break while loop*/
230 tmp_u1b = odm_read_1byte(dm, 0x7c0);
231
232 if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) {
233 ODM_RT_TRACE(
234 dm, ODM_COMP_UNCOND,
235 "[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
236 break;
237
238 } else if (tmp_u1b & target_polling_bit) {
239 ODM_delay_ms(100);
240 while_cnt = while_cnt + 1;
241 continue;
242 } else {
243 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
244 "[LA Query OK] polling_bit=((0x%x))\n",
245 target_polling_bit);
246 polling_ok = true;
247 if (dm->support_ic_type & ODM_RTL8197F)
248 odm_set_bb_reg(dm, 0x7c0, BIT(0), 0x0);
249 break;
250 }
251 } while (while_cnt < 20);
252
253 if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) {
254 if (polling_ok)
255 phydm_la_get_tx_pkt_buf(dm);
256 else
257 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
258 "[Polling timeout]\n");
259 }
260
261 if (adc_smp->adc_smp_state == ADCSMP_STATE_SET)
262 adc_smp->adc_smp_state = ADCSMP_STATE_QUERY;
263
264 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
265 "[LA mode] LA_pattern_count = ((%d))\n",
266 adc_smp->la_count);
267
268 adc_smp_stop(dm);
269
270 if (adc_smp->la_count == 0) {
271 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
272 "LA Dump finished ---------->\n\n\n");
273 /**/
274 } else {
275 adc_smp->la_count--;
276 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
277 "LA Dump more ---------->\n\n\n");
278 adc_smp_set(dm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel,
279 adc_smp->la_dma_type, adc_smp->la_trigger_time, 0);
280 }
281 }
282
adc_smp_set(void * dm_void,u8 trig_mode,u32 trig_sig_sel,u8 dma_data_sig_sel,u32 trigger_time,u16 polling_time)283 void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
284 u8 dma_data_sig_sel, u32 trigger_time, u16 polling_time)
285 {
286 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
287 bool is_set_success = true;
288 struct rt_adcsmp *adc_smp = &dm->adcsmp;
289
290 adc_smp->la_trig_mode = trig_mode;
291 adc_smp->la_trig_sig_sel = trig_sig_sel;
292 adc_smp->la_dma_type = dma_data_sig_sel;
293 adc_smp->la_trigger_time = trigger_time;
294
295 if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE)
296 is_set_success = false;
297 else if (adc_smp->adc_smp_buf.length == 0)
298 is_set_success = phydm_la_buffer_allocate(dm);
299
300 if (is_set_success) {
301 adc_smp->adc_smp_state = ADCSMP_STATE_SET;
302
303 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
304 "[LA Set Success] LA_State=((%d))\n",
305 adc_smp->adc_smp_state);
306
307 phydm_adc_smp_start(dm);
308 } else {
309 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
310 "[LA Set Fail] LA_State=((%d))\n",
311 adc_smp->adc_smp_state);
312 }
313 }
314
adc_smp_query(void * dm_void,void * output,u32 out_len,u32 * pused)315 void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused)
316 {
317 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
318 struct rt_adcsmp *adc_smp = &dm->adcsmp;
319 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
320 u32 used = *pused;
321 u32 i;
322
323 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%s adc_smp_state %d", __func__,
324 adc_smp->adc_smp_state);
325
326 for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) {
327 PHYDM_SNPRINTF(output + used, out_len - used, "%08x%08x\n",
328 adc_smp_buf->octet[i],
329 adc_smp_buf->octet[i + 1]);
330 }
331
332 PHYDM_SNPRINTF(output + used, out_len - used, "\n");
333 *pused = used;
334 }
335
adc_smp_get_sample_counts(void * dm_void)336 s32 adc_smp_get_sample_counts(void *dm_void)
337 {
338 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
339 struct rt_adcsmp *adc_smp = &dm->adcsmp;
340 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
341
342 return (adc_smp_buf->length >> 2) - 2;
343 }
344
adc_smp_query_single_data(void * dm_void,void * output,u32 out_len,u32 index)345 s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
346 u32 index)
347 {
348 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
349 struct rt_adcsmp *adc_smp = &dm->adcsmp;
350 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
351 u32 used = 0;
352
353 if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
354 PHYDM_SNPRINTF(output + used, out_len - used,
355 "Error: la data is not ready yet ...\n");
356 return -1;
357 }
358
359 if (index < ((adc_smp_buf->length >> 2) - 2)) {
360 PHYDM_SNPRINTF(output + used, out_len - used, "%08x%08x\n",
361 adc_smp_buf->octet[index],
362 adc_smp_buf->octet[index + 1]);
363 }
364 return 0;
365 }
366
adc_smp_stop(void * dm_void)367 void adc_smp_stop(void *dm_void)
368 {
369 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
370 struct rt_adcsmp *adc_smp = &dm->adcsmp;
371
372 adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
373 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "[LA_Stop] LA_state = ((%d))\n",
374 adc_smp->adc_smp_state);
375 }
376
adc_smp_init(void * dm_void)377 void adc_smp_init(void *dm_void)
378 {
379 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
380 struct rt_adcsmp *adc_smp = &dm->adcsmp;
381 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
382
383 adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
384
385 if (dm->support_ic_type & ODM_RTL8814A) {
386 adc_smp_buf->start_pos = 0x30000;
387 adc_smp_buf->buffer_size = 0x10000;
388 } else if (dm->support_ic_type & ODM_RTL8822B) {
389 adc_smp_buf->start_pos = 0x20000;
390 adc_smp_buf->buffer_size = 0x20000;
391 } else if (dm->support_ic_type & ODM_RTL8197F) {
392 adc_smp_buf->start_pos = 0x00000;
393 adc_smp_buf->buffer_size = 0x10000;
394 } else if (dm->support_ic_type & ODM_RTL8821C) {
395 adc_smp_buf->start_pos = 0x8000;
396 adc_smp_buf->buffer_size = 0x8000;
397 }
398 }
399
adc_smp_de_init(void * dm_void)400 void adc_smp_de_init(void *dm_void)
401 {
402 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
403 struct rt_adcsmp *adc_smp = &dm->adcsmp;
404 struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
405
406 adc_smp_stop(dm);
407
408 if (adc_smp_buf->length != 0x0) {
409 odm_free_memory(dm, adc_smp_buf->octet, adc_smp_buf->length);
410 adc_smp_buf->length = 0x0;
411 }
412 }
413
phydm_la_mode_bb_setting(void * dm_void)414 void phydm_la_mode_bb_setting(void *dm_void)
415 {
416 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
417 struct rt_adcsmp *adc_smp = &dm->adcsmp;
418
419 u8 trig_mode = adc_smp->la_trig_mode;
420 u32 trig_sig_sel = adc_smp->la_trig_sig_sel;
421 u32 dbg_port = adc_smp->la_dbg_port;
422 u8 is_trigger_edge = adc_smp->la_trigger_edge;
423 u8 sampling_rate = adc_smp->la_smp_rate;
424
425 ODM_RT_TRACE(
426 dm, ODM_COMP_UNCOND,
427 "1. [LA mode bb_setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n",
428 trig_mode, dbg_port, is_trigger_edge, sampling_rate,
429 trig_sig_sel);
430
431 if (trig_mode == PHYDM_MAC_TRIG)
432 trig_sig_sel = 0; /*ignore this setting*/
433
434 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
435 if (trig_mode == PHYDM_ADC_RF0_TRIG) {
436 /*DBGOUT_RFC_a[31:0]*/
437 odm_set_bb_reg(dm, 0x8f8,
438 BIT(25) | BIT(24) | BIT(23) | BIT(22),
439 9);
440 } else if (trig_mode == PHYDM_ADC_RF1_TRIG) {
441 /*DBGOUT_RFC_b[31:0]*/
442 odm_set_bb_reg(dm, 0x8f8,
443 BIT(25) | BIT(24) | BIT(23) | BIT(22),
444 8);
445 } else {
446 odm_set_bb_reg(dm, 0x8f8,
447 BIT(25) | BIT(24) | BIT(23) | BIT(22),
448 0);
449 }
450 /*
451 * (0:) '{ofdm_dbg[31:0]}'
452 * (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}'
453 * (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}'
454 * (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}'
455 * (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}'
456 * (5:) '{dbg_iqk_anta}'
457 * (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}'
458 * (7:) '{dbg_iqk_antb}'
459 * (8:) '{DBGOUT_RFC_b[31:0]}'
460 * (9:) '{DBGOUT_RFC_a[31:0]}'
461 * (a:) '{dbg_ofdm}'
462 * (b:) '{dbg_cck}'
463 */
464
465 /*disable dbg clk gating*/
466 odm_set_bb_reg(dm, 0x198C, BIT(2) | BIT(1) | BIT(0), 7);
467
468 /*0x95C[4:0], BB debug port bit*/
469 odm_set_bb_reg(dm, 0x95C, 0x1f, trig_sig_sel);
470 odm_set_bb_reg(dm, 0x8FC, MASKDWORD, dbg_port);
471 /*0: posedge, 1: negedge*/
472 odm_set_bb_reg(dm, 0x95C, BIT(31), is_trigger_edge);
473 odm_set_bb_reg(dm, 0x95c, 0xe0, sampling_rate);
474 /* (0:) '80MHz'
475 * (1:) '40MHz'
476 * (2:) '20MHz'
477 * (3:) '10MHz'
478 * (4:) '5MHz'
479 * (5:) '2.5MHz'
480 * (6:) '1.25MHz'
481 * (7:) '160MHz (for BW160 ic)'
482 */
483 } else {
484 /*0x9A0[4:0], BB debug port bit*/
485 odm_set_bb_reg(dm, 0x9a0, 0x1f, trig_sig_sel);
486 odm_set_bb_reg(dm, 0x908, MASKDWORD, dbg_port);
487 /*0: posedge, 1: negedge*/
488 odm_set_bb_reg(dm, 0x9A0, BIT(31), is_trigger_edge);
489 odm_set_bb_reg(dm, 0x9A0, 0xe0, sampling_rate);
490 /* (0:) '80MHz'
491 * (1:) '40MHz'
492 * (2:) '20MHz'
493 * (3:) '10MHz'
494 * (4:) '5MHz'
495 * (5:) '2.5MHz'
496 * (6:) '1.25MHz'
497 * (7:) '160MHz (for BW160 ic)'
498 */
499 }
500 }
501
phydm_la_mode_set_trigger_time(void * dm_void,u32 trigger_time_mu_sec)502 void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
503 {
504 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
505 u8 trigger_time_unit_num;
506 u32 time_unit = 0;
507
508 if (trigger_time_mu_sec < 128)
509 time_unit = 0; /*unit: 1mu sec*/
510 else if (trigger_time_mu_sec < 256)
511 time_unit = 1; /*unit: 2mu sec*/
512 else if (trigger_time_mu_sec < 512)
513 time_unit = 2; /*unit: 4mu sec*/
514 else if (trigger_time_mu_sec < 1024)
515 time_unit = 3; /*unit: 8mu sec*/
516 else if (trigger_time_mu_sec < 2048)
517 time_unit = 4; /*unit: 16mu sec*/
518 else if (trigger_time_mu_sec < 4096)
519 time_unit = 5; /*unit: 32mu sec*/
520 else if (trigger_time_mu_sec < 8192)
521 time_unit = 6; /*unit: 64mu sec*/
522
523 trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit);
524
525 ODM_RT_TRACE(
526 dm, ODM_COMP_UNCOND,
527 "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
528 trigger_time_unit_num, time_unit);
529
530 odm_set_mac_reg(dm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit);
531 odm_set_mac_reg(dm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f));
532 }
533
phydm_lamode_trigger_setting(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len,u32 input_num)534 void phydm_lamode_trigger_setting(void *dm_void, char input[][16], u32 *_used,
535 char *output, u32 *_out_len, u32 input_num)
536 {
537 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
538 struct rt_adcsmp *adc_smp = &dm->adcsmp;
539 u8 trig_mode, dma_data_sig_sel;
540 u32 trig_sig_sel;
541 bool is_enable_la_mode;
542 u32 trigger_time_mu_sec;
543 char help[] = "-h";
544 u32 var1[10] = {0};
545 u32 used = *_used;
546 u32 out_len = *_out_len;
547
548 if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
549 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
550 is_enable_la_mode = (bool)var1[0];
551 /*dbg_print("echo cmd input_num = %d\n", input_num);*/
552
553 if ((strcmp(input[1], help) == 0)) {
554 PHYDM_SNPRINTF(
555 output + used, out_len - used,
556 "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC}\n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime}\n {polling_time/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n");
557 /**/
558 } else if ((is_enable_la_mode == 1)) {
559 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
560
561 trig_mode = (u8)var1[1];
562
563 if (trig_mode == PHYDM_MAC_TRIG)
564 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
565 else
566 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
567 trig_sig_sel = var1[2];
568
569 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
570 PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
571 PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
572 PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
573 PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
574 PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
575 PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
576
577 dma_data_sig_sel = (u8)var1[3];
578 trigger_time_mu_sec = var1[4]; /*unit: us*/
579
580 adc_smp->la_mac_ref_mask = var1[5];
581 adc_smp->la_dbg_port = var1[6];
582 adc_smp->la_trigger_edge = (u8)var1[7];
583 adc_smp->la_smp_rate = (u8)(var1[8] & 0x7);
584 adc_smp->la_count = var1[9];
585
586 ODM_RT_TRACE(
587 dm, ODM_COMP_UNCOND,
588 "echo lamode %d %d %d %d %d %d %x %d %d %d\n",
589 var1[0], var1[1], var1[2], var1[3], var1[4],
590 var1[5], var1[6], var1[7], var1[8], var1[9]);
591
592 PHYDM_SNPRINTF(
593 output + used, out_len - used,
594 "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
595 trig_mode, trig_sig_sel, dma_data_sig_sel);
596 PHYDM_SNPRINTF(
597 output + used, out_len - used,
598 "e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
599 trigger_time_mu_sec, adc_smp->la_mac_ref_mask,
600 adc_smp->la_dbg_port);
601 PHYDM_SNPRINTF(
602 output + used, out_len - used,
603 "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
604 adc_smp->la_trigger_edge,
605 (80 >> adc_smp->la_smp_rate),
606 adc_smp->la_count);
607
608 adc_smp_set(dm, trig_mode, trig_sig_sel,
609 dma_data_sig_sel, trigger_time_mu_sec, 0);
610
611 } else {
612 adc_smp_stop(dm);
613 PHYDM_SNPRINTF(output + used, out_len - used,
614 "Disable LA mode\n");
615 }
616 }
617 }
618
