1 /*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/types.h>
16 #include <linux/init.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/mtd/physmap.h>
20 #include <linux/mtd/plat-ram.h>
21 #include <linux/memory.h>
22 #include <linux/gpio.h>
23 #include <linux/smsc911x.h>
24 #include <linux/interrupt.h>
25 #include <linux/i2c.h>
26 #include <linux/property.h>
27 #include <linux/delay.h>
28 #include <linux/spi/spi.h>
29 #include <linux/irq.h>
30 #include <linux/can/platform/sja1000.h>
31 #include <linux/usb/otg.h>
32 #include <linux/usb/ulpi.h>
33 #include <linux/gfp.h>
34 #include <linux/regulator/machine.h>
35 #include <linux/regulator/fixed.h>
36
37 #include <asm/mach-types.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/time.h>
40 #include <asm/mach/map.h>
41
42 #include "common.h"
43 #include "devices-imx31.h"
44 #include "ehci.h"
45 #include "hardware.h"
46 #include "iomux-mx3.h"
47 #include "pcm037.h"
48 #include "ulpi.h"
49
50 static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
51
pcm037_variant_setup(char * str)52 static int __init pcm037_variant_setup(char *str)
53 {
54 if (!strcmp("eet", str))
55 pcm037_instance = PCM037_EET;
56 else if (strcmp("pcm970", str))
57 pr_warn("Unknown pcm037 baseboard variant %s\n", str);
58
59 return 1;
60 }
61
62 /* Supported values: "pcm970" (default) and "eet" */
63 __setup("pcm037_variant=", pcm037_variant_setup);
64
pcm037_variant(void)65 enum pcm037_board_variant pcm037_variant(void)
66 {
67 return pcm037_instance;
68 }
69
70 /* UART1 with RTS/CTS handshake signals */
71 static unsigned int pcm037_uart1_handshake_pins[] = {
72 MX31_PIN_CTS1__CTS1,
73 MX31_PIN_RTS1__RTS1,
74 MX31_PIN_TXD1__TXD1,
75 MX31_PIN_RXD1__RXD1,
76 };
77
78 /* UART1 without RTS/CTS handshake signals */
79 static unsigned int pcm037_uart1_pins[] = {
80 MX31_PIN_TXD1__TXD1,
81 MX31_PIN_RXD1__RXD1,
82 };
83
84 static unsigned int pcm037_pins[] = {
85 /* I2C */
86 MX31_PIN_CSPI2_MOSI__SCL,
87 MX31_PIN_CSPI2_MISO__SDA,
88 MX31_PIN_CSPI2_SS2__I2C3_SDA,
89 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
90 /* SDHC1 */
91 MX31_PIN_SD1_DATA3__SD1_DATA3,
92 MX31_PIN_SD1_DATA2__SD1_DATA2,
93 MX31_PIN_SD1_DATA1__SD1_DATA1,
94 MX31_PIN_SD1_DATA0__SD1_DATA0,
95 MX31_PIN_SD1_CLK__SD1_CLK,
96 MX31_PIN_SD1_CMD__SD1_CMD,
97 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
98 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
99 /* SPI1 */
100 MX31_PIN_CSPI1_MOSI__MOSI,
101 MX31_PIN_CSPI1_MISO__MISO,
102 MX31_PIN_CSPI1_SCLK__SCLK,
103 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
104 MX31_PIN_CSPI1_SS0__SS0,
105 MX31_PIN_CSPI1_SS1__SS1,
106 MX31_PIN_CSPI1_SS2__SS2,
107 /* UART2 */
108 MX31_PIN_TXD2__TXD2,
109 MX31_PIN_RXD2__RXD2,
110 MX31_PIN_CTS2__CTS2,
111 MX31_PIN_RTS2__RTS2,
112 /* UART3 */
113 MX31_PIN_CSPI3_MOSI__RXD3,
114 MX31_PIN_CSPI3_MISO__TXD3,
115 MX31_PIN_CSPI3_SCLK__RTS3,
116 MX31_PIN_CSPI3_SPI_RDY__CTS3,
117 /* LAN9217 irq pin */
118 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
119 /* Onewire */
120 MX31_PIN_BATT_LINE__OWIRE,
121 /* Framebuffer */
122 MX31_PIN_LD0__LD0,
123 MX31_PIN_LD1__LD1,
124 MX31_PIN_LD2__LD2,
125 MX31_PIN_LD3__LD3,
126 MX31_PIN_LD4__LD4,
127 MX31_PIN_LD5__LD5,
128 MX31_PIN_LD6__LD6,
129 MX31_PIN_LD7__LD7,
130 MX31_PIN_LD8__LD8,
131 MX31_PIN_LD9__LD9,
132 MX31_PIN_LD10__LD10,
133 MX31_PIN_LD11__LD11,
134 MX31_PIN_LD12__LD12,
135 MX31_PIN_LD13__LD13,
136 MX31_PIN_LD14__LD14,
137 MX31_PIN_LD15__LD15,
138 MX31_PIN_LD16__LD16,
139 MX31_PIN_LD17__LD17,
140 MX31_PIN_VSYNC3__VSYNC3,
141 MX31_PIN_HSYNC__HSYNC,
142 MX31_PIN_FPSHIFT__FPSHIFT,
143 MX31_PIN_DRDY0__DRDY0,
144 MX31_PIN_D3_REV__D3_REV,
145 MX31_PIN_CONTRAST__CONTRAST,
146 MX31_PIN_D3_SPL__D3_SPL,
147 MX31_PIN_D3_CLS__D3_CLS,
148 MX31_PIN_LCS0__GPIO3_23,
149 /* GPIO */
150 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
151 /* OTG */
152 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
153 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
154 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
155 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
156 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
157 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
158 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
159 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
160 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
161 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
162 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
163 MX31_PIN_USBOTG_STP__USBOTG_STP,
164 /* USB host 2 */
165 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
166 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
167 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
168 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
169 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
170 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
171 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
172 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
173 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
174 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
175 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
176 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
177 };
178
179 static struct physmap_flash_data pcm037_flash_data = {
180 .width = 2,
181 };
182
183 static struct resource pcm037_flash_resource = {
184 .start = 0xa0000000,
185 .end = 0xa1ffffff,
186 .flags = IORESOURCE_MEM,
187 };
188
189 static struct platform_device pcm037_flash = {
190 .name = "physmap-flash",
191 .id = 0,
192 .dev = {
193 .platform_data = &pcm037_flash_data,
194 },
195 .resource = &pcm037_flash_resource,
196 .num_resources = 1,
197 };
198
199 static const struct imxuart_platform_data uart_pdata __initconst = {
200 .flags = IMXUART_HAVE_RTSCTS,
201 };
202
203 static struct resource smsc911x_resources[] = {
204 {
205 .start = MX31_CS1_BASE_ADDR + 0x300,
206 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
207 .flags = IORESOURCE_MEM,
208 }, {
209 /* irq number is run-time assigned */
210 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
211 },
212 };
213
214 static struct smsc911x_platform_config smsc911x_info = {
215 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
216 SMSC911X_SAVE_MAC_ADDRESS,
217 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
218 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
219 .phy_interface = PHY_INTERFACE_MODE_MII,
220 };
221
222 static struct platform_device pcm037_eth = {
223 .name = "smsc911x",
224 .id = -1,
225 .num_resources = ARRAY_SIZE(smsc911x_resources),
226 .resource = smsc911x_resources,
227 .dev = {
228 .platform_data = &smsc911x_info,
229 },
230 };
231
232 static struct platdata_mtd_ram pcm038_sram_data = {
233 .bankwidth = 2,
234 };
235
236 static struct resource pcm038_sram_resource = {
237 .start = MX31_CS4_BASE_ADDR,
238 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
239 .flags = IORESOURCE_MEM,
240 };
241
242 static struct platform_device pcm037_sram_device = {
243 .name = "mtd-ram",
244 .id = 0,
245 .dev = {
246 .platform_data = &pcm038_sram_data,
247 },
248 .num_resources = 1,
249 .resource = &pcm038_sram_resource,
250 };
251
252 static const struct mxc_nand_platform_data
253 pcm037_nand_board_info __initconst = {
254 .width = 1,
255 .hw_ecc = 1,
256 };
257
258 static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
259 .bitrate = 100000,
260 };
261
262 static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
263 .bitrate = 20000,
264 };
265
266 static const struct property_entry board_eeprom_properties[] = {
267 PROPERTY_ENTRY_U32("pagesize", 32),
268 { }
269 };
270
271 static struct i2c_board_info pcm037_i2c_devices[] = {
272 {
273 I2C_BOARD_INFO("24c32", 0x52), /* E0=0, E1=1, E2=0 */
274 .properties = board_eeprom_properties,
275 }, {
276 I2C_BOARD_INFO("pcf8563", 0x51),
277 }
278 };
279
280 /* Not connected by default */
281 #ifdef PCM970_SDHC_RW_SWITCH
pcm970_sdhc1_get_ro(struct device * dev)282 static int pcm970_sdhc1_get_ro(struct device *dev)
283 {
284 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
285 }
286 #endif
287
288 #define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
289 #define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
290
pcm970_sdhc1_init(struct device * dev,irq_handler_t detect_irq,void * data)291 static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
292 void *data)
293 {
294 int ret;
295
296 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
297 if (ret)
298 return ret;
299
300 gpio_direction_input(SDHC1_GPIO_DET);
301
302 #ifdef PCM970_SDHC_RW_SWITCH
303 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
304 if (ret)
305 goto err_gpio_free;
306 gpio_direction_input(SDHC1_GPIO_WP);
307 #endif
308
309 ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
310 IRQF_TRIGGER_FALLING, "sdhc-detect", data);
311 if (ret)
312 goto err_gpio_free_2;
313
314 return 0;
315
316 err_gpio_free_2:
317 #ifdef PCM970_SDHC_RW_SWITCH
318 gpio_free(SDHC1_GPIO_WP);
319 err_gpio_free:
320 #endif
321 gpio_free(SDHC1_GPIO_DET);
322
323 return ret;
324 }
325
pcm970_sdhc1_exit(struct device * dev,void * data)326 static void pcm970_sdhc1_exit(struct device *dev, void *data)
327 {
328 free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
329 gpio_free(SDHC1_GPIO_DET);
330 gpio_free(SDHC1_GPIO_WP);
331 }
332
333 static const struct imxmmc_platform_data sdhc_pdata __initconst = {
334 #ifdef PCM970_SDHC_RW_SWITCH
335 .get_ro = pcm970_sdhc1_get_ro,
336 #endif
337 .init = pcm970_sdhc1_init,
338 .exit = pcm970_sdhc1_exit,
339 };
340
341 static struct platform_device *devices[] __initdata = {
342 &pcm037_flash,
343 &pcm037_sram_device,
344 };
345
346 static const struct fb_videomode fb_modedb[] = {
347 {
348 /* 240x320 @ 60 Hz Sharp */
349 .name = "Sharp-LQ035Q7DH06-QVGA",
350 .refresh = 60,
351 .xres = 240,
352 .yres = 320,
353 .pixclock = 185925,
354 .left_margin = 9,
355 .right_margin = 16,
356 .upper_margin = 7,
357 .lower_margin = 9,
358 .hsync_len = 1,
359 .vsync_len = 1,
360 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
361 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
362 .vmode = FB_VMODE_NONINTERLACED,
363 .flag = 0,
364 }, {
365 /* 240x320 @ 60 Hz */
366 .name = "TX090",
367 .refresh = 60,
368 .xres = 240,
369 .yres = 320,
370 .pixclock = 38255,
371 .left_margin = 144,
372 .right_margin = 0,
373 .upper_margin = 7,
374 .lower_margin = 40,
375 .hsync_len = 96,
376 .vsync_len = 1,
377 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
378 .vmode = FB_VMODE_NONINTERLACED,
379 .flag = 0,
380 }, {
381 /* 240x320 @ 60 Hz */
382 .name = "CMEL-OLED",
383 .refresh = 60,
384 .xres = 240,
385 .yres = 320,
386 .pixclock = 185925,
387 .left_margin = 9,
388 .right_margin = 16,
389 .upper_margin = 7,
390 .lower_margin = 9,
391 .hsync_len = 1,
392 .vsync_len = 1,
393 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
394 .vmode = FB_VMODE_NONINTERLACED,
395 .flag = 0,
396 },
397 };
398
399 static struct mx3fb_platform_data mx3fb_pdata = {
400 .name = "Sharp-LQ035Q7DH06-QVGA",
401 .mode = fb_modedb,
402 .num_modes = ARRAY_SIZE(fb_modedb),
403 };
404
405 static struct resource pcm970_sja1000_resources[] = {
406 {
407 .start = MX31_CS5_BASE_ADDR,
408 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
409 .flags = IORESOURCE_MEM,
410 }, {
411 /* irq number is run-time assigned */
412 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
413 },
414 };
415
416 struct sja1000_platform_data pcm970_sja1000_platform_data = {
417 .osc_freq = 16000000,
418 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
419 .cdr = CDR_CBP,
420 };
421
422 static struct platform_device pcm970_sja1000 = {
423 .name = "sja1000_platform",
424 .dev = {
425 .platform_data = &pcm970_sja1000_platform_data,
426 },
427 .resource = pcm970_sja1000_resources,
428 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
429 };
430
pcm037_otg_init(struct platform_device * pdev)431 static int pcm037_otg_init(struct platform_device *pdev)
432 {
433 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
434 }
435
436 static struct mxc_usbh_platform_data otg_pdata __initdata = {
437 .init = pcm037_otg_init,
438 .portsc = MXC_EHCI_MODE_ULPI,
439 };
440
pcm037_usbh2_init(struct platform_device * pdev)441 static int pcm037_usbh2_init(struct platform_device *pdev)
442 {
443 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
444 }
445
446 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
447 .init = pcm037_usbh2_init,
448 .portsc = MXC_EHCI_MODE_ULPI,
449 };
450
451 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
452 .operating_mode = FSL_USB2_DR_DEVICE,
453 .phy_mode = FSL_USB2_PHY_ULPI,
454 };
455
456 static bool otg_mode_host __initdata;
457
pcm037_otg_mode(char * options)458 static int __init pcm037_otg_mode(char *options)
459 {
460 if (!strcmp(options, "host"))
461 otg_mode_host = true;
462 else if (!strcmp(options, "device"))
463 otg_mode_host = false;
464 else
465 pr_info("otg_mode neither \"host\" nor \"device\". "
466 "Defaulting to device\n");
467 return 1;
468 }
469 __setup("otg_mode=", pcm037_otg_mode);
470
471 static struct regulator_consumer_supply dummy_supplies[] = {
472 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
473 REGULATOR_SUPPLY("vddvario", "smsc911x"),
474 };
475
476 /*
477 * Board specific initialization.
478 */
pcm037_init(void)479 static void __init pcm037_init(void)
480 {
481 imx31_soc_init();
482
483 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
484
485 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
486
487 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
488 "pcm037");
489
490 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
491 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
492
493 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
494 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
495 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
496 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
497 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
498 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
499 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
500 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
501 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
502 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
503 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
504 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
505
506 if (pcm037_variant() == PCM037_EET)
507 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
508 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
509 else
510 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
511 ARRAY_SIZE(pcm037_uart1_handshake_pins),
512 "pcm037_uart1");
513
514 platform_add_devices(devices, ARRAY_SIZE(devices));
515
516 imx31_add_imx2_wdt();
517 imx31_add_imx_uart0(&uart_pdata);
518 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
519 imx31_add_imx_uart1(&uart_pdata);
520 imx31_add_imx_uart2(&uart_pdata);
521
522 imx31_add_mxc_w1();
523
524 /* I2C adapters and devices */
525 i2c_register_board_info(1, pcm037_i2c_devices,
526 ARRAY_SIZE(pcm037_i2c_devices));
527
528 imx31_add_imx_i2c1(&pcm037_i2c1_data);
529 imx31_add_imx_i2c2(&pcm037_i2c2_data);
530
531 imx31_add_mxc_nand(&pcm037_nand_board_info);
532 imx31_add_ipu_core();
533 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
534
535 if (otg_mode_host) {
536 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
537 ULPI_OTG_DRVVBUS_EXT);
538 if (otg_pdata.otg)
539 imx31_add_mxc_ehci_otg(&otg_pdata);
540 }
541
542 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
543 ULPI_OTG_DRVVBUS_EXT);
544 if (usbh2_pdata.otg)
545 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
546
547 if (!otg_mode_host)
548 imx31_add_fsl_usb2_udc(&otg_device_pdata);
549 }
550
pcm037_timer_init(void)551 static void __init pcm037_timer_init(void)
552 {
553 mx31_clocks_init(26000000);
554 }
555
pcm037_init_late(void)556 static void __init pcm037_init_late(void)
557 {
558 int ret;
559
560 /* LAN9217 IRQ pin */
561 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
562 if (!ret) {
563 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
564 smsc911x_resources[1].start =
565 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
566 smsc911x_resources[1].end =
567 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
568 platform_device_register(&pcm037_eth);
569 } else {
570 pr_warn("could not get LAN irq gpio\n");
571 }
572
573 imx31_add_mxc_mmc(0, &sdhc_pdata);
574
575 pcm970_sja1000_resources[1].start =
576 gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
577 pcm970_sja1000_resources[1].end =
578 gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
579 platform_device_register(&pcm970_sja1000);
580
581 pcm037_eet_init_devices();
582 }
583
584 MACHINE_START(PCM037, "Phytec Phycore pcm037")
585 /* Maintainer: Pengutronix */
586 .atag_offset = 0x100,
587 .map_io = mx31_map_io,
588 .init_early = imx31_init_early,
589 .init_irq = mx31_init_irq,
590 .init_time = pcm037_timer_init,
591 .init_machine = pcm037_init,
592 .init_late = pcm037_init_late,
593 .restart = mxc_restart,
594 MACHINE_END
595
