1 // SPDX-License-Identifier: GPL-2.0
2 /* pci.c: UltraSparc PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 *
8 * OF tree based PCI bus probing taken from the PowerPC port
9 * with minor modifications, see there for credits.
10 */
11
12 #include <linux/export.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/sched.h>
16 #include <linux/capability.h>
17 #include <linux/errno.h>
18 #include <linux/pci.h>
19 #include <linux/msi.h>
20 #include <linux/irq.h>
21 #include <linux/init.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24
25 #include <linux/uaccess.h>
26 #include <asm/pgtable.h>
27 #include <asm/irq.h>
28 #include <asm/prom.h>
29 #include <asm/apb.h>
30
31 #include "pci_impl.h"
32 #include "kernel.h"
33
34 /* List of all PCI controllers found in the system. */
35 struct pci_pbm_info *pci_pbm_root = NULL;
36
37 /* Each PBM found gets a unique index. */
38 int pci_num_pbms = 0;
39
40 volatile int pci_poke_in_progress;
41 volatile int pci_poke_cpu = -1;
42 volatile int pci_poke_faulted;
43
44 static DEFINE_SPINLOCK(pci_poke_lock);
45
pci_config_read8(u8 * addr,u8 * ret)46 void pci_config_read8(u8 *addr, u8 *ret)
47 {
48 unsigned long flags;
49 u8 byte;
50
51 spin_lock_irqsave(&pci_poke_lock, flags);
52 pci_poke_cpu = smp_processor_id();
53 pci_poke_in_progress = 1;
54 pci_poke_faulted = 0;
55 __asm__ __volatile__("membar #Sync\n\t"
56 "lduba [%1] %2, %0\n\t"
57 "membar #Sync"
58 : "=r" (byte)
59 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
60 : "memory");
61 pci_poke_in_progress = 0;
62 pci_poke_cpu = -1;
63 if (!pci_poke_faulted)
64 *ret = byte;
65 spin_unlock_irqrestore(&pci_poke_lock, flags);
66 }
67
pci_config_read16(u16 * addr,u16 * ret)68 void pci_config_read16(u16 *addr, u16 *ret)
69 {
70 unsigned long flags;
71 u16 word;
72
73 spin_lock_irqsave(&pci_poke_lock, flags);
74 pci_poke_cpu = smp_processor_id();
75 pci_poke_in_progress = 1;
76 pci_poke_faulted = 0;
77 __asm__ __volatile__("membar #Sync\n\t"
78 "lduha [%1] %2, %0\n\t"
79 "membar #Sync"
80 : "=r" (word)
81 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
82 : "memory");
83 pci_poke_in_progress = 0;
84 pci_poke_cpu = -1;
85 if (!pci_poke_faulted)
86 *ret = word;
87 spin_unlock_irqrestore(&pci_poke_lock, flags);
88 }
89
pci_config_read32(u32 * addr,u32 * ret)90 void pci_config_read32(u32 *addr, u32 *ret)
91 {
92 unsigned long flags;
93 u32 dword;
94
95 spin_lock_irqsave(&pci_poke_lock, flags);
96 pci_poke_cpu = smp_processor_id();
97 pci_poke_in_progress = 1;
98 pci_poke_faulted = 0;
99 __asm__ __volatile__("membar #Sync\n\t"
100 "lduwa [%1] %2, %0\n\t"
101 "membar #Sync"
102 : "=r" (dword)
103 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
104 : "memory");
105 pci_poke_in_progress = 0;
106 pci_poke_cpu = -1;
107 if (!pci_poke_faulted)
108 *ret = dword;
109 spin_unlock_irqrestore(&pci_poke_lock, flags);
110 }
111
pci_config_write8(u8 * addr,u8 val)112 void pci_config_write8(u8 *addr, u8 val)
113 {
114 unsigned long flags;
115
116 spin_lock_irqsave(&pci_poke_lock, flags);
117 pci_poke_cpu = smp_processor_id();
118 pci_poke_in_progress = 1;
119 pci_poke_faulted = 0;
120 __asm__ __volatile__("membar #Sync\n\t"
121 "stba %0, [%1] %2\n\t"
122 "membar #Sync"
123 : /* no outputs */
124 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
125 : "memory");
126 pci_poke_in_progress = 0;
127 pci_poke_cpu = -1;
128 spin_unlock_irqrestore(&pci_poke_lock, flags);
129 }
130
pci_config_write16(u16 * addr,u16 val)131 void pci_config_write16(u16 *addr, u16 val)
132 {
133 unsigned long flags;
134
135 spin_lock_irqsave(&pci_poke_lock, flags);
136 pci_poke_cpu = smp_processor_id();
137 pci_poke_in_progress = 1;
138 pci_poke_faulted = 0;
139 __asm__ __volatile__("membar #Sync\n\t"
140 "stha %0, [%1] %2\n\t"
141 "membar #Sync"
142 : /* no outputs */
143 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
144 : "memory");
145 pci_poke_in_progress = 0;
146 pci_poke_cpu = -1;
147 spin_unlock_irqrestore(&pci_poke_lock, flags);
148 }
149
pci_config_write32(u32 * addr,u32 val)150 void pci_config_write32(u32 *addr, u32 val)
151 {
152 unsigned long flags;
153
154 spin_lock_irqsave(&pci_poke_lock, flags);
155 pci_poke_cpu = smp_processor_id();
156 pci_poke_in_progress = 1;
157 pci_poke_faulted = 0;
158 __asm__ __volatile__("membar #Sync\n\t"
159 "stwa %0, [%1] %2\n\t"
160 "membar #Sync"
161 : /* no outputs */
162 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
163 : "memory");
164 pci_poke_in_progress = 0;
165 pci_poke_cpu = -1;
166 spin_unlock_irqrestore(&pci_poke_lock, flags);
167 }
168
169 static int ofpci_verbose;
170
ofpci_debug(char * str)171 static int __init ofpci_debug(char *str)
172 {
173 int val = 0;
174
175 get_option(&str, &val);
176 if (val)
177 ofpci_verbose = 1;
178 return 1;
179 }
180
181 __setup("ofpci_debug=", ofpci_debug);
182
pci_parse_of_flags(u32 addr0)183 static unsigned long pci_parse_of_flags(u32 addr0)
184 {
185 unsigned long flags = 0;
186
187 if (addr0 & 0x02000000) {
188 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
189 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
190 if (addr0 & 0x01000000)
191 flags |= IORESOURCE_MEM_64
192 | PCI_BASE_ADDRESS_MEM_TYPE_64;
193 if (addr0 & 0x40000000)
194 flags |= IORESOURCE_PREFETCH
195 | PCI_BASE_ADDRESS_MEM_PREFETCH;
196 } else if (addr0 & 0x01000000)
197 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
198 return flags;
199 }
200
201 /* The of_device layer has translated all of the assigned-address properties
202 * into physical address resources, we only have to figure out the register
203 * mapping.
204 */
pci_parse_of_addrs(struct platform_device * op,struct device_node * node,struct pci_dev * dev)205 static void pci_parse_of_addrs(struct platform_device *op,
206 struct device_node *node,
207 struct pci_dev *dev)
208 {
209 struct resource *op_res;
210 const u32 *addrs;
211 int proplen;
212
213 addrs = of_get_property(node, "assigned-addresses", &proplen);
214 if (!addrs)
215 return;
216 if (ofpci_verbose)
217 pci_info(dev, " parse addresses (%d bytes) @ %p\n",
218 proplen, addrs);
219 op_res = &op->resource[0];
220 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
221 struct resource *res;
222 unsigned long flags;
223 int i;
224
225 flags = pci_parse_of_flags(addrs[0]);
226 if (!flags)
227 continue;
228 i = addrs[0] & 0xff;
229 if (ofpci_verbose)
230 pci_info(dev, " start: %llx, end: %llx, i: %x\n",
231 op_res->start, op_res->end, i);
232
233 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
234 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
235 } else if (i == dev->rom_base_reg) {
236 res = &dev->resource[PCI_ROM_RESOURCE];
237 flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
238 } else {
239 pci_err(dev, "bad cfg reg num 0x%x\n", i);
240 continue;
241 }
242 res->start = op_res->start;
243 res->end = op_res->end;
244 res->flags = flags;
245 res->name = pci_name(dev);
246
247 pci_info(dev, "reg 0x%x: %pR\n", i, res);
248 }
249 }
250
pci_init_dev_archdata(struct dev_archdata * sd,void * iommu,void * stc,void * host_controller,struct platform_device * op,int numa_node)251 static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
252 void *stc, void *host_controller,
253 struct platform_device *op,
254 int numa_node)
255 {
256 sd->iommu = iommu;
257 sd->stc = stc;
258 sd->host_controller = host_controller;
259 sd->op = op;
260 sd->numa_node = numa_node;
261 }
262
of_create_pci_dev(struct pci_pbm_info * pbm,struct device_node * node,struct pci_bus * bus,int devfn)263 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
264 struct device_node *node,
265 struct pci_bus *bus, int devfn)
266 {
267 struct dev_archdata *sd;
268 struct platform_device *op;
269 struct pci_dev *dev;
270 const char *type;
271 u32 class;
272
273 dev = pci_alloc_dev(bus);
274 if (!dev)
275 return NULL;
276
277 op = of_find_device_by_node(node);
278 sd = &dev->dev.archdata;
279 pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
280 pbm->numa_node);
281 sd = &op->dev.archdata;
282 sd->iommu = pbm->iommu;
283 sd->stc = &pbm->stc;
284 sd->numa_node = pbm->numa_node;
285
286 if (!strcmp(node->name, "ebus"))
287 of_propagate_archdata(op);
288
289 type = of_get_property(node, "device_type", NULL);
290 if (type == NULL)
291 type = "";
292
293 if (ofpci_verbose)
294 pci_info(bus," create device, devfn: %x, type: %s\n",
295 devfn, type);
296
297 dev->sysdata = node;
298 dev->dev.parent = bus->bridge;
299 dev->dev.bus = &pci_bus_type;
300 dev->dev.of_node = of_node_get(node);
301 dev->devfn = devfn;
302 dev->multifunction = 0; /* maybe a lie? */
303 set_pcie_port_type(dev);
304
305 pci_dev_assign_slot(dev);
306 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
307 dev->device = of_getintprop_default(node, "device-id", 0xffff);
308 dev->subsystem_vendor =
309 of_getintprop_default(node, "subsystem-vendor-id", 0);
310 dev->subsystem_device =
311 of_getintprop_default(node, "subsystem-id", 0);
312
313 dev->cfg_size = pci_cfg_space_size(dev);
314
315 /* We can't actually use the firmware value, we have
316 * to read what is in the register right now. One
317 * reason is that in the case of IDE interfaces the
318 * firmware can sample the value before the the IDE
319 * interface is programmed into native mode.
320 */
321 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
322 dev->class = class >> 8;
323 dev->revision = class & 0xff;
324
325 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
326 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
327
328 /* I have seen IDE devices which will not respond to
329 * the bmdma simplex check reads if bus mastering is
330 * disabled.
331 */
332 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
333 pci_set_master(dev);
334
335 dev->current_state = PCI_UNKNOWN; /* unknown power state */
336 dev->error_state = pci_channel_io_normal;
337 dev->dma_mask = 0xffffffff;
338
339 if (!strcmp(node->name, "pci")) {
340 /* a PCI-PCI bridge */
341 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
342 dev->rom_base_reg = PCI_ROM_ADDRESS1;
343 } else if (!strcmp(type, "cardbus")) {
344 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
345 } else {
346 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
347 dev->rom_base_reg = PCI_ROM_ADDRESS;
348
349 dev->irq = sd->op->archdata.irqs[0];
350 if (dev->irq == 0xffffffff)
351 dev->irq = PCI_IRQ_NONE;
352 }
353
354 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
355 dev->vendor, dev->device, dev->hdr_type, dev->class);
356
357 pci_parse_of_addrs(sd->op, node, dev);
358
359 if (ofpci_verbose)
360 pci_info(dev, " adding to system ...\n");
361
362 pci_device_add(dev, bus);
363
364 return dev;
365 }
366
apb_calc_first_last(u8 map,u32 * first_p,u32 * last_p)367 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
368 {
369 u32 idx, first, last;
370
371 first = 8;
372 last = 0;
373 for (idx = 0; idx < 8; idx++) {
374 if ((map & (1 << idx)) != 0) {
375 if (first > idx)
376 first = idx;
377 if (last < idx)
378 last = idx;
379 }
380 }
381
382 *first_p = first;
383 *last_p = last;
384 }
385
386 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
387 * a proper 'ranges' property.
388 */
apb_fake_ranges(struct pci_dev * dev,struct pci_bus * bus,struct pci_pbm_info * pbm)389 static void apb_fake_ranges(struct pci_dev *dev,
390 struct pci_bus *bus,
391 struct pci_pbm_info *pbm)
392 {
393 struct pci_bus_region region;
394 struct resource *res;
395 u32 first, last;
396 u8 map;
397
398 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
399 apb_calc_first_last(map, &first, &last);
400 res = bus->resource[0];
401 res->flags = IORESOURCE_IO;
402 region.start = (first << 21);
403 region.end = (last << 21) + ((1 << 21) - 1);
404 pcibios_bus_to_resource(dev->bus, res, ®ion);
405
406 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
407 apb_calc_first_last(map, &first, &last);
408 res = bus->resource[1];
409 res->flags = IORESOURCE_MEM;
410 region.start = (first << 29);
411 region.end = (last << 29) + ((1 << 29) - 1);
412 pcibios_bus_to_resource(dev->bus, res, ®ion);
413 }
414
415 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
416 struct device_node *node,
417 struct pci_bus *bus);
418
419 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
420
of_scan_pci_bridge(struct pci_pbm_info * pbm,struct device_node * node,struct pci_dev * dev)421 static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
422 struct device_node *node,
423 struct pci_dev *dev)
424 {
425 struct pci_bus *bus;
426 const u32 *busrange, *ranges;
427 int len, i, simba;
428 struct pci_bus_region region;
429 struct resource *res;
430 unsigned int flags;
431 u64 size;
432
433 if (ofpci_verbose)
434 pci_info(dev, "of_scan_pci_bridge(%s)\n", node->full_name);
435
436 /* parse bus-range property */
437 busrange = of_get_property(node, "bus-range", &len);
438 if (busrange == NULL || len != 8) {
439 pci_info(dev, "Can't get bus-range for PCI-PCI bridge %s\n",
440 node->full_name);
441 return;
442 }
443
444 if (ofpci_verbose)
445 pci_info(dev, " Bridge bus range [%u --> %u]\n",
446 busrange[0], busrange[1]);
447
448 ranges = of_get_property(node, "ranges", &len);
449 simba = 0;
450 if (ranges == NULL) {
451 const char *model = of_get_property(node, "model", NULL);
452 if (model && !strcmp(model, "SUNW,simba"))
453 simba = 1;
454 }
455
456 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
457 if (!bus) {
458 pci_err(dev, "Failed to create pci bus for %s\n",
459 node->full_name);
460 return;
461 }
462
463 bus->primary = dev->bus->number;
464 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
465 bus->bridge_ctl = 0;
466
467 if (ofpci_verbose)
468 pci_info(dev, " Bridge ranges[%p] simba[%d]\n",
469 ranges, simba);
470
471 /* parse ranges property, or cook one up by hand for Simba */
472 /* PCI #address-cells == 3 and #size-cells == 2 always */
473 res = &dev->resource[PCI_BRIDGE_RESOURCES];
474 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
475 res->flags = 0;
476 bus->resource[i] = res;
477 ++res;
478 }
479 if (simba) {
480 apb_fake_ranges(dev, bus, pbm);
481 goto after_ranges;
482 } else if (ranges == NULL) {
483 pci_read_bridge_bases(bus);
484 goto after_ranges;
485 }
486 i = 1;
487 for (; len >= 32; len -= 32, ranges += 8) {
488 u64 start;
489
490 if (ofpci_verbose)
491 pci_info(dev, " RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
492 "%08x:%08x]\n",
493 ranges[0], ranges[1], ranges[2], ranges[3],
494 ranges[4], ranges[5], ranges[6], ranges[7]);
495
496 flags = pci_parse_of_flags(ranges[0]);
497 size = GET_64BIT(ranges, 6);
498 if (flags == 0 || size == 0)
499 continue;
500
501 /* On PCI-Express systems, PCI bridges that have no devices downstream
502 * have a bogus size value where the first 32-bit cell is 0xffffffff.
503 * This results in a bogus range where start + size overflows.
504 *
505 * Just skip these otherwise the kernel will complain when the resource
506 * tries to be claimed.
507 */
508 if (size >> 32 == 0xffffffff)
509 continue;
510
511 if (flags & IORESOURCE_IO) {
512 res = bus->resource[0];
513 if (res->flags) {
514 pci_err(dev, "ignoring extra I/O range"
515 " for bridge %s\n", node->full_name);
516 continue;
517 }
518 } else {
519 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
520 pci_err(dev, "too many memory ranges"
521 " for bridge %s\n", node->full_name);
522 continue;
523 }
524 res = bus->resource[i];
525 ++i;
526 }
527
528 res->flags = flags;
529 region.start = start = GET_64BIT(ranges, 1);
530 region.end = region.start + size - 1;
531
532 if (ofpci_verbose)
533 pci_info(dev, " Using flags[%08x] start[%016llx] size[%016llx]\n",
534 flags, start, size);
535
536 pcibios_bus_to_resource(dev->bus, res, ®ion);
537 }
538 after_ranges:
539 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
540 bus->number);
541 if (ofpci_verbose)
542 pci_info(dev, " bus name: %s\n", bus->name);
543
544 pci_of_scan_bus(pbm, node, bus);
545 }
546
pci_of_scan_bus(struct pci_pbm_info * pbm,struct device_node * node,struct pci_bus * bus)547 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
548 struct device_node *node,
549 struct pci_bus *bus)
550 {
551 struct device_node *child;
552 const u32 *reg;
553 int reglen, devfn, prev_devfn;
554 struct pci_dev *dev;
555
556 if (ofpci_verbose)
557 pci_info(bus, "scan_bus[%s] bus no %d\n",
558 node->full_name, bus->number);
559
560 child = NULL;
561 prev_devfn = -1;
562 while ((child = of_get_next_child(node, child)) != NULL) {
563 if (ofpci_verbose)
564 pci_info(bus, " * %s\n", child->full_name);
565 reg = of_get_property(child, "reg", ®len);
566 if (reg == NULL || reglen < 20)
567 continue;
568
569 devfn = (reg[0] >> 8) & 0xff;
570
571 /* This is a workaround for some device trees
572 * which list PCI devices twice. On the V100
573 * for example, device number 3 is listed twice.
574 * Once as "pm" and once again as "lomp".
575 */
576 if (devfn == prev_devfn)
577 continue;
578 prev_devfn = devfn;
579
580 /* create a new pci_dev for this device */
581 dev = of_create_pci_dev(pbm, child, bus, devfn);
582 if (!dev)
583 continue;
584 if (ofpci_verbose)
585 pci_info(dev, "dev header type: %x\n", dev->hdr_type);
586
587 if (pci_is_bridge(dev))
588 of_scan_pci_bridge(pbm, child, dev);
589 }
590 }
591
592 static ssize_t
show_pciobppath_attr(struct device * dev,struct device_attribute * attr,char * buf)593 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
594 {
595 struct pci_dev *pdev;
596 struct device_node *dp;
597
598 pdev = to_pci_dev(dev);
599 dp = pdev->dev.of_node;
600
601 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
602 }
603
604 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
605
pci_bus_register_of_sysfs(struct pci_bus * bus)606 static void pci_bus_register_of_sysfs(struct pci_bus *bus)
607 {
608 struct pci_dev *dev;
609 struct pci_bus *child_bus;
610 int err;
611
612 list_for_each_entry(dev, &bus->devices, bus_list) {
613 /* we don't really care if we can create this file or
614 * not, but we need to assign the result of the call
615 * or the world will fall under alien invasion and
616 * everybody will be frozen on a spaceship ready to be
617 * eaten on alpha centauri by some green and jelly
618 * humanoid.
619 */
620 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
621 (void) err;
622 }
623 list_for_each_entry(child_bus, &bus->children, node)
624 pci_bus_register_of_sysfs(child_bus);
625 }
626
pci_claim_legacy_resources(struct pci_dev * dev)627 static void pci_claim_legacy_resources(struct pci_dev *dev)
628 {
629 struct pci_bus_region region;
630 struct resource *p, *root, *conflict;
631
632 if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
633 return;
634
635 p = kzalloc(sizeof(*p), GFP_KERNEL);
636 if (!p)
637 return;
638
639 p->name = "Video RAM area";
640 p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
641
642 region.start = 0xa0000UL;
643 region.end = region.start + 0x1ffffUL;
644 pcibios_bus_to_resource(dev->bus, p, ®ion);
645
646 root = pci_find_parent_resource(dev, p);
647 if (!root) {
648 pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p);
649 goto err;
650 }
651
652 conflict = request_resource_conflict(root, p);
653 if (conflict) {
654 pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n",
655 p, conflict->name, conflict);
656 goto err;
657 }
658
659 pci_info(dev, "VGA legacy framebuffer %pR\n", p);
660 return;
661
662 err:
663 kfree(p);
664 }
665
pci_claim_bus_resources(struct pci_bus * bus)666 static void pci_claim_bus_resources(struct pci_bus *bus)
667 {
668 struct pci_bus *child_bus;
669 struct pci_dev *dev;
670
671 list_for_each_entry(dev, &bus->devices, bus_list) {
672 int i;
673
674 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
675 struct resource *r = &dev->resource[i];
676
677 if (r->parent || !r->start || !r->flags)
678 continue;
679
680 if (ofpci_verbose)
681 pci_info(dev, "Claiming Resource %d: %pR\n",
682 i, r);
683
684 pci_claim_resource(dev, i);
685 }
686
687 pci_claim_legacy_resources(dev);
688 }
689
690 list_for_each_entry(child_bus, &bus->children, node)
691 pci_claim_bus_resources(child_bus);
692 }
693
pci_scan_one_pbm(struct pci_pbm_info * pbm,struct device * parent)694 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
695 struct device *parent)
696 {
697 LIST_HEAD(resources);
698 struct device_node *node = pbm->op->dev.of_node;
699 struct pci_bus *bus;
700
701 printk("PCI: Scanning PBM %s\n", node->full_name);
702
703 pci_add_resource_offset(&resources, &pbm->io_space,
704 pbm->io_offset);
705 pci_add_resource_offset(&resources, &pbm->mem_space,
706 pbm->mem_offset);
707 if (pbm->mem64_space.flags)
708 pci_add_resource_offset(&resources, &pbm->mem64_space,
709 pbm->mem64_offset);
710 pbm->busn.start = pbm->pci_first_busno;
711 pbm->busn.end = pbm->pci_last_busno;
712 pbm->busn.flags = IORESOURCE_BUS;
713 pci_add_resource(&resources, &pbm->busn);
714 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
715 pbm, &resources);
716 if (!bus) {
717 printk(KERN_ERR "Failed to create bus for %s\n",
718 node->full_name);
719 pci_free_resource_list(&resources);
720 return NULL;
721 }
722
723 pci_of_scan_bus(pbm, node, bus);
724 pci_bus_register_of_sysfs(bus);
725
726 pci_claim_bus_resources(bus);
727
728 pci_bus_add_devices(bus);
729 return bus;
730 }
731
pcibios_enable_device(struct pci_dev * dev,int mask)732 int pcibios_enable_device(struct pci_dev *dev, int mask)
733 {
734 u16 cmd, oldcmd;
735 int i;
736
737 pci_read_config_word(dev, PCI_COMMAND, &cmd);
738 oldcmd = cmd;
739
740 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
741 struct resource *res = &dev->resource[i];
742
743 /* Only set up the requested stuff */
744 if (!(mask & (1<<i)))
745 continue;
746
747 if (res->flags & IORESOURCE_IO)
748 cmd |= PCI_COMMAND_IO;
749 if (res->flags & IORESOURCE_MEM)
750 cmd |= PCI_COMMAND_MEMORY;
751 }
752
753 if (cmd != oldcmd) {
754 pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
755 pci_write_config_word(dev, PCI_COMMAND, cmd);
756 }
757 return 0;
758 }
759
760 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
761
762 /* If the user uses a host-bridge as the PCI device, he may use
763 * this to perform a raw mmap() of the I/O or MEM space behind
764 * that controller.
765 *
766 * This can be useful for execution of x86 PCI bios initialization code
767 * on a PCI card, like the xfree86 int10 stuff does.
768 */
__pci_mmap_make_offset_bus(struct pci_dev * pdev,struct vm_area_struct * vma,enum pci_mmap_state mmap_state)769 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
770 enum pci_mmap_state mmap_state)
771 {
772 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
773 unsigned long space_size, user_offset, user_size;
774
775 if (mmap_state == pci_mmap_io) {
776 space_size = resource_size(&pbm->io_space);
777 } else {
778 space_size = resource_size(&pbm->mem_space);
779 }
780
781 /* Make sure the request is in range. */
782 user_offset = vma->vm_pgoff << PAGE_SHIFT;
783 user_size = vma->vm_end - vma->vm_start;
784
785 if (user_offset >= space_size ||
786 (user_offset + user_size) > space_size)
787 return -EINVAL;
788
789 if (mmap_state == pci_mmap_io) {
790 vma->vm_pgoff = (pbm->io_space.start +
791 user_offset) >> PAGE_SHIFT;
792 } else {
793 vma->vm_pgoff = (pbm->mem_space.start +
794 user_offset) >> PAGE_SHIFT;
795 }
796
797 return 0;
798 }
799
800 /* Adjust vm_pgoff of VMA such that it is the physical page offset
801 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
802 *
803 * Basically, the user finds the base address for his device which he wishes
804 * to mmap. They read the 32-bit value from the config space base register,
805 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
806 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
807 *
808 * Returns negative error code on failure, zero on success.
809 */
__pci_mmap_make_offset(struct pci_dev * pdev,struct vm_area_struct * vma,enum pci_mmap_state mmap_state)810 static int __pci_mmap_make_offset(struct pci_dev *pdev,
811 struct vm_area_struct *vma,
812 enum pci_mmap_state mmap_state)
813 {
814 unsigned long user_paddr, user_size;
815 int i, err;
816
817 /* First compute the physical address in vma->vm_pgoff,
818 * making sure the user offset is within range in the
819 * appropriate PCI space.
820 */
821 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
822 if (err)
823 return err;
824
825 /* If this is a mapping on a host bridge, any address
826 * is OK.
827 */
828 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
829 return err;
830
831 /* Otherwise make sure it's in the range for one of the
832 * device's resources.
833 */
834 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
835 user_size = vma->vm_end - vma->vm_start;
836
837 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
838 struct resource *rp = &pdev->resource[i];
839 resource_size_t aligned_end;
840
841 /* Active? */
842 if (!rp->flags)
843 continue;
844
845 /* Same type? */
846 if (i == PCI_ROM_RESOURCE) {
847 if (mmap_state != pci_mmap_mem)
848 continue;
849 } else {
850 if ((mmap_state == pci_mmap_io &&
851 (rp->flags & IORESOURCE_IO) == 0) ||
852 (mmap_state == pci_mmap_mem &&
853 (rp->flags & IORESOURCE_MEM) == 0))
854 continue;
855 }
856
857 /* Align the resource end to the next page address.
858 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
859 * because actually we need the address of the next byte
860 * after rp->end.
861 */
862 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
863
864 if ((rp->start <= user_paddr) &&
865 (user_paddr + user_size) <= aligned_end)
866 break;
867 }
868
869 if (i > PCI_ROM_RESOURCE)
870 return -EINVAL;
871
872 return 0;
873 }
874
875 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
876 * device mapping.
877 */
__pci_mmap_set_pgprot(struct pci_dev * dev,struct vm_area_struct * vma,enum pci_mmap_state mmap_state)878 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
879 enum pci_mmap_state mmap_state)
880 {
881 /* Our io_remap_pfn_range takes care of this, do nothing. */
882 }
883
884 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
885 * for this architecture. The region in the process to map is described by vm_start
886 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
887 * The pci device structure is provided so that architectures may make mapping
888 * decisions on a per-device or per-bus basis.
889 *
890 * Returns a negative error code on failure, zero on success.
891 */
pci_mmap_page_range(struct pci_dev * dev,int bar,struct vm_area_struct * vma,enum pci_mmap_state mmap_state,int write_combine)892 int pci_mmap_page_range(struct pci_dev *dev, int bar,
893 struct vm_area_struct *vma,
894 enum pci_mmap_state mmap_state, int write_combine)
895 {
896 int ret;
897
898 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
899 if (ret < 0)
900 return ret;
901
902 __pci_mmap_set_pgprot(dev, vma, mmap_state);
903
904 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
905 ret = io_remap_pfn_range(vma, vma->vm_start,
906 vma->vm_pgoff,
907 vma->vm_end - vma->vm_start,
908 vma->vm_page_prot);
909 if (ret)
910 return ret;
911
912 return 0;
913 }
914
915 #ifdef CONFIG_NUMA
pcibus_to_node(struct pci_bus * pbus)916 int pcibus_to_node(struct pci_bus *pbus)
917 {
918 struct pci_pbm_info *pbm = pbus->sysdata;
919
920 return pbm->numa_node;
921 }
922 EXPORT_SYMBOL(pcibus_to_node);
923 #endif
924
925 /* Return the domain number for this pci bus */
926
pci_domain_nr(struct pci_bus * pbus)927 int pci_domain_nr(struct pci_bus *pbus)
928 {
929 struct pci_pbm_info *pbm = pbus->sysdata;
930 int ret;
931
932 if (!pbm) {
933 ret = -ENXIO;
934 } else {
935 ret = pbm->index;
936 }
937
938 return ret;
939 }
940 EXPORT_SYMBOL(pci_domain_nr);
941
942 #ifdef CONFIG_PCI_MSI
arch_setup_msi_irq(struct pci_dev * pdev,struct msi_desc * desc)943 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
944 {
945 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
946 unsigned int irq;
947
948 if (!pbm->setup_msi_irq)
949 return -EINVAL;
950
951 return pbm->setup_msi_irq(&irq, pdev, desc);
952 }
953
arch_teardown_msi_irq(unsigned int irq)954 void arch_teardown_msi_irq(unsigned int irq)
955 {
956 struct msi_desc *entry = irq_get_msi_desc(irq);
957 struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
958 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
959
960 if (pbm->teardown_msi_irq)
961 pbm->teardown_msi_irq(irq, pdev);
962 }
963 #endif /* !(CONFIG_PCI_MSI) */
964
ali_sound_dma_hack(struct pci_dev * pdev,int set_bit)965 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
966 {
967 struct pci_dev *ali_isa_bridge;
968 u8 val;
969
970 /* ALI sound chips generate 31-bits of DMA, a special register
971 * determines what bit 31 is emitted as.
972 */
973 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
974 PCI_DEVICE_ID_AL_M1533,
975 NULL);
976
977 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
978 if (set_bit)
979 val |= 0x01;
980 else
981 val &= ~0x01;
982 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
983 pci_dev_put(ali_isa_bridge);
984 }
985
pci64_dma_supported(struct pci_dev * pdev,u64 device_mask)986 int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
987 {
988 u64 dma_addr_mask;
989
990 if (pdev == NULL) {
991 dma_addr_mask = 0xffffffff;
992 } else {
993 struct iommu *iommu = pdev->dev.archdata.iommu;
994
995 dma_addr_mask = iommu->dma_addr_mask;
996
997 if (pdev->vendor == PCI_VENDOR_ID_AL &&
998 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
999 device_mask == 0x7fffffff) {
1000 ali_sound_dma_hack(pdev,
1001 (dma_addr_mask & 0x80000000) != 0);
1002 return 1;
1003 }
1004 }
1005
1006 if (device_mask >= (1UL << 32UL))
1007 return 0;
1008
1009 return (device_mask & dma_addr_mask) == dma_addr_mask;
1010 }
1011
pci_resource_to_user(const struct pci_dev * pdev,int bar,const struct resource * rp,resource_size_t * start,resource_size_t * end)1012 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
1013 const struct resource *rp, resource_size_t *start,
1014 resource_size_t *end)
1015 {
1016 struct pci_bus_region region;
1017
1018 /*
1019 * "User" addresses are shown in /sys/devices/pci.../.../resource
1020 * and /proc/bus/pci/devices and used as mmap offsets for
1021 * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
1022 *
1023 * On sparc, these are PCI bus addresses, i.e., raw BAR values.
1024 */
1025 pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp);
1026 *start = region.start;
1027 *end = region.end;
1028 }
1029
pcibios_set_master(struct pci_dev * dev)1030 void pcibios_set_master(struct pci_dev *dev)
1031 {
1032 /* No special bus mastering setup handling */
1033 }
1034
1035 #ifdef CONFIG_PCI_IOV
pcibios_add_device(struct pci_dev * dev)1036 int pcibios_add_device(struct pci_dev *dev)
1037 {
1038 struct pci_dev *pdev;
1039
1040 /* Add sriov arch specific initialization here.
1041 * Copy dev_archdata from PF to VF
1042 */
1043 if (dev->is_virtfn) {
1044 struct dev_archdata *psd;
1045
1046 pdev = dev->physfn;
1047 psd = &pdev->dev.archdata;
1048 pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
1049 psd->stc, psd->host_controller, NULL,
1050 psd->numa_node);
1051 }
1052 return 0;
1053 }
1054 #endif /* CONFIG_PCI_IOV */
1055
pcibios_init(void)1056 static int __init pcibios_init(void)
1057 {
1058 pci_dfl_cache_line_size = 64 >> 2;
1059 return 0;
1060 }
1061 subsys_initcall(pcibios_init);
1062
1063 #ifdef CONFIG_SYSFS
1064
1065 #define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */
1066
pcie_bus_slot_names(struct pci_bus * pbus)1067 static void pcie_bus_slot_names(struct pci_bus *pbus)
1068 {
1069 struct pci_dev *pdev;
1070 struct pci_bus *bus;
1071
1072 list_for_each_entry(pdev, &pbus->devices, bus_list) {
1073 char name[SLOT_NAME_SIZE];
1074 struct pci_slot *pci_slot;
1075 const u32 *slot_num;
1076 int len;
1077
1078 slot_num = of_get_property(pdev->dev.of_node,
1079 "physical-slot#", &len);
1080
1081 if (slot_num == NULL || len != 4)
1082 continue;
1083
1084 snprintf(name, sizeof(name), "%u", slot_num[0]);
1085 pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
1086
1087 if (IS_ERR(pci_slot))
1088 pr_err("PCI: pci_create_slot returned %ld.\n",
1089 PTR_ERR(pci_slot));
1090 }
1091
1092 list_for_each_entry(bus, &pbus->children, node)
1093 pcie_bus_slot_names(bus);
1094 }
1095
pci_bus_slot_names(struct device_node * node,struct pci_bus * bus)1096 static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
1097 {
1098 const struct pci_slot_names {
1099 u32 slot_mask;
1100 char names[0];
1101 } *prop;
1102 const char *sp;
1103 int len, i;
1104 u32 mask;
1105
1106 prop = of_get_property(node, "slot-names", &len);
1107 if (!prop)
1108 return;
1109
1110 mask = prop->slot_mask;
1111 sp = prop->names;
1112
1113 if (ofpci_verbose)
1114 pci_info(bus, "Making slots for [%s] mask[0x%02x]\n",
1115 node->full_name, mask);
1116
1117 i = 0;
1118 while (mask) {
1119 struct pci_slot *pci_slot;
1120 u32 this_bit = 1 << i;
1121
1122 if (!(mask & this_bit)) {
1123 i++;
1124 continue;
1125 }
1126
1127 if (ofpci_verbose)
1128 pci_info(bus, "Making slot [%s]\n", sp);
1129
1130 pci_slot = pci_create_slot(bus, i, sp, NULL);
1131 if (IS_ERR(pci_slot))
1132 pci_err(bus, "pci_create_slot returned %ld\n",
1133 PTR_ERR(pci_slot));
1134
1135 sp += strlen(sp) + 1;
1136 mask &= ~this_bit;
1137 i++;
1138 }
1139 }
1140
of_pci_slot_init(void)1141 static int __init of_pci_slot_init(void)
1142 {
1143 struct pci_bus *pbus = NULL;
1144
1145 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
1146 struct device_node *node;
1147 struct pci_dev *pdev;
1148
1149 pdev = list_first_entry(&pbus->devices, struct pci_dev,
1150 bus_list);
1151
1152 if (pdev && pci_is_pcie(pdev)) {
1153 pcie_bus_slot_names(pbus);
1154 } else {
1155
1156 if (pbus->self) {
1157
1158 /* PCI->PCI bridge */
1159 node = pbus->self->dev.of_node;
1160
1161 } else {
1162 struct pci_pbm_info *pbm = pbus->sysdata;
1163
1164 /* Host PCI controller */
1165 node = pbm->op->dev.of_node;
1166 }
1167
1168 pci_bus_slot_names(node, pbus);
1169 }
1170 }
1171
1172 return 0;
1173 }
1174 device_initcall(of_pci_slot_init);
1175 #endif
1176
