1 /*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #ifndef __TEGRA_CLK_H
18 #define __TEGRA_CLK_H
19
20 #include <linux/clk-provider.h>
21 #include <linux/clkdev.h>
22 #include <linux/delay.h>
23
24 /**
25 * struct tegra_clk_sync_source - external clock source from codec
26 *
27 * @hw: handle between common and hardware-specific interfaces
28 * @rate: input frequency from source
29 * @max_rate: max rate allowed
30 */
31 struct tegra_clk_sync_source {
32 struct clk_hw hw;
33 unsigned long rate;
34 unsigned long max_rate;
35 };
36
37 #define to_clk_sync_source(_hw) \
38 container_of(_hw, struct tegra_clk_sync_source, hw)
39
40 extern const struct clk_ops tegra_clk_sync_source_ops;
41 extern int *periph_clk_enb_refcnt;
42
43 struct clk *tegra_clk_register_sync_source(const char *name,
44 unsigned long fixed_rate, unsigned long max_rate);
45
46 /**
47 * struct tegra_clk_frac_div - fractional divider clock
48 *
49 * @hw: handle between common and hardware-specific interfaces
50 * @reg: register containing divider
51 * @flags: hardware-specific flags
52 * @shift: shift to the divider bit field
53 * @width: width of the divider bit field
54 * @frac_width: width of the fractional bit field
55 * @lock: register lock
56 *
57 * Flags:
58 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
59 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
60 * flag indicates that this divider is for fixed rate PLL.
61 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
62 * fraction bit is set. This flags indicates to calculate divider for which
63 * fracton bit will be zero.
64 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
65 * set when divider value is not 0. This flags indicates that the divider
66 * is for UART module.
67 */
68 struct tegra_clk_frac_div {
69 struct clk_hw hw;
70 void __iomem *reg;
71 u8 flags;
72 u8 shift;
73 u8 width;
74 u8 frac_width;
75 spinlock_t *lock;
76 };
77
78 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
79
80 #define TEGRA_DIVIDER_ROUND_UP BIT(0)
81 #define TEGRA_DIVIDER_FIXED BIT(1)
82 #define TEGRA_DIVIDER_INT BIT(2)
83 #define TEGRA_DIVIDER_UART BIT(3)
84
85 extern const struct clk_ops tegra_clk_frac_div_ops;
86 struct clk *tegra_clk_register_divider(const char *name,
87 const char *parent_name, void __iomem *reg,
88 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
89 u8 frac_width, spinlock_t *lock);
90 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
91 void __iomem *reg, spinlock_t *lock);
92
93 /*
94 * Tegra PLL:
95 *
96 * In general, there are 3 requirements for each PLL
97 * that SW needs to be comply with.
98 * (1) Input frequency range (REF).
99 * (2) Comparison frequency range (CF). CF = REF/DIVM.
100 * (3) VCO frequency range (VCO). VCO = CF * DIVN.
101 *
102 * The final PLL output frequency (FO) = VCO >> DIVP.
103 */
104
105 /**
106 * struct tegra_clk_pll_freq_table - PLL frequecy table
107 *
108 * @input_rate: input rate from source
109 * @output_rate: output rate from PLL for the input rate
110 * @n: feedback divider
111 * @m: input divider
112 * @p: post divider
113 * @cpcon: charge pump current
114 * @sdm_data: fraction divider setting (0 = disabled)
115 */
116 struct tegra_clk_pll_freq_table {
117 unsigned long input_rate;
118 unsigned long output_rate;
119 u32 n;
120 u32 m;
121 u8 p;
122 u8 cpcon;
123 u16 sdm_data;
124 };
125
126 /**
127 * struct pdiv_map - map post divider to hw value
128 *
129 * @pdiv: post divider
130 * @hw_val: value to be written to the PLL hw
131 */
132 struct pdiv_map {
133 u8 pdiv;
134 u8 hw_val;
135 };
136
137 /**
138 * struct div_nmp - offset and width of m,n and p fields
139 *
140 * @divn_shift: shift to the feedback divider bit field
141 * @divn_width: width of the feedback divider bit field
142 * @divm_shift: shift to the input divider bit field
143 * @divm_width: width of the input divider bit field
144 * @divp_shift: shift to the post divider bit field
145 * @divp_width: width of the post divider bit field
146 * @override_divn_shift: shift to the feedback divider bitfield in override reg
147 * @override_divm_shift: shift to the input divider bitfield in override reg
148 * @override_divp_shift: shift to the post divider bitfield in override reg
149 */
150 struct div_nmp {
151 u8 divn_shift;
152 u8 divn_width;
153 u8 divm_shift;
154 u8 divm_width;
155 u8 divp_shift;
156 u8 divp_width;
157 u8 override_divn_shift;
158 u8 override_divm_shift;
159 u8 override_divp_shift;
160 };
161
162 #define MAX_PLL_MISC_REG_COUNT 6
163
164 struct tegra_clk_pll;
165
166 /**
167 * struct tegra_clk_pll_params - PLL parameters
168 *
169 * @input_min: Minimum input frequency
170 * @input_max: Maximum input frequency
171 * @cf_min: Minimum comparison frequency
172 * @cf_max: Maximum comparison frequency
173 * @vco_min: Minimum VCO frequency
174 * @vco_max: Maximum VCO frequency
175 * @base_reg: PLL base reg offset
176 * @misc_reg: PLL misc reg offset
177 * @lock_reg: PLL lock reg offset
178 * @lock_mask: Bitmask for PLL lock status
179 * @lock_enable_bit_idx: Bit index to enable PLL lock
180 * @iddq_reg: PLL IDDQ register offset
181 * @iddq_bit_idx: Bit index to enable PLL IDDQ
182 * @reset_reg: Register offset of where RESET bit is
183 * @reset_bit_idx: Shift of reset bit in reset_reg
184 * @sdm_din_reg: Register offset where SDM settings are
185 * @sdm_din_mask: Mask of SDM divider bits
186 * @sdm_ctrl_reg: Register offset where SDM enable is
187 * @sdm_ctrl_en_mask: Mask of SDM enable bit
188 * @ssc_ctrl_reg: Register offset where SSC settings are
189 * @ssc_ctrl_en_mask: Mask of SSC enable bit
190 * @aux_reg: AUX register offset
191 * @dyn_ramp_reg: Dynamic ramp control register offset
192 * @ext_misc_reg: Miscellaneous control register offsets
193 * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM)
194 * @pmc_divp_reg: p divider PMC override register offset (PLLM)
195 * @flags: PLL flags
196 * @stepa_shift: Dynamic ramp step A field shift
197 * @stepb_shift: Dynamic ramp step B field shift
198 * @lock_delay: Delay in us if PLL lock is not used
199 * @max_p: maximum value for the p divider
200 * @defaults_set: Boolean signaling all reg defaults for PLL set.
201 * @pdiv_tohw: mapping of p divider to register values
202 * @div_nmp: offsets and widths on n, m and p fields
203 * @freq_table: array of frequencies supported by PLL
204 * @fixed_rate: PLL rate if it is fixed
205 * @mdiv_default: Default value for fixed mdiv for this PLL
206 * @round_p_to_pdiv: Callback used to round p to the closed pdiv
207 * @set_gain: Callback to adjust N div for SDM enabled
208 * PLL's based on fractional divider value.
209 * @calc_rate: Callback used to change how out of table
210 * rates (dividers and multipler) are calculated.
211 * @adjust_vco: Callback to adjust the programming range of the
212 * divider range (if SDM is present)
213 * @set_defaults: Callback which will try to initialize PLL
214 * registers to sane default values. This is first
215 * tried during PLL registration, but if the PLL
216 * is already enabled, it will be done the first
217 * time the rate is changed while the PLL is
218 * disabled.
219 * @dyn_ramp: Callback which can be used to define a custom
220 * dynamic ramp function for a given PLL.
221 *
222 * Flags:
223 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
224 * PLL locking. If not set it will use lock_delay value to wait.
225 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
226 * to be programmed to change output frequency of the PLL.
227 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
228 * to be programmed to change output frequency of the PLL.
229 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
230 * to be programmed to change output frequency of the PLL.
231 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
232 * that it is PLLU and invert post divider value.
233 * TEGRA_PLLM - PLLM has additional override settings in PMC. This
234 * flag indicates that it is PLLM and use override settings.
235 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
236 * of some plls.
237 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
238 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
239 * base register.
240 * TEGRA_PLL_BYPASS - PLL has bypass bit
241 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
242 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
243 * it may be more accurate (especially if SDM present)
244 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
245 * flag indicated that it is PLLMB.
246 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
247 */
248 struct tegra_clk_pll_params {
249 unsigned long input_min;
250 unsigned long input_max;
251 unsigned long cf_min;
252 unsigned long cf_max;
253 unsigned long vco_min;
254 unsigned long vco_max;
255
256 u32 base_reg;
257 u32 misc_reg;
258 u32 lock_reg;
259 u32 lock_mask;
260 u32 lock_enable_bit_idx;
261 u32 iddq_reg;
262 u32 iddq_bit_idx;
263 u32 reset_reg;
264 u32 reset_bit_idx;
265 u32 sdm_din_reg;
266 u32 sdm_din_mask;
267 u32 sdm_ctrl_reg;
268 u32 sdm_ctrl_en_mask;
269 u32 ssc_ctrl_reg;
270 u32 ssc_ctrl_en_mask;
271 u32 aux_reg;
272 u32 dyn_ramp_reg;
273 u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
274 u32 pmc_divnm_reg;
275 u32 pmc_divp_reg;
276 u32 flags;
277 int stepa_shift;
278 int stepb_shift;
279 int lock_delay;
280 int max_p;
281 bool defaults_set;
282 const struct pdiv_map *pdiv_tohw;
283 struct div_nmp *div_nmp;
284 struct tegra_clk_pll_freq_table *freq_table;
285 unsigned long fixed_rate;
286 u16 mdiv_default;
287 u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv);
288 void (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
289 int (*calc_rate)(struct clk_hw *hw,
290 struct tegra_clk_pll_freq_table *cfg,
291 unsigned long rate, unsigned long parent_rate);
292 unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
293 unsigned long parent_rate);
294 void (*set_defaults)(struct tegra_clk_pll *pll);
295 int (*dyn_ramp)(struct tegra_clk_pll *pll,
296 struct tegra_clk_pll_freq_table *cfg);
297 };
298
299 #define TEGRA_PLL_USE_LOCK BIT(0)
300 #define TEGRA_PLL_HAS_CPCON BIT(1)
301 #define TEGRA_PLL_SET_LFCON BIT(2)
302 #define TEGRA_PLL_SET_DCCON BIT(3)
303 #define TEGRA_PLLU BIT(4)
304 #define TEGRA_PLLM BIT(5)
305 #define TEGRA_PLL_FIXED BIT(6)
306 #define TEGRA_PLLE_CONFIGURE BIT(7)
307 #define TEGRA_PLL_LOCK_MISC BIT(8)
308 #define TEGRA_PLL_BYPASS BIT(9)
309 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
310 #define TEGRA_MDIV_NEW BIT(11)
311 #define TEGRA_PLLMB BIT(12)
312 #define TEGRA_PLL_VCO_OUT BIT(13)
313
314 /**
315 * struct tegra_clk_pll - Tegra PLL clock
316 *
317 * @hw: handle between common and hardware-specifix interfaces
318 * @clk_base: address of CAR controller
319 * @pmc: address of PMC, required to read override bits
320 * @lock: register lock
321 * @params: PLL parameters
322 */
323 struct tegra_clk_pll {
324 struct clk_hw hw;
325 void __iomem *clk_base;
326 void __iomem *pmc;
327 spinlock_t *lock;
328 struct tegra_clk_pll_params *params;
329 };
330
331 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
332
333 /**
334 * struct tegra_audio_clk_info - Tegra Audio Clk Information
335 *
336 * @name: name for the audio pll
337 * @pll_params: pll_params for audio pll
338 * @clk_id: clk_ids for the audio pll
339 * @parent: name of the parent of the audio pll
340 */
341 struct tegra_audio_clk_info {
342 char *name;
343 struct tegra_clk_pll_params *pll_params;
344 int clk_id;
345 char *parent;
346 };
347
348 extern const struct clk_ops tegra_clk_pll_ops;
349 extern const struct clk_ops tegra_clk_plle_ops;
350 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
351 void __iomem *clk_base, void __iomem *pmc,
352 unsigned long flags, struct tegra_clk_pll_params *pll_params,
353 spinlock_t *lock);
354
355 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
356 void __iomem *clk_base, void __iomem *pmc,
357 unsigned long flags, struct tegra_clk_pll_params *pll_params,
358 spinlock_t *lock);
359
360 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
361 void __iomem *clk_base, void __iomem *pmc,
362 unsigned long flags,
363 struct tegra_clk_pll_params *pll_params,
364 spinlock_t *lock);
365
366 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
367 void __iomem *clk_base, void __iomem *pmc,
368 unsigned long flags,
369 struct tegra_clk_pll_params *pll_params,
370 spinlock_t *lock);
371
372 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
373 void __iomem *clk_base, void __iomem *pmc,
374 unsigned long flags,
375 struct tegra_clk_pll_params *pll_params,
376 spinlock_t *lock);
377
378 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
379 void __iomem *clk_base, void __iomem *pmc,
380 unsigned long flags,
381 struct tegra_clk_pll_params *pll_params,
382 spinlock_t *lock, unsigned long parent_rate);
383
384 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
385 const char *parent_name, void __iomem *clk_base,
386 void __iomem *pmc, unsigned long flags,
387 struct tegra_clk_pll_params *pll_params,
388 spinlock_t *lock, unsigned long parent_rate);
389
390 struct clk *tegra_clk_register_plle_tegra114(const char *name,
391 const char *parent_name,
392 void __iomem *clk_base, unsigned long flags,
393 struct tegra_clk_pll_params *pll_params,
394 spinlock_t *lock);
395
396 struct clk *tegra_clk_register_plle_tegra210(const char *name,
397 const char *parent_name,
398 void __iomem *clk_base, unsigned long flags,
399 struct tegra_clk_pll_params *pll_params,
400 spinlock_t *lock);
401
402 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
403 const char *parent_name, void __iomem *clk_base,
404 void __iomem *pmc, unsigned long flags,
405 struct tegra_clk_pll_params *pll_params,
406 spinlock_t *lock);
407
408 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
409 const char *parent_name, void __iomem *clk_base,
410 unsigned long flags,
411 struct tegra_clk_pll_params *pll_params,
412 spinlock_t *lock);
413
414 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
415 void __iomem *clk_base, unsigned long flags,
416 struct tegra_clk_pll_params *pll_params,
417 spinlock_t *lock);
418
419 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
420 void __iomem *clk_base, void __iomem *pmc,
421 unsigned long flags,
422 struct tegra_clk_pll_params *pll_params,
423 spinlock_t *lock);
424
425 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
426 void __iomem *clk_base, unsigned long flags,
427 struct tegra_clk_pll_params *pll_params,
428 spinlock_t *lock);
429
430 struct clk *tegra_clk_register_pllu_tegra114(const char *name,
431 const char *parent_name,
432 void __iomem *clk_base, unsigned long flags,
433 struct tegra_clk_pll_params *pll_params,
434 spinlock_t *lock);
435
436 struct clk *tegra_clk_register_pllu_tegra210(const char *name,
437 const char *parent_name,
438 void __iomem *clk_base, unsigned long flags,
439 struct tegra_clk_pll_params *pll_params,
440 spinlock_t *lock);
441
442 /**
443 * struct tegra_clk_pll_out - PLL divider down clock
444 *
445 * @hw: handle between common and hardware-specific interfaces
446 * @reg: register containing the PLL divider
447 * @enb_bit_idx: bit to enable/disable PLL divider
448 * @rst_bit_idx: bit to reset PLL divider
449 * @lock: register lock
450 * @flags: hardware-specific flags
451 */
452 struct tegra_clk_pll_out {
453 struct clk_hw hw;
454 void __iomem *reg;
455 u8 enb_bit_idx;
456 u8 rst_bit_idx;
457 spinlock_t *lock;
458 u8 flags;
459 };
460
461 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
462
463 extern const struct clk_ops tegra_clk_pll_out_ops;
464 struct clk *tegra_clk_register_pll_out(const char *name,
465 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
466 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags,
467 spinlock_t *lock);
468
469 /**
470 * struct tegra_clk_periph_regs - Registers controlling peripheral clock
471 *
472 * @enb_reg: read the enable status
473 * @enb_set_reg: write 1 to enable clock
474 * @enb_clr_reg: write 1 to disable clock
475 * @rst_reg: read the reset status
476 * @rst_set_reg: write 1 to assert the reset of peripheral
477 * @rst_clr_reg: write 1 to deassert the reset of peripheral
478 */
479 struct tegra_clk_periph_regs {
480 u32 enb_reg;
481 u32 enb_set_reg;
482 u32 enb_clr_reg;
483 u32 rst_reg;
484 u32 rst_set_reg;
485 u32 rst_clr_reg;
486 };
487
488 /**
489 * struct tegra_clk_periph_gate - peripheral gate clock
490 *
491 * @magic: magic number to validate type
492 * @hw: handle between common and hardware-specific interfaces
493 * @clk_base: address of CAR controller
494 * @regs: Registers to control the peripheral
495 * @flags: hardware-specific flags
496 * @clk_num: Clock number
497 * @enable_refcnt: array to maintain reference count of the clock
498 *
499 * Flags:
500 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
501 * for this module.
502 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module
503 * after clock enable and driver for the module is responsible for
504 * doing reset.
505 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
506 * bus to flush the write operation in apb bus. This flag indicates
507 * that this peripheral is in apb bus.
508 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
509 */
510 struct tegra_clk_periph_gate {
511 u32 magic;
512 struct clk_hw hw;
513 void __iomem *clk_base;
514 u8 flags;
515 int clk_num;
516 int *enable_refcnt;
517 const struct tegra_clk_periph_regs *regs;
518 };
519
520 #define to_clk_periph_gate(_hw) \
521 container_of(_hw, struct tegra_clk_periph_gate, hw)
522
523 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
524
525 #define TEGRA_PERIPH_NO_RESET BIT(0)
526 #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
527 #define TEGRA_PERIPH_ON_APB BIT(2)
528 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
529 #define TEGRA_PERIPH_NO_DIV BIT(4)
530 #define TEGRA_PERIPH_NO_GATE BIT(5)
531
532 extern const struct clk_ops tegra_clk_periph_gate_ops;
533 struct clk *tegra_clk_register_periph_gate(const char *name,
534 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
535 unsigned long flags, int clk_num, int *enable_refcnt);
536
537 struct tegra_clk_periph_fixed {
538 struct clk_hw hw;
539 void __iomem *base;
540 const struct tegra_clk_periph_regs *regs;
541 unsigned int mul;
542 unsigned int div;
543 unsigned int num;
544 };
545
546 struct clk *tegra_clk_register_periph_fixed(const char *name,
547 const char *parent,
548 unsigned long flags,
549 void __iomem *base,
550 unsigned int mul,
551 unsigned int div,
552 unsigned int num);
553
554 /**
555 * struct clk-periph - peripheral clock
556 *
557 * @magic: magic number to validate type
558 * @hw: handle between common and hardware-specific interfaces
559 * @mux: mux clock
560 * @divider: divider clock
561 * @gate: gate clock
562 * @mux_ops: mux clock ops
563 * @div_ops: divider clock ops
564 * @gate_ops: gate clock ops
565 */
566 struct tegra_clk_periph {
567 u32 magic;
568 struct clk_hw hw;
569 struct clk_mux mux;
570 struct tegra_clk_frac_div divider;
571 struct tegra_clk_periph_gate gate;
572
573 const struct clk_ops *mux_ops;
574 const struct clk_ops *div_ops;
575 const struct clk_ops *gate_ops;
576 };
577
578 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
579
580 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223
581
582 extern const struct clk_ops tegra_clk_periph_ops;
583 struct clk *tegra_clk_register_periph(const char *name,
584 const char * const *parent_names, int num_parents,
585 struct tegra_clk_periph *periph, void __iomem *clk_base,
586 u32 offset, unsigned long flags);
587 struct clk *tegra_clk_register_periph_nodiv(const char *name,
588 const char * const *parent_names, int num_parents,
589 struct tegra_clk_periph *periph, void __iomem *clk_base,
590 u32 offset);
591
592 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
593 _div_shift, _div_width, _div_frac_width, \
594 _div_flags, _clk_num,\
595 _gate_flags, _table, _lock) \
596 { \
597 .mux = { \
598 .flags = _mux_flags, \
599 .shift = _mux_shift, \
600 .mask = _mux_mask, \
601 .table = _table, \
602 .lock = _lock, \
603 }, \
604 .divider = { \
605 .flags = _div_flags, \
606 .shift = _div_shift, \
607 .width = _div_width, \
608 .frac_width = _div_frac_width, \
609 .lock = _lock, \
610 }, \
611 .gate = { \
612 .flags = _gate_flags, \
613 .clk_num = _clk_num, \
614 }, \
615 .mux_ops = &clk_mux_ops, \
616 .div_ops = &tegra_clk_frac_div_ops, \
617 .gate_ops = &tegra_clk_periph_gate_ops, \
618 }
619
620 struct tegra_periph_init_data {
621 const char *name;
622 int clk_id;
623 union {
624 const char *const *parent_names;
625 const char *parent_name;
626 } p;
627 int num_parents;
628 struct tegra_clk_periph periph;
629 u32 offset;
630 const char *con_id;
631 const char *dev_id;
632 unsigned long flags;
633 };
634
635 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
636 _mux_shift, _mux_mask, _mux_flags, _div_shift, \
637 _div_width, _div_frac_width, _div_flags, \
638 _clk_num, _gate_flags, _clk_id, _table, \
639 _flags, _lock) \
640 { \
641 .name = _name, \
642 .clk_id = _clk_id, \
643 .p.parent_names = _parent_names, \
644 .num_parents = ARRAY_SIZE(_parent_names), \
645 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
646 _mux_flags, _div_shift, \
647 _div_width, _div_frac_width, \
648 _div_flags, _clk_num, \
649 _gate_flags, _table, _lock), \
650 .offset = _offset, \
651 .con_id = _con_id, \
652 .dev_id = _dev_id, \
653 .flags = _flags \
654 }
655
656 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
657 _mux_shift, _mux_width, _mux_flags, _div_shift, \
658 _div_width, _div_frac_width, _div_flags, \
659 _clk_num, _gate_flags, _clk_id) \
660 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
661 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
662 _div_shift, _div_width, _div_frac_width, _div_flags, \
663 _clk_num, _gate_flags, _clk_id,\
664 NULL, 0, NULL)
665
666 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
667 struct tegra_periph_init_data *init);
668
669 /**
670 * struct clk_super_mux - super clock
671 *
672 * @hw: handle between common and hardware-specific interfaces
673 * @reg: register controlling multiplexer
674 * @width: width of the multiplexer bit field
675 * @flags: hardware-specific flags
676 * @div2_index: bit controlling divide-by-2
677 * @pllx_index: PLLX index in the parent list
678 * @lock: register lock
679 *
680 * Flags:
681 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
682 * that this is LP cluster clock.
683 */
684 struct tegra_clk_super_mux {
685 struct clk_hw hw;
686 void __iomem *reg;
687 struct tegra_clk_frac_div frac_div;
688 const struct clk_ops *div_ops;
689 u8 width;
690 u8 flags;
691 u8 div2_index;
692 u8 pllx_index;
693 spinlock_t *lock;
694 };
695
696 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
697
698 #define TEGRA_DIVIDER_2 BIT(0)
699
700 extern const struct clk_ops tegra_clk_super_ops;
701 struct clk *tegra_clk_register_super_mux(const char *name,
702 const char **parent_names, u8 num_parents,
703 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
704 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
705 struct clk *tegra_clk_register_super_clk(const char *name,
706 const char * const *parent_names, u8 num_parents,
707 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
708 spinlock_t *lock);
709
710 /**
711 * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
712 *
713 * @hw: handle between common and hardware-specific interfaces
714 * @reg: register controlling mux and divider
715 * @flags: hardware-specific flags
716 * @lock: optional register lock
717 * @gate: gate clock
718 * @gate_ops: gate clock ops
719 */
720 struct tegra_sdmmc_mux {
721 struct clk_hw hw;
722 void __iomem *reg;
723 spinlock_t *lock;
724 const struct clk_ops *gate_ops;
725 struct tegra_clk_periph_gate gate;
726 u8 div_flags;
727 };
728
729 #define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
730
731 struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
732 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
733 unsigned long flags, void *lock);
734
735 /**
736 * struct clk_init_table - clock initialization table
737 * @clk_id: clock id as mentioned in device tree bindings
738 * @parent_id: parent clock id as mentioned in device tree bindings
739 * @rate: rate to set
740 * @state: enable/disable
741 */
742 struct tegra_clk_init_table {
743 unsigned int clk_id;
744 unsigned int parent_id;
745 unsigned long rate;
746 int state;
747 };
748
749 /**
750 * struct clk_duplicate - duplicate clocks
751 * @clk_id: clock id as mentioned in device tree bindings
752 * @lookup: duplicate lookup entry for the clock
753 */
754 struct tegra_clk_duplicate {
755 int clk_id;
756 struct clk_lookup lookup;
757 };
758
759 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \
760 { \
761 .clk_id = _clk_id, \
762 .lookup = { \
763 .dev_id = _dev, \
764 .con_id = _con, \
765 }, \
766 }
767
768 struct tegra_clk {
769 int dt_id;
770 bool present;
771 };
772
773 struct tegra_devclk {
774 int dt_id;
775 char *dev_id;
776 char *con_id;
777 };
778
779 void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long),
780 int (*deassert)(unsigned long));
781
782 void tegra_init_from_table(struct tegra_clk_init_table *tbl,
783 struct clk *clks[], int clk_max);
784
785 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
786 struct clk *clks[], int clk_max);
787
788 const struct tegra_clk_periph_regs *get_reg_bank(int clkid);
789 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
790
791 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
792
793 void tegra_add_of_provider(struct device_node *np, void *clk_src_onecell_get);
794 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
795
796 void tegra_audio_clk_init(void __iomem *clk_base,
797 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
798 struct tegra_audio_clk_info *audio_info,
799 unsigned int num_plls);
800
801 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
802 struct tegra_clk *tegra_clks,
803 struct tegra_clk_pll_params *pll_params);
804
805 void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
806 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
807 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
808 unsigned long *input_freqs, unsigned int num,
809 unsigned int clk_m_div, unsigned long *osc_freq,
810 unsigned long *pll_ref_freq);
811 void tegra_super_clk_gen4_init(void __iomem *clk_base,
812 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
813 struct tegra_clk_pll_params *pll_params);
814 void tegra_super_clk_gen5_init(void __iomem *clk_base,
815 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
816 struct tegra_clk_pll_params *pll_params);
817
818 #ifdef CONFIG_TEGRA_CLK_EMC
819 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
820 spinlock_t *lock);
821 #else
tegra_clk_register_emc(void __iomem * base,struct device_node * np,spinlock_t * lock)822 static inline struct clk *tegra_clk_register_emc(void __iomem *base,
823 struct device_node *np,
824 spinlock_t *lock)
825 {
826 return NULL;
827 }
828 #endif
829
830 void tegra114_clock_tune_cpu_trimmers_high(void);
831 void tegra114_clock_tune_cpu_trimmers_low(void);
832 void tegra114_clock_tune_cpu_trimmers_init(void);
833 void tegra114_clock_assert_dfll_dvco_reset(void);
834 void tegra114_clock_deassert_dfll_dvco_reset(void);
835
836 typedef void (*tegra_clk_apply_init_table_func)(void);
837 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
838 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
839 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
840 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
841 int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
842 u8 frac_width, u8 flags);
843
844
845 /* Combined read fence with delay */
846 #define fence_udelay(delay, reg) \
847 do { \
848 readl(reg); \
849 udelay(delay); \
850 } while (0)
851
852 #endif /* TEGRA_CLK_H */
853
