1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 RVU Physcial Function ethernet driver
3 *
4 * Copyright (C) 2020 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/etherdevice.h>
15 #include <linux/of.h>
16 #include <linux/if_vlan.h>
17 #include <linux/iommu.h>
18 #include <net/ip.h>
19
20 #include "otx2_reg.h"
21 #include "otx2_common.h"
22 #include "otx2_txrx.h"
23 #include "otx2_struct.h"
24 #include "otx2_ptp.h"
25 #include <rvu_trace.h>
26
27 #define DRV_NAME "octeontx2-nicpf"
28 #define DRV_STRING "Marvell OcteonTX2 NIC Physical Function Driver"
29
30 /* Supported devices */
31 static const struct pci_device_id otx2_pf_id_table[] = {
32 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) },
33 { 0, } /* end of table */
34 };
35
36 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
37 MODULE_DESCRIPTION(DRV_STRING);
38 MODULE_LICENSE("GPL v2");
39 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table);
40
41 enum {
42 TYPE_PFAF,
43 TYPE_PFVF,
44 };
45
46 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable);
47 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable);
48
otx2_change_mtu(struct net_device * netdev,int new_mtu)49 static int otx2_change_mtu(struct net_device *netdev, int new_mtu)
50 {
51 bool if_up = netif_running(netdev);
52 int err = 0;
53
54 if (if_up)
55 otx2_stop(netdev);
56
57 netdev_info(netdev, "Changing MTU from %d to %d\n",
58 netdev->mtu, new_mtu);
59 netdev->mtu = new_mtu;
60
61 if (if_up)
62 err = otx2_open(netdev);
63
64 return err;
65 }
66
otx2_disable_flr_me_intr(struct otx2_nic * pf)67 static void otx2_disable_flr_me_intr(struct otx2_nic *pf)
68 {
69 int irq, vfs = pf->total_vfs;
70
71 /* Disable VFs ME interrupts */
72 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
73 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0);
74 free_irq(irq, pf);
75
76 /* Disable VFs FLR interrupts */
77 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
78 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0);
79 free_irq(irq, pf);
80
81 if (vfs <= 64)
82 return;
83
84 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
85 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1);
86 free_irq(irq, pf);
87
88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1);
90 free_irq(irq, pf);
91 }
92
otx2_flr_wq_destroy(struct otx2_nic * pf)93 static void otx2_flr_wq_destroy(struct otx2_nic *pf)
94 {
95 if (!pf->flr_wq)
96 return;
97 destroy_workqueue(pf->flr_wq);
98 pf->flr_wq = NULL;
99 devm_kfree(pf->dev, pf->flr_wrk);
100 }
101
otx2_flr_handler(struct work_struct * work)102 static void otx2_flr_handler(struct work_struct *work)
103 {
104 struct flr_work *flrwork = container_of(work, struct flr_work, work);
105 struct otx2_nic *pf = flrwork->pf;
106 struct mbox *mbox = &pf->mbox;
107 struct msg_req *req;
108 int vf, reg = 0;
109
110 vf = flrwork - pf->flr_wrk;
111
112 mutex_lock(&mbox->lock);
113 req = otx2_mbox_alloc_msg_vf_flr(mbox);
114 if (!req) {
115 mutex_unlock(&mbox->lock);
116 return;
117 }
118 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK;
119 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK;
120
121 if (!otx2_sync_mbox_msg(&pf->mbox)) {
122 if (vf >= 64) {
123 reg = 1;
124 vf = vf - 64;
125 }
126 /* clear transcation pending bit */
127 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
128 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
129 }
130
131 mutex_unlock(&mbox->lock);
132 }
133
otx2_pf_flr_intr_handler(int irq,void * pf_irq)134 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq)
135 {
136 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
137 int reg, dev, vf, start_vf, num_reg = 1;
138 u64 intr;
139
140 if (pf->total_vfs > 64)
141 num_reg = 2;
142
143 for (reg = 0; reg < num_reg; reg++) {
144 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg));
145 if (!intr)
146 continue;
147 start_vf = 64 * reg;
148 for (vf = 0; vf < 64; vf++) {
149 if (!(intr & BIT_ULL(vf)))
150 continue;
151 dev = vf + start_vf;
152 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work);
153 /* Clear interrupt */
154 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
155 /* Disable the interrupt */
156 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg),
157 BIT_ULL(vf));
158 }
159 }
160 return IRQ_HANDLED;
161 }
162
otx2_pf_me_intr_handler(int irq,void * pf_irq)163 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq)
164 {
165 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
166 int vf, reg, num_reg = 1;
167 u64 intr;
168
169 if (pf->total_vfs > 64)
170 num_reg = 2;
171
172 for (reg = 0; reg < num_reg; reg++) {
173 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg));
174 if (!intr)
175 continue;
176 for (vf = 0; vf < 64; vf++) {
177 if (!(intr & BIT_ULL(vf)))
178 continue;
179 /* clear trpend bit */
180 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
181 /* clear interrupt */
182 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf));
183 }
184 }
185 return IRQ_HANDLED;
186 }
187
otx2_register_flr_me_intr(struct otx2_nic * pf,int numvfs)188 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs)
189 {
190 struct otx2_hw *hw = &pf->hw;
191 char *irq_name;
192 int ret;
193
194 /* Register ME interrupt handler*/
195 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE];
196 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc));
197 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0),
198 otx2_pf_me_intr_handler, 0, irq_name, pf);
199 if (ret) {
200 dev_err(pf->dev,
201 "RVUPF: IRQ registration failed for ME0\n");
202 }
203
204 /* Register FLR interrupt handler */
205 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE];
206 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc));
207 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0),
208 otx2_pf_flr_intr_handler, 0, irq_name, pf);
209 if (ret) {
210 dev_err(pf->dev,
211 "RVUPF: IRQ registration failed for FLR0\n");
212 return ret;
213 }
214
215 if (numvfs > 64) {
216 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE];
217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1",
218 rvu_get_pf(pf->pcifunc));
219 ret = request_irq(pci_irq_vector
220 (pf->pdev, RVU_PF_INT_VEC_VFME1),
221 otx2_pf_me_intr_handler, 0, irq_name, pf);
222 if (ret) {
223 dev_err(pf->dev,
224 "RVUPF: IRQ registration failed for ME1\n");
225 }
226 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE];
227 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1",
228 rvu_get_pf(pf->pcifunc));
229 ret = request_irq(pci_irq_vector
230 (pf->pdev, RVU_PF_INT_VEC_VFFLR1),
231 otx2_pf_flr_intr_handler, 0, irq_name, pf);
232 if (ret) {
233 dev_err(pf->dev,
234 "RVUPF: IRQ registration failed for FLR1\n");
235 return ret;
236 }
237 }
238
239 /* Enable ME interrupt for all VFs*/
240 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs));
241 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs));
242
243 /* Enable FLR interrupt for all VFs*/
244 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs));
245 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs));
246
247 if (numvfs > 64) {
248 numvfs -= 64;
249
250 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs));
251 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1),
252 INTR_MASK(numvfs));
253
254 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs));
255 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1),
256 INTR_MASK(numvfs));
257 }
258 return 0;
259 }
260
otx2_pf_flr_init(struct otx2_nic * pf,int num_vfs)261 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs)
262 {
263 int vf;
264
265 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq",
266 WQ_UNBOUND | WQ_HIGHPRI, 1);
267 if (!pf->flr_wq)
268 return -ENOMEM;
269
270 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs,
271 sizeof(struct flr_work), GFP_KERNEL);
272 if (!pf->flr_wrk) {
273 destroy_workqueue(pf->flr_wq);
274 return -ENOMEM;
275 }
276
277 for (vf = 0; vf < num_vfs; vf++) {
278 pf->flr_wrk[vf].pf = pf;
279 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler);
280 }
281
282 return 0;
283 }
284
otx2_queue_work(struct mbox * mw,struct workqueue_struct * mbox_wq,int first,int mdevs,u64 intr,int type)285 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq,
286 int first, int mdevs, u64 intr, int type)
287 {
288 struct otx2_mbox_dev *mdev;
289 struct otx2_mbox *mbox;
290 struct mbox_hdr *hdr;
291 int i;
292
293 for (i = first; i < mdevs; i++) {
294 /* start from 0 */
295 if (!(intr & BIT_ULL(i - first)))
296 continue;
297
298 mbox = &mw->mbox;
299 mdev = &mbox->dev[i];
300 if (type == TYPE_PFAF)
301 otx2_sync_mbox_bbuf(mbox, i);
302 hdr = mdev->mbase + mbox->rx_start;
303 /* The hdr->num_msgs is set to zero immediately in the interrupt
304 * handler to ensure that it holds a correct value next time
305 * when the interrupt handler is called.
306 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
307 * pf>mbox.up_num_msgs holds the data for use in
308 * pfaf_mbox_up_handler.
309 */
310 if (hdr->num_msgs) {
311 mw[i].num_msgs = hdr->num_msgs;
312 hdr->num_msgs = 0;
313 if (type == TYPE_PFAF)
314 memset(mbox->hwbase + mbox->rx_start, 0,
315 ALIGN(sizeof(struct mbox_hdr),
316 sizeof(u64)));
317
318 queue_work(mbox_wq, &mw[i].mbox_wrk);
319 }
320
321 mbox = &mw->mbox_up;
322 mdev = &mbox->dev[i];
323 if (type == TYPE_PFAF)
324 otx2_sync_mbox_bbuf(mbox, i);
325 hdr = mdev->mbase + mbox->rx_start;
326 if (hdr->num_msgs) {
327 mw[i].up_num_msgs = hdr->num_msgs;
328 hdr->num_msgs = 0;
329 if (type == TYPE_PFAF)
330 memset(mbox->hwbase + mbox->rx_start, 0,
331 ALIGN(sizeof(struct mbox_hdr),
332 sizeof(u64)));
333
334 queue_work(mbox_wq, &mw[i].mbox_up_wrk);
335 }
336 }
337 }
338
otx2_forward_msg_pfvf(struct otx2_mbox_dev * mdev,struct otx2_mbox * pfvf_mbox,void * bbuf_base,int devid)339 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev,
340 struct otx2_mbox *pfvf_mbox, void *bbuf_base,
341 int devid)
342 {
343 struct otx2_mbox_dev *src_mdev = mdev;
344 int offset;
345
346 /* Msgs are already copied, trigger VF's mbox irq */
347 smp_wmb();
348
349 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift);
350 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset);
351
352 /* Restore VF's mbox bounce buffer region address */
353 src_mdev->mbase = bbuf_base;
354 }
355
otx2_forward_vf_mbox_msgs(struct otx2_nic * pf,struct otx2_mbox * src_mbox,int dir,int vf,int num_msgs)356 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf,
357 struct otx2_mbox *src_mbox,
358 int dir, int vf, int num_msgs)
359 {
360 struct otx2_mbox_dev *src_mdev, *dst_mdev;
361 struct mbox_hdr *mbox_hdr;
362 struct mbox_hdr *req_hdr;
363 struct mbox *dst_mbox;
364 int dst_size, err;
365
366 if (dir == MBOX_DIR_PFAF) {
367 /* Set VF's mailbox memory as PF's bounce buffer memory, so
368 * that explicit copying of VF's msgs to PF=>AF mbox region
369 * and AF=>PF responses to VF's mbox region can be avoided.
370 */
371 src_mdev = &src_mbox->dev[vf];
372 mbox_hdr = src_mbox->hwbase +
373 src_mbox->rx_start + (vf * MBOX_SIZE);
374
375 dst_mbox = &pf->mbox;
376 dst_size = dst_mbox->mbox.tx_size -
377 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
378 /* Check if msgs fit into destination area and has valid size */
379 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size)
380 return -EINVAL;
381
382 dst_mdev = &dst_mbox->mbox.dev[0];
383
384 mutex_lock(&pf->mbox.lock);
385 dst_mdev->mbase = src_mdev->mbase;
386 dst_mdev->msg_size = mbox_hdr->msg_size;
387 dst_mdev->num_msgs = num_msgs;
388 err = otx2_sync_mbox_msg(dst_mbox);
389 if (err) {
390 dev_warn(pf->dev,
391 "AF not responding to VF%d messages\n", vf);
392 /* restore PF mbase and exit */
393 dst_mdev->mbase = pf->mbox.bbuf_base;
394 mutex_unlock(&pf->mbox.lock);
395 return err;
396 }
397 /* At this point, all the VF messages sent to AF are acked
398 * with proper responses and responses are copied to VF
399 * mailbox hence raise interrupt to VF.
400 */
401 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase +
402 dst_mbox->mbox.rx_start);
403 req_hdr->num_msgs = num_msgs;
404
405 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox,
406 pf->mbox.bbuf_base, vf);
407 mutex_unlock(&pf->mbox.lock);
408 } else if (dir == MBOX_DIR_PFVF_UP) {
409 src_mdev = &src_mbox->dev[0];
410 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start;
411 req_hdr = (struct mbox_hdr *)(src_mdev->mbase +
412 src_mbox->rx_start);
413 req_hdr->num_msgs = num_msgs;
414
415 dst_mbox = &pf->mbox_pfvf[0];
416 dst_size = dst_mbox->mbox_up.tx_size -
417 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
418 /* Check if msgs fit into destination area */
419 if (mbox_hdr->msg_size > dst_size)
420 return -EINVAL;
421
422 dst_mdev = &dst_mbox->mbox_up.dev[vf];
423 dst_mdev->mbase = src_mdev->mbase;
424 dst_mdev->msg_size = mbox_hdr->msg_size;
425 dst_mdev->num_msgs = mbox_hdr->num_msgs;
426 err = otx2_sync_mbox_up_msg(dst_mbox, vf);
427 if (err) {
428 dev_warn(pf->dev,
429 "VF%d is not responding to mailbox\n", vf);
430 return err;
431 }
432 } else if (dir == MBOX_DIR_VFPF_UP) {
433 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase +
434 src_mbox->rx_start);
435 req_hdr->num_msgs = num_msgs;
436 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf],
437 &pf->mbox.mbox_up,
438 pf->mbox_pfvf[vf].bbuf_base,
439 0);
440 }
441
442 return 0;
443 }
444
otx2_pfvf_mbox_handler(struct work_struct * work)445 static void otx2_pfvf_mbox_handler(struct work_struct *work)
446 {
447 struct mbox_msghdr *msg = NULL;
448 int offset, vf_idx, id, err;
449 struct otx2_mbox_dev *mdev;
450 struct mbox_hdr *req_hdr;
451 struct otx2_mbox *mbox;
452 struct mbox *vf_mbox;
453 struct otx2_nic *pf;
454
455 vf_mbox = container_of(work, struct mbox, mbox_wrk);
456 pf = vf_mbox->pfvf;
457 vf_idx = vf_mbox - pf->mbox_pfvf;
458
459 mbox = &pf->mbox_pfvf[0].mbox;
460 mdev = &mbox->dev[vf_idx];
461 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
462
463 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
464
465 for (id = 0; id < vf_mbox->num_msgs; id++) {
466 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start +
467 offset);
468
469 if (msg->sig != OTX2_MBOX_REQ_SIG)
470 goto inval_msg;
471
472 /* Set VF's number in each of the msg */
473 msg->pcifunc &= RVU_PFVF_FUNC_MASK;
474 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK;
475 offset = msg->next_msgoff;
476 }
477 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx,
478 vf_mbox->num_msgs);
479 if (err)
480 goto inval_msg;
481 return;
482
483 inval_msg:
484 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id);
485 otx2_mbox_msg_send(mbox, vf_idx);
486 }
487
otx2_pfvf_mbox_up_handler(struct work_struct * work)488 static void otx2_pfvf_mbox_up_handler(struct work_struct *work)
489 {
490 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
491 struct otx2_nic *pf = vf_mbox->pfvf;
492 struct otx2_mbox_dev *mdev;
493 int offset, id, vf_idx = 0;
494 struct mbox_hdr *rsp_hdr;
495 struct mbox_msghdr *msg;
496 struct otx2_mbox *mbox;
497
498 vf_idx = vf_mbox - pf->mbox_pfvf;
499 mbox = &pf->mbox_pfvf[0].mbox_up;
500 mdev = &mbox->dev[vf_idx];
501
502 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
503 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
504
505 for (id = 0; id < vf_mbox->up_num_msgs; id++) {
506 msg = mdev->mbase + offset;
507
508 if (msg->id >= MBOX_MSG_MAX) {
509 dev_err(pf->dev,
510 "Mbox msg with unknown ID 0x%x\n", msg->id);
511 goto end;
512 }
513
514 if (msg->sig != OTX2_MBOX_RSP_SIG) {
515 dev_err(pf->dev,
516 "Mbox msg with wrong signature %x, ID 0x%x\n",
517 msg->sig, msg->id);
518 goto end;
519 }
520
521 switch (msg->id) {
522 case MBOX_MSG_CGX_LINK_EVENT:
523 break;
524 default:
525 if (msg->rc)
526 dev_err(pf->dev,
527 "Mbox msg response has err %d, ID 0x%x\n",
528 msg->rc, msg->id);
529 break;
530 }
531
532 end:
533 offset = mbox->rx_start + msg->next_msgoff;
534 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1))
535 __otx2_mbox_reset(mbox, 0);
536 mdev->msgs_acked++;
537 }
538 }
539
otx2_pfvf_mbox_intr_handler(int irq,void * pf_irq)540 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq)
541 {
542 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq);
543 int vfs = pf->total_vfs;
544 struct mbox *mbox;
545 u64 intr;
546
547 mbox = pf->mbox_pfvf;
548 /* Handle VF interrupts */
549 if (vfs > 64) {
550 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1));
551 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr);
552 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr,
553 TYPE_PFVF);
554 vfs -= 64;
555 }
556
557 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0));
558 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr);
559
560 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF);
561
562 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr);
563
564 return IRQ_HANDLED;
565 }
566
otx2_pfvf_mbox_init(struct otx2_nic * pf,int numvfs)567 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs)
568 {
569 void __iomem *hwbase;
570 struct mbox *mbox;
571 int err, vf;
572 u64 base;
573
574 if (!numvfs)
575 return -EINVAL;
576
577 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs,
578 sizeof(struct mbox), GFP_KERNEL);
579 if (!pf->mbox_pfvf)
580 return -ENOMEM;
581
582 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox",
583 WQ_UNBOUND | WQ_HIGHPRI |
584 WQ_MEM_RECLAIM, 1);
585 if (!pf->mbox_pfvf_wq)
586 return -ENOMEM;
587
588 base = readq((void __iomem *)((u64)pf->reg_base + RVU_PF_VF_BAR4_ADDR));
589 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs);
590
591 if (!hwbase) {
592 err = -ENOMEM;
593 goto free_wq;
594 }
595
596 mbox = &pf->mbox_pfvf[0];
597 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
598 MBOX_DIR_PFVF, numvfs);
599 if (err)
600 goto free_iomem;
601
602 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
603 MBOX_DIR_PFVF_UP, numvfs);
604 if (err)
605 goto free_iomem;
606
607 for (vf = 0; vf < numvfs; vf++) {
608 mbox->pfvf = pf;
609 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler);
610 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler);
611 mbox++;
612 }
613
614 return 0;
615
616 free_iomem:
617 if (hwbase)
618 iounmap(hwbase);
619 free_wq:
620 destroy_workqueue(pf->mbox_pfvf_wq);
621 return err;
622 }
623
otx2_pfvf_mbox_destroy(struct otx2_nic * pf)624 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf)
625 {
626 struct mbox *mbox = &pf->mbox_pfvf[0];
627
628 if (!mbox)
629 return;
630
631 if (pf->mbox_pfvf_wq) {
632 destroy_workqueue(pf->mbox_pfvf_wq);
633 pf->mbox_pfvf_wq = NULL;
634 }
635
636 if (mbox->mbox.hwbase)
637 iounmap(mbox->mbox.hwbase);
638
639 otx2_mbox_destroy(&mbox->mbox);
640 }
641
otx2_enable_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)642 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
643 {
644 /* Clear PF <=> VF mailbox IRQ */
645 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
646 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
647
648 /* Enable PF <=> VF mailbox IRQ */
649 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs));
650 if (numvfs > 64) {
651 numvfs -= 64;
652 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
653 INTR_MASK(numvfs));
654 }
655 }
656
otx2_disable_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)657 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
658 {
659 int vector;
660
661 /* Disable PF <=> VF mailbox IRQ */
662 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull);
663 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull);
664
665 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
666 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0);
667 free_irq(vector, pf);
668
669 if (numvfs > 64) {
670 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
671 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1);
672 free_irq(vector, pf);
673 }
674 }
675
otx2_register_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)676 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
677 {
678 struct otx2_hw *hw = &pf->hw;
679 char *irq_name;
680 int err;
681
682 /* Register MBOX0 interrupt handler */
683 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE];
684 if (pf->pcifunc)
685 snprintf(irq_name, NAME_SIZE,
686 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc));
687 else
688 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0");
689 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0),
690 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf);
691 if (err) {
692 dev_err(pf->dev,
693 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n");
694 return err;
695 }
696
697 if (numvfs > 64) {
698 /* Register MBOX1 interrupt handler */
699 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE];
700 if (pf->pcifunc)
701 snprintf(irq_name, NAME_SIZE,
702 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc));
703 else
704 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1");
705 err = request_irq(pci_irq_vector(pf->pdev,
706 RVU_PF_INT_VEC_VFPF_MBOX1),
707 otx2_pfvf_mbox_intr_handler,
708 0, irq_name, pf);
709 if (err) {
710 dev_err(pf->dev,
711 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n");
712 return err;
713 }
714 }
715
716 otx2_enable_pfvf_mbox_intr(pf, numvfs);
717
718 return 0;
719 }
720
otx2_process_pfaf_mbox_msg(struct otx2_nic * pf,struct mbox_msghdr * msg)721 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf,
722 struct mbox_msghdr *msg)
723 {
724 int devid;
725
726 if (msg->id >= MBOX_MSG_MAX) {
727 dev_err(pf->dev,
728 "Mbox msg with unknown ID 0x%x\n", msg->id);
729 return;
730 }
731
732 if (msg->sig != OTX2_MBOX_RSP_SIG) {
733 dev_err(pf->dev,
734 "Mbox msg with wrong signature %x, ID 0x%x\n",
735 msg->sig, msg->id);
736 return;
737 }
738
739 /* message response heading VF */
740 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
741 if (devid) {
742 struct otx2_vf_config *config = &pf->vf_configs[devid - 1];
743 struct delayed_work *dwork;
744
745 switch (msg->id) {
746 case MBOX_MSG_NIX_LF_START_RX:
747 config->intf_down = false;
748 dwork = &config->link_event_work;
749 schedule_delayed_work(dwork, msecs_to_jiffies(100));
750 break;
751 case MBOX_MSG_NIX_LF_STOP_RX:
752 config->intf_down = true;
753 break;
754 }
755
756 return;
757 }
758
759 switch (msg->id) {
760 case MBOX_MSG_READY:
761 pf->pcifunc = msg->pcifunc;
762 break;
763 case MBOX_MSG_MSIX_OFFSET:
764 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg);
765 break;
766 case MBOX_MSG_NPA_LF_ALLOC:
767 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg);
768 break;
769 case MBOX_MSG_NIX_LF_ALLOC:
770 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg);
771 break;
772 case MBOX_MSG_NIX_TXSCH_ALLOC:
773 mbox_handler_nix_txsch_alloc(pf,
774 (struct nix_txsch_alloc_rsp *)msg);
775 break;
776 case MBOX_MSG_NIX_BP_ENABLE:
777 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg);
778 break;
779 case MBOX_MSG_CGX_STATS:
780 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg);
781 break;
782 default:
783 if (msg->rc)
784 dev_err(pf->dev,
785 "Mbox msg response has err %d, ID 0x%x\n",
786 msg->rc, msg->id);
787 break;
788 }
789 }
790
otx2_pfaf_mbox_handler(struct work_struct * work)791 static void otx2_pfaf_mbox_handler(struct work_struct *work)
792 {
793 struct otx2_mbox_dev *mdev;
794 struct mbox_hdr *rsp_hdr;
795 struct mbox_msghdr *msg;
796 struct otx2_mbox *mbox;
797 struct mbox *af_mbox;
798 struct otx2_nic *pf;
799 int offset, id;
800
801 af_mbox = container_of(work, struct mbox, mbox_wrk);
802 mbox = &af_mbox->mbox;
803 mdev = &mbox->dev[0];
804 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
805
806 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
807 pf = af_mbox->pfvf;
808
809 for (id = 0; id < af_mbox->num_msgs; id++) {
810 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
811 otx2_process_pfaf_mbox_msg(pf, msg);
812 offset = mbox->rx_start + msg->next_msgoff;
813 if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
814 __otx2_mbox_reset(mbox, 0);
815 mdev->msgs_acked++;
816 }
817
818 }
819
otx2_handle_link_event(struct otx2_nic * pf)820 static void otx2_handle_link_event(struct otx2_nic *pf)
821 {
822 struct cgx_link_user_info *linfo = &pf->linfo;
823 struct net_device *netdev = pf->netdev;
824
825 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name,
826 linfo->link_up ? "UP" : "DOWN", linfo->speed,
827 linfo->full_duplex ? "Full" : "Half");
828 if (linfo->link_up) {
829 netif_carrier_on(netdev);
830 netif_tx_start_all_queues(netdev);
831 } else {
832 netif_tx_stop_all_queues(netdev);
833 netif_carrier_off(netdev);
834 }
835 }
836
otx2_mbox_up_handler_cgx_link_event(struct otx2_nic * pf,struct cgx_link_info_msg * msg,struct msg_rsp * rsp)837 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf,
838 struct cgx_link_info_msg *msg,
839 struct msg_rsp *rsp)
840 {
841 int i;
842
843 /* Copy the link info sent by AF */
844 pf->linfo = msg->link_info;
845
846 /* notify VFs about link event */
847 for (i = 0; i < pci_num_vf(pf->pdev); i++) {
848 struct otx2_vf_config *config = &pf->vf_configs[i];
849 struct delayed_work *dwork = &config->link_event_work;
850
851 if (config->intf_down)
852 continue;
853
854 schedule_delayed_work(dwork, msecs_to_jiffies(100));
855 }
856
857 /* interface has not been fully configured yet */
858 if (pf->flags & OTX2_FLAG_INTF_DOWN)
859 return 0;
860
861 otx2_handle_link_event(pf);
862 return 0;
863 }
864
otx2_process_mbox_msg_up(struct otx2_nic * pf,struct mbox_msghdr * req)865 static int otx2_process_mbox_msg_up(struct otx2_nic *pf,
866 struct mbox_msghdr *req)
867 {
868 /* Check if valid, if not reply with a invalid msg */
869 if (req->sig != OTX2_MBOX_REQ_SIG) {
870 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
871 return -ENODEV;
872 }
873
874 switch (req->id) {
875 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
876 case _id: { \
877 struct _rsp_type *rsp; \
878 int err; \
879 \
880 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \
881 &pf->mbox.mbox_up, 0, \
882 sizeof(struct _rsp_type)); \
883 if (!rsp) \
884 return -ENOMEM; \
885 \
886 rsp->hdr.id = _id; \
887 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \
888 rsp->hdr.pcifunc = 0; \
889 rsp->hdr.rc = 0; \
890 \
891 err = otx2_mbox_up_handler_ ## _fn_name( \
892 pf, (struct _req_type *)req, rsp); \
893 return err; \
894 }
895 MBOX_UP_CGX_MESSAGES
896 #undef M
897 break;
898 default:
899 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
900 return -ENODEV;
901 }
902 return 0;
903 }
904
otx2_pfaf_mbox_up_handler(struct work_struct * work)905 static void otx2_pfaf_mbox_up_handler(struct work_struct *work)
906 {
907 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk);
908 struct otx2_mbox *mbox = &af_mbox->mbox_up;
909 struct otx2_mbox_dev *mdev = &mbox->dev[0];
910 struct otx2_nic *pf = af_mbox->pfvf;
911 int offset, id, devid = 0;
912 struct mbox_hdr *rsp_hdr;
913 struct mbox_msghdr *msg;
914
915 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
916
917 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
918
919 for (id = 0; id < af_mbox->up_num_msgs; id++) {
920 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
921
922 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
923 /* Skip processing VF's messages */
924 if (!devid)
925 otx2_process_mbox_msg_up(pf, msg);
926 offset = mbox->rx_start + msg->next_msgoff;
927 }
928 if (devid) {
929 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up,
930 MBOX_DIR_PFVF_UP, devid - 1,
931 af_mbox->up_num_msgs);
932 return;
933 }
934
935 otx2_mbox_msg_send(mbox, 0);
936 }
937
otx2_pfaf_mbox_intr_handler(int irq,void * pf_irq)938 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq)
939 {
940 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
941 struct mbox *mbox;
942
943 /* Clear the IRQ */
944 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
945
946 mbox = &pf->mbox;
947
948 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0));
949
950 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF);
951
952 return IRQ_HANDLED;
953 }
954
otx2_disable_mbox_intr(struct otx2_nic * pf)955 static void otx2_disable_mbox_intr(struct otx2_nic *pf)
956 {
957 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX);
958
959 /* Disable AF => PF mailbox IRQ */
960 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0));
961 free_irq(vector, pf);
962 }
963
otx2_register_mbox_intr(struct otx2_nic * pf,bool probe_af)964 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af)
965 {
966 struct otx2_hw *hw = &pf->hw;
967 struct msg_req *req;
968 char *irq_name;
969 int err;
970
971 /* Register mailbox interrupt handler */
972 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE];
973 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox");
974 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX),
975 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf);
976 if (err) {
977 dev_err(pf->dev,
978 "RVUPF: IRQ registration failed for PFAF mbox irq\n");
979 return err;
980 }
981
982 /* Enable mailbox interrupt for msgs coming from AF.
983 * First clear to avoid spurious interrupts, if any.
984 */
985 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
986 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0));
987
988 if (!probe_af)
989 return 0;
990
991 /* Check mailbox communication with AF */
992 req = otx2_mbox_alloc_msg_ready(&pf->mbox);
993 if (!req) {
994 otx2_disable_mbox_intr(pf);
995 return -ENOMEM;
996 }
997 err = otx2_sync_mbox_msg(&pf->mbox);
998 if (err) {
999 dev_warn(pf->dev,
1000 "AF not responding to mailbox, deferring probe\n");
1001 otx2_disable_mbox_intr(pf);
1002 return -EPROBE_DEFER;
1003 }
1004
1005 return 0;
1006 }
1007
otx2_pfaf_mbox_destroy(struct otx2_nic * pf)1008 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf)
1009 {
1010 struct mbox *mbox = &pf->mbox;
1011
1012 if (pf->mbox_wq) {
1013 destroy_workqueue(pf->mbox_wq);
1014 pf->mbox_wq = NULL;
1015 }
1016
1017 if (mbox->mbox.hwbase)
1018 iounmap((void __iomem *)mbox->mbox.hwbase);
1019
1020 otx2_mbox_destroy(&mbox->mbox);
1021 otx2_mbox_destroy(&mbox->mbox_up);
1022 }
1023
otx2_pfaf_mbox_init(struct otx2_nic * pf)1024 static int otx2_pfaf_mbox_init(struct otx2_nic *pf)
1025 {
1026 struct mbox *mbox = &pf->mbox;
1027 void __iomem *hwbase;
1028 int err;
1029
1030 mbox->pfvf = pf;
1031 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox",
1032 WQ_UNBOUND | WQ_HIGHPRI |
1033 WQ_MEM_RECLAIM, 1);
1034 if (!pf->mbox_wq)
1035 return -ENOMEM;
1036
1037 /* Mailbox is a reserved memory (in RAM) region shared between
1038 * admin function (i.e AF) and this PF, shouldn't be mapped as
1039 * device memory to allow unaligned accesses.
1040 */
1041 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM),
1042 pci_resource_len(pf->pdev, PCI_MBOX_BAR_NUM));
1043 if (!hwbase) {
1044 dev_err(pf->dev, "Unable to map PFAF mailbox region\n");
1045 err = -ENOMEM;
1046 goto exit;
1047 }
1048
1049 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
1050 MBOX_DIR_PFAF, 1);
1051 if (err)
1052 goto exit;
1053
1054 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
1055 MBOX_DIR_PFAF_UP, 1);
1056 if (err)
1057 goto exit;
1058
1059 err = otx2_mbox_bbuf_init(mbox, pf->pdev);
1060 if (err)
1061 goto exit;
1062
1063 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler);
1064 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler);
1065 mutex_init(&mbox->lock);
1066
1067 return 0;
1068 exit:
1069 otx2_pfaf_mbox_destroy(pf);
1070 return err;
1071 }
1072
otx2_cgx_config_linkevents(struct otx2_nic * pf,bool enable)1073 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable)
1074 {
1075 struct msg_req *msg;
1076 int err;
1077
1078 mutex_lock(&pf->mbox.lock);
1079 if (enable)
1080 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox);
1081 else
1082 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox);
1083
1084 if (!msg) {
1085 mutex_unlock(&pf->mbox.lock);
1086 return -ENOMEM;
1087 }
1088
1089 err = otx2_sync_mbox_msg(&pf->mbox);
1090 mutex_unlock(&pf->mbox.lock);
1091 return err;
1092 }
1093
otx2_cgx_config_loopback(struct otx2_nic * pf,bool enable)1094 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable)
1095 {
1096 struct msg_req *msg;
1097 int err;
1098
1099 mutex_lock(&pf->mbox.lock);
1100 if (enable)
1101 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox);
1102 else
1103 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox);
1104
1105 if (!msg) {
1106 mutex_unlock(&pf->mbox.lock);
1107 return -ENOMEM;
1108 }
1109
1110 err = otx2_sync_mbox_msg(&pf->mbox);
1111 mutex_unlock(&pf->mbox.lock);
1112 return err;
1113 }
1114
otx2_set_real_num_queues(struct net_device * netdev,int tx_queues,int rx_queues)1115 int otx2_set_real_num_queues(struct net_device *netdev,
1116 int tx_queues, int rx_queues)
1117 {
1118 int err;
1119
1120 err = netif_set_real_num_tx_queues(netdev, tx_queues);
1121 if (err) {
1122 netdev_err(netdev,
1123 "Failed to set no of Tx queues: %d\n", tx_queues);
1124 return err;
1125 }
1126
1127 err = netif_set_real_num_rx_queues(netdev, rx_queues);
1128 if (err)
1129 netdev_err(netdev,
1130 "Failed to set no of Rx queues: %d\n", rx_queues);
1131 return err;
1132 }
1133 EXPORT_SYMBOL(otx2_set_real_num_queues);
1134
otx2_q_intr_handler(int irq,void * data)1135 static irqreturn_t otx2_q_intr_handler(int irq, void *data)
1136 {
1137 struct otx2_nic *pf = data;
1138 u64 val, *ptr;
1139 u64 qidx = 0;
1140
1141 /* CQ */
1142 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) {
1143 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT);
1144 val = otx2_atomic64_add((qidx << 44), ptr);
1145
1146 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) |
1147 (val & NIX_CQERRINT_BITS));
1148 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42))))
1149 continue;
1150
1151 if (val & BIT_ULL(42)) {
1152 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1153 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1154 } else {
1155 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
1156 netdev_err(pf->netdev, "CQ%lld: Doorbell error",
1157 qidx);
1158 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
1159 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM",
1160 qidx);
1161 }
1162
1163 schedule_work(&pf->reset_task);
1164 }
1165
1166 /* SQ */
1167 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) {
1168 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);
1169 val = otx2_atomic64_add((qidx << 44), ptr);
1170 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) |
1171 (val & NIX_SQINT_BITS));
1172
1173 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42))))
1174 continue;
1175
1176 if (val & BIT_ULL(42)) {
1177 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1178 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1179 } else {
1180 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) {
1181 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx",
1182 qidx,
1183 otx2_read64(pf,
1184 NIX_LF_SQ_OP_ERR_DBG));
1185 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG,
1186 BIT_ULL(44));
1187 }
1188 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
1189 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n",
1190 qidx,
1191 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG));
1192 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG,
1193 BIT_ULL(44));
1194 }
1195 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) {
1196 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx",
1197 qidx,
1198 otx2_read64(pf,
1199 NIX_LF_SEND_ERR_DBG));
1200 otx2_write64(pf, NIX_LF_SEND_ERR_DBG,
1201 BIT_ULL(44));
1202 }
1203 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
1204 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
1205 qidx);
1206 }
1207
1208 schedule_work(&pf->reset_task);
1209 }
1210
1211 return IRQ_HANDLED;
1212 }
1213
otx2_cq_intr_handler(int irq,void * cq_irq)1214 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq)
1215 {
1216 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq;
1217 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev;
1218 int qidx = cq_poll->cint_idx;
1219
1220 /* Disable interrupts.
1221 *
1222 * Completion interrupts behave in a level-triggered interrupt
1223 * fashion, and hence have to be cleared only after it is serviced.
1224 */
1225 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1226
1227 /* Schedule NAPI */
1228 napi_schedule_irqoff(&cq_poll->napi);
1229
1230 return IRQ_HANDLED;
1231 }
1232
otx2_disable_napi(struct otx2_nic * pf)1233 static void otx2_disable_napi(struct otx2_nic *pf)
1234 {
1235 struct otx2_qset *qset = &pf->qset;
1236 struct otx2_cq_poll *cq_poll;
1237 int qidx;
1238
1239 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1240 cq_poll = &qset->napi[qidx];
1241 napi_disable(&cq_poll->napi);
1242 netif_napi_del(&cq_poll->napi);
1243 }
1244 }
1245
otx2_free_cq_res(struct otx2_nic * pf)1246 static void otx2_free_cq_res(struct otx2_nic *pf)
1247 {
1248 struct otx2_qset *qset = &pf->qset;
1249 struct otx2_cq_queue *cq;
1250 int qidx;
1251
1252 /* Disable CQs */
1253 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false);
1254 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1255 cq = &qset->cq[qidx];
1256 qmem_free(pf->dev, cq->cqe);
1257 }
1258 }
1259
otx2_free_sq_res(struct otx2_nic * pf)1260 static void otx2_free_sq_res(struct otx2_nic *pf)
1261 {
1262 struct otx2_qset *qset = &pf->qset;
1263 struct otx2_snd_queue *sq;
1264 int qidx;
1265
1266 /* Disable SQs */
1267 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false);
1268 /* Free SQB pointers */
1269 otx2_sq_free_sqbs(pf);
1270 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) {
1271 sq = &qset->sq[qidx];
1272 qmem_free(pf->dev, sq->sqe);
1273 qmem_free(pf->dev, sq->tso_hdrs);
1274 kfree(sq->sg);
1275 kfree(sq->sqb_ptrs);
1276 }
1277 }
1278
otx2_init_hw_resources(struct otx2_nic * pf)1279 static int otx2_init_hw_resources(struct otx2_nic *pf)
1280 {
1281 struct mbox *mbox = &pf->mbox;
1282 struct otx2_hw *hw = &pf->hw;
1283 struct msg_req *req;
1284 int err = 0, lvl;
1285
1286 /* Set required NPA LF's pool counts
1287 * Auras and Pools are used in a 1:1 mapping,
1288 * so, aura count = pool count.
1289 */
1290 hw->rqpool_cnt = hw->rx_queues;
1291 hw->sqpool_cnt = hw->tx_queues;
1292 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt;
1293
1294 /* Get the size of receive buffers to allocate */
1295 pf->rbsize = RCV_FRAG_LEN(OTX2_HW_TIMESTAMP_LEN + pf->netdev->mtu +
1296 OTX2_ETH_HLEN);
1297
1298 mutex_lock(&mbox->lock);
1299 /* NPA init */
1300 err = otx2_config_npa(pf);
1301 if (err)
1302 goto exit;
1303
1304 /* NIX init */
1305 err = otx2_config_nix(pf);
1306 if (err)
1307 goto err_free_npa_lf;
1308
1309 /* Enable backpressure */
1310 otx2_nix_config_bp(pf, true);
1311
1312 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */
1313 err = otx2_rq_aura_pool_init(pf);
1314 if (err) {
1315 mutex_unlock(&mbox->lock);
1316 goto err_free_nix_lf;
1317 }
1318 /* Init Auras and pools used by NIX SQ, for queueing SQEs */
1319 err = otx2_sq_aura_pool_init(pf);
1320 if (err) {
1321 mutex_unlock(&mbox->lock);
1322 goto err_free_rq_ptrs;
1323 }
1324
1325 err = otx2_txsch_alloc(pf);
1326 if (err) {
1327 mutex_unlock(&mbox->lock);
1328 goto err_free_sq_ptrs;
1329 }
1330
1331 err = otx2_config_nix_queues(pf);
1332 if (err) {
1333 mutex_unlock(&mbox->lock);
1334 goto err_free_txsch;
1335 }
1336 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
1337 err = otx2_txschq_config(pf, lvl);
1338 if (err) {
1339 mutex_unlock(&mbox->lock);
1340 goto err_free_nix_queues;
1341 }
1342 }
1343 mutex_unlock(&mbox->lock);
1344 return err;
1345
1346 err_free_nix_queues:
1347 otx2_free_sq_res(pf);
1348 otx2_free_cq_res(pf);
1349 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1350 err_free_txsch:
1351 if (otx2_txschq_stop(pf))
1352 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__);
1353 err_free_sq_ptrs:
1354 otx2_sq_free_sqbs(pf);
1355 err_free_rq_ptrs:
1356 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1357 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1358 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1359 otx2_aura_pool_free(pf);
1360 err_free_nix_lf:
1361 mutex_lock(&mbox->lock);
1362 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1363 if (req) {
1364 if (otx2_sync_mbox_msg(mbox))
1365 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1366 }
1367 err_free_npa_lf:
1368 /* Reset NPA LF */
1369 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1370 if (req) {
1371 if (otx2_sync_mbox_msg(mbox))
1372 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1373 }
1374 exit:
1375 mutex_unlock(&mbox->lock);
1376 return err;
1377 }
1378
otx2_free_hw_resources(struct otx2_nic * pf)1379 static void otx2_free_hw_resources(struct otx2_nic *pf)
1380 {
1381 struct otx2_qset *qset = &pf->qset;
1382 struct mbox *mbox = &pf->mbox;
1383 struct otx2_cq_queue *cq;
1384 struct msg_req *req;
1385 int qidx, err;
1386
1387 /* Ensure all SQE are processed */
1388 otx2_sqb_flush(pf);
1389
1390 /* Stop transmission */
1391 err = otx2_txschq_stop(pf);
1392 if (err)
1393 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n");
1394
1395 mutex_lock(&mbox->lock);
1396 /* Disable backpressure */
1397 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1398 otx2_nix_config_bp(pf, false);
1399 mutex_unlock(&mbox->lock);
1400
1401 /* Disable RQs */
1402 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1403
1404 /*Dequeue all CQEs */
1405 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1406 cq = &qset->cq[qidx];
1407 if (cq->cq_type == CQ_RX)
1408 otx2_cleanup_rx_cqes(pf, cq);
1409 else
1410 otx2_cleanup_tx_cqes(pf, cq);
1411 }
1412
1413 otx2_free_sq_res(pf);
1414
1415 /* Free RQ buffer pointers*/
1416 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1417
1418 otx2_free_cq_res(pf);
1419
1420 mutex_lock(&mbox->lock);
1421 /* Reset NIX LF */
1422 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1423 if (req) {
1424 if (otx2_sync_mbox_msg(mbox))
1425 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1426 }
1427 mutex_unlock(&mbox->lock);
1428
1429 /* Disable NPA Pool and Aura hw context */
1430 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1431 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1432 otx2_aura_pool_free(pf);
1433
1434 mutex_lock(&mbox->lock);
1435 /* Reset NPA LF */
1436 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1437 if (req) {
1438 if (otx2_sync_mbox_msg(mbox))
1439 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1440 }
1441 mutex_unlock(&mbox->lock);
1442 }
1443
otx2_open(struct net_device * netdev)1444 int otx2_open(struct net_device *netdev)
1445 {
1446 struct otx2_nic *pf = netdev_priv(netdev);
1447 struct otx2_cq_poll *cq_poll = NULL;
1448 struct otx2_qset *qset = &pf->qset;
1449 int err = 0, qidx, vec;
1450 char *irq_name;
1451
1452 netif_carrier_off(netdev);
1453
1454 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tx_queues;
1455 /* RQ and SQs are mapped to different CQs,
1456 * so find out max CQ IRQs (i.e CINTs) needed.
1457 */
1458 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues);
1459 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL);
1460 if (!qset->napi)
1461 return -ENOMEM;
1462
1463 /* CQ size of RQ */
1464 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256);
1465 /* CQ size of SQ */
1466 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K);
1467
1468 err = -ENOMEM;
1469 qset->cq = kcalloc(pf->qset.cq_cnt,
1470 sizeof(struct otx2_cq_queue), GFP_KERNEL);
1471 if (!qset->cq)
1472 goto err_free_mem;
1473
1474 qset->sq = kcalloc(pf->hw.tx_queues,
1475 sizeof(struct otx2_snd_queue), GFP_KERNEL);
1476 if (!qset->sq)
1477 goto err_free_mem;
1478
1479 qset->rq = kcalloc(pf->hw.rx_queues,
1480 sizeof(struct otx2_rcv_queue), GFP_KERNEL);
1481 if (!qset->rq)
1482 goto err_free_mem;
1483
1484 err = otx2_init_hw_resources(pf);
1485 if (err)
1486 goto err_free_mem;
1487
1488 /* Register NAPI handler */
1489 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1490 cq_poll = &qset->napi[qidx];
1491 cq_poll->cint_idx = qidx;
1492 /* RQ0 & SQ0 are mapped to CINT0 and so on..
1493 * 'cq_ids[0]' points to RQ's CQ and
1494 * 'cq_ids[1]' points to SQ's CQ and
1495 */
1496 cq_poll->cq_ids[CQ_RX] =
1497 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ;
1498 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ?
1499 qidx + pf->hw.rx_queues : CINT_INVALID_CQ;
1500 cq_poll->dev = (void *)pf;
1501 netif_napi_add(netdev, &cq_poll->napi,
1502 otx2_napi_handler, NAPI_POLL_WEIGHT);
1503 napi_enable(&cq_poll->napi);
1504 }
1505
1506 /* Set maximum frame size allowed in HW */
1507 err = otx2_hw_set_mtu(pf, netdev->mtu);
1508 if (err)
1509 goto err_disable_napi;
1510
1511 /* Setup segmentation algorithms, if failed, clear offload capability */
1512 otx2_setup_segmentation(pf);
1513
1514 /* Initialize RSS */
1515 err = otx2_rss_init(pf);
1516 if (err)
1517 goto err_disable_napi;
1518
1519 /* Register Queue IRQ handlers */
1520 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START;
1521 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1522
1523 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name);
1524
1525 err = request_irq(pci_irq_vector(pf->pdev, vec),
1526 otx2_q_intr_handler, 0, irq_name, pf);
1527 if (err) {
1528 dev_err(pf->dev,
1529 "RVUPF%d: IRQ registration failed for QERR\n",
1530 rvu_get_pf(pf->pcifunc));
1531 goto err_disable_napi;
1532 }
1533
1534 /* Enable QINT IRQ */
1535 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0));
1536
1537 /* Register CQ IRQ handlers */
1538 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1539 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1540 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1541
1542 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name,
1543 qidx);
1544
1545 err = request_irq(pci_irq_vector(pf->pdev, vec),
1546 otx2_cq_intr_handler, 0, irq_name,
1547 &qset->napi[qidx]);
1548 if (err) {
1549 dev_err(pf->dev,
1550 "RVUPF%d: IRQ registration failed for CQ%d\n",
1551 rvu_get_pf(pf->pcifunc), qidx);
1552 goto err_free_cints;
1553 }
1554 vec++;
1555
1556 otx2_config_irq_coalescing(pf, qidx);
1557
1558 /* Enable CQ IRQ */
1559 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0));
1560 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0));
1561 }
1562
1563 otx2_set_cints_affinity(pf);
1564
1565 /* When reinitializing enable time stamping if it is enabled before */
1566 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) {
1567 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1568 otx2_config_hw_tx_tstamp(pf, true);
1569 }
1570 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) {
1571 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1572 otx2_config_hw_rx_tstamp(pf, true);
1573 }
1574
1575 pf->flags &= ~OTX2_FLAG_INTF_DOWN;
1576 /* 'intf_down' may be checked on any cpu */
1577 smp_wmb();
1578
1579 /* we have already received link status notification */
1580 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1581 otx2_handle_link_event(pf);
1582
1583 /* Restore pause frame settings */
1584 otx2_config_pause_frm(pf);
1585
1586 err = otx2_rxtx_enable(pf, true);
1587 if (err)
1588 goto err_tx_stop_queues;
1589
1590 return 0;
1591
1592 err_tx_stop_queues:
1593 netif_tx_stop_all_queues(netdev);
1594 netif_carrier_off(netdev);
1595 err_free_cints:
1596 otx2_free_cints(pf, qidx);
1597 vec = pci_irq_vector(pf->pdev,
1598 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1599 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1600 synchronize_irq(vec);
1601 free_irq(vec, pf);
1602 err_disable_napi:
1603 otx2_disable_napi(pf);
1604 otx2_free_hw_resources(pf);
1605 err_free_mem:
1606 kfree(qset->sq);
1607 kfree(qset->cq);
1608 kfree(qset->rq);
1609 kfree(qset->napi);
1610 return err;
1611 }
1612 EXPORT_SYMBOL(otx2_open);
1613
otx2_stop(struct net_device * netdev)1614 int otx2_stop(struct net_device *netdev)
1615 {
1616 struct otx2_nic *pf = netdev_priv(netdev);
1617 struct otx2_cq_poll *cq_poll = NULL;
1618 struct otx2_qset *qset = &pf->qset;
1619 int qidx, vec, wrk;
1620
1621 netif_carrier_off(netdev);
1622 netif_tx_stop_all_queues(netdev);
1623
1624 pf->flags |= OTX2_FLAG_INTF_DOWN;
1625 /* 'intf_down' may be checked on any cpu */
1626 smp_wmb();
1627
1628 /* First stop packet Rx/Tx */
1629 otx2_rxtx_enable(pf, false);
1630
1631 /* Cleanup Queue IRQ */
1632 vec = pci_irq_vector(pf->pdev,
1633 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1634 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1635 synchronize_irq(vec);
1636 free_irq(vec, pf);
1637
1638 /* Cleanup CQ NAPI and IRQ */
1639 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1640 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1641 /* Disable interrupt */
1642 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1643
1644 synchronize_irq(pci_irq_vector(pf->pdev, vec));
1645
1646 cq_poll = &qset->napi[qidx];
1647 napi_synchronize(&cq_poll->napi);
1648 vec++;
1649 }
1650
1651 netif_tx_disable(netdev);
1652
1653 otx2_free_hw_resources(pf);
1654 otx2_free_cints(pf, pf->hw.cint_cnt);
1655 otx2_disable_napi(pf);
1656
1657 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++)
1658 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx));
1659
1660 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++)
1661 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work);
1662 devm_kfree(pf->dev, pf->refill_wrk);
1663
1664 kfree(qset->sq);
1665 kfree(qset->cq);
1666 kfree(qset->rq);
1667 kfree(qset->napi);
1668 /* Do not clear RQ/SQ ringsize settings */
1669 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0,
1670 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt));
1671 return 0;
1672 }
1673 EXPORT_SYMBOL(otx2_stop);
1674
otx2_xmit(struct sk_buff * skb,struct net_device * netdev)1675 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev)
1676 {
1677 struct otx2_nic *pf = netdev_priv(netdev);
1678 int qidx = skb_get_queue_mapping(skb);
1679 struct otx2_snd_queue *sq;
1680 struct netdev_queue *txq;
1681
1682 /* Check for minimum and maximum packet length */
1683 if (skb->len <= ETH_HLEN ||
1684 (!skb_shinfo(skb)->gso_size && skb->len > pf->max_frs)) {
1685 dev_kfree_skb(skb);
1686 return NETDEV_TX_OK;
1687 }
1688
1689 sq = &pf->qset.sq[qidx];
1690 txq = netdev_get_tx_queue(netdev, qidx);
1691
1692 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
1693 netif_tx_stop_queue(txq);
1694
1695 /* Check again, incase SQBs got freed up */
1696 smp_mb();
1697 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
1698 > sq->sqe_thresh)
1699 netif_tx_wake_queue(txq);
1700
1701 return NETDEV_TX_BUSY;
1702 }
1703
1704 return NETDEV_TX_OK;
1705 }
1706
otx2_set_rx_mode(struct net_device * netdev)1707 static void otx2_set_rx_mode(struct net_device *netdev)
1708 {
1709 struct otx2_nic *pf = netdev_priv(netdev);
1710
1711 queue_work(pf->otx2_wq, &pf->rx_mode_work);
1712 }
1713
otx2_do_set_rx_mode(struct work_struct * work)1714 static void otx2_do_set_rx_mode(struct work_struct *work)
1715 {
1716 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work);
1717 struct net_device *netdev = pf->netdev;
1718 struct nix_rx_mode *req;
1719
1720 if (!(netdev->flags & IFF_UP))
1721 return;
1722
1723 mutex_lock(&pf->mbox.lock);
1724 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox);
1725 if (!req) {
1726 mutex_unlock(&pf->mbox.lock);
1727 return;
1728 }
1729
1730 req->mode = NIX_RX_MODE_UCAST;
1731
1732 /* We don't support MAC address filtering yet */
1733 if (netdev->flags & IFF_PROMISC)
1734 req->mode |= NIX_RX_MODE_PROMISC;
1735 else if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
1736 req->mode |= NIX_RX_MODE_ALLMULTI;
1737
1738 otx2_sync_mbox_msg(&pf->mbox);
1739 mutex_unlock(&pf->mbox.lock);
1740 }
1741
otx2_set_features(struct net_device * netdev,netdev_features_t features)1742 static int otx2_set_features(struct net_device *netdev,
1743 netdev_features_t features)
1744 {
1745 netdev_features_t changed = features ^ netdev->features;
1746 struct otx2_nic *pf = netdev_priv(netdev);
1747
1748 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev))
1749 return otx2_cgx_config_loopback(pf,
1750 features & NETIF_F_LOOPBACK);
1751 return 0;
1752 }
1753
otx2_reset_task(struct work_struct * work)1754 static void otx2_reset_task(struct work_struct *work)
1755 {
1756 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task);
1757
1758 if (!netif_running(pf->netdev))
1759 return;
1760
1761 rtnl_lock();
1762 otx2_stop(pf->netdev);
1763 pf->reset_count++;
1764 otx2_open(pf->netdev);
1765 netif_trans_update(pf->netdev);
1766 rtnl_unlock();
1767 }
1768
otx2_config_hw_rx_tstamp(struct otx2_nic * pfvf,bool enable)1769 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable)
1770 {
1771 struct msg_req *req;
1772 int err;
1773
1774 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable)
1775 return 0;
1776
1777 mutex_lock(&pfvf->mbox.lock);
1778 if (enable)
1779 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox);
1780 else
1781 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox);
1782 if (!req) {
1783 mutex_unlock(&pfvf->mbox.lock);
1784 return -ENOMEM;
1785 }
1786
1787 err = otx2_sync_mbox_msg(&pfvf->mbox);
1788 if (err) {
1789 mutex_unlock(&pfvf->mbox.lock);
1790 return err;
1791 }
1792
1793 mutex_unlock(&pfvf->mbox.lock);
1794 if (enable)
1795 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED;
1796 else
1797 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1798 return 0;
1799 }
1800
otx2_config_hw_tx_tstamp(struct otx2_nic * pfvf,bool enable)1801 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable)
1802 {
1803 struct msg_req *req;
1804 int err;
1805
1806 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable)
1807 return 0;
1808
1809 mutex_lock(&pfvf->mbox.lock);
1810 if (enable)
1811 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox);
1812 else
1813 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox);
1814 if (!req) {
1815 mutex_unlock(&pfvf->mbox.lock);
1816 return -ENOMEM;
1817 }
1818
1819 err = otx2_sync_mbox_msg(&pfvf->mbox);
1820 if (err) {
1821 mutex_unlock(&pfvf->mbox.lock);
1822 return err;
1823 }
1824
1825 mutex_unlock(&pfvf->mbox.lock);
1826 if (enable)
1827 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED;
1828 else
1829 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1830 return 0;
1831 }
1832
otx2_config_hwtstamp(struct net_device * netdev,struct ifreq * ifr)1833 static int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr)
1834 {
1835 struct otx2_nic *pfvf = netdev_priv(netdev);
1836 struct hwtstamp_config config;
1837
1838 if (!pfvf->ptp)
1839 return -ENODEV;
1840
1841 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1842 return -EFAULT;
1843
1844 /* reserved for future extensions */
1845 if (config.flags)
1846 return -EINVAL;
1847
1848 switch (config.tx_type) {
1849 case HWTSTAMP_TX_OFF:
1850 otx2_config_hw_tx_tstamp(pfvf, false);
1851 break;
1852 case HWTSTAMP_TX_ON:
1853 otx2_config_hw_tx_tstamp(pfvf, true);
1854 break;
1855 default:
1856 return -ERANGE;
1857 }
1858
1859 switch (config.rx_filter) {
1860 case HWTSTAMP_FILTER_NONE:
1861 otx2_config_hw_rx_tstamp(pfvf, false);
1862 break;
1863 case HWTSTAMP_FILTER_ALL:
1864 case HWTSTAMP_FILTER_SOME:
1865 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1866 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1867 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1868 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1869 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1870 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1871 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1872 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1873 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1874 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1875 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1876 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1877 otx2_config_hw_rx_tstamp(pfvf, true);
1878 config.rx_filter = HWTSTAMP_FILTER_ALL;
1879 break;
1880 default:
1881 return -ERANGE;
1882 }
1883
1884 memcpy(&pfvf->tstamp, &config, sizeof(config));
1885
1886 return copy_to_user(ifr->ifr_data, &config,
1887 sizeof(config)) ? -EFAULT : 0;
1888 }
1889
otx2_ioctl(struct net_device * netdev,struct ifreq * req,int cmd)1890 static int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
1891 {
1892 struct otx2_nic *pfvf = netdev_priv(netdev);
1893 struct hwtstamp_config *cfg = &pfvf->tstamp;
1894
1895 switch (cmd) {
1896 case SIOCSHWTSTAMP:
1897 return otx2_config_hwtstamp(netdev, req);
1898 case SIOCGHWTSTAMP:
1899 return copy_to_user(req->ifr_data, cfg,
1900 sizeof(*cfg)) ? -EFAULT : 0;
1901 default:
1902 return -EOPNOTSUPP;
1903 }
1904 }
1905
1906 static const struct net_device_ops otx2_netdev_ops = {
1907 .ndo_open = otx2_open,
1908 .ndo_stop = otx2_stop,
1909 .ndo_start_xmit = otx2_xmit,
1910 .ndo_set_mac_address = otx2_set_mac_address,
1911 .ndo_change_mtu = otx2_change_mtu,
1912 .ndo_set_rx_mode = otx2_set_rx_mode,
1913 .ndo_set_features = otx2_set_features,
1914 .ndo_tx_timeout = otx2_tx_timeout,
1915 .ndo_get_stats64 = otx2_get_stats64,
1916 .ndo_do_ioctl = otx2_ioctl,
1917 };
1918
otx2_wq_init(struct otx2_nic * pf)1919 static int otx2_wq_init(struct otx2_nic *pf)
1920 {
1921 pf->otx2_wq = create_singlethread_workqueue("otx2_wq");
1922 if (!pf->otx2_wq)
1923 return -ENOMEM;
1924
1925 INIT_WORK(&pf->rx_mode_work, otx2_do_set_rx_mode);
1926 INIT_WORK(&pf->reset_task, otx2_reset_task);
1927 return 0;
1928 }
1929
otx2_check_pf_usable(struct otx2_nic * nic)1930 static int otx2_check_pf_usable(struct otx2_nic *nic)
1931 {
1932 u64 rev;
1933
1934 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM));
1935 rev = (rev >> 12) & 0xFF;
1936 /* Check if AF has setup revision for RVUM block,
1937 * otherwise this driver probe should be deferred
1938 * until AF driver comes up.
1939 */
1940 if (!rev) {
1941 dev_warn(nic->dev,
1942 "AF is not initialized, deferring probe\n");
1943 return -EPROBE_DEFER;
1944 }
1945 return 0;
1946 }
1947
otx2_realloc_msix_vectors(struct otx2_nic * pf)1948 static int otx2_realloc_msix_vectors(struct otx2_nic *pf)
1949 {
1950 struct otx2_hw *hw = &pf->hw;
1951 int num_vec, err;
1952
1953 /* NPA interrupts are inot registered, so alloc only
1954 * upto NIX vector offset.
1955 */
1956 num_vec = hw->nix_msixoff;
1957 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
1958
1959 otx2_disable_mbox_intr(pf);
1960 pci_free_irq_vectors(hw->pdev);
1961 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
1962 if (err < 0) {
1963 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n",
1964 __func__, num_vec);
1965 return err;
1966 }
1967
1968 return otx2_register_mbox_intr(pf, false);
1969 }
1970
otx2_probe(struct pci_dev * pdev,const struct pci_device_id * id)1971 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1972 {
1973 struct device *dev = &pdev->dev;
1974 struct net_device *netdev;
1975 struct otx2_nic *pf;
1976 struct otx2_hw *hw;
1977 int err, qcount;
1978 int num_vec;
1979
1980 err = pcim_enable_device(pdev);
1981 if (err) {
1982 dev_err(dev, "Failed to enable PCI device\n");
1983 return err;
1984 }
1985
1986 err = pci_request_regions(pdev, DRV_NAME);
1987 if (err) {
1988 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1989 return err;
1990 }
1991
1992 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
1993 if (err) {
1994 dev_err(dev, "DMA mask config failed, abort\n");
1995 goto err_release_regions;
1996 }
1997
1998 pci_set_master(pdev);
1999
2000 /* Set number of queues */
2001 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT);
2002
2003 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount);
2004 if (!netdev) {
2005 err = -ENOMEM;
2006 goto err_release_regions;
2007 }
2008
2009 pci_set_drvdata(pdev, netdev);
2010 SET_NETDEV_DEV(netdev, &pdev->dev);
2011 pf = netdev_priv(netdev);
2012 pf->netdev = netdev;
2013 pf->pdev = pdev;
2014 pf->dev = dev;
2015 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
2016 pf->flags |= OTX2_FLAG_INTF_DOWN;
2017
2018 hw = &pf->hw;
2019 hw->pdev = pdev;
2020 hw->rx_queues = qcount;
2021 hw->tx_queues = qcount;
2022 hw->max_queues = qcount;
2023
2024 num_vec = pci_msix_vec_count(pdev);
2025 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
2026 GFP_KERNEL);
2027 if (!hw->irq_name) {
2028 err = -ENOMEM;
2029 goto err_free_netdev;
2030 }
2031
2032 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
2033 sizeof(cpumask_var_t), GFP_KERNEL);
2034 if (!hw->affinity_mask) {
2035 err = -ENOMEM;
2036 goto err_free_netdev;
2037 }
2038
2039 /* Map CSRs */
2040 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
2041 if (!pf->reg_base) {
2042 dev_err(dev, "Unable to map physical function CSRs, aborting\n");
2043 err = -ENOMEM;
2044 goto err_free_netdev;
2045 }
2046
2047 err = otx2_check_pf_usable(pf);
2048 if (err)
2049 goto err_free_netdev;
2050
2051 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT,
2052 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX);
2053 if (err < 0) {
2054 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
2055 __func__, num_vec);
2056 goto err_free_netdev;
2057 }
2058
2059 /* Init PF <=> AF mailbox stuff */
2060 err = otx2_pfaf_mbox_init(pf);
2061 if (err)
2062 goto err_free_irq_vectors;
2063
2064 /* Register mailbox interrupt */
2065 err = otx2_register_mbox_intr(pf, true);
2066 if (err)
2067 goto err_mbox_destroy;
2068
2069 /* Request AF to attach NPA and NIX LFs to this PF.
2070 * NIX and NPA LFs are needed for this PF to function as a NIC.
2071 */
2072 err = otx2_attach_npa_nix(pf);
2073 if (err)
2074 goto err_disable_mbox_intr;
2075
2076 err = otx2_realloc_msix_vectors(pf);
2077 if (err)
2078 goto err_detach_rsrc;
2079
2080 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues);
2081 if (err)
2082 goto err_detach_rsrc;
2083
2084 otx2_setup_dev_hw_settings(pf);
2085
2086 /* Assign default mac address */
2087 otx2_get_mac_from_af(netdev);
2088
2089 /* Don't check for error. Proceed without ptp */
2090 otx2_ptp_init(pf);
2091
2092 /* NPA's pool is a stack to which SW frees buffer pointers via Aura.
2093 * HW allocates buffer pointer from stack and uses it for DMA'ing
2094 * ingress packet. In some scenarios HW can free back allocated buffer
2095 * pointers to pool. This makes it impossible for SW to maintain a
2096 * parallel list where physical addresses of buffer pointers (IOVAs)
2097 * given to HW can be saved for later reference.
2098 *
2099 * So the only way to convert Rx packet's buffer address is to use
2100 * IOMMU's iova_to_phys() handler which translates the address by
2101 * walking through the translation tables.
2102 */
2103 pf->iommu_domain = iommu_get_domain_for_dev(dev);
2104
2105 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
2106 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
2107 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
2108 NETIF_F_GSO_UDP_L4);
2109 netdev->features |= netdev->hw_features;
2110
2111 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL;
2112
2113 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS;
2114 netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
2115
2116 netdev->netdev_ops = &otx2_netdev_ops;
2117
2118 /* MTU range: 64 - 9190 */
2119 netdev->min_mtu = OTX2_MIN_MTU;
2120 netdev->max_mtu = OTX2_MAX_MTU;
2121
2122 err = register_netdev(netdev);
2123 if (err) {
2124 dev_err(dev, "Failed to register netdevice\n");
2125 goto err_ptp_destroy;
2126 }
2127
2128 err = otx2_wq_init(pf);
2129 if (err)
2130 goto err_unreg_netdev;
2131
2132 otx2_set_ethtool_ops(netdev);
2133
2134 /* Enable link notifications */
2135 otx2_cgx_config_linkevents(pf, true);
2136
2137 /* Enable pause frames by default */
2138 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED;
2139 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED;
2140
2141 return 0;
2142
2143 err_unreg_netdev:
2144 unregister_netdev(netdev);
2145 err_ptp_destroy:
2146 otx2_ptp_destroy(pf);
2147 err_detach_rsrc:
2148 otx2_detach_resources(&pf->mbox);
2149 err_disable_mbox_intr:
2150 otx2_disable_mbox_intr(pf);
2151 err_mbox_destroy:
2152 otx2_pfaf_mbox_destroy(pf);
2153 err_free_irq_vectors:
2154 pci_free_irq_vectors(hw->pdev);
2155 err_free_netdev:
2156 pci_set_drvdata(pdev, NULL);
2157 free_netdev(netdev);
2158 err_release_regions:
2159 pci_release_regions(pdev);
2160 return err;
2161 }
2162
otx2_vf_link_event_task(struct work_struct * work)2163 static void otx2_vf_link_event_task(struct work_struct *work)
2164 {
2165 struct otx2_vf_config *config;
2166 struct cgx_link_info_msg *req;
2167 struct mbox_msghdr *msghdr;
2168 struct otx2_nic *pf;
2169 int vf_idx;
2170
2171 config = container_of(work, struct otx2_vf_config,
2172 link_event_work.work);
2173 vf_idx = config - config->pf->vf_configs;
2174 pf = config->pf;
2175
2176 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx,
2177 sizeof(*req), sizeof(struct msg_rsp));
2178 if (!msghdr) {
2179 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx);
2180 return;
2181 }
2182
2183 req = (struct cgx_link_info_msg *)msghdr;
2184 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
2185 req->hdr.sig = OTX2_MBOX_REQ_SIG;
2186 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info));
2187
2188 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx);
2189 }
2190
otx2_sriov_enable(struct pci_dev * pdev,int numvfs)2191 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs)
2192 {
2193 struct net_device *netdev = pci_get_drvdata(pdev);
2194 struct otx2_nic *pf = netdev_priv(netdev);
2195 int ret, i;
2196
2197 /* Init PF <=> VF mailbox stuff */
2198 ret = otx2_pfvf_mbox_init(pf, numvfs);
2199 if (ret)
2200 return ret;
2201
2202 ret = otx2_register_pfvf_mbox_intr(pf, numvfs);
2203 if (ret)
2204 goto free_mbox;
2205
2206 pf->vf_configs = kcalloc(numvfs, sizeof(struct otx2_vf_config),
2207 GFP_KERNEL);
2208 if (!pf->vf_configs) {
2209 ret = -ENOMEM;
2210 goto free_intr;
2211 }
2212
2213 for (i = 0; i < numvfs; i++) {
2214 pf->vf_configs[i].pf = pf;
2215 pf->vf_configs[i].intf_down = true;
2216 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work,
2217 otx2_vf_link_event_task);
2218 }
2219
2220 ret = otx2_pf_flr_init(pf, numvfs);
2221 if (ret)
2222 goto free_configs;
2223
2224 ret = otx2_register_flr_me_intr(pf, numvfs);
2225 if (ret)
2226 goto free_flr;
2227
2228 ret = pci_enable_sriov(pdev, numvfs);
2229 if (ret)
2230 goto free_flr_intr;
2231
2232 return numvfs;
2233 free_flr_intr:
2234 otx2_disable_flr_me_intr(pf);
2235 free_flr:
2236 otx2_flr_wq_destroy(pf);
2237 free_configs:
2238 kfree(pf->vf_configs);
2239 free_intr:
2240 otx2_disable_pfvf_mbox_intr(pf, numvfs);
2241 free_mbox:
2242 otx2_pfvf_mbox_destroy(pf);
2243 return ret;
2244 }
2245
otx2_sriov_disable(struct pci_dev * pdev)2246 static int otx2_sriov_disable(struct pci_dev *pdev)
2247 {
2248 struct net_device *netdev = pci_get_drvdata(pdev);
2249 struct otx2_nic *pf = netdev_priv(netdev);
2250 int numvfs = pci_num_vf(pdev);
2251 int i;
2252
2253 if (!numvfs)
2254 return 0;
2255
2256 pci_disable_sriov(pdev);
2257
2258 for (i = 0; i < pci_num_vf(pdev); i++)
2259 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work);
2260 kfree(pf->vf_configs);
2261
2262 otx2_disable_flr_me_intr(pf);
2263 otx2_flr_wq_destroy(pf);
2264 otx2_disable_pfvf_mbox_intr(pf, numvfs);
2265 otx2_pfvf_mbox_destroy(pf);
2266
2267 return 0;
2268 }
2269
otx2_sriov_configure(struct pci_dev * pdev,int numvfs)2270 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs)
2271 {
2272 if (numvfs == 0)
2273 return otx2_sriov_disable(pdev);
2274 else
2275 return otx2_sriov_enable(pdev, numvfs);
2276 }
2277
otx2_remove(struct pci_dev * pdev)2278 static void otx2_remove(struct pci_dev *pdev)
2279 {
2280 struct net_device *netdev = pci_get_drvdata(pdev);
2281 struct otx2_nic *pf;
2282
2283 if (!netdev)
2284 return;
2285
2286 pf = netdev_priv(netdev);
2287
2288 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED)
2289 otx2_config_hw_tx_tstamp(pf, false);
2290 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)
2291 otx2_config_hw_rx_tstamp(pf, false);
2292
2293 cancel_work_sync(&pf->reset_task);
2294 /* Disable link notifications */
2295 otx2_cgx_config_linkevents(pf, false);
2296
2297 unregister_netdev(netdev);
2298 otx2_sriov_disable(pf->pdev);
2299 if (pf->otx2_wq)
2300 destroy_workqueue(pf->otx2_wq);
2301
2302 otx2_ptp_destroy(pf);
2303 otx2_detach_resources(&pf->mbox);
2304 otx2_disable_mbox_intr(pf);
2305 otx2_pfaf_mbox_destroy(pf);
2306 pci_free_irq_vectors(pf->pdev);
2307 pci_set_drvdata(pdev, NULL);
2308 free_netdev(netdev);
2309
2310 pci_release_regions(pdev);
2311 }
2312
2313 static struct pci_driver otx2_pf_driver = {
2314 .name = DRV_NAME,
2315 .id_table = otx2_pf_id_table,
2316 .probe = otx2_probe,
2317 .shutdown = otx2_remove,
2318 .remove = otx2_remove,
2319 .sriov_configure = otx2_sriov_configure
2320 };
2321
otx2_rvupf_init_module(void)2322 static int __init otx2_rvupf_init_module(void)
2323 {
2324 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
2325
2326 return pci_register_driver(&otx2_pf_driver);
2327 }
2328
otx2_rvupf_cleanup_module(void)2329 static void __exit otx2_rvupf_cleanup_module(void)
2330 {
2331 pci_unregister_driver(&otx2_pf_driver);
2332 }
2333
2334 module_init(otx2_rvupf_init_module);
2335 module_exit(otx2_rvupf_cleanup_module);
2336
