1 /*
2 * arch/arm/mach-orion5x/common.c
3 *
4 * Core functions for Marvell Orion 5x SoCs
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/serial_8250.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/ata_platform.h>
20 #include <linux/delay.h>
21 #include <linux/clk-provider.h>
22 #include <linux/cpu.h>
23 #include <net/dsa.h>
24 #include <asm/page.h>
25 #include <asm/setup.h>
26 #include <asm/system_misc.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/time.h>
30 #include <linux/platform_data/mtd-orion_nand.h>
31 #include <linux/platform_data/usb-ehci-orion.h>
32 #include <plat/time.h>
33 #include <plat/common.h>
34
35 #include "bridge-regs.h"
36 #include "common.h"
37 #include "orion5x.h"
38
39 /*****************************************************************************
40 * I/O Address Mapping
41 ****************************************************************************/
42 static struct map_desc orion5x_io_desc[] __initdata = {
43 {
44 .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE,
45 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
46 .length = ORION5X_REGS_SIZE,
47 .type = MT_DEVICE,
48 }, {
49 .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
50 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
51 .length = ORION5X_PCIE_WA_SIZE,
52 .type = MT_DEVICE,
53 },
54 };
55
orion5x_map_io(void)56 void __init orion5x_map_io(void)
57 {
58 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
59 }
60
61
62 /*****************************************************************************
63 * CLK tree
64 ****************************************************************************/
65 static struct clk *tclk;
66
clk_init(void)67 void __init clk_init(void)
68 {
69 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk);
70
71 orion_clkdev_init(tclk);
72 }
73
74 /*****************************************************************************
75 * EHCI0
76 ****************************************************************************/
orion5x_ehci0_init(void)77 void __init orion5x_ehci0_init(void)
78 {
79 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
80 EHCI_PHY_ORION);
81 }
82
83
84 /*****************************************************************************
85 * EHCI1
86 ****************************************************************************/
orion5x_ehci1_init(void)87 void __init orion5x_ehci1_init(void)
88 {
89 orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
90 }
91
92
93 /*****************************************************************************
94 * GE00
95 ****************************************************************************/
orion5x_eth_init(struct mv643xx_eth_platform_data * eth_data)96 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
97 {
98 orion_ge00_init(eth_data,
99 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
100 IRQ_ORION5X_ETH_ERR,
101 MV643XX_TX_CSUM_DEFAULT_LIMIT);
102 }
103
104
105 /*****************************************************************************
106 * Ethernet switch
107 ****************************************************************************/
orion5x_eth_switch_init(struct dsa_chip_data * d)108 void __init orion5x_eth_switch_init(struct dsa_chip_data *d)
109 {
110 orion_ge00_switch_init(d);
111 }
112
113
114 /*****************************************************************************
115 * I2C
116 ****************************************************************************/
orion5x_i2c_init(void)117 void __init orion5x_i2c_init(void)
118 {
119 orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
120
121 }
122
123
124 /*****************************************************************************
125 * SATA
126 ****************************************************************************/
orion5x_sata_init(struct mv_sata_platform_data * sata_data)127 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
128 {
129 orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
130 }
131
132
133 /*****************************************************************************
134 * SPI
135 ****************************************************************************/
orion5x_spi_init(void)136 void __init orion5x_spi_init(void)
137 {
138 orion_spi_init(SPI_PHYS_BASE);
139 }
140
141
142 /*****************************************************************************
143 * UART0
144 ****************************************************************************/
orion5x_uart0_init(void)145 void __init orion5x_uart0_init(void)
146 {
147 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
148 IRQ_ORION5X_UART0, tclk);
149 }
150
151 /*****************************************************************************
152 * UART1
153 ****************************************************************************/
orion5x_uart1_init(void)154 void __init orion5x_uart1_init(void)
155 {
156 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
157 IRQ_ORION5X_UART1, tclk);
158 }
159
160 /*****************************************************************************
161 * XOR engine
162 ****************************************************************************/
orion5x_xor_init(void)163 void __init orion5x_xor_init(void)
164 {
165 orion_xor0_init(ORION5X_XOR_PHYS_BASE,
166 ORION5X_XOR_PHYS_BASE + 0x200,
167 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
168 }
169
170 /*****************************************************************************
171 * Cryptographic Engines and Security Accelerator (CESA)
172 ****************************************************************************/
orion5x_crypto_init(void)173 static void __init orion5x_crypto_init(void)
174 {
175 mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
176 ORION_MBUS_SRAM_ATTR,
177 ORION5X_SRAM_PHYS_BASE,
178 ORION5X_SRAM_SIZE);
179 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
180 SZ_8K, IRQ_ORION5X_CESA);
181 }
182
183 /*****************************************************************************
184 * Watchdog
185 ****************************************************************************/
186 static struct resource orion_wdt_resource[] = {
187 DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
188 DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
189 };
190
191 static struct platform_device orion_wdt_device = {
192 .name = "orion_wdt",
193 .id = -1,
194 .num_resources = ARRAY_SIZE(orion_wdt_resource),
195 .resource = orion_wdt_resource,
196 };
197
orion5x_wdt_init(void)198 static void __init orion5x_wdt_init(void)
199 {
200 platform_device_register(&orion_wdt_device);
201 }
202
203
204 /*****************************************************************************
205 * Time handling
206 ****************************************************************************/
orion5x_init_early(void)207 void __init orion5x_init_early(void)
208 {
209 u32 rev, dev;
210 const char *mbus_soc_name;
211
212 orion_time_set_base(TIMER_VIRT_BASE);
213
214 /* Initialize the MBUS driver */
215 orion5x_pcie_id(&dev, &rev);
216 if (dev == MV88F5281_DEV_ID)
217 mbus_soc_name = "marvell,orion5x-88f5281-mbus";
218 else if (dev == MV88F5182_DEV_ID)
219 mbus_soc_name = "marvell,orion5x-88f5182-mbus";
220 else if (dev == MV88F5181_DEV_ID)
221 mbus_soc_name = "marvell,orion5x-88f5181-mbus";
222 else if (dev == MV88F6183_DEV_ID)
223 mbus_soc_name = "marvell,orion5x-88f6183-mbus";
224 else
225 mbus_soc_name = NULL;
226 mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
227 ORION5X_BRIDGE_WINS_SZ,
228 ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
229 }
230
orion5x_setup_wins(void)231 void orion5x_setup_wins(void)
232 {
233 /*
234 * The PCIe windows will no longer be statically allocated
235 * here once Orion5x is migrated to the pci-mvebu driver.
236 */
237 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
238 ORION_MBUS_PCIE_IO_ATTR,
239 ORION5X_PCIE_IO_PHYS_BASE,
240 ORION5X_PCIE_IO_SIZE,
241 ORION5X_PCIE_IO_BUS_BASE);
242 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
243 ORION_MBUS_PCIE_MEM_ATTR,
244 ORION5X_PCIE_MEM_PHYS_BASE,
245 ORION5X_PCIE_MEM_SIZE);
246 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
247 ORION_MBUS_PCI_IO_ATTR,
248 ORION5X_PCI_IO_PHYS_BASE,
249 ORION5X_PCI_IO_SIZE,
250 ORION5X_PCI_IO_BUS_BASE);
251 mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
252 ORION_MBUS_PCI_MEM_ATTR,
253 ORION5X_PCI_MEM_PHYS_BASE,
254 ORION5X_PCI_MEM_SIZE);
255 }
256
257 int orion5x_tclk;
258
orion5x_find_tclk(void)259 static int __init orion5x_find_tclk(void)
260 {
261 u32 dev, rev;
262
263 orion5x_pcie_id(&dev, &rev);
264 if (dev == MV88F6183_DEV_ID &&
265 (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
266 return 133333333;
267
268 return 166666667;
269 }
270
orion5x_timer_init(void)271 void __init orion5x_timer_init(void)
272 {
273 orion5x_tclk = orion5x_find_tclk();
274
275 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
276 IRQ_ORION5X_BRIDGE, orion5x_tclk);
277 }
278
279
280 /*****************************************************************************
281 * General
282 ****************************************************************************/
283 /*
284 * Identify device ID and rev from PCIe configuration header space '0'.
285 */
orion5x_id(u32 * dev,u32 * rev,char ** dev_name)286 void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
287 {
288 orion5x_pcie_id(dev, rev);
289
290 if (*dev == MV88F5281_DEV_ID) {
291 if (*rev == MV88F5281_REV_D2) {
292 *dev_name = "MV88F5281-D2";
293 } else if (*rev == MV88F5281_REV_D1) {
294 *dev_name = "MV88F5281-D1";
295 } else if (*rev == MV88F5281_REV_D0) {
296 *dev_name = "MV88F5281-D0";
297 } else {
298 *dev_name = "MV88F5281-Rev-Unsupported";
299 }
300 } else if (*dev == MV88F5182_DEV_ID) {
301 if (*rev == MV88F5182_REV_A2) {
302 *dev_name = "MV88F5182-A2";
303 } else {
304 *dev_name = "MV88F5182-Rev-Unsupported";
305 }
306 } else if (*dev == MV88F5181_DEV_ID) {
307 if (*rev == MV88F5181_REV_B1) {
308 *dev_name = "MV88F5181-Rev-B1";
309 } else if (*rev == MV88F5181L_REV_A1) {
310 *dev_name = "MV88F5181L-Rev-A1";
311 } else {
312 *dev_name = "MV88F5181(L)-Rev-Unsupported";
313 }
314 } else if (*dev == MV88F6183_DEV_ID) {
315 if (*rev == MV88F6183_REV_B0) {
316 *dev_name = "MV88F6183-Rev-B0";
317 } else {
318 *dev_name = "MV88F6183-Rev-Unsupported";
319 }
320 } else {
321 *dev_name = "Device-Unknown";
322 }
323 }
324
orion5x_init(void)325 void __init orion5x_init(void)
326 {
327 char *dev_name;
328 u32 dev, rev;
329
330 orion5x_id(&dev, &rev, &dev_name);
331 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
332
333 /*
334 * Setup Orion address map
335 */
336 orion5x_setup_wins();
337
338 /* Setup root of clk tree */
339 clk_init();
340
341 /*
342 * Don't issue "Wait for Interrupt" instruction if we are
343 * running on D0 5281 silicon.
344 */
345 if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
346 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
347 cpu_idle_poll_ctrl(true);
348 }
349
350 /*
351 * The 5082/5181l/5182/6082/6082l/6183 have crypto
352 * while 5180n/5181/5281 don't have crypto.
353 */
354 if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
355 dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
356 orion5x_crypto_init();
357
358 /*
359 * Register watchdog driver
360 */
361 orion5x_wdt_init();
362 }
363
orion5x_restart(enum reboot_mode mode,const char * cmd)364 void orion5x_restart(enum reboot_mode mode, const char *cmd)
365 {
366 /*
367 * Enable and issue soft reset
368 */
369 orion5x_setbits(RSTOUTn_MASK, (1 << 2));
370 orion5x_setbits(CPU_SOFT_RESET, 1);
371 mdelay(200);
372 orion5x_clrbits(CPU_SOFT_RESET, 1);
373 }
374
375 /*
376 * Many orion-based systems have buggy bootloader implementations.
377 * This is a common fixup for bogus memory tags.
378 */
tag_fixup_mem32(struct tag * t,char ** from)379 void __init tag_fixup_mem32(struct tag *t, char **from)
380 {
381 for (; t->hdr.size; t = tag_next(t))
382 if (t->hdr.tag == ATAG_MEM &&
383 (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
384 t->u.mem.start & ~PAGE_MASK)) {
385 printk(KERN_WARNING
386 "Clearing invalid memory bank %dKB@0x%08x\n",
387 t->u.mem.size / 1024, t->u.mem.start);
388 t->hdr.tag = 0;
389 }
390 }
391
