1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
4  *
5  * Copyright (C) 2009-2011 Nokia Corporation
6  * Paul Walmsley
7  *
8  * XXX handle crossbar/shared link difference for L3?
9  * XXX these should be marked initdata for multi-OMAP kernels
10  */
11 #include <linux/sizes.h>
12 
13 #include "omap_hwmod.h"
14 #include "l3_2xxx.h"
15 #include "l4_2xxx.h"
16 #include "serial.h"
17 
18 #include "omap_hwmod_common_data.h"
19 
20 /*
21  * Common interconnect data
22  */
23 
24 /* L3 -> L4_CORE interface */
25 struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
26 	.master	= &omap2xxx_l3_main_hwmod,
27 	.slave	= &omap2xxx_l4_core_hwmod,
28 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
29 };
30 
31 /* MPU -> L3 interface */
32 struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
33 	.master = &omap2xxx_mpu_hwmod,
34 	.slave	= &omap2xxx_l3_main_hwmod,
35 	.user	= OCP_USER_MPU,
36 };
37 
38 /* DSS -> l3 */
39 struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
40 	.master		= &omap2xxx_dss_core_hwmod,
41 	.slave		= &omap2xxx_l3_main_hwmod,
42 	.fw = {
43 		.omap2 = {
44 			.l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
45 			.flags	= OMAP_FIREWALL_L3,
46 		},
47 	},
48 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
49 };
50 
51 /* L4_CORE -> L4_WKUP interface */
52 struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
53 	.master	= &omap2xxx_l4_core_hwmod,
54 	.slave	= &omap2xxx_l4_wkup_hwmod,
55 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
56 };
57 
58 /* L4 CORE -> UART1 interface */
59 struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
60 	.master		= &omap2xxx_l4_core_hwmod,
61 	.slave		= &omap2xxx_uart1_hwmod,
62 	.clk		= "uart1_ick",
63 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
64 };
65 
66 /* L4 CORE -> UART2 interface */
67 struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
68 	.master		= &omap2xxx_l4_core_hwmod,
69 	.slave		= &omap2xxx_uart2_hwmod,
70 	.clk		= "uart2_ick",
71 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
72 };
73 
74 /* L4 PER -> UART3 interface */
75 struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
76 	.master		= &omap2xxx_l4_core_hwmod,
77 	.slave		= &omap2xxx_uart3_hwmod,
78 	.clk		= "uart3_ick",
79 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
80 };
81 
82 /* l4 core -> mcspi1 interface */
83 struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
84 	.master		= &omap2xxx_l4_core_hwmod,
85 	.slave		= &omap2xxx_mcspi1_hwmod,
86 	.clk		= "mcspi1_ick",
87 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
88 };
89 
90 /* l4 core -> mcspi2 interface */
91 struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
92 	.master		= &omap2xxx_l4_core_hwmod,
93 	.slave		= &omap2xxx_mcspi2_hwmod,
94 	.clk		= "mcspi2_ick",
95 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
96 };
97 
98 /* l4_core -> timer2 */
99 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
100 	.master		= &omap2xxx_l4_core_hwmod,
101 	.slave		= &omap2xxx_timer2_hwmod,
102 	.clk		= "gpt2_ick",
103 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
104 };
105 
106 /* l4_core -> timer3 */
107 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
108 	.master		= &omap2xxx_l4_core_hwmod,
109 	.slave		= &omap2xxx_timer3_hwmod,
110 	.clk		= "gpt3_ick",
111 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
112 };
113 
114 /* l4_core -> timer4 */
115 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
116 	.master		= &omap2xxx_l4_core_hwmod,
117 	.slave		= &omap2xxx_timer4_hwmod,
118 	.clk		= "gpt4_ick",
119 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
120 };
121 
122 /* l4_core -> timer5 */
123 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
124 	.master		= &omap2xxx_l4_core_hwmod,
125 	.slave		= &omap2xxx_timer5_hwmod,
126 	.clk		= "gpt5_ick",
127 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
128 };
129 
130 /* l4_core -> timer6 */
131 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
132 	.master		= &omap2xxx_l4_core_hwmod,
133 	.slave		= &omap2xxx_timer6_hwmod,
134 	.clk		= "gpt6_ick",
135 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
136 };
137 
138 /* l4_core -> timer7 */
139 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
140 	.master		= &omap2xxx_l4_core_hwmod,
141 	.slave		= &omap2xxx_timer7_hwmod,
142 	.clk		= "gpt7_ick",
143 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
144 };
145 
146 /* l4_core -> timer8 */
147 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
148 	.master		= &omap2xxx_l4_core_hwmod,
149 	.slave		= &omap2xxx_timer8_hwmod,
150 	.clk		= "gpt8_ick",
151 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
152 };
153 
154 /* l4_core -> timer9 */
155 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
156 	.master		= &omap2xxx_l4_core_hwmod,
157 	.slave		= &omap2xxx_timer9_hwmod,
158 	.clk		= "gpt9_ick",
159 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
160 };
161 
162 /* l4_core -> timer10 */
163 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
164 	.master		= &omap2xxx_l4_core_hwmod,
165 	.slave		= &omap2xxx_timer10_hwmod,
166 	.clk		= "gpt10_ick",
167 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
168 };
169 
170 /* l4_core -> timer11 */
171 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
172 	.master		= &omap2xxx_l4_core_hwmod,
173 	.slave		= &omap2xxx_timer11_hwmod,
174 	.clk		= "gpt11_ick",
175 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
176 };
177 
178 /* l4_core -> timer12 */
179 struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
180 	.master		= &omap2xxx_l4_core_hwmod,
181 	.slave		= &omap2xxx_timer12_hwmod,
182 	.clk		= "gpt12_ick",
183 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
184 };
185 
186 /* l4_core -> dss */
187 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
188 	.master		= &omap2xxx_l4_core_hwmod,
189 	.slave		= &omap2xxx_dss_core_hwmod,
190 	.clk		= "dss_ick",
191 	.fw = {
192 		.omap2 = {
193 			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
194 			.flags	= OMAP_FIREWALL_L4,
195 		},
196 	},
197 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
198 };
199 
200 /* l4_core -> dss_dispc */
201 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
202 	.master		= &omap2xxx_l4_core_hwmod,
203 	.slave		= &omap2xxx_dss_dispc_hwmod,
204 	.clk		= "dss_ick",
205 	.fw = {
206 		.omap2 = {
207 			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
208 			.flags	= OMAP_FIREWALL_L4,
209 		},
210 	},
211 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
212 };
213 
214 /* l4_core -> dss_rfbi */
215 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
216 	.master		= &omap2xxx_l4_core_hwmod,
217 	.slave		= &omap2xxx_dss_rfbi_hwmod,
218 	.clk		= "dss_ick",
219 	.fw = {
220 		.omap2 = {
221 			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
222 			.flags	= OMAP_FIREWALL_L4,
223 		},
224 	},
225 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
226 };
227 
228 /* l4_core -> dss_venc */
229 struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
230 	.master		= &omap2xxx_l4_core_hwmod,
231 	.slave		= &omap2xxx_dss_venc_hwmod,
232 	.clk		= "dss_ick",
233 	.fw = {
234 		.omap2 = {
235 			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
236 			.flags	= OMAP_FIREWALL_L4,
237 		},
238 	},
239 	.flags		= OCPIF_SWSUP_IDLE,
240 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
241 };
242 
243 /* l4_core -> rng */
244 struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
245 	.master		= &omap2xxx_l4_core_hwmod,
246 	.slave		= &omap2xxx_rng_hwmod,
247 	.clk		= "rng_ick",
248 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
249 };
250 
251 /* l4 core -> sham interface */
252 struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
253 	.master		= &omap2xxx_l4_core_hwmod,
254 	.slave		= &omap2xxx_sham_hwmod,
255 	.clk		= "sha_ick",
256 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
257 };
258 
259 /* l4 core -> aes interface */
260 struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
261 	.master		= &omap2xxx_l4_core_hwmod,
262 	.slave		= &omap2xxx_aes_hwmod,
263 	.clk		= "aes_ick",
264 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
265 };
266