1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2016 Realtek Corporation.
5 *
6 * Contact Information:
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
9 * Hsinchu 300, Taiwan.
10 *
11 * Larry Finger <Larry.Finger@lwfinger.net>
12 *
13 *****************************************************************************/
14
15 #include "../mp_precomp.h"
16 #include "../phydm_precomp.h"
17
odm_config_rf_reg_8822b(struct phy_dm_struct * dm,u32 addr,u32 data,enum odm_rf_radio_path RF_PATH,u32 reg_addr)18 void odm_config_rf_reg_8822b(struct phy_dm_struct *dm, u32 addr, u32 data,
19 enum odm_rf_radio_path RF_PATH, u32 reg_addr)
20 {
21 if (addr == 0xffe) {
22 ODM_sleep_ms(50);
23 } else if (addr == 0xfe) {
24 ODM_delay_us(100);
25 } else {
26 odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
27
28 /* Add 1us delay between BB/RF register setting. */
29 ODM_delay_us(1);
30 }
31 }
32
odm_config_rf_radio_a_8822b(struct phy_dm_struct * dm,u32 addr,u32 data)33 void odm_config_rf_radio_a_8822b(struct phy_dm_struct *dm, u32 addr, u32 data)
34 {
35 u32 content = 0x1000; /* RF_Content: radioa_txt */
36 u32 maskfor_phy_set = (u32)(content & 0xE000);
37
38 odm_config_rf_reg_8822b(dm, addr, data, ODM_RF_PATH_A,
39 addr | maskfor_phy_set);
40
41 ODM_RT_TRACE(
42 dm, ODM_COMP_INIT,
43 "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
44 addr, data);
45 }
46
odm_config_rf_radio_b_8822b(struct phy_dm_struct * dm,u32 addr,u32 data)47 void odm_config_rf_radio_b_8822b(struct phy_dm_struct *dm, u32 addr, u32 data)
48 {
49 u32 content = 0x1001; /* RF_Content: radiob_txt */
50 u32 maskfor_phy_set = (u32)(content & 0xE000);
51
52 odm_config_rf_reg_8822b(dm, addr, data, ODM_RF_PATH_B,
53 addr | maskfor_phy_set);
54
55 ODM_RT_TRACE(
56 dm, ODM_COMP_INIT,
57 "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
58 addr, data);
59 }
60
odm_config_mac_8822b(struct phy_dm_struct * dm,u32 addr,u8 data)61 void odm_config_mac_8822b(struct phy_dm_struct *dm, u32 addr, u8 data)
62 {
63 odm_write_1byte(dm, addr, data);
64 ODM_RT_TRACE(
65 dm, ODM_COMP_INIT,
66 "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
67 addr, data);
68 }
69
odm_update_agc_big_jump_lmt_8822b(struct phy_dm_struct * dm,u32 addr,u32 data)70 void odm_update_agc_big_jump_lmt_8822b(struct phy_dm_struct *dm, u32 addr,
71 u32 data)
72 {
73 struct dig_thres *dig_tab = &dm->dm_dig_table;
74 u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24);
75 u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16);
76 u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8);
77 static bool is_limit;
78
79 if (addr != 0x81c)
80 return;
81
82 if (bb_gain_idx > 0x3c) {
83 if ((rf_gain_idx == dig_tab->rf_gain_idx) && !is_limit) {
84 is_limit = true;
85 dig_tab->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2;
86 ODM_RT_TRACE(
87 dm, ODM_COMP_DIG,
88 "===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n",
89 agc_table_idx,
90 dig_tab->big_jump_lmt[agc_table_idx]);
91 }
92 } else {
93 is_limit = false;
94 }
95
96 dig_tab->rf_gain_idx = rf_gain_idx;
97 }
98
odm_config_bb_agc_8822b(struct phy_dm_struct * dm,u32 addr,u32 bitmask,u32 data)99 void odm_config_bb_agc_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
100 u32 data)
101 {
102 odm_update_agc_big_jump_lmt_8822b(dm, addr, data);
103
104 odm_set_bb_reg(dm, addr, bitmask, data);
105
106 /* Add 1us delay between BB/RF register setting. */
107 ODM_delay_us(1);
108
109 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [AGC_TAB] %08X %08X\n",
110 __func__, addr, data);
111 }
112
odm_config_bb_phy_reg_pg_8822b(struct phy_dm_struct * dm,u32 band,u32 rf_path,u32 tx_num,u32 addr,u32 bitmask,u32 data)113 void odm_config_bb_phy_reg_pg_8822b(struct phy_dm_struct *dm, u32 band,
114 u32 rf_path, u32 tx_num, u32 addr,
115 u32 bitmask, u32 data)
116 {
117 if (addr == 0xfe || addr == 0xffe) {
118 ODM_sleep_ms(50);
119 } else {
120 phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num,
121 addr, bitmask, data);
122 }
123 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [PHY_REG] %08X %08X %08X\n",
124 __func__, addr, bitmask, data);
125 }
126
odm_config_bb_phy_8822b(struct phy_dm_struct * dm,u32 addr,u32 bitmask,u32 data)127 void odm_config_bb_phy_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
128 u32 data)
129 {
130 if (addr == 0xfe)
131 ODM_sleep_ms(50);
132 else if (addr == 0xfd)
133 ODM_delay_ms(5);
134 else if (addr == 0xfc)
135 ODM_delay_ms(1);
136 else if (addr == 0xfb)
137 ODM_delay_us(50);
138 else if (addr == 0xfa)
139 ODM_delay_us(5);
140 else if (addr == 0xf9)
141 ODM_delay_us(1);
142 else
143 odm_set_bb_reg(dm, addr, bitmask, data);
144
145 /* Add 1us delay between BB/RF register setting. */
146 ODM_delay_us(1);
147 ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [PHY_REG] %08X %08X\n",
148 __func__, addr, data);
149 }
150
odm_config_bb_txpwr_lmt_8822b(struct phy_dm_struct * dm,u8 * regulation,u8 * band,u8 * bandwidth,u8 * rate_section,u8 * rf_path,u8 * channel,u8 * power_limit)151 void odm_config_bb_txpwr_lmt_8822b(struct phy_dm_struct *dm, u8 *regulation,
152 u8 *band, u8 *bandwidth, u8 *rate_section,
153 u8 *rf_path, u8 *channel, u8 *power_limit)
154 {
155 phy_set_tx_power_limit(dm, regulation, band, bandwidth, rate_section,
156 rf_path, channel, power_limit);
157 }
158