1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2017 Cavium, Inc.
7 * Copyright (C) 2008 Wind River Systems
8 */
9
10 #include <linux/etherdevice.h>
11 #include <linux/of_platform.h>
12 #include <linux/of_fdt.h>
13 #include <linux/libfdt.h>
14
15 #include <asm/octeon/octeon.h>
16 #include <asm/octeon/cvmx-helper-board.h>
17
18 #ifdef CONFIG_USB
19 #include <linux/usb/ehci_def.h>
20 #include <linux/usb/ehci_pdriver.h>
21 #include <linux/usb/ohci_pdriver.h>
22 #include <asm/octeon/cvmx-uctlx-defs.h>
23
24 #define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
25 #define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
26
27 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
28
29 static int octeon2_usb_clock_start_cnt;
30
octeon2_usb_reset(void)31 static int __init octeon2_usb_reset(void)
32 {
33 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
34 u32 ucmd;
35
36 if (!OCTEON_IS_OCTEON2())
37 return 0;
38
39 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
40 if (clk_rst_ctl.s.hrst) {
41 ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD);
42 ucmd &= ~CMD_RUN;
43 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
44 mdelay(2);
45 ucmd |= CMD_RESET;
46 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
47 ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD);
48 ucmd |= CMD_RUN;
49 cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd);
50 }
51
52 return 0;
53 }
54 arch_initcall(octeon2_usb_reset);
55
octeon2_usb_clocks_start(struct device * dev)56 static void octeon2_usb_clocks_start(struct device *dev)
57 {
58 u64 div;
59 union cvmx_uctlx_if_ena if_ena;
60 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
61 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
62 int i;
63 unsigned long io_clk_64_to_ns;
64 u32 clock_rate = 12000000;
65 bool is_crystal_clock = false;
66
67
68 mutex_lock(&octeon2_usb_clocks_mutex);
69
70 octeon2_usb_clock_start_cnt++;
71 if (octeon2_usb_clock_start_cnt != 1)
72 goto exit;
73
74 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
75
76 if (dev->of_node) {
77 struct device_node *uctl_node;
78 const char *clock_type;
79
80 uctl_node = of_get_parent(dev->of_node);
81 if (!uctl_node) {
82 dev_err(dev, "No UCTL device node\n");
83 goto exit;
84 }
85 i = of_property_read_u32(uctl_node,
86 "refclk-frequency", &clock_rate);
87 if (i) {
88 dev_err(dev, "No UCTL \"refclk-frequency\"\n");
89 goto exit;
90 }
91 i = of_property_read_string(uctl_node,
92 "refclk-type", &clock_type);
93
94 if (!i && strcmp("crystal", clock_type) == 0)
95 is_crystal_clock = true;
96 }
97
98 /*
99 * Step 1: Wait for voltages stable. That surely happened
100 * before starting the kernel.
101 *
102 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
103 */
104 if_ena.u64 = 0;
105 if_ena.s.en = 1;
106 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
107
108 for (i = 0; i <= 1; i++) {
109 port_ctl_status.u64 =
110 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
111 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
112 port_ctl_status.s.txvreftune = 15;
113 port_ctl_status.s.txrisetune = 1;
114 port_ctl_status.s.txpreemphasistune = 1;
115 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
116 port_ctl_status.u64);
117 }
118
119 /* Step 3: Configure the reference clock, PHY, and HCLK */
120 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
121
122 /*
123 * If the UCTL looks like it has already been started, skip
124 * the initialization, otherwise bus errors are obtained.
125 */
126 if (clk_rst_ctl.s.hrst)
127 goto end_clock;
128 /* 3a */
129 clk_rst_ctl.s.p_por = 1;
130 clk_rst_ctl.s.hrst = 0;
131 clk_rst_ctl.s.p_prst = 0;
132 clk_rst_ctl.s.h_clkdiv_rst = 0;
133 clk_rst_ctl.s.o_clkdiv_rst = 0;
134 clk_rst_ctl.s.h_clkdiv_en = 0;
135 clk_rst_ctl.s.o_clkdiv_en = 0;
136 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
137
138 /* 3b */
139 clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
140 switch (clock_rate) {
141 default:
142 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
143 clock_rate);
144 /* Fall through */
145 case 12000000:
146 clk_rst_ctl.s.p_refclk_div = 0;
147 break;
148 case 24000000:
149 clk_rst_ctl.s.p_refclk_div = 1;
150 break;
151 case 48000000:
152 clk_rst_ctl.s.p_refclk_div = 2;
153 break;
154 }
155 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
156
157 /* 3c */
158 div = octeon_get_io_clock_rate() / 130000000ull;
159
160 switch (div) {
161 case 0:
162 div = 1;
163 break;
164 case 1:
165 case 2:
166 case 3:
167 case 4:
168 break;
169 case 5:
170 div = 4;
171 break;
172 case 6:
173 case 7:
174 div = 6;
175 break;
176 case 8:
177 case 9:
178 case 10:
179 case 11:
180 div = 8;
181 break;
182 default:
183 div = 12;
184 break;
185 }
186 clk_rst_ctl.s.h_div = div;
187 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
188 /* Read it back, */
189 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
190 clk_rst_ctl.s.h_clkdiv_en = 1;
191 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
192 /* 3d */
193 clk_rst_ctl.s.h_clkdiv_rst = 1;
194 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
195
196 /* 3e: delay 64 io clocks */
197 ndelay(io_clk_64_to_ns);
198
199 /*
200 * Step 4: Program the power-on reset field in the UCTL
201 * clock-reset-control register.
202 */
203 clk_rst_ctl.s.p_por = 0;
204 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
205
206 /* Step 5: Wait 3 ms for the PHY clock to start. */
207 mdelay(3);
208
209 /* Steps 6..9 for ATE only, are skipped. */
210
211 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
212 /* 10a */
213 clk_rst_ctl.s.o_clkdiv_rst = 1;
214 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
215
216 /* 10b */
217 clk_rst_ctl.s.o_clkdiv_en = 1;
218 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
219
220 /* 10c */
221 ndelay(io_clk_64_to_ns);
222
223 /*
224 * Step 11: Program the PHY reset field:
225 * UCTL0_CLK_RST_CTL[P_PRST] = 1
226 */
227 clk_rst_ctl.s.p_prst = 1;
228 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
229
230 /* Step 11b */
231 udelay(1);
232
233 /* Step 11c */
234 clk_rst_ctl.s.p_prst = 0;
235 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
236
237 /* Step 11d */
238 mdelay(1);
239
240 /* Step 11e */
241 clk_rst_ctl.s.p_prst = 1;
242 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
243
244 /* Step 12: Wait 1 uS. */
245 udelay(1);
246
247 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
248 clk_rst_ctl.s.hrst = 1;
249 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
250
251 end_clock:
252 /* Set uSOF cycle period to 60,000 bits. */
253 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
254
255 exit:
256 mutex_unlock(&octeon2_usb_clocks_mutex);
257 }
258
octeon2_usb_clocks_stop(void)259 static void octeon2_usb_clocks_stop(void)
260 {
261 mutex_lock(&octeon2_usb_clocks_mutex);
262 octeon2_usb_clock_start_cnt--;
263 mutex_unlock(&octeon2_usb_clocks_mutex);
264 }
265
octeon_ehci_power_on(struct platform_device * pdev)266 static int octeon_ehci_power_on(struct platform_device *pdev)
267 {
268 octeon2_usb_clocks_start(&pdev->dev);
269 return 0;
270 }
271
octeon_ehci_power_off(struct platform_device * pdev)272 static void octeon_ehci_power_off(struct platform_device *pdev)
273 {
274 octeon2_usb_clocks_stop();
275 }
276
277 static struct usb_ehci_pdata octeon_ehci_pdata = {
278 /* Octeon EHCI matches CPU endianness. */
279 #ifdef __BIG_ENDIAN
280 .big_endian_mmio = 1,
281 #endif
282 /*
283 * We can DMA from anywhere. But the descriptors must be in
284 * the lower 4GB.
285 */
286 .dma_mask_64 = 0,
287 .power_on = octeon_ehci_power_on,
288 .power_off = octeon_ehci_power_off,
289 };
290
octeon_ehci_hw_start(struct device * dev)291 static void __init octeon_ehci_hw_start(struct device *dev)
292 {
293 union cvmx_uctlx_ehci_ctl ehci_ctl;
294
295 octeon2_usb_clocks_start(dev);
296
297 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
298 /* Use 64-bit addressing. */
299 ehci_ctl.s.ehci_64b_addr_en = 1;
300 ehci_ctl.s.l2c_addr_msb = 0;
301 #ifdef __BIG_ENDIAN
302 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
303 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
304 #else
305 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
306 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
307 ehci_ctl.s.inv_reg_a2 = 1;
308 #endif
309 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
310
311 octeon2_usb_clocks_stop();
312 }
313
octeon_ehci_device_init(void)314 static int __init octeon_ehci_device_init(void)
315 {
316 struct platform_device *pd;
317 struct device_node *ehci_node;
318 int ret = 0;
319
320 ehci_node = of_find_node_by_name(NULL, "ehci");
321 if (!ehci_node)
322 return 0;
323
324 pd = of_find_device_by_node(ehci_node);
325 of_node_put(ehci_node);
326 if (!pd)
327 return 0;
328
329 pd->dev.platform_data = &octeon_ehci_pdata;
330 octeon_ehci_hw_start(&pd->dev);
331
332 return ret;
333 }
334 device_initcall(octeon_ehci_device_init);
335
octeon_ohci_power_on(struct platform_device * pdev)336 static int octeon_ohci_power_on(struct platform_device *pdev)
337 {
338 octeon2_usb_clocks_start(&pdev->dev);
339 return 0;
340 }
341
octeon_ohci_power_off(struct platform_device * pdev)342 static void octeon_ohci_power_off(struct platform_device *pdev)
343 {
344 octeon2_usb_clocks_stop();
345 }
346
347 static struct usb_ohci_pdata octeon_ohci_pdata = {
348 /* Octeon OHCI matches CPU endianness. */
349 #ifdef __BIG_ENDIAN
350 .big_endian_mmio = 1,
351 #endif
352 .power_on = octeon_ohci_power_on,
353 .power_off = octeon_ohci_power_off,
354 };
355
octeon_ohci_hw_start(struct device * dev)356 static void __init octeon_ohci_hw_start(struct device *dev)
357 {
358 union cvmx_uctlx_ohci_ctl ohci_ctl;
359
360 octeon2_usb_clocks_start(dev);
361
362 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
363 ohci_ctl.s.l2c_addr_msb = 0;
364 #ifdef __BIG_ENDIAN
365 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
366 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
367 #else
368 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
369 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
370 ohci_ctl.s.inv_reg_a2 = 1;
371 #endif
372 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
373
374 octeon2_usb_clocks_stop();
375 }
376
octeon_ohci_device_init(void)377 static int __init octeon_ohci_device_init(void)
378 {
379 struct platform_device *pd;
380 struct device_node *ohci_node;
381 int ret = 0;
382
383 ohci_node = of_find_node_by_name(NULL, "ohci");
384 if (!ohci_node)
385 return 0;
386
387 pd = of_find_device_by_node(ohci_node);
388 of_node_put(ohci_node);
389 if (!pd)
390 return 0;
391
392 pd->dev.platform_data = &octeon_ohci_pdata;
393 octeon_ohci_hw_start(&pd->dev);
394
395 return ret;
396 }
397 device_initcall(octeon_ohci_device_init);
398
399 #endif /* CONFIG_USB */
400
401 /* Octeon Random Number Generator. */
octeon_rng_device_init(void)402 static int __init octeon_rng_device_init(void)
403 {
404 struct platform_device *pd;
405 int ret = 0;
406
407 struct resource rng_resources[] = {
408 {
409 .flags = IORESOURCE_MEM,
410 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
411 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
412 }, {
413 .flags = IORESOURCE_MEM,
414 .start = cvmx_build_io_address(8, 0),
415 .end = cvmx_build_io_address(8, 0) + 0x7
416 }
417 };
418
419 pd = platform_device_alloc("octeon_rng", -1);
420 if (!pd) {
421 ret = -ENOMEM;
422 goto out;
423 }
424
425 ret = platform_device_add_resources(pd, rng_resources,
426 ARRAY_SIZE(rng_resources));
427 if (ret)
428 goto fail;
429
430 ret = platform_device_add(pd);
431 if (ret)
432 goto fail;
433
434 return ret;
435 fail:
436 platform_device_put(pd);
437
438 out:
439 return ret;
440 }
441 device_initcall(octeon_rng_device_init);
442
443 const struct of_device_id octeon_ids[] __initconst = {
444 { .compatible = "simple-bus", },
445 { .compatible = "cavium,octeon-6335-uctl", },
446 { .compatible = "cavium,octeon-5750-usbn", },
447 { .compatible = "cavium,octeon-3860-bootbus", },
448 { .compatible = "cavium,mdio-mux", },
449 { .compatible = "gpio-leds", },
450 { .compatible = "cavium,octeon-7130-usb-uctl", },
451 {},
452 };
453
octeon_has_88e1145(void)454 static bool __init octeon_has_88e1145(void)
455 {
456 return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
457 !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
458 !OCTEON_IS_MODEL(OCTEON_CN56XX);
459 }
460
octeon_fdt_set_phy(int eth,int phy_addr)461 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
462 {
463 const __be32 *phy_handle;
464 const __be32 *alt_phy_handle;
465 const __be32 *reg;
466 u32 phandle;
467 int phy;
468 int alt_phy;
469 const char *p;
470 int current_len;
471 char new_name[20];
472
473 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
474 if (!phy_handle)
475 return;
476
477 phandle = be32_to_cpup(phy_handle);
478 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
479
480 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
481 if (alt_phy_handle) {
482 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
483
484 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
485 } else {
486 alt_phy = -1;
487 }
488
489 if (phy_addr < 0 || phy < 0) {
490 /* Delete the PHY things */
491 fdt_nop_property(initial_boot_params, eth, "phy-handle");
492 /* This one may fail */
493 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
494 if (phy >= 0)
495 fdt_nop_node(initial_boot_params, phy);
496 if (alt_phy >= 0)
497 fdt_nop_node(initial_boot_params, alt_phy);
498 return;
499 }
500
501 if (phy_addr >= 256 && alt_phy > 0) {
502 const struct fdt_property *phy_prop;
503 struct fdt_property *alt_prop;
504 u32 phy_handle_name;
505
506 /* Use the alt phy node instead.*/
507 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
508 phy_handle_name = phy_prop->nameoff;
509 fdt_nop_node(initial_boot_params, phy);
510 fdt_nop_property(initial_boot_params, eth, "phy-handle");
511 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
512 alt_prop->nameoff = phy_handle_name;
513 phy = alt_phy;
514 }
515
516 phy_addr &= 0xff;
517
518 if (octeon_has_88e1145()) {
519 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
520 memset(new_name, 0, sizeof(new_name));
521 strcpy(new_name, "marvell,88e1145");
522 p = fdt_getprop(initial_boot_params, phy, "compatible",
523 ¤t_len);
524 if (p && current_len >= strlen(new_name))
525 fdt_setprop_inplace(initial_boot_params, phy,
526 "compatible", new_name, current_len);
527 }
528
529 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
530 if (phy_addr == be32_to_cpup(reg))
531 return;
532
533 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
534
535 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
536
537 p = fdt_get_name(initial_boot_params, phy, ¤t_len);
538 if (p && current_len == strlen(new_name))
539 fdt_set_name(initial_boot_params, phy, new_name);
540 else
541 pr_err("Error: could not rename ethernet phy: <%s>", p);
542 }
543
octeon_fdt_set_mac_addr(int n,u64 * pmac)544 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
545 {
546 const u8 *old_mac;
547 int old_len;
548 u8 new_mac[6];
549 u64 mac = *pmac;
550 int r;
551
552 old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address",
553 &old_len);
554 if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac))
555 return;
556
557 new_mac[0] = (mac >> 40) & 0xff;
558 new_mac[1] = (mac >> 32) & 0xff;
559 new_mac[2] = (mac >> 24) & 0xff;
560 new_mac[3] = (mac >> 16) & 0xff;
561 new_mac[4] = (mac >> 8) & 0xff;
562 new_mac[5] = mac & 0xff;
563
564 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
565 new_mac, sizeof(new_mac));
566
567 if (r) {
568 pr_err("Setting \"local-mac-address\" failed %d", r);
569 return;
570 }
571 *pmac = mac + 1;
572 }
573
octeon_fdt_rm_ethernet(int node)574 static void __init octeon_fdt_rm_ethernet(int node)
575 {
576 const __be32 *phy_handle;
577
578 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
579 if (phy_handle) {
580 u32 ph = be32_to_cpup(phy_handle);
581 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
582
583 if (p >= 0)
584 fdt_nop_node(initial_boot_params, p);
585 }
586 fdt_nop_node(initial_boot_params, node);
587 }
588
octeon_fdt_pip_port(int iface,int i,int p,int max)589 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
590 {
591 char name_buffer[20];
592 int eth;
593 int phy_addr;
594 int ipd_port;
595
596 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
597 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
598 if (eth < 0)
599 return;
600 if (p > max) {
601 pr_debug("Deleting port %x:%x\n", i, p);
602 octeon_fdt_rm_ethernet(eth);
603 return;
604 }
605 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
606 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
607 else
608 ipd_port = 16 * i + p;
609
610 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
611 octeon_fdt_set_phy(eth, phy_addr);
612 }
613
octeon_fdt_pip_iface(int pip,int idx)614 static void __init octeon_fdt_pip_iface(int pip, int idx)
615 {
616 char name_buffer[20];
617 int iface;
618 int p;
619 int count = 0;
620
621 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
622 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
623 if (iface < 0)
624 return;
625
626 if (cvmx_helper_interface_enumerate(idx) == 0)
627 count = cvmx_helper_ports_on_interface(idx);
628
629 for (p = 0; p < 16; p++)
630 octeon_fdt_pip_port(iface, idx, p, count - 1);
631 }
632
octeon_fill_mac_addresses(void)633 void __init octeon_fill_mac_addresses(void)
634 {
635 const char *alias_prop;
636 char name_buffer[20];
637 u64 mac_addr_base;
638 int aliases;
639 int pip;
640 int i;
641
642 aliases = fdt_path_offset(initial_boot_params, "/aliases");
643 if (aliases < 0)
644 return;
645
646 mac_addr_base =
647 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
648 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
649 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
650 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
651 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
652 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
653
654 for (i = 0; i < 2; i++) {
655 int mgmt;
656
657 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i);
658 alias_prop = fdt_getprop(initial_boot_params, aliases,
659 name_buffer, NULL);
660 if (!alias_prop)
661 continue;
662 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
663 if (mgmt < 0)
664 continue;
665 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
666 }
667
668 alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
669 if (!alias_prop)
670 return;
671
672 pip = fdt_path_offset(initial_boot_params, alias_prop);
673 if (pip < 0)
674 return;
675
676 for (i = 0; i <= 4; i++) {
677 int iface;
678 int p;
679
680 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i);
681 iface = fdt_subnode_offset(initial_boot_params, pip,
682 name_buffer);
683 if (iface < 0)
684 continue;
685 for (p = 0; p < 16; p++) {
686 int eth;
687
688 snprintf(name_buffer, sizeof(name_buffer),
689 "ethernet@%x", p);
690 eth = fdt_subnode_offset(initial_boot_params, iface,
691 name_buffer);
692 if (eth < 0)
693 continue;
694 octeon_fdt_set_mac_addr(eth, &mac_addr_base);
695 }
696 }
697 }
698
octeon_prune_device_tree(void)699 int __init octeon_prune_device_tree(void)
700 {
701 int i, max_port, uart_mask;
702 const char *pip_path;
703 const char *alias_prop;
704 char name_buffer[20];
705 int aliases;
706
707 if (fdt_check_header(initial_boot_params))
708 panic("Corrupt Device Tree.");
709
710 WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,
711 "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.",
712 cvmx_board_type_to_string(octeon_bootinfo->board_type));
713
714 aliases = fdt_path_offset(initial_boot_params, "/aliases");
715 if (aliases < 0) {
716 pr_err("Error: No /aliases node in device tree.");
717 return -EINVAL;
718 }
719
720 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
721 max_port = 2;
722 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
723 max_port = 1;
724 else
725 max_port = 0;
726
727 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
728 max_port = 0;
729
730 for (i = 0; i < 2; i++) {
731 int mgmt;
732
733 snprintf(name_buffer, sizeof(name_buffer),
734 "mix%d", i);
735 alias_prop = fdt_getprop(initial_boot_params, aliases,
736 name_buffer, NULL);
737 if (alias_prop) {
738 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
739 if (mgmt < 0)
740 continue;
741 if (i >= max_port) {
742 pr_debug("Deleting mix%d\n", i);
743 octeon_fdt_rm_ethernet(mgmt);
744 fdt_nop_property(initial_boot_params, aliases,
745 name_buffer);
746 } else {
747 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
748
749 octeon_fdt_set_phy(mgmt, phy_addr);
750 }
751 }
752 }
753
754 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
755 if (pip_path) {
756 int pip = fdt_path_offset(initial_boot_params, pip_path);
757
758 if (pip >= 0)
759 for (i = 0; i <= 4; i++)
760 octeon_fdt_pip_iface(pip, i);
761 }
762
763 /* I2C */
764 if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
765 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
766 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
767 OCTEON_IS_MODEL(OCTEON_CN56XX))
768 max_port = 2;
769 else
770 max_port = 1;
771
772 for (i = 0; i < 2; i++) {
773 int i2c;
774
775 snprintf(name_buffer, sizeof(name_buffer),
776 "twsi%d", i);
777 alias_prop = fdt_getprop(initial_boot_params, aliases,
778 name_buffer, NULL);
779
780 if (alias_prop) {
781 i2c = fdt_path_offset(initial_boot_params, alias_prop);
782 if (i2c < 0)
783 continue;
784 if (i >= max_port) {
785 pr_debug("Deleting twsi%d\n", i);
786 fdt_nop_node(initial_boot_params, i2c);
787 fdt_nop_property(initial_boot_params, aliases,
788 name_buffer);
789 }
790 }
791 }
792
793 /* SMI/MDIO */
794 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
795 max_port = 4;
796 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
797 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
798 OCTEON_IS_MODEL(OCTEON_CN56XX))
799 max_port = 2;
800 else
801 max_port = 1;
802
803 for (i = 0; i < 2; i++) {
804 int i2c;
805
806 snprintf(name_buffer, sizeof(name_buffer),
807 "smi%d", i);
808 alias_prop = fdt_getprop(initial_boot_params, aliases,
809 name_buffer, NULL);
810 if (alias_prop) {
811 i2c = fdt_path_offset(initial_boot_params, alias_prop);
812 if (i2c < 0)
813 continue;
814 if (i >= max_port) {
815 pr_debug("Deleting smi%d\n", i);
816 fdt_nop_node(initial_boot_params, i2c);
817 fdt_nop_property(initial_boot_params, aliases,
818 name_buffer);
819 }
820 }
821 }
822
823 /* Serial */
824 uart_mask = 3;
825
826 /* Right now CN52XX is the only chip with a third uart */
827 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
828 uart_mask |= 4; /* uart2 */
829
830 for (i = 0; i < 3; i++) {
831 int uart;
832
833 snprintf(name_buffer, sizeof(name_buffer),
834 "uart%d", i);
835 alias_prop = fdt_getprop(initial_boot_params, aliases,
836 name_buffer, NULL);
837
838 if (alias_prop) {
839 uart = fdt_path_offset(initial_boot_params, alias_prop);
840 if (uart_mask & (1 << i)) {
841 __be32 f;
842
843 f = cpu_to_be32(octeon_get_io_clock_rate());
844 fdt_setprop_inplace(initial_boot_params,
845 uart, "clock-frequency",
846 &f, sizeof(f));
847 continue;
848 }
849 pr_debug("Deleting uart%d\n", i);
850 fdt_nop_node(initial_boot_params, uart);
851 fdt_nop_property(initial_boot_params, aliases,
852 name_buffer);
853 }
854 }
855
856 /* Compact Flash */
857 alias_prop = fdt_getprop(initial_boot_params, aliases,
858 "cf0", NULL);
859 if (alias_prop) {
860 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
861 unsigned long base_ptr, region_base, region_size;
862 unsigned long region1_base = 0;
863 unsigned long region1_size = 0;
864 int cs, bootbus;
865 bool is_16bit = false;
866 bool is_true_ide = false;
867 __be32 new_reg[6];
868 __be32 *ranges;
869 int len;
870
871 int cf = fdt_path_offset(initial_boot_params, alias_prop);
872
873 base_ptr = 0;
874 if (octeon_bootinfo->major_version == 1
875 && octeon_bootinfo->minor_version >= 1) {
876 if (octeon_bootinfo->compact_flash_common_base_addr)
877 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
878 } else {
879 base_ptr = 0x1d000800;
880 }
881
882 if (!base_ptr)
883 goto no_cf;
884
885 /* Find CS0 region. */
886 for (cs = 0; cs < 8; cs++) {
887 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
888 region_base = mio_boot_reg_cfg.s.base << 16;
889 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
890 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
891 && base_ptr < region_base + region_size) {
892 is_16bit = mio_boot_reg_cfg.s.width;
893 break;
894 }
895 }
896 if (cs >= 7) {
897 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
898 goto no_cf;
899 }
900
901 if (!(base_ptr & 0xfffful)) {
902 /*
903 * Boot loader signals availability of DMA (true_ide
904 * mode) by setting low order bits of base_ptr to
905 * zero.
906 */
907
908 /* Asume that CS1 immediately follows. */
909 mio_boot_reg_cfg.u64 =
910 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
911 region1_base = mio_boot_reg_cfg.s.base << 16;
912 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
913 if (!mio_boot_reg_cfg.s.en)
914 goto no_cf;
915 is_true_ide = true;
916
917 } else {
918 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
919 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
920 if (!is_16bit) {
921 __be32 width = cpu_to_be32(8);
922
923 fdt_setprop_inplace(initial_boot_params, cf,
924 "cavium,bus-width", &width, sizeof(width));
925 }
926 }
927 new_reg[0] = cpu_to_be32(cs);
928 new_reg[1] = cpu_to_be32(0);
929 new_reg[2] = cpu_to_be32(0x10000);
930 new_reg[3] = cpu_to_be32(cs + 1);
931 new_reg[4] = cpu_to_be32(0);
932 new_reg[5] = cpu_to_be32(0x10000);
933 fdt_setprop_inplace(initial_boot_params, cf,
934 "reg", new_reg, sizeof(new_reg));
935
936 bootbus = fdt_parent_offset(initial_boot_params, cf);
937 if (bootbus < 0)
938 goto no_cf;
939 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
940 if (!ranges || len < (5 * 8 * sizeof(__be32)))
941 goto no_cf;
942
943 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
944 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
945 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
946 if (is_true_ide) {
947 cs++;
948 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
949 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
950 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
951 }
952 goto end_cf;
953 no_cf:
954 fdt_nop_node(initial_boot_params, cf);
955
956 end_cf:
957 ;
958 }
959
960 /* 8 char LED */
961 alias_prop = fdt_getprop(initial_boot_params, aliases,
962 "led0", NULL);
963 if (alias_prop) {
964 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
965 unsigned long base_ptr, region_base, region_size;
966 int cs, bootbus;
967 __be32 new_reg[6];
968 __be32 *ranges;
969 int len;
970 int led = fdt_path_offset(initial_boot_params, alias_prop);
971
972 base_ptr = octeon_bootinfo->led_display_base_addr;
973 if (base_ptr == 0)
974 goto no_led;
975 /* Find CS0 region. */
976 for (cs = 0; cs < 8; cs++) {
977 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
978 region_base = mio_boot_reg_cfg.s.base << 16;
979 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
980 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
981 && base_ptr < region_base + region_size)
982 break;
983 }
984
985 if (cs > 7)
986 goto no_led;
987
988 new_reg[0] = cpu_to_be32(cs);
989 new_reg[1] = cpu_to_be32(0x20);
990 new_reg[2] = cpu_to_be32(0x20);
991 new_reg[3] = cpu_to_be32(cs);
992 new_reg[4] = cpu_to_be32(0);
993 new_reg[5] = cpu_to_be32(0x20);
994 fdt_setprop_inplace(initial_boot_params, led,
995 "reg", new_reg, sizeof(new_reg));
996
997 bootbus = fdt_parent_offset(initial_boot_params, led);
998 if (bootbus < 0)
999 goto no_led;
1000 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
1001 if (!ranges || len < (5 * 8 * sizeof(__be32)))
1002 goto no_led;
1003
1004 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
1005 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
1006 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
1007 goto end_led;
1008
1009 no_led:
1010 fdt_nop_node(initial_boot_params, led);
1011 end_led:
1012 ;
1013 }
1014
1015 #ifdef CONFIG_USB
1016 /* OHCI/UHCI USB */
1017 alias_prop = fdt_getprop(initial_boot_params, aliases,
1018 "uctl", NULL);
1019 if (alias_prop) {
1020 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
1021
1022 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
1023 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
1024 pr_debug("Deleting uctl\n");
1025 fdt_nop_node(initial_boot_params, uctl);
1026 fdt_nop_property(initial_boot_params, aliases, "uctl");
1027 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
1028 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
1029 /* Missing "refclk-type" defaults to crystal. */
1030 fdt_nop_property(initial_boot_params, uctl, "refclk-type");
1031 }
1032 }
1033
1034 /* DWC2 USB */
1035 alias_prop = fdt_getprop(initial_boot_params, aliases,
1036 "usbn", NULL);
1037 if (alias_prop) {
1038 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
1039
1040 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
1041 !octeon_has_feature(OCTEON_FEATURE_USB))) {
1042 pr_debug("Deleting usbn\n");
1043 fdt_nop_node(initial_boot_params, usbn);
1044 fdt_nop_property(initial_boot_params, aliases, "usbn");
1045 } else {
1046 __be32 new_f[1];
1047 enum cvmx_helper_board_usb_clock_types c;
1048
1049 c = __cvmx_helper_board_usb_get_clock_type();
1050 switch (c) {
1051 case USB_CLOCK_TYPE_REF_48:
1052 new_f[0] = cpu_to_be32(48000000);
1053 fdt_setprop_inplace(initial_boot_params, usbn,
1054 "refclk-frequency", new_f, sizeof(new_f));
1055 /* Fall through ...*/
1056 case USB_CLOCK_TYPE_REF_12:
1057 /* Missing "refclk-type" defaults to external. */
1058 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
1059 break;
1060 default:
1061 break;
1062 }
1063 }
1064 }
1065 #endif
1066
1067 return 0;
1068 }
1069
octeon_publish_devices(void)1070 static int __init octeon_publish_devices(void)
1071 {
1072 return of_platform_populate(NULL, octeon_ids, NULL, NULL);
1073 }
1074 arch_initcall(octeon_publish_devices);
1075
