1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7 #include <linux/etherdevice.h>
8 #include <linux/ethtool.h>
9 #include <linux/if_bridge.h>
10 #include <linux/if_ether.h>
11 #include <linux/if_vlan.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
17 #include <linux/skbuff.h>
18 #include <net/arp.h>
19 #include <net/netevent.h>
20 #include <net/rtnetlink.h>
21 #include <net/switchdev.h>
22
23 #include "ocelot.h"
24
25 /* MAC table entry types.
26 * ENTRYTYPE_NORMAL is subject to aging.
27 * ENTRYTYPE_LOCKED is not subject to aging.
28 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
29 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
30 */
31 enum macaccess_entry_type {
32 ENTRYTYPE_NORMAL = 0,
33 ENTRYTYPE_LOCKED,
34 ENTRYTYPE_MACv4,
35 ENTRYTYPE_MACv6,
36 };
37
38 struct ocelot_mact_entry {
39 u8 mac[ETH_ALEN];
40 u16 vid;
41 enum macaccess_entry_type type;
42 };
43
ocelot_mact_wait_for_completion(struct ocelot * ocelot)44 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
45 {
46 unsigned int val, timeout = 10;
47
48 /* Wait for the issued mac table command to be completed, or timeout.
49 * When the command read from ANA_TABLES_MACACCESS is
50 * MACACCESS_CMD_IDLE, the issued command completed successfully.
51 */
52 do {
53 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
54 val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
55 } while (val != MACACCESS_CMD_IDLE && timeout--);
56
57 if (!timeout)
58 return -ETIMEDOUT;
59
60 return 0;
61 }
62
ocelot_mact_select(struct ocelot * ocelot,const unsigned char mac[ETH_ALEN],unsigned int vid)63 static void ocelot_mact_select(struct ocelot *ocelot,
64 const unsigned char mac[ETH_ALEN],
65 unsigned int vid)
66 {
67 u32 macl = 0, mach = 0;
68
69 /* Set the MAC address to handle and the vlan associated in a format
70 * understood by the hardware.
71 */
72 mach |= vid << 16;
73 mach |= mac[0] << 8;
74 mach |= mac[1] << 0;
75 macl |= mac[2] << 24;
76 macl |= mac[3] << 16;
77 macl |= mac[4] << 8;
78 macl |= mac[5] << 0;
79
80 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
81 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
82
83 }
84
ocelot_mact_learn(struct ocelot * ocelot,int port,const unsigned char mac[ETH_ALEN],unsigned int vid,enum macaccess_entry_type type)85 static int ocelot_mact_learn(struct ocelot *ocelot, int port,
86 const unsigned char mac[ETH_ALEN],
87 unsigned int vid,
88 enum macaccess_entry_type type)
89 {
90 ocelot_mact_select(ocelot, mac, vid);
91
92 /* Issue a write command */
93 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
94 ANA_TABLES_MACACCESS_DEST_IDX(port) |
95 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
96 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
97 ANA_TABLES_MACACCESS);
98
99 return ocelot_mact_wait_for_completion(ocelot);
100 }
101
ocelot_mact_forget(struct ocelot * ocelot,const unsigned char mac[ETH_ALEN],unsigned int vid)102 static int ocelot_mact_forget(struct ocelot *ocelot,
103 const unsigned char mac[ETH_ALEN],
104 unsigned int vid)
105 {
106 ocelot_mact_select(ocelot, mac, vid);
107
108 /* Issue a forget command */
109 ocelot_write(ocelot,
110 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
111 ANA_TABLES_MACACCESS);
112
113 return ocelot_mact_wait_for_completion(ocelot);
114 }
115
ocelot_mact_init(struct ocelot * ocelot)116 static void ocelot_mact_init(struct ocelot *ocelot)
117 {
118 /* Configure the learning mode entries attributes:
119 * - Do not copy the frame to the CPU extraction queues.
120 * - Use the vlan and mac_cpoy for dmac lookup.
121 */
122 ocelot_rmw(ocelot, 0,
123 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
124 | ANA_AGENCTRL_LEARN_FWD_KILL
125 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
126 ANA_AGENCTRL);
127
128 /* Clear the MAC table */
129 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
130 }
131
ocelot_vlant_wait_for_completion(struct ocelot * ocelot)132 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
133 {
134 unsigned int val, timeout = 10;
135
136 /* Wait for the issued vlan table command to be completed, or timeout.
137 * When the command read from ANA_TABLES_VLANACCESS is
138 * VLANACCESS_CMD_IDLE, the issued command completed successfully.
139 */
140 do {
141 val = ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
142 val &= ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M;
143 } while (val != ANA_TABLES_VLANACCESS_CMD_IDLE && timeout--);
144
145 if (!timeout)
146 return -ETIMEDOUT;
147
148 return 0;
149 }
150
ocelot_vlant_set_mask(struct ocelot * ocelot,u16 vid,u32 mask)151 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
152 {
153 /* Select the VID to configure */
154 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
155 ANA_TABLES_VLANTIDX);
156 /* Set the vlan port members mask and issue a write command */
157 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
158 ANA_TABLES_VLANACCESS_CMD_WRITE,
159 ANA_TABLES_VLANACCESS);
160
161 return ocelot_vlant_wait_for_completion(ocelot);
162 }
163
ocelot_vlan_mode(struct ocelot_port * port,netdev_features_t features)164 static void ocelot_vlan_mode(struct ocelot_port *port,
165 netdev_features_t features)
166 {
167 struct ocelot *ocelot = port->ocelot;
168 u8 p = port->chip_port;
169 u32 val;
170
171 /* Filtering */
172 val = ocelot_read(ocelot, ANA_VLANMASK);
173 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
174 val |= BIT(p);
175 else
176 val &= ~BIT(p);
177 ocelot_write(ocelot, val, ANA_VLANMASK);
178 }
179
ocelot_vlan_port_apply(struct ocelot * ocelot,struct ocelot_port * port)180 static void ocelot_vlan_port_apply(struct ocelot *ocelot,
181 struct ocelot_port *port)
182 {
183 u32 val;
184
185 /* Ingress clasification (ANA_PORT_VLAN_CFG) */
186 /* Default vlan to clasify for untagged frames (may be zero) */
187 val = ANA_PORT_VLAN_CFG_VLAN_VID(port->pvid);
188 if (port->vlan_aware)
189 val |= ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
190 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
191
192 ocelot_rmw_gix(ocelot, val,
193 ANA_PORT_VLAN_CFG_VLAN_VID_M |
194 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
195 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
196 ANA_PORT_VLAN_CFG, port->chip_port);
197
198 /* Drop frames with multicast source address */
199 val = ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA;
200 if (port->vlan_aware && !port->vid)
201 /* If port is vlan-aware and tagged, drop untagged and priority
202 * tagged frames.
203 */
204 val |= ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
205 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
206 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
207 ocelot_write_gix(ocelot, val, ANA_PORT_DROP_CFG, port->chip_port);
208
209 /* Egress configuration (REW_TAG_CFG): VLAN tag type to 8021Q. */
210 val = REW_TAG_CFG_TAG_TPID_CFG(0);
211
212 if (port->vlan_aware) {
213 if (port->vid)
214 /* Tag all frames except when VID == DEFAULT_VLAN */
215 val |= REW_TAG_CFG_TAG_CFG(1);
216 else
217 /* Tag all frames */
218 val |= REW_TAG_CFG_TAG_CFG(3);
219 }
220 ocelot_rmw_gix(ocelot, val,
221 REW_TAG_CFG_TAG_TPID_CFG_M |
222 REW_TAG_CFG_TAG_CFG_M,
223 REW_TAG_CFG, port->chip_port);
224
225 /* Set default VLAN and tag type to 8021Q. */
226 val = REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q) |
227 REW_PORT_VLAN_CFG_PORT_VID(port->vid);
228 ocelot_rmw_gix(ocelot, val,
229 REW_PORT_VLAN_CFG_PORT_TPID_M |
230 REW_PORT_VLAN_CFG_PORT_VID_M,
231 REW_PORT_VLAN_CFG, port->chip_port);
232 }
233
ocelot_vlan_vid_add(struct net_device * dev,u16 vid,bool pvid,bool untagged)234 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
235 bool untagged)
236 {
237 struct ocelot_port *port = netdev_priv(dev);
238 struct ocelot *ocelot = port->ocelot;
239 int ret;
240
241 /* Add the port MAC address to with the right VLAN information */
242 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid,
243 ENTRYTYPE_LOCKED);
244
245 /* Make the port a member of the VLAN */
246 ocelot->vlan_mask[vid] |= BIT(port->chip_port);
247 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
248 if (ret)
249 return ret;
250
251 /* Default ingress vlan classification */
252 if (pvid)
253 port->pvid = vid;
254
255 /* Untagged egress vlan clasification */
256 if (untagged)
257 port->vid = vid;
258
259 ocelot_vlan_port_apply(ocelot, port);
260
261 return 0;
262 }
263
ocelot_vlan_vid_del(struct net_device * dev,u16 vid)264 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
265 {
266 struct ocelot_port *port = netdev_priv(dev);
267 struct ocelot *ocelot = port->ocelot;
268 int ret;
269
270 /* 8021q removes VID 0 on module unload for all interfaces
271 * with VLAN filtering feature. We need to keep it to receive
272 * untagged traffic.
273 */
274 if (vid == 0)
275 return 0;
276
277 /* Del the port MAC address to with the right VLAN information */
278 ocelot_mact_forget(ocelot, dev->dev_addr, vid);
279
280 /* Stop the port from being a member of the vlan */
281 ocelot->vlan_mask[vid] &= ~BIT(port->chip_port);
282 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
283 if (ret)
284 return ret;
285
286 /* Ingress */
287 if (port->pvid == vid)
288 port->pvid = 0;
289
290 /* Egress */
291 if (port->vid == vid)
292 port->vid = 0;
293
294 ocelot_vlan_port_apply(ocelot, port);
295
296 return 0;
297 }
298
ocelot_vlan_init(struct ocelot * ocelot)299 static void ocelot_vlan_init(struct ocelot *ocelot)
300 {
301 u16 port, vid;
302
303 /* Clear VLAN table, by default all ports are members of all VLANs */
304 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
305 ANA_TABLES_VLANACCESS);
306 ocelot_vlant_wait_for_completion(ocelot);
307
308 /* Configure the port VLAN memberships */
309 for (vid = 1; vid < VLAN_N_VID; vid++) {
310 ocelot->vlan_mask[vid] = 0;
311 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
312 }
313
314 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
315 * traffic. It is added automatically if 8021q module is loaded, but
316 * we can't rely on it since module may be not loaded.
317 */
318 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
319 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
320
321 /* Configure the CPU port to be VLAN aware */
322 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
323 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
324 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
325 ANA_PORT_VLAN_CFG, ocelot->num_phys_ports);
326
327 /* Set vlan ingress filter mask to all ports but the CPU port by
328 * default.
329 */
330 ocelot_write(ocelot, GENMASK(9, 0), ANA_VLANMASK);
331
332 for (port = 0; port < ocelot->num_phys_ports; port++) {
333 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
334 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
335 }
336 }
337
338 /* Watermark encode
339 * Bit 8: Unit; 0:1, 1:16
340 * Bit 7-0: Value to be multiplied with unit
341 */
ocelot_wm_enc(u16 value)342 static u16 ocelot_wm_enc(u16 value)
343 {
344 if (value >= BIT(8))
345 return BIT(8) | (value / 16);
346
347 return value;
348 }
349
ocelot_port_adjust_link(struct net_device * dev)350 static void ocelot_port_adjust_link(struct net_device *dev)
351 {
352 struct ocelot_port *port = netdev_priv(dev);
353 struct ocelot *ocelot = port->ocelot;
354 u8 p = port->chip_port;
355 int speed, atop_wm, mode = 0;
356
357 switch (dev->phydev->speed) {
358 case SPEED_10:
359 speed = OCELOT_SPEED_10;
360 break;
361 case SPEED_100:
362 speed = OCELOT_SPEED_100;
363 break;
364 case SPEED_1000:
365 speed = OCELOT_SPEED_1000;
366 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
367 break;
368 case SPEED_2500:
369 speed = OCELOT_SPEED_2500;
370 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
371 break;
372 default:
373 netdev_err(dev, "Unsupported PHY speed: %d\n",
374 dev->phydev->speed);
375 return;
376 }
377
378 phy_print_status(dev->phydev);
379
380 if (!dev->phydev->link)
381 return;
382
383 /* Only full duplex supported for now */
384 ocelot_port_writel(port, DEV_MAC_MODE_CFG_FDX_ENA |
385 mode, DEV_MAC_MODE_CFG);
386
387 /* Set MAC IFG Gaps
388 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
389 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
390 */
391 ocelot_port_writel(port, DEV_MAC_IFG_CFG_TX_IFG(5), DEV_MAC_IFG_CFG);
392
393 /* Load seed (0) and set MAC HDX late collision */
394 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
395 DEV_MAC_HDX_CFG_SEED_LOAD,
396 DEV_MAC_HDX_CFG);
397 mdelay(1);
398 ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
399 DEV_MAC_HDX_CFG);
400
401 /* Disable HDX fast control */
402 ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC);
403
404 /* SGMII only for now */
405 ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG);
406 ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
407
408 /* Enable PCS */
409 ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
410
411 /* No aneg on SGMII */
412 ocelot_port_writel(port, 0, PCS1G_ANEG_CFG);
413
414 /* No loopback */
415 ocelot_port_writel(port, 0, PCS1G_LB_CFG);
416
417 /* Set Max Length and maximum tags allowed */
418 ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG);
419 ocelot_port_writel(port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
420 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
421 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
422 DEV_MAC_TAGS_CFG);
423
424 /* Enable MAC module */
425 ocelot_port_writel(port, DEV_MAC_ENA_CFG_RX_ENA |
426 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
427
428 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
429 * reset */
430 ocelot_port_writel(port, DEV_CLOCK_CFG_LINK_SPEED(speed),
431 DEV_CLOCK_CFG);
432
433 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
434 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
435 ocelot_port_writel(port, 0, DEV_MAC_FC_MAC_LOW_CFG);
436
437 /* No PFC */
438 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
439 ANA_PFC_PFC_CFG, p);
440
441 /* Set Pause WM hysteresis
442 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
443 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
444 */
445 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
446 SYS_PAUSE_CFG_PAUSE_STOP(101) |
447 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, p);
448
449 /* Core: Enable port for frame transfer */
450 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
451 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
452 QSYS_SWITCH_PORT_MODE_PORT_ENA,
453 QSYS_SWITCH_PORT_MODE, p);
454
455 /* Flow control */
456 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
457 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
458 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
459 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
460 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
461 SYS_MAC_FC_CFG, p);
462 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, p);
463
464 /* Tail dropping watermark */
465 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
466 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
467 SYS_ATOP, p);
468 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
469 }
470
ocelot_port_open(struct net_device * dev)471 static int ocelot_port_open(struct net_device *dev)
472 {
473 struct ocelot_port *port = netdev_priv(dev);
474 struct ocelot *ocelot = port->ocelot;
475 int err;
476
477 /* Enable receiving frames on the port, and activate auto-learning of
478 * MAC addresses.
479 */
480 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
481 ANA_PORT_PORT_CFG_RECV_ENA |
482 ANA_PORT_PORT_CFG_PORTID_VAL(port->chip_port),
483 ANA_PORT_PORT_CFG, port->chip_port);
484
485 err = phy_connect_direct(dev, port->phy, &ocelot_port_adjust_link,
486 PHY_INTERFACE_MODE_NA);
487 if (err) {
488 netdev_err(dev, "Could not attach to PHY\n");
489 return err;
490 }
491
492 dev->phydev = port->phy;
493
494 phy_attached_info(port->phy);
495 phy_start(port->phy);
496 return 0;
497 }
498
ocelot_port_stop(struct net_device * dev)499 static int ocelot_port_stop(struct net_device *dev)
500 {
501 struct ocelot_port *port = netdev_priv(dev);
502
503 phy_disconnect(port->phy);
504
505 dev->phydev = NULL;
506
507 ocelot_port_writel(port, 0, DEV_MAC_ENA_CFG);
508 ocelot_rmw_rix(port->ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
509 QSYS_SWITCH_PORT_MODE, port->chip_port);
510 return 0;
511 }
512
513 /* Generate the IFH for frame injection
514 *
515 * The IFH is a 128bit-value
516 * bit 127: bypass the analyzer processing
517 * bit 56-67: destination mask
518 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
519 * bit 20-27: cpu extraction queue mask
520 * bit 16: tag type 0: C-tag, 1: S-tag
521 * bit 0-11: VID
522 */
ocelot_gen_ifh(u32 * ifh,struct frame_info * info)523 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info)
524 {
525 ifh[0] = IFH_INJ_BYPASS;
526 ifh[1] = (0xf00 & info->port) >> 8;
527 ifh[2] = (0xff & info->port) << 24;
528 ifh[3] = (info->tag_type << 16) | info->vid;
529
530 return 0;
531 }
532
ocelot_port_xmit(struct sk_buff * skb,struct net_device * dev)533 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
534 {
535 struct ocelot_port *port = netdev_priv(dev);
536 struct ocelot *ocelot = port->ocelot;
537 u32 val, ifh[IFH_LEN];
538 struct frame_info info = {};
539 u8 grp = 0; /* Send everything on CPU group 0 */
540 unsigned int i, count, last;
541
542 val = ocelot_read(ocelot, QS_INJ_STATUS);
543 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
544 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))))
545 return NETDEV_TX_BUSY;
546
547 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
548 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
549
550 info.port = BIT(port->chip_port);
551 info.tag_type = IFH_TAG_TYPE_C;
552 info.vid = skb_vlan_tag_get(skb);
553 ocelot_gen_ifh(ifh, &info);
554
555 for (i = 0; i < IFH_LEN; i++)
556 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]),
557 QS_INJ_WR, grp);
558
559 count = (skb->len + 3) / 4;
560 last = skb->len % 4;
561 for (i = 0; i < count; i++) {
562 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
563 }
564
565 /* Add padding */
566 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
567 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
568 i++;
569 }
570
571 /* Indicate EOF and valid bytes in last word */
572 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
573 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
574 QS_INJ_CTRL_EOF,
575 QS_INJ_CTRL, grp);
576
577 /* Add dummy CRC */
578 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
579 skb_tx_timestamp(skb);
580
581 dev->stats.tx_packets++;
582 dev->stats.tx_bytes += skb->len;
583 dev_kfree_skb_any(skb);
584
585 return NETDEV_TX_OK;
586 }
587
ocelot_mact_mc_reset(struct ocelot_port * port)588 static void ocelot_mact_mc_reset(struct ocelot_port *port)
589 {
590 struct ocelot *ocelot = port->ocelot;
591 struct netdev_hw_addr *ha, *n;
592
593 /* Free and forget all the MAC addresses stored in the port private mc
594 * list. These are mc addresses that were previously added by calling
595 * ocelot_mact_mc_add().
596 */
597 list_for_each_entry_safe(ha, n, &port->mc, list) {
598 ocelot_mact_forget(ocelot, ha->addr, port->pvid);
599 list_del(&ha->list);
600 kfree(ha);
601 }
602 }
603
ocelot_mact_mc_add(struct ocelot_port * port,struct netdev_hw_addr * hw_addr)604 static int ocelot_mact_mc_add(struct ocelot_port *port,
605 struct netdev_hw_addr *hw_addr)
606 {
607 struct ocelot *ocelot = port->ocelot;
608 struct netdev_hw_addr *ha = kzalloc(sizeof(*ha), GFP_KERNEL);
609
610 if (!ha)
611 return -ENOMEM;
612
613 memcpy(ha, hw_addr, sizeof(*ha));
614 list_add_tail(&ha->list, &port->mc);
615
616 ocelot_mact_learn(ocelot, PGID_CPU, ha->addr, port->pvid,
617 ENTRYTYPE_LOCKED);
618
619 return 0;
620 }
621
ocelot_set_rx_mode(struct net_device * dev)622 static void ocelot_set_rx_mode(struct net_device *dev)
623 {
624 struct ocelot_port *port = netdev_priv(dev);
625 struct ocelot *ocelot = port->ocelot;
626 struct netdev_hw_addr *ha;
627 int i;
628 u32 val;
629
630 /* This doesn't handle promiscuous mode because the bridge core is
631 * setting IFF_PROMISC on all slave interfaces and all frames would be
632 * forwarded to the CPU port.
633 */
634 val = GENMASK(ocelot->num_phys_ports - 1, 0);
635 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++)
636 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
637
638 /* Handle the device multicast addresses. First remove all the
639 * previously installed addresses and then add the latest ones to the
640 * mac table.
641 */
642 ocelot_mact_mc_reset(port);
643 netdev_for_each_mc_addr(ha, dev)
644 ocelot_mact_mc_add(port, ha);
645 }
646
ocelot_port_get_phys_port_name(struct net_device * dev,char * buf,size_t len)647 static int ocelot_port_get_phys_port_name(struct net_device *dev,
648 char *buf, size_t len)
649 {
650 struct ocelot_port *port = netdev_priv(dev);
651 int ret;
652
653 ret = snprintf(buf, len, "p%d", port->chip_port);
654 if (ret >= len)
655 return -EINVAL;
656
657 return 0;
658 }
659
ocelot_port_set_mac_address(struct net_device * dev,void * p)660 static int ocelot_port_set_mac_address(struct net_device *dev, void *p)
661 {
662 struct ocelot_port *port = netdev_priv(dev);
663 struct ocelot *ocelot = port->ocelot;
664 const struct sockaddr *addr = p;
665
666 /* Learn the new net device MAC address in the mac table. */
667 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, port->pvid,
668 ENTRYTYPE_LOCKED);
669 /* Then forget the previous one. */
670 ocelot_mact_forget(ocelot, dev->dev_addr, port->pvid);
671
672 ether_addr_copy(dev->dev_addr, addr->sa_data);
673 return 0;
674 }
675
ocelot_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)676 static void ocelot_get_stats64(struct net_device *dev,
677 struct rtnl_link_stats64 *stats)
678 {
679 struct ocelot_port *port = netdev_priv(dev);
680 struct ocelot *ocelot = port->ocelot;
681
682 /* Configure the port to read the stats from */
683 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port->chip_port),
684 SYS_STAT_CFG);
685
686 /* Get Rx stats */
687 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS);
688 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) +
689 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) +
690 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) +
691 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) +
692 ocelot_read(ocelot, SYS_COUNT_RX_64) +
693 ocelot_read(ocelot, SYS_COUNT_RX_65_127) +
694 ocelot_read(ocelot, SYS_COUNT_RX_128_255) +
695 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) +
696 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) +
697 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX);
698 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST);
699 stats->rx_dropped = dev->stats.rx_dropped;
700
701 /* Get Tx stats */
702 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS);
703 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) +
704 ocelot_read(ocelot, SYS_COUNT_TX_65_127) +
705 ocelot_read(ocelot, SYS_COUNT_TX_128_511) +
706 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) +
707 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) +
708 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX);
709 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) +
710 ocelot_read(ocelot, SYS_COUNT_TX_AGING);
711 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
712 }
713
ocelot_fdb_add(struct ndmsg * ndm,struct nlattr * tb[],struct net_device * dev,const unsigned char * addr,u16 vid,u16 flags)714 static int ocelot_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
715 struct net_device *dev, const unsigned char *addr,
716 u16 vid, u16 flags)
717 {
718 struct ocelot_port *port = netdev_priv(dev);
719 struct ocelot *ocelot = port->ocelot;
720
721 if (!vid) {
722 if (!port->vlan_aware)
723 /* If the bridge is not VLAN aware and no VID was
724 * provided, set it to pvid to ensure the MAC entry
725 * matches incoming untagged packets
726 */
727 vid = port->pvid;
728 else
729 /* If the bridge is VLAN aware a VID must be provided as
730 * otherwise the learnt entry wouldn't match any frame.
731 */
732 return -EINVAL;
733 }
734
735 return ocelot_mact_learn(ocelot, port->chip_port, addr, vid,
736 ENTRYTYPE_NORMAL);
737 }
738
ocelot_fdb_del(struct ndmsg * ndm,struct nlattr * tb[],struct net_device * dev,const unsigned char * addr,u16 vid)739 static int ocelot_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
740 struct net_device *dev,
741 const unsigned char *addr, u16 vid)
742 {
743 struct ocelot_port *port = netdev_priv(dev);
744 struct ocelot *ocelot = port->ocelot;
745
746 return ocelot_mact_forget(ocelot, addr, vid);
747 }
748
749 struct ocelot_dump_ctx {
750 struct net_device *dev;
751 struct sk_buff *skb;
752 struct netlink_callback *cb;
753 int idx;
754 };
755
ocelot_fdb_do_dump(struct ocelot_mact_entry * entry,struct ocelot_dump_ctx * dump)756 static int ocelot_fdb_do_dump(struct ocelot_mact_entry *entry,
757 struct ocelot_dump_ctx *dump)
758 {
759 u32 portid = NETLINK_CB(dump->cb->skb).portid;
760 u32 seq = dump->cb->nlh->nlmsg_seq;
761 struct nlmsghdr *nlh;
762 struct ndmsg *ndm;
763
764 if (dump->idx < dump->cb->args[2])
765 goto skip;
766
767 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
768 sizeof(*ndm), NLM_F_MULTI);
769 if (!nlh)
770 return -EMSGSIZE;
771
772 ndm = nlmsg_data(nlh);
773 ndm->ndm_family = AF_BRIDGE;
774 ndm->ndm_pad1 = 0;
775 ndm->ndm_pad2 = 0;
776 ndm->ndm_flags = NTF_SELF;
777 ndm->ndm_type = 0;
778 ndm->ndm_ifindex = dump->dev->ifindex;
779 ndm->ndm_state = NUD_REACHABLE;
780
781 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, entry->mac))
782 goto nla_put_failure;
783
784 if (entry->vid && nla_put_u16(dump->skb, NDA_VLAN, entry->vid))
785 goto nla_put_failure;
786
787 nlmsg_end(dump->skb, nlh);
788
789 skip:
790 dump->idx++;
791 return 0;
792
793 nla_put_failure:
794 nlmsg_cancel(dump->skb, nlh);
795 return -EMSGSIZE;
796 }
797
ocelot_mact_read(struct ocelot_port * port,int row,int col,struct ocelot_mact_entry * entry)798 static inline int ocelot_mact_read(struct ocelot_port *port, int row, int col,
799 struct ocelot_mact_entry *entry)
800 {
801 struct ocelot *ocelot = port->ocelot;
802 char mac[ETH_ALEN];
803 u32 val, dst, macl, mach;
804
805 /* Set row and column to read from */
806 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
807 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
808
809 /* Issue a read command */
810 ocelot_write(ocelot,
811 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
812 ANA_TABLES_MACACCESS);
813
814 if (ocelot_mact_wait_for_completion(ocelot))
815 return -ETIMEDOUT;
816
817 /* Read the entry flags */
818 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
819 if (!(val & ANA_TABLES_MACACCESS_VALID))
820 return -EINVAL;
821
822 /* If the entry read has another port configured as its destination,
823 * do not report it.
824 */
825 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
826 if (dst != port->chip_port)
827 return -EINVAL;
828
829 /* Get the entry's MAC address and VLAN id */
830 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
831 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
832
833 mac[0] = (mach >> 8) & 0xff;
834 mac[1] = (mach >> 0) & 0xff;
835 mac[2] = (macl >> 24) & 0xff;
836 mac[3] = (macl >> 16) & 0xff;
837 mac[4] = (macl >> 8) & 0xff;
838 mac[5] = (macl >> 0) & 0xff;
839
840 entry->vid = (mach >> 16) & 0xfff;
841 ether_addr_copy(entry->mac, mac);
842
843 return 0;
844 }
845
ocelot_fdb_dump(struct sk_buff * skb,struct netlink_callback * cb,struct net_device * dev,struct net_device * filter_dev,int * idx)846 static int ocelot_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb,
847 struct net_device *dev,
848 struct net_device *filter_dev, int *idx)
849 {
850 struct ocelot_port *port = netdev_priv(dev);
851 int i, j, ret = 0;
852 struct ocelot_dump_ctx dump = {
853 .dev = dev,
854 .skb = skb,
855 .cb = cb,
856 .idx = *idx,
857 };
858
859 struct ocelot_mact_entry entry;
860
861 /* Loop through all the mac tables entries. There are 1024 rows of 4
862 * entries.
863 */
864 for (i = 0; i < 1024; i++) {
865 for (j = 0; j < 4; j++) {
866 ret = ocelot_mact_read(port, i, j, &entry);
867 /* If the entry is invalid (wrong port, invalid...),
868 * skip it.
869 */
870 if (ret == -EINVAL)
871 continue;
872 else if (ret)
873 goto end;
874
875 ret = ocelot_fdb_do_dump(&entry, &dump);
876 if (ret)
877 goto end;
878 }
879 }
880
881 end:
882 *idx = dump.idx;
883 return ret;
884 }
885
ocelot_vlan_rx_add_vid(struct net_device * dev,__be16 proto,u16 vid)886 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
887 u16 vid)
888 {
889 return ocelot_vlan_vid_add(dev, vid, false, true);
890 }
891
ocelot_vlan_rx_kill_vid(struct net_device * dev,__be16 proto,u16 vid)892 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
893 u16 vid)
894 {
895 return ocelot_vlan_vid_del(dev, vid);
896 }
897
ocelot_set_features(struct net_device * dev,netdev_features_t features)898 static int ocelot_set_features(struct net_device *dev,
899 netdev_features_t features)
900 {
901 struct ocelot_port *port = netdev_priv(dev);
902 netdev_features_t changed = dev->features ^ features;
903
904 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER)
905 ocelot_vlan_mode(port, features);
906
907 return 0;
908 }
909
910 static const struct net_device_ops ocelot_port_netdev_ops = {
911 .ndo_open = ocelot_port_open,
912 .ndo_stop = ocelot_port_stop,
913 .ndo_start_xmit = ocelot_port_xmit,
914 .ndo_set_rx_mode = ocelot_set_rx_mode,
915 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name,
916 .ndo_set_mac_address = ocelot_port_set_mac_address,
917 .ndo_get_stats64 = ocelot_get_stats64,
918 .ndo_fdb_add = ocelot_fdb_add,
919 .ndo_fdb_del = ocelot_fdb_del,
920 .ndo_fdb_dump = ocelot_fdb_dump,
921 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid,
922 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid,
923 .ndo_set_features = ocelot_set_features,
924 };
925
ocelot_get_strings(struct net_device * netdev,u32 sset,u8 * data)926 static void ocelot_get_strings(struct net_device *netdev, u32 sset, u8 *data)
927 {
928 struct ocelot_port *port = netdev_priv(netdev);
929 struct ocelot *ocelot = port->ocelot;
930 int i;
931
932 if (sset != ETH_SS_STATS)
933 return;
934
935 for (i = 0; i < ocelot->num_stats; i++)
936 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
937 ETH_GSTRING_LEN);
938 }
939
ocelot_check_stats(struct work_struct * work)940 static void ocelot_check_stats(struct work_struct *work)
941 {
942 struct delayed_work *del_work = to_delayed_work(work);
943 struct ocelot *ocelot = container_of(del_work, struct ocelot, stats_work);
944 int i, j;
945
946 mutex_lock(&ocelot->stats_lock);
947
948 for (i = 0; i < ocelot->num_phys_ports; i++) {
949 /* Configure the port to read the stats from */
950 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
951
952 for (j = 0; j < ocelot->num_stats; j++) {
953 u32 val;
954 unsigned int idx = i * ocelot->num_stats + j;
955
956 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
957 ocelot->stats_layout[j].offset);
958
959 if (val < (ocelot->stats[idx] & U32_MAX))
960 ocelot->stats[idx] += (u64)1 << 32;
961
962 ocelot->stats[idx] = (ocelot->stats[idx] &
963 ~(u64)U32_MAX) + val;
964 }
965 }
966
967 cancel_delayed_work(&ocelot->stats_work);
968 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
969 OCELOT_STATS_CHECK_DELAY);
970
971 mutex_unlock(&ocelot->stats_lock);
972 }
973
ocelot_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)974 static void ocelot_get_ethtool_stats(struct net_device *dev,
975 struct ethtool_stats *stats, u64 *data)
976 {
977 struct ocelot_port *port = netdev_priv(dev);
978 struct ocelot *ocelot = port->ocelot;
979 int i;
980
981 /* check and update now */
982 ocelot_check_stats(&ocelot->stats_work.work);
983
984 /* Copy all counters */
985 for (i = 0; i < ocelot->num_stats; i++)
986 *data++ = ocelot->stats[port->chip_port * ocelot->num_stats + i];
987 }
988
ocelot_get_sset_count(struct net_device * dev,int sset)989 static int ocelot_get_sset_count(struct net_device *dev, int sset)
990 {
991 struct ocelot_port *port = netdev_priv(dev);
992 struct ocelot *ocelot = port->ocelot;
993
994 if (sset != ETH_SS_STATS)
995 return -EOPNOTSUPP;
996 return ocelot->num_stats;
997 }
998
999 static const struct ethtool_ops ocelot_ethtool_ops = {
1000 .get_strings = ocelot_get_strings,
1001 .get_ethtool_stats = ocelot_get_ethtool_stats,
1002 .get_sset_count = ocelot_get_sset_count,
1003 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1004 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1005 };
1006
ocelot_port_attr_get(struct net_device * dev,struct switchdev_attr * attr)1007 static int ocelot_port_attr_get(struct net_device *dev,
1008 struct switchdev_attr *attr)
1009 {
1010 struct ocelot_port *ocelot_port = netdev_priv(dev);
1011 struct ocelot *ocelot = ocelot_port->ocelot;
1012
1013 switch (attr->id) {
1014 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
1015 attr->u.ppid.id_len = sizeof(ocelot->base_mac);
1016 memcpy(&attr->u.ppid.id, &ocelot->base_mac,
1017 attr->u.ppid.id_len);
1018 break;
1019 default:
1020 return -EOPNOTSUPP;
1021 }
1022
1023 return 0;
1024 }
1025
ocelot_port_attr_stp_state_set(struct ocelot_port * ocelot_port,struct switchdev_trans * trans,u8 state)1026 static int ocelot_port_attr_stp_state_set(struct ocelot_port *ocelot_port,
1027 struct switchdev_trans *trans,
1028 u8 state)
1029 {
1030 struct ocelot *ocelot = ocelot_port->ocelot;
1031 u32 port_cfg;
1032 int port, i;
1033
1034 if (switchdev_trans_ph_prepare(trans))
1035 return 0;
1036
1037 if (!(BIT(ocelot_port->chip_port) & ocelot->bridge_mask))
1038 return 0;
1039
1040 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG,
1041 ocelot_port->chip_port);
1042
1043 switch (state) {
1044 case BR_STATE_FORWARDING:
1045 ocelot->bridge_fwd_mask |= BIT(ocelot_port->chip_port);
1046 /* Fallthrough */
1047 case BR_STATE_LEARNING:
1048 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1049 break;
1050
1051 default:
1052 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1053 ocelot->bridge_fwd_mask &= ~BIT(ocelot_port->chip_port);
1054 break;
1055 }
1056
1057 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG,
1058 ocelot_port->chip_port);
1059
1060 /* Apply FWD mask. The loop is needed to add/remove the current port as
1061 * a source for the other ports.
1062 */
1063 for (port = 0; port < ocelot->num_phys_ports; port++) {
1064 if (ocelot->bridge_fwd_mask & BIT(port)) {
1065 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port);
1066
1067 for (i = 0; i < ocelot->num_phys_ports; i++) {
1068 unsigned long bond_mask = ocelot->lags[i];
1069
1070 if (!bond_mask)
1071 continue;
1072
1073 if (bond_mask & BIT(port)) {
1074 mask &= ~bond_mask;
1075 break;
1076 }
1077 }
1078
1079 ocelot_write_rix(ocelot,
1080 BIT(ocelot->num_phys_ports) | mask,
1081 ANA_PGID_PGID, PGID_SRC + port);
1082 } else {
1083 /* Only the CPU port, this is compatible with link
1084 * aggregation.
1085 */
1086 ocelot_write_rix(ocelot,
1087 BIT(ocelot->num_phys_ports),
1088 ANA_PGID_PGID, PGID_SRC + port);
1089 }
1090 }
1091
1092 return 0;
1093 }
1094
ocelot_port_attr_ageing_set(struct ocelot_port * ocelot_port,unsigned long ageing_clock_t)1095 static void ocelot_port_attr_ageing_set(struct ocelot_port *ocelot_port,
1096 unsigned long ageing_clock_t)
1097 {
1098 struct ocelot *ocelot = ocelot_port->ocelot;
1099 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
1100 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
1101
1102 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(ageing_time / 2),
1103 ANA_AUTOAGE);
1104 }
1105
ocelot_port_attr_mc_set(struct ocelot_port * port,bool mc)1106 static void ocelot_port_attr_mc_set(struct ocelot_port *port, bool mc)
1107 {
1108 struct ocelot *ocelot = port->ocelot;
1109 u32 val = ocelot_read_gix(ocelot, ANA_PORT_CPU_FWD_CFG,
1110 port->chip_port);
1111
1112 if (mc)
1113 val |= ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1114 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1115 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
1116 else
1117 val &= ~(ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1118 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1119 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA);
1120
1121 ocelot_write_gix(ocelot, val, ANA_PORT_CPU_FWD_CFG, port->chip_port);
1122 }
1123
ocelot_port_attr_set(struct net_device * dev,const struct switchdev_attr * attr,struct switchdev_trans * trans)1124 static int ocelot_port_attr_set(struct net_device *dev,
1125 const struct switchdev_attr *attr,
1126 struct switchdev_trans *trans)
1127 {
1128 struct ocelot_port *ocelot_port = netdev_priv(dev);
1129 int err = 0;
1130
1131 switch (attr->id) {
1132 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
1133 ocelot_port_attr_stp_state_set(ocelot_port, trans,
1134 attr->u.stp_state);
1135 break;
1136 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
1137 ocelot_port_attr_ageing_set(ocelot_port, attr->u.ageing_time);
1138 break;
1139 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
1140 ocelot_port->vlan_aware = attr->u.vlan_filtering;
1141 ocelot_vlan_port_apply(ocelot_port->ocelot, ocelot_port);
1142 break;
1143 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
1144 ocelot_port_attr_mc_set(ocelot_port, !attr->u.mc_disabled);
1145 break;
1146 default:
1147 err = -EOPNOTSUPP;
1148 break;
1149 }
1150
1151 return err;
1152 }
1153
ocelot_port_obj_add_vlan(struct net_device * dev,const struct switchdev_obj_port_vlan * vlan,struct switchdev_trans * trans)1154 static int ocelot_port_obj_add_vlan(struct net_device *dev,
1155 const struct switchdev_obj_port_vlan *vlan,
1156 struct switchdev_trans *trans)
1157 {
1158 int ret;
1159 u16 vid;
1160
1161 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1162 ret = ocelot_vlan_vid_add(dev, vid,
1163 vlan->flags & BRIDGE_VLAN_INFO_PVID,
1164 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
1165 if (ret)
1166 return ret;
1167 }
1168
1169 return 0;
1170 }
1171
ocelot_port_vlan_del_vlan(struct net_device * dev,const struct switchdev_obj_port_vlan * vlan)1172 static int ocelot_port_vlan_del_vlan(struct net_device *dev,
1173 const struct switchdev_obj_port_vlan *vlan)
1174 {
1175 int ret;
1176 u16 vid;
1177
1178 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1179 ret = ocelot_vlan_vid_del(dev, vid);
1180
1181 if (ret)
1182 return ret;
1183 }
1184
1185 return 0;
1186 }
1187
ocelot_multicast_get(struct ocelot * ocelot,const unsigned char * addr,u16 vid)1188 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1189 const unsigned char *addr,
1190 u16 vid)
1191 {
1192 struct ocelot_multicast *mc;
1193
1194 list_for_each_entry(mc, &ocelot->multicast, list) {
1195 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1196 return mc;
1197 }
1198
1199 return NULL;
1200 }
1201
ocelot_port_obj_add_mdb(struct net_device * dev,const struct switchdev_obj_port_mdb * mdb,struct switchdev_trans * trans)1202 static int ocelot_port_obj_add_mdb(struct net_device *dev,
1203 const struct switchdev_obj_port_mdb *mdb,
1204 struct switchdev_trans *trans)
1205 {
1206 struct ocelot_port *port = netdev_priv(dev);
1207 struct ocelot *ocelot = port->ocelot;
1208 struct ocelot_multicast *mc;
1209 unsigned char addr[ETH_ALEN];
1210 u16 vid = mdb->vid;
1211 bool new = false;
1212
1213 if (!vid)
1214 vid = port->pvid;
1215
1216 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1217 if (!mc) {
1218 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1219 if (!mc)
1220 return -ENOMEM;
1221
1222 memcpy(mc->addr, mdb->addr, ETH_ALEN);
1223 mc->vid = vid;
1224
1225 list_add_tail(&mc->list, &ocelot->multicast);
1226 new = true;
1227 }
1228
1229 memcpy(addr, mc->addr, ETH_ALEN);
1230 addr[0] = 0;
1231
1232 if (!new) {
1233 addr[2] = mc->ports << 0;
1234 addr[1] = mc->ports << 8;
1235 ocelot_mact_forget(ocelot, addr, vid);
1236 }
1237
1238 mc->ports |= BIT(port->chip_port);
1239 addr[2] = mc->ports << 0;
1240 addr[1] = mc->ports << 8;
1241
1242 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1243 }
1244
ocelot_port_obj_del_mdb(struct net_device * dev,const struct switchdev_obj_port_mdb * mdb)1245 static int ocelot_port_obj_del_mdb(struct net_device *dev,
1246 const struct switchdev_obj_port_mdb *mdb)
1247 {
1248 struct ocelot_port *port = netdev_priv(dev);
1249 struct ocelot *ocelot = port->ocelot;
1250 struct ocelot_multicast *mc;
1251 unsigned char addr[ETH_ALEN];
1252 u16 vid = mdb->vid;
1253
1254 if (!vid)
1255 vid = port->pvid;
1256
1257 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1258 if (!mc)
1259 return -ENOENT;
1260
1261 memcpy(addr, mc->addr, ETH_ALEN);
1262 addr[2] = mc->ports << 0;
1263 addr[1] = mc->ports << 8;
1264 addr[0] = 0;
1265 ocelot_mact_forget(ocelot, addr, vid);
1266
1267 mc->ports &= ~BIT(port->chip_port);
1268 if (!mc->ports) {
1269 list_del(&mc->list);
1270 devm_kfree(ocelot->dev, mc);
1271 return 0;
1272 }
1273
1274 addr[2] = mc->ports << 0;
1275 addr[1] = mc->ports << 8;
1276
1277 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1278 }
1279
ocelot_port_obj_add(struct net_device * dev,const struct switchdev_obj * obj,struct switchdev_trans * trans)1280 static int ocelot_port_obj_add(struct net_device *dev,
1281 const struct switchdev_obj *obj,
1282 struct switchdev_trans *trans)
1283 {
1284 int ret = 0;
1285
1286 switch (obj->id) {
1287 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1288 ret = ocelot_port_obj_add_vlan(dev,
1289 SWITCHDEV_OBJ_PORT_VLAN(obj),
1290 trans);
1291 break;
1292 case SWITCHDEV_OBJ_ID_PORT_MDB:
1293 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj),
1294 trans);
1295 break;
1296 default:
1297 return -EOPNOTSUPP;
1298 }
1299
1300 return ret;
1301 }
1302
ocelot_port_obj_del(struct net_device * dev,const struct switchdev_obj * obj)1303 static int ocelot_port_obj_del(struct net_device *dev,
1304 const struct switchdev_obj *obj)
1305 {
1306 int ret = 0;
1307
1308 switch (obj->id) {
1309 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1310 ret = ocelot_port_vlan_del_vlan(dev,
1311 SWITCHDEV_OBJ_PORT_VLAN(obj));
1312 break;
1313 case SWITCHDEV_OBJ_ID_PORT_MDB:
1314 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj));
1315 break;
1316 default:
1317 return -EOPNOTSUPP;
1318 }
1319
1320 return ret;
1321 }
1322
1323 static const struct switchdev_ops ocelot_port_switchdev_ops = {
1324 .switchdev_port_attr_get = ocelot_port_attr_get,
1325 .switchdev_port_attr_set = ocelot_port_attr_set,
1326 .switchdev_port_obj_add = ocelot_port_obj_add,
1327 .switchdev_port_obj_del = ocelot_port_obj_del,
1328 };
1329
ocelot_port_bridge_join(struct ocelot_port * ocelot_port,struct net_device * bridge)1330 static int ocelot_port_bridge_join(struct ocelot_port *ocelot_port,
1331 struct net_device *bridge)
1332 {
1333 struct ocelot *ocelot = ocelot_port->ocelot;
1334
1335 if (!ocelot->bridge_mask) {
1336 ocelot->hw_bridge_dev = bridge;
1337 } else {
1338 if (ocelot->hw_bridge_dev != bridge)
1339 /* This is adding the port to a second bridge, this is
1340 * unsupported */
1341 return -ENODEV;
1342 }
1343
1344 ocelot->bridge_mask |= BIT(ocelot_port->chip_port);
1345
1346 return 0;
1347 }
1348
ocelot_port_bridge_leave(struct ocelot_port * ocelot_port,struct net_device * bridge)1349 static void ocelot_port_bridge_leave(struct ocelot_port *ocelot_port,
1350 struct net_device *bridge)
1351 {
1352 struct ocelot *ocelot = ocelot_port->ocelot;
1353
1354 ocelot->bridge_mask &= ~BIT(ocelot_port->chip_port);
1355
1356 if (!ocelot->bridge_mask)
1357 ocelot->hw_bridge_dev = NULL;
1358
1359 /* Clear bridge vlan settings before calling ocelot_vlan_port_apply */
1360 ocelot_port->vlan_aware = 0;
1361 ocelot_port->pvid = 0;
1362 ocelot_port->vid = 0;
1363 }
1364
ocelot_set_aggr_pgids(struct ocelot * ocelot)1365 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1366 {
1367 int i, port, lag;
1368
1369 /* Reset destination and aggregation PGIDS */
1370 for (port = 0; port < ocelot->num_phys_ports; port++)
1371 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1372
1373 for (i = PGID_AGGR; i < PGID_SRC; i++)
1374 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1375 ANA_PGID_PGID, i);
1376
1377 /* Now, set PGIDs for each LAG */
1378 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1379 unsigned long bond_mask;
1380 int aggr_count = 0;
1381 u8 aggr_idx[16];
1382
1383 bond_mask = ocelot->lags[lag];
1384 if (!bond_mask)
1385 continue;
1386
1387 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1388 // Destination mask
1389 ocelot_write_rix(ocelot, bond_mask,
1390 ANA_PGID_PGID, port);
1391 aggr_idx[aggr_count] = port;
1392 aggr_count++;
1393 }
1394
1395 for (i = PGID_AGGR; i < PGID_SRC; i++) {
1396 u32 ac;
1397
1398 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1399 ac &= ~bond_mask;
1400 ac |= BIT(aggr_idx[i % aggr_count]);
1401 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1402 }
1403 }
1404 }
1405
ocelot_setup_lag(struct ocelot * ocelot,int lag)1406 static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
1407 {
1408 unsigned long bond_mask = ocelot->lags[lag];
1409 unsigned int p;
1410
1411 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
1412 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1413
1414 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1415
1416 /* Use lag port as logical port for port i */
1417 ocelot_write_gix(ocelot, port_cfg |
1418 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1419 ANA_PORT_PORT_CFG, p);
1420 }
1421 }
1422
ocelot_port_lag_join(struct ocelot_port * ocelot_port,struct net_device * bond)1423 static int ocelot_port_lag_join(struct ocelot_port *ocelot_port,
1424 struct net_device *bond)
1425 {
1426 struct ocelot *ocelot = ocelot_port->ocelot;
1427 int p = ocelot_port->chip_port;
1428 int lag, lp;
1429 struct net_device *ndev;
1430 u32 bond_mask = 0;
1431
1432 rcu_read_lock();
1433 for_each_netdev_in_bond_rcu(bond, ndev) {
1434 struct ocelot_port *port = netdev_priv(ndev);
1435
1436 bond_mask |= BIT(port->chip_port);
1437 }
1438 rcu_read_unlock();
1439
1440 lp = __ffs(bond_mask);
1441
1442 /* If the new port is the lowest one, use it as the logical port from
1443 * now on
1444 */
1445 if (p == lp) {
1446 lag = p;
1447 ocelot->lags[p] = bond_mask;
1448 bond_mask &= ~BIT(p);
1449 if (bond_mask) {
1450 lp = __ffs(bond_mask);
1451 ocelot->lags[lp] = 0;
1452 }
1453 } else {
1454 lag = lp;
1455 ocelot->lags[lp] |= BIT(p);
1456 }
1457
1458 ocelot_setup_lag(ocelot, lag);
1459 ocelot_set_aggr_pgids(ocelot);
1460
1461 return 0;
1462 }
1463
ocelot_port_lag_leave(struct ocelot_port * ocelot_port,struct net_device * bond)1464 static void ocelot_port_lag_leave(struct ocelot_port *ocelot_port,
1465 struct net_device *bond)
1466 {
1467 struct ocelot *ocelot = ocelot_port->ocelot;
1468 int p = ocelot_port->chip_port;
1469 u32 port_cfg;
1470 int i;
1471
1472 /* Remove port from any lag */
1473 for (i = 0; i < ocelot->num_phys_ports; i++)
1474 ocelot->lags[i] &= ~BIT(ocelot_port->chip_port);
1475
1476 /* if it was the logical port of the lag, move the lag config to the
1477 * next port
1478 */
1479 if (ocelot->lags[p]) {
1480 int n = __ffs(ocelot->lags[p]);
1481
1482 ocelot->lags[n] = ocelot->lags[p];
1483 ocelot->lags[p] = 0;
1484
1485 ocelot_setup_lag(ocelot, n);
1486 }
1487
1488 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1489 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1490 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(p),
1491 ANA_PORT_PORT_CFG, p);
1492
1493 ocelot_set_aggr_pgids(ocelot);
1494 }
1495
1496 /* Checks if the net_device instance given to us originate from our driver. */
ocelot_netdevice_dev_check(const struct net_device * dev)1497 static bool ocelot_netdevice_dev_check(const struct net_device *dev)
1498 {
1499 return dev->netdev_ops == &ocelot_port_netdev_ops;
1500 }
1501
ocelot_netdevice_port_event(struct net_device * dev,unsigned long event,struct netdev_notifier_changeupper_info * info)1502 static int ocelot_netdevice_port_event(struct net_device *dev,
1503 unsigned long event,
1504 struct netdev_notifier_changeupper_info *info)
1505 {
1506 struct ocelot_port *ocelot_port = netdev_priv(dev);
1507 int err = 0;
1508
1509 if (!ocelot_netdevice_dev_check(dev))
1510 return 0;
1511
1512 switch (event) {
1513 case NETDEV_CHANGEUPPER:
1514 if (netif_is_bridge_master(info->upper_dev)) {
1515 if (info->linking)
1516 err = ocelot_port_bridge_join(ocelot_port,
1517 info->upper_dev);
1518 else
1519 ocelot_port_bridge_leave(ocelot_port,
1520 info->upper_dev);
1521
1522 ocelot_vlan_port_apply(ocelot_port->ocelot,
1523 ocelot_port);
1524 }
1525 if (netif_is_lag_master(info->upper_dev)) {
1526 if (info->linking)
1527 err = ocelot_port_lag_join(ocelot_port,
1528 info->upper_dev);
1529 else
1530 ocelot_port_lag_leave(ocelot_port,
1531 info->upper_dev);
1532 }
1533 break;
1534 default:
1535 break;
1536 }
1537
1538 return err;
1539 }
1540
ocelot_netdevice_event(struct notifier_block * unused,unsigned long event,void * ptr)1541 static int ocelot_netdevice_event(struct notifier_block *unused,
1542 unsigned long event, void *ptr)
1543 {
1544 struct netdev_notifier_changeupper_info *info = ptr;
1545 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
1546 int ret = 0;
1547
1548 if (event == NETDEV_PRECHANGEUPPER &&
1549 netif_is_lag_master(info->upper_dev)) {
1550 struct netdev_lag_upper_info *lag_upper_info = info->upper_info;
1551 struct netlink_ext_ack *extack;
1552
1553 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1554 extack = netdev_notifier_info_to_extack(&info->info);
1555 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
1556
1557 ret = -EINVAL;
1558 goto notify;
1559 }
1560 }
1561
1562 if (netif_is_lag_master(dev)) {
1563 struct net_device *slave;
1564 struct list_head *iter;
1565
1566 netdev_for_each_lower_dev(dev, slave, iter) {
1567 ret = ocelot_netdevice_port_event(slave, event, info);
1568 if (ret)
1569 goto notify;
1570 }
1571 } else {
1572 ret = ocelot_netdevice_port_event(dev, event, info);
1573 }
1574
1575 notify:
1576 return notifier_from_errno(ret);
1577 }
1578
1579 struct notifier_block ocelot_netdevice_nb __read_mostly = {
1580 .notifier_call = ocelot_netdevice_event,
1581 };
1582 EXPORT_SYMBOL(ocelot_netdevice_nb);
1583
ocelot_probe_port(struct ocelot * ocelot,u8 port,void __iomem * regs,struct phy_device * phy)1584 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
1585 void __iomem *regs,
1586 struct phy_device *phy)
1587 {
1588 struct ocelot_port *ocelot_port;
1589 struct net_device *dev;
1590 int err;
1591
1592 dev = alloc_etherdev(sizeof(struct ocelot_port));
1593 if (!dev)
1594 return -ENOMEM;
1595 SET_NETDEV_DEV(dev, ocelot->dev);
1596 ocelot_port = netdev_priv(dev);
1597 ocelot_port->dev = dev;
1598 ocelot_port->ocelot = ocelot;
1599 ocelot_port->regs = regs;
1600 ocelot_port->chip_port = port;
1601 ocelot_port->phy = phy;
1602 INIT_LIST_HEAD(&ocelot_port->mc);
1603 ocelot->ports[port] = ocelot_port;
1604
1605 dev->netdev_ops = &ocelot_port_netdev_ops;
1606 dev->ethtool_ops = &ocelot_ethtool_ops;
1607 dev->switchdev_ops = &ocelot_port_switchdev_ops;
1608
1609 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1610 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1611
1612 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN);
1613 dev->dev_addr[ETH_ALEN - 1] += port;
1614 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid,
1615 ENTRYTYPE_LOCKED);
1616
1617 err = register_netdev(dev);
1618 if (err) {
1619 dev_err(ocelot->dev, "register_netdev failed\n");
1620 goto err_register_netdev;
1621 }
1622
1623 /* Basic L2 initialization */
1624 ocelot_vlan_port_apply(ocelot, ocelot_port);
1625
1626 return 0;
1627
1628 err_register_netdev:
1629 free_netdev(dev);
1630 return err;
1631 }
1632 EXPORT_SYMBOL(ocelot_probe_port);
1633
ocelot_init(struct ocelot * ocelot)1634 int ocelot_init(struct ocelot *ocelot)
1635 {
1636 u32 port;
1637 int i, cpu = ocelot->num_phys_ports;
1638 char queue_name[32];
1639
1640 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
1641 sizeof(u32), GFP_KERNEL);
1642 if (!ocelot->lags)
1643 return -ENOMEM;
1644
1645 ocelot->stats = devm_kcalloc(ocelot->dev,
1646 ocelot->num_phys_ports * ocelot->num_stats,
1647 sizeof(u64), GFP_KERNEL);
1648 if (!ocelot->stats)
1649 return -ENOMEM;
1650
1651 mutex_init(&ocelot->stats_lock);
1652 snprintf(queue_name, sizeof(queue_name), "%s-stats",
1653 dev_name(ocelot->dev));
1654 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
1655 if (!ocelot->stats_queue)
1656 return -ENOMEM;
1657
1658 ocelot_mact_init(ocelot);
1659 ocelot_vlan_init(ocelot);
1660
1661 for (port = 0; port < ocelot->num_phys_ports; port++) {
1662 /* Clear all counters (5 groups) */
1663 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
1664 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
1665 SYS_STAT_CFG);
1666 }
1667
1668 /* Only use S-Tag */
1669 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
1670
1671 /* Aggregation mode */
1672 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
1673 ANA_AGGR_CFG_AC_DMAC_ENA |
1674 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
1675 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
1676
1677 /* Set MAC age time to default value. The entry is aged after
1678 * 2*AGE_PERIOD
1679 */
1680 ocelot_write(ocelot,
1681 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
1682 ANA_AUTOAGE);
1683
1684 /* Disable learning for frames discarded by VLAN ingress filtering */
1685 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
1686
1687 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
1688 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
1689 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
1690
1691 /* Setup flooding PGIDs */
1692 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
1693 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
1694 ANA_FLOODING_FLD_UNICAST(PGID_UC),
1695 ANA_FLOODING, 0);
1696 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
1697 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
1698 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
1699 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
1700 ANA_FLOODING_IPMC);
1701
1702 for (port = 0; port < ocelot->num_phys_ports; port++) {
1703 /* Transmit the frame to the local port. */
1704 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1705 /* Do not forward BPDU frames to the front ports. */
1706 ocelot_write_gix(ocelot,
1707 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
1708 ANA_PORT_CPU_FWD_BPDU_CFG,
1709 port);
1710 /* Ensure bridging is disabled */
1711 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
1712 }
1713
1714 /* Configure and enable the CPU port. */
1715 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
1716 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
1717 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
1718 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
1719 ANA_PORT_PORT_CFG, cpu);
1720
1721 /* Allow broadcast MAC frames. */
1722 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
1723 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
1724
1725 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
1726 }
1727 ocelot_write_rix(ocelot,
1728 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
1729 ANA_PGID_PGID, PGID_MC);
1730 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
1731 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
1732
1733 /* CPU port Injection/Extraction configuration */
1734 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
1735 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
1736 QSYS_SWITCH_PORT_MODE_PORT_ENA,
1737 QSYS_SWITCH_PORT_MODE, cpu);
1738 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) |
1739 SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu);
1740 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
1741 * registers endianness.
1742 */
1743 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
1744 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
1745 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
1746 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
1747 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
1748 ANA_CPUQ_CFG_CPUQ_LRN(2) |
1749 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
1750 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
1751 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
1752 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
1753 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
1754 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
1755 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
1756 for (i = 0; i < 16; i++)
1757 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
1758 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
1759 ANA_CPUQ_8021_CFG, i);
1760
1761 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats);
1762 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1763 OCELOT_STATS_CHECK_DELAY);
1764 return 0;
1765 }
1766 EXPORT_SYMBOL(ocelot_init);
1767
ocelot_deinit(struct ocelot * ocelot)1768 void ocelot_deinit(struct ocelot *ocelot)
1769 {
1770 destroy_workqueue(ocelot->stats_queue);
1771 mutex_destroy(&ocelot->stats_lock);
1772 }
1773 EXPORT_SYMBOL(ocelot_deinit);
1774
1775 MODULE_LICENSE("Dual MIT/GPL");
1776
