1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7 #include <linux/if_bridge.h>
8 #include <soc/mscc/ocelot_vcap.h>
9 #include "ocelot.h"
10 #include "ocelot_vcap.h"
11
12 #define TABLE_UPDATE_SLEEP_US 10
13 #define TABLE_UPDATE_TIMEOUT_US 100000
14
15 struct ocelot_mact_entry {
16 u8 mac[ETH_ALEN];
17 u16 vid;
18 enum macaccess_entry_type type;
19 };
20
ocelot_mact_read_macaccess(struct ocelot * ocelot)21 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
22 {
23 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
24 }
25
ocelot_mact_wait_for_completion(struct ocelot * ocelot)26 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
27 {
28 u32 val;
29
30 return readx_poll_timeout(ocelot_mact_read_macaccess,
31 ocelot, val,
32 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
33 MACACCESS_CMD_IDLE,
34 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
35 }
36
ocelot_mact_select(struct ocelot * ocelot,const unsigned char mac[ETH_ALEN],unsigned int vid)37 static void ocelot_mact_select(struct ocelot *ocelot,
38 const unsigned char mac[ETH_ALEN],
39 unsigned int vid)
40 {
41 u32 macl = 0, mach = 0;
42
43 /* Set the MAC address to handle and the vlan associated in a format
44 * understood by the hardware.
45 */
46 mach |= vid << 16;
47 mach |= mac[0] << 8;
48 mach |= mac[1] << 0;
49 macl |= mac[2] << 24;
50 macl |= mac[3] << 16;
51 macl |= mac[4] << 8;
52 macl |= mac[5] << 0;
53
54 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
55 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
56
57 }
58
ocelot_mact_learn(struct ocelot * ocelot,int port,const unsigned char mac[ETH_ALEN],unsigned int vid,enum macaccess_entry_type type)59 int ocelot_mact_learn(struct ocelot *ocelot, int port,
60 const unsigned char mac[ETH_ALEN],
61 unsigned int vid, enum macaccess_entry_type type)
62 {
63 ocelot_mact_select(ocelot, mac, vid);
64
65 /* Issue a write command */
66 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
67 ANA_TABLES_MACACCESS_DEST_IDX(port) |
68 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
69 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
70 ANA_TABLES_MACACCESS);
71
72 return ocelot_mact_wait_for_completion(ocelot);
73 }
74 EXPORT_SYMBOL(ocelot_mact_learn);
75
ocelot_mact_forget(struct ocelot * ocelot,const unsigned char mac[ETH_ALEN],unsigned int vid)76 int ocelot_mact_forget(struct ocelot *ocelot,
77 const unsigned char mac[ETH_ALEN], unsigned int vid)
78 {
79 ocelot_mact_select(ocelot, mac, vid);
80
81 /* Issue a forget command */
82 ocelot_write(ocelot,
83 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
84 ANA_TABLES_MACACCESS);
85
86 return ocelot_mact_wait_for_completion(ocelot);
87 }
88 EXPORT_SYMBOL(ocelot_mact_forget);
89
ocelot_mact_init(struct ocelot * ocelot)90 static void ocelot_mact_init(struct ocelot *ocelot)
91 {
92 /* Configure the learning mode entries attributes:
93 * - Do not copy the frame to the CPU extraction queues.
94 * - Use the vlan and mac_cpoy for dmac lookup.
95 */
96 ocelot_rmw(ocelot, 0,
97 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
98 | ANA_AGENCTRL_LEARN_FWD_KILL
99 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
100 ANA_AGENCTRL);
101
102 /* Clear the MAC table */
103 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
104 }
105
ocelot_vcap_enable(struct ocelot * ocelot,int port)106 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
107 {
108 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
109 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
110 ANA_PORT_VCAP_S2_CFG, port);
111
112 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
113 ANA_PORT_VCAP_CFG, port);
114
115 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
116 REW_PORT_CFG_ES0_EN,
117 REW_PORT_CFG, port);
118 }
119
ocelot_vlant_read_vlanaccess(struct ocelot * ocelot)120 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
121 {
122 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
123 }
124
ocelot_vlant_wait_for_completion(struct ocelot * ocelot)125 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
126 {
127 u32 val;
128
129 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
130 ocelot,
131 val,
132 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
133 ANA_TABLES_VLANACCESS_CMD_IDLE,
134 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
135 }
136
ocelot_vlant_set_mask(struct ocelot * ocelot,u16 vid,u32 mask)137 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
138 {
139 /* Select the VID to configure */
140 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
141 ANA_TABLES_VLANTIDX);
142 /* Set the vlan port members mask and issue a write command */
143 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
144 ANA_TABLES_VLANACCESS_CMD_WRITE,
145 ANA_TABLES_VLANACCESS);
146
147 return ocelot_vlant_wait_for_completion(ocelot);
148 }
149
ocelot_port_set_native_vlan(struct ocelot * ocelot,int port,u16 vid)150 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port,
151 u16 vid)
152 {
153 struct ocelot_port *ocelot_port = ocelot->ports[port];
154 u32 val = 0;
155
156 if (ocelot_port->vid != vid) {
157 /* Always permit deleting the native VLAN (vid = 0) */
158 if (ocelot_port->vid && vid) {
159 dev_err(ocelot->dev,
160 "Port already has a native VLAN: %d\n",
161 ocelot_port->vid);
162 return -EBUSY;
163 }
164 ocelot_port->vid = vid;
165 }
166
167 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid),
168 REW_PORT_VLAN_CFG_PORT_VID_M,
169 REW_PORT_VLAN_CFG, port);
170
171 if (ocelot_port->vlan_aware && !ocelot_port->vid)
172 /* If port is vlan-aware and tagged, drop untagged and priority
173 * tagged frames.
174 */
175 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
176 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
177 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
178 ocelot_rmw_gix(ocelot, val,
179 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
180 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
181 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
182 ANA_PORT_DROP_CFG, port);
183
184 if (ocelot_port->vlan_aware) {
185 if (ocelot_port->vid)
186 /* Tag all frames except when VID == DEFAULT_VLAN */
187 val = REW_TAG_CFG_TAG_CFG(1);
188 else
189 /* Tag all frames */
190 val = REW_TAG_CFG_TAG_CFG(3);
191 } else {
192 /* Port tagging disabled. */
193 val = REW_TAG_CFG_TAG_CFG(0);
194 }
195 ocelot_rmw_gix(ocelot, val,
196 REW_TAG_CFG_TAG_CFG_M,
197 REW_TAG_CFG, port);
198
199 return 0;
200 }
201
ocelot_port_vlan_filtering(struct ocelot * ocelot,int port,bool vlan_aware,struct switchdev_trans * trans)202 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
203 bool vlan_aware, struct switchdev_trans *trans)
204 {
205 struct ocelot_port *ocelot_port = ocelot->ports[port];
206 u32 val;
207
208 if (switchdev_trans_ph_prepare(trans)) {
209 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
210 struct ocelot_vcap_filter *filter;
211
212 list_for_each_entry(filter, &block->rules, list) {
213 if (filter->ingress_port_mask & BIT(port) &&
214 filter->action.vid_replace_ena) {
215 dev_err(ocelot->dev,
216 "Cannot change VLAN state with vlan modify rules active\n");
217 return -EBUSY;
218 }
219 }
220
221 return 0;
222 }
223
224 ocelot_port->vlan_aware = vlan_aware;
225
226 if (vlan_aware)
227 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
228 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
229 else
230 val = 0;
231 ocelot_rmw_gix(ocelot, val,
232 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
233 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
234 ANA_PORT_VLAN_CFG, port);
235
236 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->vid);
237
238 return 0;
239 }
240 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
241
242 /* Default vlan to clasify for untagged frames (may be zero) */
ocelot_port_set_pvid(struct ocelot * ocelot,int port,u16 pvid)243 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid)
244 {
245 struct ocelot_port *ocelot_port = ocelot->ports[port];
246
247 ocelot_rmw_gix(ocelot,
248 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
249 ANA_PORT_VLAN_CFG_VLAN_VID_M,
250 ANA_PORT_VLAN_CFG, port);
251
252 ocelot_port->pvid = pvid;
253 }
254
ocelot_vlan_add(struct ocelot * ocelot,int port,u16 vid,bool pvid,bool untagged)255 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
256 bool untagged)
257 {
258 int ret;
259
260 /* Make the port a member of the VLAN */
261 ocelot->vlan_mask[vid] |= BIT(port);
262 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
263 if (ret)
264 return ret;
265
266 /* Default ingress vlan classification */
267 if (pvid)
268 ocelot_port_set_pvid(ocelot, port, vid);
269
270 /* Untagged egress vlan clasification */
271 if (untagged) {
272 ret = ocelot_port_set_native_vlan(ocelot, port, vid);
273 if (ret)
274 return ret;
275 }
276
277 return 0;
278 }
279 EXPORT_SYMBOL(ocelot_vlan_add);
280
ocelot_vlan_del(struct ocelot * ocelot,int port,u16 vid)281 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
282 {
283 struct ocelot_port *ocelot_port = ocelot->ports[port];
284 int ret;
285
286 /* Stop the port from being a member of the vlan */
287 ocelot->vlan_mask[vid] &= ~BIT(port);
288 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
289 if (ret)
290 return ret;
291
292 /* Ingress */
293 if (ocelot_port->pvid == vid)
294 ocelot_port_set_pvid(ocelot, port, 0);
295
296 /* Egress */
297 if (ocelot_port->vid == vid)
298 ocelot_port_set_native_vlan(ocelot, port, 0);
299
300 return 0;
301 }
302 EXPORT_SYMBOL(ocelot_vlan_del);
303
ocelot_vlan_init(struct ocelot * ocelot)304 static void ocelot_vlan_init(struct ocelot *ocelot)
305 {
306 u16 port, vid;
307
308 /* Clear VLAN table, by default all ports are members of all VLANs */
309 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
310 ANA_TABLES_VLANACCESS);
311 ocelot_vlant_wait_for_completion(ocelot);
312
313 /* Configure the port VLAN memberships */
314 for (vid = 1; vid < VLAN_N_VID; vid++) {
315 ocelot->vlan_mask[vid] = 0;
316 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
317 }
318
319 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
320 * traffic. It is added automatically if 8021q module is loaded, but
321 * we can't rely on it since module may be not loaded.
322 */
323 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
324 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
325
326 /* Set vlan ingress filter mask to all ports but the CPU port by
327 * default.
328 */
329 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
330 ANA_VLANMASK);
331
332 for (port = 0; port < ocelot->num_phys_ports; port++) {
333 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
334 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
335 }
336 }
337
ocelot_adjust_link(struct ocelot * ocelot,int port,struct phy_device * phydev)338 void ocelot_adjust_link(struct ocelot *ocelot, int port,
339 struct phy_device *phydev)
340 {
341 struct ocelot_port *ocelot_port = ocelot->ports[port];
342 int speed, mode = 0;
343
344 switch (phydev->speed) {
345 case SPEED_10:
346 speed = OCELOT_SPEED_10;
347 break;
348 case SPEED_100:
349 speed = OCELOT_SPEED_100;
350 break;
351 case SPEED_1000:
352 speed = OCELOT_SPEED_1000;
353 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
354 break;
355 case SPEED_2500:
356 speed = OCELOT_SPEED_2500;
357 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
358 break;
359 default:
360 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n",
361 port, phydev->speed);
362 return;
363 }
364
365 phy_print_status(phydev);
366
367 if (!phydev->link)
368 return;
369
370 /* Only full duplex supported for now */
371 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
372 mode, DEV_MAC_MODE_CFG);
373
374 /* Disable HDX fast control */
375 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
376 DEV_PORT_MISC);
377
378 /* SGMII only for now */
379 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
380 PCS1G_MODE_CFG);
381 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
382
383 /* Enable PCS */
384 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
385
386 /* No aneg on SGMII */
387 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
388
389 /* No loopback */
390 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
391
392 /* Enable MAC module */
393 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
394 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
395
396 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
397 * reset */
398 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
399 DEV_CLOCK_CFG);
400
401 /* No PFC */
402 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
403 ANA_PFC_PFC_CFG, port);
404
405 /* Core: Enable port for frame transfer */
406 ocelot_fields_write(ocelot, port,
407 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
408
409 /* Flow control */
410 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
411 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
412 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
413 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
414 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
415 SYS_MAC_FC_CFG, port);
416 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
417 }
418 EXPORT_SYMBOL(ocelot_adjust_link);
419
ocelot_port_enable(struct ocelot * ocelot,int port,struct phy_device * phy)420 void ocelot_port_enable(struct ocelot *ocelot, int port,
421 struct phy_device *phy)
422 {
423 /* Enable receiving frames on the port, and activate auto-learning of
424 * MAC addresses.
425 */
426 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
427 ANA_PORT_PORT_CFG_RECV_ENA |
428 ANA_PORT_PORT_CFG_PORTID_VAL(port),
429 ANA_PORT_PORT_CFG, port);
430 }
431 EXPORT_SYMBOL(ocelot_port_enable);
432
ocelot_port_disable(struct ocelot * ocelot,int port)433 void ocelot_port_disable(struct ocelot *ocelot, int port)
434 {
435 struct ocelot_port *ocelot_port = ocelot->ports[port];
436
437 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);
438 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
439 }
440 EXPORT_SYMBOL(ocelot_port_disable);
441
ocelot_port_add_txtstamp_skb(struct ocelot * ocelot,int port,struct sk_buff * clone)442 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
443 struct sk_buff *clone)
444 {
445 struct ocelot_port *ocelot_port = ocelot->ports[port];
446
447 spin_lock(&ocelot_port->ts_id_lock);
448
449 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS;
450 /* Store timestamp ID in cb[0] of sk_buff */
451 clone->cb[0] = ocelot_port->ts_id;
452 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4;
453 skb_queue_tail(&ocelot_port->tx_skbs, clone);
454
455 spin_unlock(&ocelot_port->ts_id_lock);
456 }
457 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb);
458
ocelot_get_hwtimestamp(struct ocelot * ocelot,struct timespec64 * ts)459 static void ocelot_get_hwtimestamp(struct ocelot *ocelot,
460 struct timespec64 *ts)
461 {
462 unsigned long flags;
463 u32 val;
464
465 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
466
467 /* Read current PTP time to get seconds */
468 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
469
470 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
471 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
472 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
473 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
474
475 /* Read packet HW timestamp from FIFO */
476 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
477 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
478
479 /* Sec has incremented since the ts was registered */
480 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
481 ts->tv_sec--;
482
483 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
484 }
485
ocelot_get_txtstamp(struct ocelot * ocelot)486 void ocelot_get_txtstamp(struct ocelot *ocelot)
487 {
488 int budget = OCELOT_PTP_QUEUE_SZ;
489
490 while (budget--) {
491 struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
492 struct skb_shared_hwtstamps shhwtstamps;
493 struct ocelot_port *port;
494 struct timespec64 ts;
495 unsigned long flags;
496 u32 val, id, txport;
497
498 val = ocelot_read(ocelot, SYS_PTP_STATUS);
499
500 /* Check if a timestamp can be retrieved */
501 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD))
502 break;
503
504 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL);
505
506 /* Retrieve the ts ID and Tx port */
507 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val);
508 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val);
509
510 /* Retrieve its associated skb */
511 port = ocelot->ports[txport];
512
513 spin_lock_irqsave(&port->tx_skbs.lock, flags);
514
515 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
516 if (skb->cb[0] != id)
517 continue;
518 __skb_unlink(skb, &port->tx_skbs);
519 skb_match = skb;
520 break;
521 }
522
523 spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
524
525 /* Get the h/w timestamp */
526 ocelot_get_hwtimestamp(ocelot, &ts);
527
528 if (unlikely(!skb_match))
529 continue;
530
531 /* Set the timestamp into the skb */
532 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
533 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
534 skb_complete_tx_timestamp(skb_match, &shhwtstamps);
535
536 /* Next ts */
537 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
538 }
539 }
540 EXPORT_SYMBOL(ocelot_get_txtstamp);
541
ocelot_fdb_add(struct ocelot * ocelot,int port,const unsigned char * addr,u16 vid)542 int ocelot_fdb_add(struct ocelot *ocelot, int port,
543 const unsigned char *addr, u16 vid)
544 {
545 struct ocelot_port *ocelot_port = ocelot->ports[port];
546 int pgid = port;
547
548 if (port == ocelot->npi)
549 pgid = PGID_CPU;
550
551 if (!vid) {
552 if (!ocelot_port->vlan_aware)
553 /* If the bridge is not VLAN aware and no VID was
554 * provided, set it to pvid to ensure the MAC entry
555 * matches incoming untagged packets
556 */
557 vid = ocelot_port->pvid;
558 else
559 /* If the bridge is VLAN aware a VID must be provided as
560 * otherwise the learnt entry wouldn't match any frame.
561 */
562 return -EINVAL;
563 }
564
565 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED);
566 }
567 EXPORT_SYMBOL(ocelot_fdb_add);
568
ocelot_fdb_del(struct ocelot * ocelot,int port,const unsigned char * addr,u16 vid)569 int ocelot_fdb_del(struct ocelot *ocelot, int port,
570 const unsigned char *addr, u16 vid)
571 {
572 return ocelot_mact_forget(ocelot, addr, vid);
573 }
574 EXPORT_SYMBOL(ocelot_fdb_del);
575
ocelot_port_fdb_do_dump(const unsigned char * addr,u16 vid,bool is_static,void * data)576 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
577 bool is_static, void *data)
578 {
579 struct ocelot_dump_ctx *dump = data;
580 u32 portid = NETLINK_CB(dump->cb->skb).portid;
581 u32 seq = dump->cb->nlh->nlmsg_seq;
582 struct nlmsghdr *nlh;
583 struct ndmsg *ndm;
584
585 if (dump->idx < dump->cb->args[2])
586 goto skip;
587
588 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
589 sizeof(*ndm), NLM_F_MULTI);
590 if (!nlh)
591 return -EMSGSIZE;
592
593 ndm = nlmsg_data(nlh);
594 ndm->ndm_family = AF_BRIDGE;
595 ndm->ndm_pad1 = 0;
596 ndm->ndm_pad2 = 0;
597 ndm->ndm_flags = NTF_SELF;
598 ndm->ndm_type = 0;
599 ndm->ndm_ifindex = dump->dev->ifindex;
600 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
601
602 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
603 goto nla_put_failure;
604
605 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
606 goto nla_put_failure;
607
608 nlmsg_end(dump->skb, nlh);
609
610 skip:
611 dump->idx++;
612 return 0;
613
614 nla_put_failure:
615 nlmsg_cancel(dump->skb, nlh);
616 return -EMSGSIZE;
617 }
618 EXPORT_SYMBOL(ocelot_port_fdb_do_dump);
619
ocelot_mact_read(struct ocelot * ocelot,int port,int row,int col,struct ocelot_mact_entry * entry)620 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
621 struct ocelot_mact_entry *entry)
622 {
623 u32 val, dst, macl, mach;
624 char mac[ETH_ALEN];
625
626 /* Set row and column to read from */
627 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
628 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
629
630 /* Issue a read command */
631 ocelot_write(ocelot,
632 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
633 ANA_TABLES_MACACCESS);
634
635 if (ocelot_mact_wait_for_completion(ocelot))
636 return -ETIMEDOUT;
637
638 /* Read the entry flags */
639 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
640 if (!(val & ANA_TABLES_MACACCESS_VALID))
641 return -EINVAL;
642
643 /* If the entry read has another port configured as its destination,
644 * do not report it.
645 */
646 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
647 if (dst != port)
648 return -EINVAL;
649
650 /* Get the entry's MAC address and VLAN id */
651 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
652 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
653
654 mac[0] = (mach >> 8) & 0xff;
655 mac[1] = (mach >> 0) & 0xff;
656 mac[2] = (macl >> 24) & 0xff;
657 mac[3] = (macl >> 16) & 0xff;
658 mac[4] = (macl >> 8) & 0xff;
659 mac[5] = (macl >> 0) & 0xff;
660
661 entry->vid = (mach >> 16) & 0xfff;
662 ether_addr_copy(entry->mac, mac);
663
664 return 0;
665 }
666
ocelot_fdb_dump(struct ocelot * ocelot,int port,dsa_fdb_dump_cb_t * cb,void * data)667 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
668 dsa_fdb_dump_cb_t *cb, void *data)
669 {
670 int i, j;
671
672 /* Loop through all the mac tables entries. */
673 for (i = 0; i < ocelot->num_mact_rows; i++) {
674 for (j = 0; j < 4; j++) {
675 struct ocelot_mact_entry entry;
676 bool is_static;
677 int ret;
678
679 ret = ocelot_mact_read(ocelot, port, i, j, &entry);
680 /* If the entry is invalid (wrong port, invalid...),
681 * skip it.
682 */
683 if (ret == -EINVAL)
684 continue;
685 else if (ret)
686 return ret;
687
688 is_static = (entry.type == ENTRYTYPE_LOCKED);
689
690 ret = cb(entry.mac, entry.vid, is_static, data);
691 if (ret)
692 return ret;
693 }
694 }
695
696 return 0;
697 }
698 EXPORT_SYMBOL(ocelot_fdb_dump);
699
ocelot_hwstamp_get(struct ocelot * ocelot,int port,struct ifreq * ifr)700 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr)
701 {
702 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
703 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
704 }
705 EXPORT_SYMBOL(ocelot_hwstamp_get);
706
ocelot_hwstamp_set(struct ocelot * ocelot,int port,struct ifreq * ifr)707 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr)
708 {
709 struct ocelot_port *ocelot_port = ocelot->ports[port];
710 struct hwtstamp_config cfg;
711
712 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
713 return -EFAULT;
714
715 /* reserved for future extensions */
716 if (cfg.flags)
717 return -EINVAL;
718
719 /* Tx type sanity check */
720 switch (cfg.tx_type) {
721 case HWTSTAMP_TX_ON:
722 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
723 break;
724 case HWTSTAMP_TX_ONESTEP_SYNC:
725 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
726 * need to update the origin time.
727 */
728 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
729 break;
730 case HWTSTAMP_TX_OFF:
731 ocelot_port->ptp_cmd = 0;
732 break;
733 default:
734 return -ERANGE;
735 }
736
737 mutex_lock(&ocelot->ptp_lock);
738
739 switch (cfg.rx_filter) {
740 case HWTSTAMP_FILTER_NONE:
741 break;
742 case HWTSTAMP_FILTER_ALL:
743 case HWTSTAMP_FILTER_SOME:
744 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
745 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
746 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
747 case HWTSTAMP_FILTER_NTP_ALL:
748 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
749 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
750 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
751 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
752 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
753 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
754 case HWTSTAMP_FILTER_PTP_V2_EVENT:
755 case HWTSTAMP_FILTER_PTP_V2_SYNC:
756 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
757 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
758 break;
759 default:
760 mutex_unlock(&ocelot->ptp_lock);
761 return -ERANGE;
762 }
763
764 /* Commit back the result & save it */
765 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
766 mutex_unlock(&ocelot->ptp_lock);
767
768 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
769 }
770 EXPORT_SYMBOL(ocelot_hwstamp_set);
771
ocelot_get_strings(struct ocelot * ocelot,int port,u32 sset,u8 * data)772 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
773 {
774 int i;
775
776 if (sset != ETH_SS_STATS)
777 return;
778
779 for (i = 0; i < ocelot->num_stats; i++)
780 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
781 ETH_GSTRING_LEN);
782 }
783 EXPORT_SYMBOL(ocelot_get_strings);
784
ocelot_update_stats(struct ocelot * ocelot)785 static void ocelot_update_stats(struct ocelot *ocelot)
786 {
787 int i, j;
788
789 mutex_lock(&ocelot->stats_lock);
790
791 for (i = 0; i < ocelot->num_phys_ports; i++) {
792 /* Configure the port to read the stats from */
793 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
794
795 for (j = 0; j < ocelot->num_stats; j++) {
796 u32 val;
797 unsigned int idx = i * ocelot->num_stats + j;
798
799 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
800 ocelot->stats_layout[j].offset);
801
802 if (val < (ocelot->stats[idx] & U32_MAX))
803 ocelot->stats[idx] += (u64)1 << 32;
804
805 ocelot->stats[idx] = (ocelot->stats[idx] &
806 ~(u64)U32_MAX) + val;
807 }
808 }
809
810 mutex_unlock(&ocelot->stats_lock);
811 }
812
ocelot_check_stats_work(struct work_struct * work)813 static void ocelot_check_stats_work(struct work_struct *work)
814 {
815 struct delayed_work *del_work = to_delayed_work(work);
816 struct ocelot *ocelot = container_of(del_work, struct ocelot,
817 stats_work);
818
819 ocelot_update_stats(ocelot);
820
821 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
822 OCELOT_STATS_CHECK_DELAY);
823 }
824
ocelot_get_ethtool_stats(struct ocelot * ocelot,int port,u64 * data)825 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
826 {
827 int i;
828
829 /* check and update now */
830 ocelot_update_stats(ocelot);
831
832 /* Copy all counters */
833 for (i = 0; i < ocelot->num_stats; i++)
834 *data++ = ocelot->stats[port * ocelot->num_stats + i];
835 }
836 EXPORT_SYMBOL(ocelot_get_ethtool_stats);
837
ocelot_get_sset_count(struct ocelot * ocelot,int port,int sset)838 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
839 {
840 if (sset != ETH_SS_STATS)
841 return -EOPNOTSUPP;
842
843 return ocelot->num_stats;
844 }
845 EXPORT_SYMBOL(ocelot_get_sset_count);
846
ocelot_get_ts_info(struct ocelot * ocelot,int port,struct ethtool_ts_info * info)847 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
848 struct ethtool_ts_info *info)
849 {
850 info->phc_index = ocelot->ptp_clock ?
851 ptp_clock_index(ocelot->ptp_clock) : -1;
852 if (info->phc_index == -1) {
853 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
854 SOF_TIMESTAMPING_RX_SOFTWARE |
855 SOF_TIMESTAMPING_SOFTWARE;
856 return 0;
857 }
858 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
859 SOF_TIMESTAMPING_RX_SOFTWARE |
860 SOF_TIMESTAMPING_SOFTWARE |
861 SOF_TIMESTAMPING_TX_HARDWARE |
862 SOF_TIMESTAMPING_RX_HARDWARE |
863 SOF_TIMESTAMPING_RAW_HARDWARE;
864 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
865 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
866 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
867
868 return 0;
869 }
870 EXPORT_SYMBOL(ocelot_get_ts_info);
871
ocelot_bridge_stp_state_set(struct ocelot * ocelot,int port,u8 state)872 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
873 {
874 u32 port_cfg;
875 int p, i;
876
877 if (!(BIT(port) & ocelot->bridge_mask))
878 return;
879
880 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
881
882 switch (state) {
883 case BR_STATE_FORWARDING:
884 ocelot->bridge_fwd_mask |= BIT(port);
885 fallthrough;
886 case BR_STATE_LEARNING:
887 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
888 break;
889
890 default:
891 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
892 ocelot->bridge_fwd_mask &= ~BIT(port);
893 break;
894 }
895
896 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port);
897
898 /* Apply FWD mask. The loop is needed to add/remove the current port as
899 * a source for the other ports.
900 */
901 for (p = 0; p < ocelot->num_phys_ports; p++) {
902 if (ocelot->bridge_fwd_mask & BIT(p)) {
903 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p);
904
905 for (i = 0; i < ocelot->num_phys_ports; i++) {
906 unsigned long bond_mask = ocelot->lags[i];
907
908 if (!bond_mask)
909 continue;
910
911 if (bond_mask & BIT(p)) {
912 mask &= ~bond_mask;
913 break;
914 }
915 }
916
917 ocelot_write_rix(ocelot, mask,
918 ANA_PGID_PGID, PGID_SRC + p);
919 } else {
920 ocelot_write_rix(ocelot, 0,
921 ANA_PGID_PGID, PGID_SRC + p);
922 }
923 }
924 }
925 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
926
ocelot_set_ageing_time(struct ocelot * ocelot,unsigned int msecs)927 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
928 {
929 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
930
931 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
932 * which is clearly not what our intention is. So avoid that.
933 */
934 if (!age_period)
935 age_period = 1;
936
937 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
938 }
939 EXPORT_SYMBOL(ocelot_set_ageing_time);
940
ocelot_multicast_get(struct ocelot * ocelot,const unsigned char * addr,u16 vid)941 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
942 const unsigned char *addr,
943 u16 vid)
944 {
945 struct ocelot_multicast *mc;
946
947 list_for_each_entry(mc, &ocelot->multicast, list) {
948 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
949 return mc;
950 }
951
952 return NULL;
953 }
954
ocelot_classify_mdb(const unsigned char * addr)955 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
956 {
957 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
958 return ENTRYTYPE_MACv4;
959 if (addr[0] == 0x33 && addr[1] == 0x33)
960 return ENTRYTYPE_MACv6;
961 return ENTRYTYPE_NORMAL;
962 }
963
ocelot_mdb_get_pgid(struct ocelot * ocelot,enum macaccess_entry_type entry_type)964 static int ocelot_mdb_get_pgid(struct ocelot *ocelot,
965 enum macaccess_entry_type entry_type)
966 {
967 int pgid;
968
969 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
970 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
971 * destination mask table (PGID), the destination set is programmed as
972 * part of the entry MAC address.", and the DEST_IDX is set to 0.
973 */
974 if (entry_type == ENTRYTYPE_MACv4 ||
975 entry_type == ENTRYTYPE_MACv6)
976 return 0;
977
978 for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) {
979 struct ocelot_multicast *mc;
980 bool used = false;
981
982 list_for_each_entry(mc, &ocelot->multicast, list) {
983 if (mc->pgid == pgid) {
984 used = true;
985 break;
986 }
987 }
988
989 if (!used)
990 return pgid;
991 }
992
993 return -1;
994 }
995
ocelot_encode_ports_to_mdb(unsigned char * addr,struct ocelot_multicast * mc,enum macaccess_entry_type entry_type)996 static void ocelot_encode_ports_to_mdb(unsigned char *addr,
997 struct ocelot_multicast *mc,
998 enum macaccess_entry_type entry_type)
999 {
1000 memcpy(addr, mc->addr, ETH_ALEN);
1001
1002 if (entry_type == ENTRYTYPE_MACv4) {
1003 addr[0] = 0;
1004 addr[1] = mc->ports >> 8;
1005 addr[2] = mc->ports & 0xff;
1006 } else if (entry_type == ENTRYTYPE_MACv6) {
1007 addr[0] = mc->ports >> 8;
1008 addr[1] = mc->ports & 0xff;
1009 }
1010 }
1011
ocelot_port_mdb_add(struct ocelot * ocelot,int port,const struct switchdev_obj_port_mdb * mdb)1012 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1013 const struct switchdev_obj_port_mdb *mdb)
1014 {
1015 struct ocelot_port *ocelot_port = ocelot->ports[port];
1016 enum macaccess_entry_type entry_type;
1017 unsigned char addr[ETH_ALEN];
1018 struct ocelot_multicast *mc;
1019 u16 vid = mdb->vid;
1020 bool new = false;
1021
1022 if (port == ocelot->npi)
1023 port = ocelot->num_phys_ports;
1024
1025 if (!vid)
1026 vid = ocelot_port->pvid;
1027
1028 entry_type = ocelot_classify_mdb(mdb->addr);
1029
1030 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1031 if (!mc) {
1032 int pgid = ocelot_mdb_get_pgid(ocelot, entry_type);
1033
1034 if (pgid < 0) {
1035 dev_err(ocelot->dev,
1036 "No more PGIDs available for mdb %pM vid %d\n",
1037 mdb->addr, vid);
1038 return -ENOSPC;
1039 }
1040
1041 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1042 if (!mc)
1043 return -ENOMEM;
1044
1045 memcpy(mc->addr, mdb->addr, ETH_ALEN);
1046 mc->vid = vid;
1047 mc->pgid = pgid;
1048
1049 list_add_tail(&mc->list, &ocelot->multicast);
1050 new = true;
1051 }
1052
1053 if (!new) {
1054 ocelot_encode_ports_to_mdb(addr, mc, entry_type);
1055 ocelot_mact_forget(ocelot, addr, vid);
1056 }
1057
1058 mc->ports |= BIT(port);
1059 ocelot_encode_ports_to_mdb(addr, mc, entry_type);
1060
1061 return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type);
1062 }
1063 EXPORT_SYMBOL(ocelot_port_mdb_add);
1064
ocelot_port_mdb_del(struct ocelot * ocelot,int port,const struct switchdev_obj_port_mdb * mdb)1065 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1066 const struct switchdev_obj_port_mdb *mdb)
1067 {
1068 struct ocelot_port *ocelot_port = ocelot->ports[port];
1069 enum macaccess_entry_type entry_type;
1070 unsigned char addr[ETH_ALEN];
1071 struct ocelot_multicast *mc;
1072 u16 vid = mdb->vid;
1073
1074 if (port == ocelot->npi)
1075 port = ocelot->num_phys_ports;
1076
1077 if (!vid)
1078 vid = ocelot_port->pvid;
1079
1080 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1081 if (!mc)
1082 return -ENOENT;
1083
1084 entry_type = ocelot_classify_mdb(mdb->addr);
1085
1086 ocelot_encode_ports_to_mdb(addr, mc, entry_type);
1087 ocelot_mact_forget(ocelot, addr, vid);
1088
1089 mc->ports &= ~BIT(port);
1090 if (!mc->ports) {
1091 list_del(&mc->list);
1092 devm_kfree(ocelot->dev, mc);
1093 return 0;
1094 }
1095
1096 ocelot_encode_ports_to_mdb(addr, mc, entry_type);
1097
1098 return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type);
1099 }
1100 EXPORT_SYMBOL(ocelot_port_mdb_del);
1101
ocelot_port_bridge_join(struct ocelot * ocelot,int port,struct net_device * bridge)1102 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1103 struct net_device *bridge)
1104 {
1105 if (!ocelot->bridge_mask) {
1106 ocelot->hw_bridge_dev = bridge;
1107 } else {
1108 if (ocelot->hw_bridge_dev != bridge)
1109 /* This is adding the port to a second bridge, this is
1110 * unsupported */
1111 return -ENODEV;
1112 }
1113
1114 ocelot->bridge_mask |= BIT(port);
1115
1116 return 0;
1117 }
1118 EXPORT_SYMBOL(ocelot_port_bridge_join);
1119
ocelot_port_bridge_leave(struct ocelot * ocelot,int port,struct net_device * bridge)1120 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1121 struct net_device *bridge)
1122 {
1123 struct switchdev_trans trans;
1124 int ret;
1125
1126 ocelot->bridge_mask &= ~BIT(port);
1127
1128 if (!ocelot->bridge_mask)
1129 ocelot->hw_bridge_dev = NULL;
1130
1131 trans.ph_prepare = true;
1132 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans);
1133 if (ret)
1134 return ret;
1135
1136 trans.ph_prepare = false;
1137 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans);
1138 if (ret)
1139 return ret;
1140
1141 ocelot_port_set_pvid(ocelot, port, 0);
1142 return ocelot_port_set_native_vlan(ocelot, port, 0);
1143 }
1144 EXPORT_SYMBOL(ocelot_port_bridge_leave);
1145
ocelot_set_aggr_pgids(struct ocelot * ocelot)1146 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1147 {
1148 int i, port, lag;
1149
1150 /* Reset destination and aggregation PGIDS */
1151 for_each_unicast_dest_pgid(ocelot, port)
1152 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1153
1154 for_each_aggr_pgid(ocelot, i)
1155 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1156 ANA_PGID_PGID, i);
1157
1158 /* Now, set PGIDs for each LAG */
1159 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1160 unsigned long bond_mask;
1161 int aggr_count = 0;
1162 u8 aggr_idx[16];
1163
1164 bond_mask = ocelot->lags[lag];
1165 if (!bond_mask)
1166 continue;
1167
1168 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1169 // Destination mask
1170 ocelot_write_rix(ocelot, bond_mask,
1171 ANA_PGID_PGID, port);
1172 aggr_idx[aggr_count] = port;
1173 aggr_count++;
1174 }
1175
1176 for_each_aggr_pgid(ocelot, i) {
1177 u32 ac;
1178
1179 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1180 ac &= ~bond_mask;
1181 ac |= BIT(aggr_idx[i % aggr_count]);
1182 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1183 }
1184 }
1185 }
1186
ocelot_setup_lag(struct ocelot * ocelot,int lag)1187 static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
1188 {
1189 unsigned long bond_mask = ocelot->lags[lag];
1190 unsigned int p;
1191
1192 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
1193 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1194
1195 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1196
1197 /* Use lag port as logical port for port i */
1198 ocelot_write_gix(ocelot, port_cfg |
1199 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1200 ANA_PORT_PORT_CFG, p);
1201 }
1202 }
1203
ocelot_port_lag_join(struct ocelot * ocelot,int port,struct net_device * bond)1204 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1205 struct net_device *bond)
1206 {
1207 struct net_device *ndev;
1208 u32 bond_mask = 0;
1209 int lag, lp;
1210
1211 rcu_read_lock();
1212 for_each_netdev_in_bond_rcu(bond, ndev) {
1213 struct ocelot_port_private *priv = netdev_priv(ndev);
1214
1215 bond_mask |= BIT(priv->chip_port);
1216 }
1217 rcu_read_unlock();
1218
1219 lp = __ffs(bond_mask);
1220
1221 /* If the new port is the lowest one, use it as the logical port from
1222 * now on
1223 */
1224 if (port == lp) {
1225 lag = port;
1226 ocelot->lags[port] = bond_mask;
1227 bond_mask &= ~BIT(port);
1228 if (bond_mask) {
1229 lp = __ffs(bond_mask);
1230 ocelot->lags[lp] = 0;
1231 }
1232 } else {
1233 lag = lp;
1234 ocelot->lags[lp] |= BIT(port);
1235 }
1236
1237 ocelot_setup_lag(ocelot, lag);
1238 ocelot_set_aggr_pgids(ocelot);
1239
1240 return 0;
1241 }
1242 EXPORT_SYMBOL(ocelot_port_lag_join);
1243
ocelot_port_lag_leave(struct ocelot * ocelot,int port,struct net_device * bond)1244 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1245 struct net_device *bond)
1246 {
1247 u32 port_cfg;
1248 int i;
1249
1250 /* Remove port from any lag */
1251 for (i = 0; i < ocelot->num_phys_ports; i++)
1252 ocelot->lags[i] &= ~BIT(port);
1253
1254 /* if it was the logical port of the lag, move the lag config to the
1255 * next port
1256 */
1257 if (ocelot->lags[port]) {
1258 int n = __ffs(ocelot->lags[port]);
1259
1260 ocelot->lags[n] = ocelot->lags[port];
1261 ocelot->lags[port] = 0;
1262
1263 ocelot_setup_lag(ocelot, n);
1264 }
1265
1266 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1267 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1268 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port),
1269 ANA_PORT_PORT_CFG, port);
1270
1271 ocelot_set_aggr_pgids(ocelot);
1272 }
1273 EXPORT_SYMBOL(ocelot_port_lag_leave);
1274
1275 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
1276 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
1277 * In the special case that it's the NPI port that we're configuring, the
1278 * length of the tag and optional prefix needs to be accounted for privately,
1279 * in order to be able to sustain communication at the requested @sdu.
1280 */
ocelot_port_set_maxlen(struct ocelot * ocelot,int port,size_t sdu)1281 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
1282 {
1283 struct ocelot_port *ocelot_port = ocelot->ports[port];
1284 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
1285 int pause_start, pause_stop;
1286 int atop, atop_tot;
1287
1288 if (port == ocelot->npi) {
1289 maxlen += OCELOT_TAG_LEN;
1290
1291 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1292 maxlen += OCELOT_SHORT_PREFIX_LEN;
1293 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG)
1294 maxlen += OCELOT_LONG_PREFIX_LEN;
1295 }
1296
1297 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
1298
1299 /* Set Pause watermark hysteresis */
1300 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
1301 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
1302 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
1303 pause_start);
1304 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
1305 pause_stop);
1306
1307 /* Tail dropping watermarks */
1308 atop_tot = (ocelot->shared_queue_sz - 9 * maxlen) /
1309 OCELOT_BUFFER_CELL_SZ;
1310 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
1311 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
1312 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
1313 }
1314 EXPORT_SYMBOL(ocelot_port_set_maxlen);
1315
ocelot_get_max_mtu(struct ocelot * ocelot,int port)1316 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
1317 {
1318 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
1319
1320 if (port == ocelot->npi) {
1321 max_mtu -= OCELOT_TAG_LEN;
1322
1323 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1324 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
1325 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG)
1326 max_mtu -= OCELOT_LONG_PREFIX_LEN;
1327 }
1328
1329 return max_mtu;
1330 }
1331 EXPORT_SYMBOL(ocelot_get_max_mtu);
1332
ocelot_init_port(struct ocelot * ocelot,int port)1333 void ocelot_init_port(struct ocelot *ocelot, int port)
1334 {
1335 struct ocelot_port *ocelot_port = ocelot->ports[port];
1336
1337 skb_queue_head_init(&ocelot_port->tx_skbs);
1338 spin_lock_init(&ocelot_port->ts_id_lock);
1339
1340 /* Basic L2 initialization */
1341
1342 /* Set MAC IFG Gaps
1343 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
1344 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
1345 */
1346 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
1347 DEV_MAC_IFG_CFG);
1348
1349 /* Load seed (0) and set MAC HDX late collision */
1350 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
1351 DEV_MAC_HDX_CFG_SEED_LOAD,
1352 DEV_MAC_HDX_CFG);
1353 mdelay(1);
1354 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
1355 DEV_MAC_HDX_CFG);
1356
1357 /* Set Max Length and maximum tags allowed */
1358 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
1359 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
1360 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
1361 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
1362 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
1363 DEV_MAC_TAGS_CFG);
1364
1365 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
1366 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
1367 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
1368
1369 /* Enable transmission of pause frames */
1370 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
1371
1372 /* Drop frames with multicast source address */
1373 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1374 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1375 ANA_PORT_DROP_CFG, port);
1376
1377 /* Set default VLAN and tag type to 8021Q. */
1378 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
1379 REW_PORT_VLAN_CFG_PORT_TPID_M,
1380 REW_PORT_VLAN_CFG, port);
1381
1382 /* Enable vcap lookups */
1383 ocelot_vcap_enable(ocelot, port);
1384 }
1385 EXPORT_SYMBOL(ocelot_init_port);
1386
1387 /* Configure and enable the CPU port module, which is a set of queues
1388 * accessible through register MMIO, frame DMA or Ethernet (in case
1389 * NPI mode is used).
1390 */
ocelot_cpu_port_init(struct ocelot * ocelot)1391 static void ocelot_cpu_port_init(struct ocelot *ocelot)
1392 {
1393 int cpu = ocelot->num_phys_ports;
1394
1395 /* The unicast destination PGID for the CPU port module is unused */
1396 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
1397 /* Instead set up a multicast destination PGID for traffic copied to
1398 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
1399 * addresses will be copied to the CPU via this PGID.
1400 */
1401 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
1402 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
1403 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
1404 ANA_PORT_PORT_CFG, cpu);
1405
1406 /* Enable CPU port module */
1407 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
1408 /* CPU port Injection/Extraction configuration */
1409 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
1410 ocelot->xtr_prefix);
1411 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
1412 ocelot->inj_prefix);
1413
1414 /* Configure the CPU port to be VLAN aware */
1415 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
1416 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
1417 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
1418 ANA_PORT_VLAN_CFG, cpu);
1419 }
1420
ocelot_init(struct ocelot * ocelot)1421 int ocelot_init(struct ocelot *ocelot)
1422 {
1423 char queue_name[32];
1424 int i, ret;
1425 u32 port;
1426
1427 if (ocelot->ops->reset) {
1428 ret = ocelot->ops->reset(ocelot);
1429 if (ret) {
1430 dev_err(ocelot->dev, "Switch reset failed\n");
1431 return ret;
1432 }
1433 }
1434
1435 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
1436 sizeof(u32), GFP_KERNEL);
1437 if (!ocelot->lags)
1438 return -ENOMEM;
1439
1440 ocelot->stats = devm_kcalloc(ocelot->dev,
1441 ocelot->num_phys_ports * ocelot->num_stats,
1442 sizeof(u64), GFP_KERNEL);
1443 if (!ocelot->stats)
1444 return -ENOMEM;
1445
1446 mutex_init(&ocelot->stats_lock);
1447 mutex_init(&ocelot->ptp_lock);
1448 spin_lock_init(&ocelot->ptp_clock_lock);
1449 snprintf(queue_name, sizeof(queue_name), "%s-stats",
1450 dev_name(ocelot->dev));
1451 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
1452 if (!ocelot->stats_queue)
1453 return -ENOMEM;
1454
1455 INIT_LIST_HEAD(&ocelot->multicast);
1456 ocelot_mact_init(ocelot);
1457 ocelot_vlan_init(ocelot);
1458 ocelot_vcap_init(ocelot);
1459 ocelot_cpu_port_init(ocelot);
1460
1461 for (port = 0; port < ocelot->num_phys_ports; port++) {
1462 /* Clear all counters (5 groups) */
1463 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
1464 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
1465 SYS_STAT_CFG);
1466 }
1467
1468 /* Only use S-Tag */
1469 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
1470
1471 /* Aggregation mode */
1472 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
1473 ANA_AGGR_CFG_AC_DMAC_ENA |
1474 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
1475 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
1476
1477 /* Set MAC age time to default value. The entry is aged after
1478 * 2*AGE_PERIOD
1479 */
1480 ocelot_write(ocelot,
1481 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
1482 ANA_AUTOAGE);
1483
1484 /* Disable learning for frames discarded by VLAN ingress filtering */
1485 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
1486
1487 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
1488 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
1489 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
1490
1491 /* Setup flooding PGIDs */
1492 for (i = 0; i < ocelot->num_flooding_pgids; i++)
1493 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
1494 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
1495 ANA_FLOODING_FLD_UNICAST(PGID_UC),
1496 ANA_FLOODING, i);
1497 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
1498 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
1499 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
1500 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
1501 ANA_FLOODING_IPMC);
1502
1503 for (port = 0; port < ocelot->num_phys_ports; port++) {
1504 /* Transmit the frame to the local port. */
1505 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1506 /* Do not forward BPDU frames to the front ports. */
1507 ocelot_write_gix(ocelot,
1508 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
1509 ANA_PORT_CPU_FWD_BPDU_CFG,
1510 port);
1511 /* Ensure bridging is disabled */
1512 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
1513 }
1514
1515 /* Allow broadcast MAC frames. */
1516 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
1517 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
1518
1519 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
1520 }
1521 ocelot_write_rix(ocelot,
1522 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
1523 ANA_PGID_PGID, PGID_MC);
1524 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
1525 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
1526
1527 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
1528 * registers endianness.
1529 */
1530 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
1531 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
1532 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
1533 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
1534 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
1535 ANA_CPUQ_CFG_CPUQ_LRN(2) |
1536 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
1537 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
1538 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
1539 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
1540 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
1541 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
1542 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
1543 for (i = 0; i < 16; i++)
1544 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
1545 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
1546 ANA_CPUQ_8021_CFG, i);
1547
1548 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
1549 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1550 OCELOT_STATS_CHECK_DELAY);
1551
1552 return 0;
1553 }
1554 EXPORT_SYMBOL(ocelot_init);
1555
ocelot_deinit(struct ocelot * ocelot)1556 void ocelot_deinit(struct ocelot *ocelot)
1557 {
1558 cancel_delayed_work(&ocelot->stats_work);
1559 destroy_workqueue(ocelot->stats_queue);
1560 mutex_destroy(&ocelot->stats_lock);
1561 }
1562 EXPORT_SYMBOL(ocelot_deinit);
1563
ocelot_deinit_port(struct ocelot * ocelot,int port)1564 void ocelot_deinit_port(struct ocelot *ocelot, int port)
1565 {
1566 struct ocelot_port *ocelot_port = ocelot->ports[port];
1567
1568 skb_queue_purge(&ocelot_port->tx_skbs);
1569 }
1570 EXPORT_SYMBOL(ocelot_deinit_port);
1571
1572 MODULE_LICENSE("Dual MIT/GPL");
1573
