1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * driver for Microchip PQI-based storage controllers 4 * Copyright (c) 2019-2022 Microchip Technology Inc. and its subsidiaries 5 * Copyright (c) 2016-2018 Microsemi Corporation 6 * Copyright (c) 2016 PMC-Sierra, Inc. 7 * 8 * Questions/Comments/Bugfixes to storagedev@microchip.com 9 * 10 */ 11 12 #include <linux/io-64-nonatomic-lo-hi.h> 13 14 #if !defined(_SMARTPQI_H) 15 #define _SMARTPQI_H 16 17 #include <scsi/scsi_host.h> 18 #include <linux/bsg-lib.h> 19 20 #pragma pack(1) 21 22 #define PQI_DEVICE_SIGNATURE "PQI DREG" 23 24 /* This structure is defined by the PQI specification. */ 25 struct pqi_device_registers { 26 __le64 signature; 27 u8 function_and_status_code; 28 u8 reserved[7]; 29 u8 max_admin_iq_elements; 30 u8 max_admin_oq_elements; 31 u8 admin_iq_element_length; /* in 16-byte units */ 32 u8 admin_oq_element_length; /* in 16-byte units */ 33 __le16 max_reset_timeout; /* in 100-millisecond units */ 34 u8 reserved1[2]; 35 __le32 legacy_intx_status; 36 __le32 legacy_intx_mask_set; 37 __le32 legacy_intx_mask_clear; 38 u8 reserved2[28]; 39 __le32 device_status; 40 u8 reserved3[4]; 41 __le64 admin_iq_pi_offset; 42 __le64 admin_oq_ci_offset; 43 __le64 admin_iq_element_array_addr; 44 __le64 admin_oq_element_array_addr; 45 __le64 admin_iq_ci_addr; 46 __le64 admin_oq_pi_addr; 47 u8 admin_iq_num_elements; 48 u8 admin_oq_num_elements; 49 __le16 admin_queue_int_msg_num; 50 u8 reserved4[4]; 51 __le32 device_error; 52 u8 reserved5[4]; 53 __le64 error_details; 54 __le32 device_reset; 55 __le32 power_action; 56 u8 reserved6[104]; 57 }; 58 59 /* 60 * controller registers 61 * 62 * These are defined by the Microchip implementation. 63 * 64 * Some registers (those named sis_*) are only used when in 65 * legacy SIS mode before we transition the controller into 66 * PQI mode. There are a number of other SIS mode registers, 67 * but we don't use them, so only the SIS registers that we 68 * care about are defined here. The offsets mentioned in the 69 * comments are the offsets from the PCIe BAR 0. 70 */ 71 struct pqi_ctrl_registers { 72 u8 reserved[0x20]; 73 __le32 sis_host_to_ctrl_doorbell; /* 20h */ 74 u8 reserved1[0x34 - (0x20 + sizeof(__le32))]; 75 __le32 sis_interrupt_mask; /* 34h */ 76 u8 reserved2[0x9c - (0x34 + sizeof(__le32))]; 77 __le32 sis_ctrl_to_host_doorbell; /* 9Ch */ 78 u8 reserved3[0xa0 - (0x9c + sizeof(__le32))]; 79 __le32 sis_ctrl_to_host_doorbell_clear; /* A0h */ 80 u8 reserved4[0xb0 - (0xa0 + sizeof(__le32))]; 81 __le32 sis_driver_scratch; /* B0h */ 82 __le32 sis_product_identifier; /* B4h */ 83 u8 reserved5[0xbc - (0xb4 + sizeof(__le32))]; 84 __le32 sis_firmware_status; /* BCh */ 85 u8 reserved6[0xcc - (0xbc + sizeof(__le32))]; 86 __le32 sis_ctrl_shutdown_reason_code; /* CCh */ 87 u8 reserved7[0x1000 - (0xcc + sizeof(__le32))]; 88 __le32 sis_mailbox[8]; /* 1000h */ 89 u8 reserved8[0x4000 - (0x1000 + (sizeof(__le32) * 8))]; 90 /* 91 * The PQI spec states that the PQI registers should be at 92 * offset 0 from the PCIe BAR 0. However, we can't map 93 * them at offset 0 because that would break compatibility 94 * with the SIS registers. So we map them at offset 4000h. 95 */ 96 struct pqi_device_registers pqi_registers; /* 4000h */ 97 }; 98 99 #define PQI_DEVICE_REGISTERS_OFFSET 0x4000 100 101 /* shutdown reasons for taking the controller offline */ 102 enum pqi_ctrl_shutdown_reason { 103 PQI_IQ_NOT_DRAINED_TIMEOUT = 1, 104 PQI_LUN_RESET_TIMEOUT = 2, 105 PQI_IO_PENDING_POST_LUN_RESET_TIMEOUT = 3, 106 PQI_NO_HEARTBEAT = 4, 107 PQI_FIRMWARE_KERNEL_NOT_UP = 5, 108 PQI_OFA_RESPONSE_TIMEOUT = 6, 109 PQI_INVALID_REQ_ID = 7, 110 PQI_UNMATCHED_REQ_ID = 8, 111 PQI_IO_PI_OUT_OF_RANGE = 9, 112 PQI_EVENT_PI_OUT_OF_RANGE = 10, 113 PQI_UNEXPECTED_IU_TYPE = 11 114 }; 115 116 enum pqi_io_path { 117 RAID_PATH = 0, 118 AIO_PATH = 1 119 }; 120 121 enum pqi_irq_mode { 122 IRQ_MODE_NONE, 123 IRQ_MODE_INTX, 124 IRQ_MODE_MSIX 125 }; 126 127 struct pqi_sg_descriptor { 128 __le64 address; 129 __le32 length; 130 __le32 flags; 131 }; 132 133 /* manifest constants for the flags field of pqi_sg_descriptor */ 134 #define CISS_SG_LAST 0x40000000 135 #define CISS_SG_CHAIN 0x80000000 136 137 struct pqi_iu_header { 138 u8 iu_type; 139 u8 reserved; 140 __le16 iu_length; /* in bytes - does not include the length */ 141 /* of this header */ 142 __le16 response_queue_id; /* specifies the OQ where the */ 143 /* response IU is to be delivered */ 144 u16 driver_flags; /* reserved for driver use */ 145 }; 146 147 /* manifest constants for pqi_iu_header.driver_flags */ 148 #define PQI_DRIVER_NONBLOCKABLE_REQUEST 0x1 149 150 /* 151 * According to the PQI spec, the IU header is only the first 4 bytes of our 152 * pqi_iu_header structure. 153 */ 154 #define PQI_REQUEST_HEADER_LENGTH 4 155 156 struct pqi_general_admin_request { 157 struct pqi_iu_header header; 158 __le16 request_id; 159 u8 function_code; 160 union { 161 struct { 162 u8 reserved[33]; 163 __le32 buffer_length; 164 struct pqi_sg_descriptor sg_descriptor; 165 } report_device_capability; 166 167 struct { 168 u8 reserved; 169 __le16 queue_id; 170 u8 reserved1[2]; 171 __le64 element_array_addr; 172 __le64 ci_addr; 173 __le16 num_elements; 174 __le16 element_length; 175 u8 queue_protocol; 176 u8 reserved2[23]; 177 __le32 vendor_specific; 178 } create_operational_iq; 179 180 struct { 181 u8 reserved; 182 __le16 queue_id; 183 u8 reserved1[2]; 184 __le64 element_array_addr; 185 __le64 pi_addr; 186 __le16 num_elements; 187 __le16 element_length; 188 u8 queue_protocol; 189 u8 reserved2[3]; 190 __le16 int_msg_num; 191 __le16 coalescing_count; 192 __le32 min_coalescing_time; 193 __le32 max_coalescing_time; 194 u8 reserved3[8]; 195 __le32 vendor_specific; 196 } create_operational_oq; 197 198 struct { 199 u8 reserved; 200 __le16 queue_id; 201 u8 reserved1[50]; 202 } delete_operational_queue; 203 204 struct { 205 u8 reserved; 206 __le16 queue_id; 207 u8 reserved1[46]; 208 __le32 vendor_specific; 209 } change_operational_iq_properties; 210 211 } data; 212 }; 213 214 struct pqi_general_admin_response { 215 struct pqi_iu_header header; 216 __le16 request_id; 217 u8 function_code; 218 u8 status; 219 union { 220 struct { 221 u8 status_descriptor[4]; 222 __le64 iq_pi_offset; 223 u8 reserved[40]; 224 } create_operational_iq; 225 226 struct { 227 u8 status_descriptor[4]; 228 __le64 oq_ci_offset; 229 u8 reserved[40]; 230 } create_operational_oq; 231 } data; 232 }; 233 234 struct pqi_iu_layer_descriptor { 235 u8 inbound_spanning_supported : 1; 236 u8 reserved : 7; 237 u8 reserved1[5]; 238 __le16 max_inbound_iu_length; 239 u8 outbound_spanning_supported : 1; 240 u8 reserved2 : 7; 241 u8 reserved3[5]; 242 __le16 max_outbound_iu_length; 243 }; 244 245 struct pqi_device_capability { 246 __le16 data_length; 247 u8 reserved[6]; 248 u8 iq_arbitration_priority_support_bitmask; 249 u8 maximum_aw_a; 250 u8 maximum_aw_b; 251 u8 maximum_aw_c; 252 u8 max_arbitration_burst : 3; 253 u8 reserved1 : 4; 254 u8 iqa : 1; 255 u8 reserved2[2]; 256 u8 iq_freeze : 1; 257 u8 reserved3 : 7; 258 __le16 max_inbound_queues; 259 __le16 max_elements_per_iq; 260 u8 reserved4[4]; 261 __le16 max_iq_element_length; 262 __le16 min_iq_element_length; 263 u8 reserved5[2]; 264 __le16 max_outbound_queues; 265 __le16 max_elements_per_oq; 266 __le16 intr_coalescing_time_granularity; 267 __le16 max_oq_element_length; 268 __le16 min_oq_element_length; 269 u8 reserved6[24]; 270 struct pqi_iu_layer_descriptor iu_layer_descriptors[32]; 271 }; 272 273 #define PQI_MAX_EMBEDDED_SG_DESCRIPTORS 4 274 #define PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS 3 275 276 struct pqi_raid_path_request { 277 struct pqi_iu_header header; 278 __le16 request_id; 279 __le16 nexus_id; 280 __le32 buffer_length; 281 u8 lun_number[8]; 282 __le16 protocol_specific; 283 u8 data_direction : 2; 284 u8 partial : 1; 285 u8 reserved1 : 4; 286 u8 fence : 1; 287 __le16 error_index; 288 u8 reserved2; 289 u8 task_attribute : 3; 290 u8 command_priority : 4; 291 u8 reserved3 : 1; 292 u8 reserved4 : 2; 293 u8 additional_cdb_bytes_usage : 3; 294 u8 reserved5 : 3; 295 u8 cdb[16]; 296 u8 reserved6[11]; 297 u8 ml_device_lun_number; 298 __le32 timeout; 299 struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS]; 300 }; 301 302 struct pqi_aio_path_request { 303 struct pqi_iu_header header; 304 __le16 request_id; 305 u8 reserved1[2]; 306 __le32 nexus_id; 307 __le32 buffer_length; 308 u8 data_direction : 2; 309 u8 partial : 1; 310 u8 memory_type : 1; 311 u8 fence : 1; 312 u8 encryption_enable : 1; 313 u8 reserved2 : 2; 314 u8 task_attribute : 3; 315 u8 command_priority : 4; 316 u8 reserved3 : 1; 317 __le16 data_encryption_key_index; 318 __le32 encrypt_tweak_lower; 319 __le32 encrypt_tweak_upper; 320 u8 cdb[16]; 321 __le16 error_index; 322 u8 num_sg_descriptors; 323 u8 cdb_length; 324 u8 lun_number[8]; 325 u8 reserved4[4]; 326 struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS]; 327 }; 328 329 #define PQI_RAID1_NVME_XFER_LIMIT (32 * 1024) /* 32 KiB */ 330 331 struct pqi_aio_r1_path_request { 332 struct pqi_iu_header header; 333 __le16 request_id; 334 __le16 volume_id; /* ID of the RAID volume */ 335 __le32 it_nexus_1; /* IT nexus of the 1st drive in the RAID volume */ 336 __le32 it_nexus_2; /* IT nexus of the 2nd drive in the RAID volume */ 337 __le32 it_nexus_3; /* IT nexus of the 3rd drive in the RAID volume */ 338 __le32 data_length; /* total bytes to read/write */ 339 u8 data_direction : 2; 340 u8 partial : 1; 341 u8 memory_type : 1; 342 u8 fence : 1; 343 u8 encryption_enable : 1; 344 u8 reserved : 2; 345 u8 task_attribute : 3; 346 u8 command_priority : 4; 347 u8 reserved2 : 1; 348 __le16 data_encryption_key_index; 349 u8 cdb[16]; 350 __le16 error_index; 351 u8 num_sg_descriptors; 352 u8 cdb_length; 353 u8 num_drives; /* number of drives in the RAID volume (2 or 3) */ 354 u8 reserved3[3]; 355 __le32 encrypt_tweak_lower; 356 __le32 encrypt_tweak_upper; 357 struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS]; 358 }; 359 360 #define PQI_DEFAULT_MAX_WRITE_RAID_5_6 (8 * 1024U) 361 #define PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_SAS_SATA (~0U) 362 #define PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_NVME (32 * 1024U) 363 364 struct pqi_aio_r56_path_request { 365 struct pqi_iu_header header; 366 __le16 request_id; 367 __le16 volume_id; /* ID of the RAID volume */ 368 __le32 data_it_nexus; /* IT nexus for the data drive */ 369 __le32 p_parity_it_nexus; /* IT nexus for the P parity drive */ 370 __le32 q_parity_it_nexus; /* IT nexus for the Q parity drive */ 371 __le32 data_length; /* total bytes to read/write */ 372 u8 data_direction : 2; 373 u8 partial : 1; 374 u8 mem_type : 1; /* 0 = PCIe, 1 = DDR */ 375 u8 fence : 1; 376 u8 encryption_enable : 1; 377 u8 reserved : 2; 378 u8 task_attribute : 3; 379 u8 command_priority : 4; 380 u8 reserved1 : 1; 381 __le16 data_encryption_key_index; 382 u8 cdb[16]; 383 __le16 error_index; 384 u8 num_sg_descriptors; 385 u8 cdb_length; 386 u8 xor_multiplier; 387 u8 reserved2[3]; 388 __le32 encrypt_tweak_lower; 389 __le32 encrypt_tweak_upper; 390 __le64 row; /* row = logical LBA/blocks per row */ 391 u8 reserved3[8]; 392 struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS]; 393 }; 394 395 struct pqi_io_response { 396 struct pqi_iu_header header; 397 __le16 request_id; 398 __le16 error_index; 399 u8 reserved2[4]; 400 }; 401 402 struct pqi_general_management_request { 403 struct pqi_iu_header header; 404 __le16 request_id; 405 union { 406 struct { 407 u8 reserved[2]; 408 __le32 buffer_length; 409 struct pqi_sg_descriptor sg_descriptors[3]; 410 } report_event_configuration; 411 412 struct { 413 __le16 global_event_oq_id; 414 __le32 buffer_length; 415 struct pqi_sg_descriptor sg_descriptors[3]; 416 } set_event_configuration; 417 } data; 418 }; 419 420 struct pqi_event_descriptor { 421 u8 event_type; 422 u8 reserved; 423 __le16 oq_id; 424 }; 425 426 struct pqi_event_config { 427 u8 reserved[2]; 428 u8 num_event_descriptors; 429 u8 reserved1; 430 struct pqi_event_descriptor descriptors[]; 431 }; 432 433 #define PQI_MAX_EVENT_DESCRIPTORS 255 434 435 #define PQI_EVENT_OFA_MEMORY_ALLOCATION 0x0 436 #define PQI_EVENT_OFA_QUIESCE 0x1 437 #define PQI_EVENT_OFA_CANCELED 0x2 438 439 struct pqi_event_response { 440 struct pqi_iu_header header; 441 u8 event_type; 442 u8 reserved2 : 7; 443 u8 request_acknowledge : 1; 444 __le16 event_id; 445 __le32 additional_event_id; 446 union { 447 struct { 448 __le32 bytes_requested; 449 u8 reserved[12]; 450 } ofa_memory_allocation; 451 452 struct { 453 __le16 reason; /* reason for cancellation */ 454 u8 reserved[14]; 455 } ofa_cancelled; 456 } data; 457 }; 458 459 struct pqi_event_acknowledge_request { 460 struct pqi_iu_header header; 461 u8 event_type; 462 u8 reserved2; 463 __le16 event_id; 464 __le32 additional_event_id; 465 }; 466 467 struct pqi_task_management_request { 468 struct pqi_iu_header header; 469 __le16 request_id; 470 __le16 nexus_id; 471 u8 reserved; 472 u8 ml_device_lun_number; 473 __le16 timeout; 474 u8 lun_number[8]; 475 __le16 protocol_specific; 476 __le16 outbound_queue_id_to_manage; 477 __le16 request_id_to_manage; 478 u8 task_management_function; 479 u8 reserved2 : 7; 480 u8 fence : 1; 481 }; 482 483 #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8 484 485 struct pqi_task_management_response { 486 struct pqi_iu_header header; 487 __le16 request_id; 488 __le16 nexus_id; 489 u8 additional_response_info[3]; 490 u8 response_code; 491 }; 492 493 struct pqi_vendor_general_request { 494 struct pqi_iu_header header; 495 __le16 request_id; 496 __le16 function_code; 497 union { 498 struct { 499 __le16 first_section; 500 __le16 last_section; 501 u8 reserved[48]; 502 } config_table_update; 503 504 struct { 505 __le64 buffer_address; 506 __le32 buffer_length; 507 u8 reserved[40]; 508 } ofa_memory_allocation; 509 } data; 510 }; 511 512 struct pqi_vendor_general_response { 513 struct pqi_iu_header header; 514 __le16 request_id; 515 __le16 function_code; 516 __le16 status; 517 u8 reserved[2]; 518 }; 519 520 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0 521 #define PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE 1 522 523 #define PQI_OFA_VERSION 1 524 #define PQI_OFA_SIGNATURE "OFA_QRM" 525 #define PQI_OFA_MAX_SG_DESCRIPTORS 64 526 527 struct pqi_ofa_memory { 528 __le64 signature; /* "OFA_QRM" */ 529 __le16 version; /* version of this struct (1 = 1st version) */ 530 u8 reserved[62]; 531 __le32 bytes_allocated; /* total allocated memory in bytes */ 532 __le16 num_memory_descriptors; 533 u8 reserved1[2]; 534 struct pqi_sg_descriptor sg_descriptor[PQI_OFA_MAX_SG_DESCRIPTORS]; 535 }; 536 537 struct pqi_aio_error_info { 538 u8 status; 539 u8 service_response; 540 u8 data_present; 541 u8 reserved; 542 __le32 residual_count; 543 __le16 data_length; 544 __le16 reserved1; 545 u8 data[256]; 546 }; 547 548 struct pqi_raid_error_info { 549 u8 data_in_result; 550 u8 data_out_result; 551 u8 reserved[3]; 552 u8 status; 553 __le16 status_qualifier; 554 __le16 sense_data_length; 555 __le16 response_data_length; 556 __le32 data_in_transferred; 557 __le32 data_out_transferred; 558 u8 data[256]; 559 }; 560 561 #define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13 562 #define PQI_REQUEST_IU_RAID_PATH_IO 0x14 563 #define PQI_REQUEST_IU_AIO_PATH_IO 0x15 564 #define PQI_REQUEST_IU_AIO_PATH_RAID5_IO 0x18 565 #define PQI_REQUEST_IU_AIO_PATH_RAID6_IO 0x19 566 #define PQI_REQUEST_IU_AIO_PATH_RAID1_IO 0x1A 567 #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60 568 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72 569 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73 570 #define PQI_REQUEST_IU_VENDOR_GENERAL 0x75 571 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 572 573 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 574 #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93 575 #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0 576 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0 577 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1 578 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2 579 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3 580 #define PQI_RESPONSE_IU_AIO_PATH_DISABLED 0xf4 581 #define PQI_RESPONSE_IU_VENDOR_EVENT 0xf5 582 #define PQI_RESPONSE_IU_VENDOR_GENERAL 0xf7 583 584 #define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY 0x0 585 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ 0x10 586 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ 0x11 587 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ 0x12 588 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ 0x13 589 #define PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY 0x14 590 591 #define PQI_GENERAL_ADMIN_STATUS_SUCCESS 0x0 592 593 #define PQI_IQ_PROPERTY_IS_AIO_QUEUE 0x1 594 595 #define PQI_GENERAL_ADMIN_IU_LENGTH 0x3c 596 #define PQI_PROTOCOL_SOP 0x0 597 598 #define PQI_DATA_IN_OUT_GOOD 0x0 599 #define PQI_DATA_IN_OUT_UNDERFLOW 0x1 600 #define PQI_DATA_IN_OUT_BUFFER_ERROR 0x40 601 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW 0x41 602 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42 603 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43 604 #define PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60 605 #define PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61 606 #define PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62 607 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED 0x63 608 #define PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64 609 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65 610 #define PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66 611 #define PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67 612 #define PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x6F 613 #define PQI_DATA_IN_OUT_ERROR 0xf0 614 #define PQI_DATA_IN_OUT_PROTOCOL_ERROR 0xf1 615 #define PQI_DATA_IN_OUT_HARDWARE_ERROR 0xf2 616 #define PQI_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3 617 #define PQI_DATA_IN_OUT_ABORTED 0xf4 618 #define PQI_DATA_IN_OUT_TIMEOUT 0xf5 619 620 #define CISS_CMD_STATUS_SUCCESS 0x0 621 #define CISS_CMD_STATUS_TARGET_STATUS 0x1 622 #define CISS_CMD_STATUS_DATA_UNDERRUN 0x2 623 #define CISS_CMD_STATUS_DATA_OVERRUN 0x3 624 #define CISS_CMD_STATUS_INVALID 0x4 625 #define CISS_CMD_STATUS_PROTOCOL_ERROR 0x5 626 #define CISS_CMD_STATUS_HARDWARE_ERROR 0x6 627 #define CISS_CMD_STATUS_CONNECTION_LOST 0x7 628 #define CISS_CMD_STATUS_ABORTED 0x8 629 #define CISS_CMD_STATUS_ABORT_FAILED 0x9 630 #define CISS_CMD_STATUS_UNSOLICITED_ABORT 0xa 631 #define CISS_CMD_STATUS_TIMEOUT 0xb 632 #define CISS_CMD_STATUS_UNABORTABLE 0xc 633 #define CISS_CMD_STATUS_TMF 0xd 634 #define CISS_CMD_STATUS_AIO_DISABLED 0xe 635 636 #define PQI_CMD_STATUS_ABORTED CISS_CMD_STATUS_ABORTED 637 638 #define PQI_NUM_EVENT_QUEUE_ELEMENTS 32 639 #define PQI_EVENT_OQ_ELEMENT_LENGTH sizeof(struct pqi_event_response) 640 641 #define PQI_EVENT_TYPE_HOTPLUG 0x1 642 #define PQI_EVENT_TYPE_HARDWARE 0x2 643 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4 644 #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5 645 #define PQI_EVENT_TYPE_OFA 0xfb 646 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd 647 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe 648 649 #pragma pack() 650 651 #define PQI_ERROR_BUFFER_ELEMENT_LENGTH \ 652 sizeof(struct pqi_raid_error_info) 653 654 /* these values are based on our implementation */ 655 #define PQI_ADMIN_IQ_NUM_ELEMENTS 8 656 #define PQI_ADMIN_OQ_NUM_ELEMENTS 20 657 #define PQI_ADMIN_IQ_ELEMENT_LENGTH 64 658 #define PQI_ADMIN_OQ_ELEMENT_LENGTH 64 659 660 #define PQI_OPERATIONAL_IQ_ELEMENT_LENGTH 128 661 #define PQI_OPERATIONAL_OQ_ELEMENT_LENGTH 16 662 663 #define PQI_MIN_MSIX_VECTORS 1 664 #define PQI_MAX_MSIX_VECTORS 64 665 666 /* these values are defined by the PQI spec */ 667 #define PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE 255 668 #define PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE 65535 669 670 #define PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT 64 671 #define PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT 16 672 #define PQI_ADMIN_INDEX_ALIGNMENT 64 673 #define PQI_OPERATIONAL_INDEX_ALIGNMENT 4 674 675 #define PQI_MIN_OPERATIONAL_QUEUE_ID 1 676 #define PQI_MAX_OPERATIONAL_QUEUE_ID 65535 677 678 #define PQI_AIO_SERV_RESPONSE_COMPLETE 0 679 #define PQI_AIO_SERV_RESPONSE_FAILURE 1 680 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2 681 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3 682 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4 683 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5 684 685 #define PQI_AIO_STATUS_IO_ERROR 0x1 686 #define PQI_AIO_STATUS_IO_ABORTED 0x2 687 #define PQI_AIO_STATUS_NO_PATH_TO_DEVICE 0x3 688 #define PQI_AIO_STATUS_INVALID_DEVICE 0x4 689 #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe 690 #define PQI_AIO_STATUS_UNDERRUN 0x51 691 #define PQI_AIO_STATUS_OVERRUN 0x75 692 693 typedef u32 pqi_index_t; 694 695 /* SOP data direction flags */ 696 #define SOP_NO_DIRECTION_FLAG 0 697 #define SOP_WRITE_FLAG 1 /* host writes data to Data-Out */ 698 /* buffer */ 699 #define SOP_READ_FLAG 2 /* host receives data from Data-In */ 700 /* buffer */ 701 #define SOP_BIDIRECTIONAL 3 /* data is transferred from the */ 702 /* Data-Out buffer and data is */ 703 /* transferred to the Data-In buffer */ 704 705 #define SOP_TASK_ATTRIBUTE_SIMPLE 0 706 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1 707 #define SOP_TASK_ATTRIBUTE_ORDERED 2 708 #define SOP_TASK_ATTRIBUTE_ACA 4 709 710 #define SOP_TMF_COMPLETE 0x0 711 #define SOP_TMF_REJECTED 0x4 712 #define SOP_TMF_FUNCTION_SUCCEEDED 0x8 713 #define SOP_RC_INCORRECT_LOGICAL_UNIT 0x9 714 715 /* additional CDB bytes usage field codes */ 716 #define SOP_ADDITIONAL_CDB_BYTES_0 0 /* 16-byte CDB */ 717 #define SOP_ADDITIONAL_CDB_BYTES_4 1 /* 20-byte CDB */ 718 #define SOP_ADDITIONAL_CDB_BYTES_8 2 /* 24-byte CDB */ 719 #define SOP_ADDITIONAL_CDB_BYTES_12 3 /* 28-byte CDB */ 720 #define SOP_ADDITIONAL_CDB_BYTES_16 4 /* 32-byte CDB */ 721 722 /* 723 * The purpose of this structure is to obtain proper alignment of objects in 724 * an admin queue pair. 725 */ 726 struct pqi_admin_queues_aligned { 727 __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT) 728 u8 iq_element_array[PQI_ADMIN_IQ_ELEMENT_LENGTH] 729 [PQI_ADMIN_IQ_NUM_ELEMENTS]; 730 __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT) 731 u8 oq_element_array[PQI_ADMIN_OQ_ELEMENT_LENGTH] 732 [PQI_ADMIN_OQ_NUM_ELEMENTS]; 733 __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t iq_ci; 734 __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t oq_pi; 735 }; 736 737 struct pqi_admin_queues { 738 void *iq_element_array; 739 void *oq_element_array; 740 pqi_index_t __iomem *iq_ci; 741 pqi_index_t __iomem *oq_pi; 742 dma_addr_t iq_element_array_bus_addr; 743 dma_addr_t oq_element_array_bus_addr; 744 dma_addr_t iq_ci_bus_addr; 745 dma_addr_t oq_pi_bus_addr; 746 __le32 __iomem *iq_pi; 747 pqi_index_t iq_pi_copy; 748 __le32 __iomem *oq_ci; 749 pqi_index_t oq_ci_copy; 750 struct task_struct *task; 751 u16 int_msg_num; 752 }; 753 754 struct pqi_queue_group { 755 struct pqi_ctrl_info *ctrl_info; /* backpointer */ 756 u16 iq_id[2]; 757 u16 oq_id; 758 u16 int_msg_num; 759 void *iq_element_array[2]; 760 void *oq_element_array; 761 dma_addr_t iq_element_array_bus_addr[2]; 762 dma_addr_t oq_element_array_bus_addr; 763 __le32 __iomem *iq_pi[2]; 764 pqi_index_t iq_pi_copy[2]; 765 pqi_index_t __iomem *iq_ci[2]; 766 pqi_index_t __iomem *oq_pi; 767 dma_addr_t iq_ci_bus_addr[2]; 768 dma_addr_t oq_pi_bus_addr; 769 __le32 __iomem *oq_ci; 770 pqi_index_t oq_ci_copy; 771 spinlock_t submit_lock[2]; /* protect submission queue */ 772 struct list_head request_list[2]; 773 }; 774 775 struct pqi_event_queue { 776 u16 oq_id; 777 u16 int_msg_num; 778 void *oq_element_array; 779 pqi_index_t __iomem *oq_pi; 780 dma_addr_t oq_element_array_bus_addr; 781 dma_addr_t oq_pi_bus_addr; 782 __le32 __iomem *oq_ci; 783 pqi_index_t oq_ci_copy; 784 }; 785 786 #define PQI_DEFAULT_QUEUE_GROUP 0 787 #define PQI_MAX_QUEUE_GROUPS PQI_MAX_MSIX_VECTORS 788 789 struct pqi_encryption_info { 790 u16 data_encryption_key_index; 791 u32 encrypt_tweak_lower; 792 u32 encrypt_tweak_upper; 793 }; 794 795 #pragma pack(1) 796 797 #define PQI_CONFIG_TABLE_SIGNATURE "CFGTABLE" 798 #define PQI_CONFIG_TABLE_MAX_LENGTH ((u16)~0) 799 800 /* configuration table section IDs */ 801 #define PQI_CONFIG_TABLE_ALL_SECTIONS (-1) 802 #define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO 0 803 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES 1 804 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA 2 805 #define PQI_CONFIG_TABLE_SECTION_DEBUG 3 806 #define PQI_CONFIG_TABLE_SECTION_HEARTBEAT 4 807 #define PQI_CONFIG_TABLE_SECTION_SOFT_RESET 5 808 809 struct pqi_config_table { 810 u8 signature[8]; /* "CFGTABLE" */ 811 __le32 first_section_offset; /* offset in bytes from the base */ 812 /* address of this table to the */ 813 /* first section */ 814 }; 815 816 struct pqi_config_table_section_header { 817 __le16 section_id; /* as defined by the */ 818 /* PQI_CONFIG_TABLE_SECTION_* */ 819 /* manifest constants above */ 820 __le16 next_section_offset; /* offset in bytes from base */ 821 /* address of the table of the */ 822 /* next section or 0 if last entry */ 823 }; 824 825 struct pqi_config_table_general_info { 826 struct pqi_config_table_section_header header; 827 __le32 section_length; /* size of this section in bytes */ 828 /* including the section header */ 829 __le32 max_outstanding_requests; /* max. outstanding */ 830 /* commands supported by */ 831 /* the controller */ 832 __le32 max_sg_size; /* max. transfer size of a single */ 833 /* command */ 834 __le32 max_sg_per_request; /* max. number of scatter-gather */ 835 /* entries supported in a single */ 836 /* command */ 837 }; 838 839 struct pqi_config_table_firmware_features { 840 struct pqi_config_table_section_header header; 841 __le16 num_elements; 842 u8 features_supported[]; 843 /* u8 features_requested_by_host[]; */ 844 /* u8 features_enabled[]; */ 845 /* The 2 fields below are only valid if the MAX_KNOWN_FEATURE bit is set. */ 846 /* __le16 firmware_max_known_feature; */ 847 /* __le16 host_max_known_feature; */ 848 }; 849 850 #define PQI_FIRMWARE_FEATURE_OFA 0 851 #define PQI_FIRMWARE_FEATURE_SMP 1 852 #define PQI_FIRMWARE_FEATURE_MAX_KNOWN_FEATURE 2 853 #define PQI_FIRMWARE_FEATURE_RAID_0_READ_BYPASS 3 854 #define PQI_FIRMWARE_FEATURE_RAID_1_READ_BYPASS 4 855 #define PQI_FIRMWARE_FEATURE_RAID_5_READ_BYPASS 5 856 #define PQI_FIRMWARE_FEATURE_RAID_6_READ_BYPASS 6 857 #define PQI_FIRMWARE_FEATURE_RAID_0_WRITE_BYPASS 7 858 #define PQI_FIRMWARE_FEATURE_RAID_1_WRITE_BYPASS 8 859 #define PQI_FIRMWARE_FEATURE_RAID_5_WRITE_BYPASS 9 860 #define PQI_FIRMWARE_FEATURE_RAID_6_WRITE_BYPASS 10 861 #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE 11 862 #define PQI_FIRMWARE_FEATURE_UNIQUE_SATA_WWN 12 863 #define PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT 13 864 #define PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT 14 865 #define PQI_FIRMWARE_FEATURE_RAID_BYPASS_ON_ENCRYPTED_NVME 15 866 #define PQI_FIRMWARE_FEATURE_UNIQUE_WWID_IN_REPORT_PHYS_LUN 16 867 #define PQI_FIRMWARE_FEATURE_FW_TRIAGE 17 868 #define PQI_FIRMWARE_FEATURE_RPL_EXTENDED_FORMAT_4_5 18 869 #define PQI_FIRMWARE_FEATURE_MULTI_LUN_DEVICE_SUPPORT 21 870 #define PQI_FIRMWARE_FEATURE_MAXIMUM 21 871 872 struct pqi_config_table_debug { 873 struct pqi_config_table_section_header header; 874 __le32 scratchpad; 875 }; 876 877 struct pqi_config_table_heartbeat { 878 struct pqi_config_table_section_header header; 879 __le32 heartbeat_counter; 880 }; 881 882 struct pqi_config_table_soft_reset { 883 struct pqi_config_table_section_header header; 884 u8 soft_reset_status; 885 }; 886 887 #define PQI_SOFT_RESET_INITIATE 0x1 888 #define PQI_SOFT_RESET_ABORT 0x2 889 890 enum pqi_soft_reset_status { 891 RESET_INITIATE_FIRMWARE, 892 RESET_INITIATE_DRIVER, 893 RESET_ABORT, 894 RESET_NORESPONSE, 895 RESET_TIMEDOUT 896 }; 897 898 union pqi_reset_register { 899 struct { 900 u32 reset_type : 3; 901 u32 reserved : 2; 902 u32 reset_action : 3; 903 u32 hold_in_pd1 : 1; 904 u32 reserved2 : 23; 905 } bits; 906 u32 all_bits; 907 }; 908 909 #define PQI_RESET_ACTION_RESET 0x1 910 911 #define PQI_RESET_TYPE_NO_RESET 0x0 912 #define PQI_RESET_TYPE_SOFT_RESET 0x1 913 #define PQI_RESET_TYPE_FIRM_RESET 0x2 914 #define PQI_RESET_TYPE_HARD_RESET 0x3 915 916 #define PQI_RESET_ACTION_COMPLETED 0x2 917 918 #define PQI_RESET_POLL_INTERVAL_MSECS 100 919 920 #define PQI_MAX_OUTSTANDING_REQUESTS ((u32)~0) 921 #define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP 32 922 #define PQI_MAX_TRANSFER_SIZE (1024U * 1024U) 923 #define PQI_MAX_TRANSFER_SIZE_KDUMP (512 * 1024U) 924 925 #define RAID_MAP_MAX_ENTRIES 1024 926 #define RAID_MAP_MAX_DATA_DISKS_PER_ROW 128 927 928 #define PQI_PHYSICAL_DEVICE_BUS 0 929 #define PQI_RAID_VOLUME_BUS 1 930 #define PQI_HBA_BUS 2 931 #define PQI_EXTERNAL_RAID_VOLUME_BUS 3 932 #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS 933 #define PQI_VSEP_CISS_BTL 379 934 935 struct report_lun_header { 936 __be32 list_length; 937 u8 flags; 938 u8 reserved[3]; 939 }; 940 941 /* for flags field of struct report_lun_header */ 942 #define CISS_REPORT_LOG_FLAG_UNIQUE_LUN_ID (1 << 0) 943 #define CISS_REPORT_LOG_FLAG_QUEUE_DEPTH (1 << 5) 944 #define CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX (1 << 6) 945 946 #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_2 0x2 947 #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_4 0x4 948 #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_MASK 0xf 949 950 struct report_log_lun { 951 u8 lunid[8]; 952 u8 volume_id[16]; 953 }; 954 955 struct report_log_lun_list { 956 struct report_lun_header header; 957 struct report_log_lun lun_entries[1]; 958 }; 959 960 struct report_phys_lun_8byte_wwid { 961 u8 lunid[8]; 962 __be64 wwid; 963 u8 device_type; 964 u8 device_flags; 965 u8 lun_count; /* number of LUNs in a multi-LUN device */ 966 u8 redundant_paths; 967 u32 aio_handle; 968 }; 969 970 struct report_phys_lun_16byte_wwid { 971 u8 lunid[8]; 972 u8 wwid[16]; 973 u8 device_type; 974 u8 device_flags; 975 u8 lun_count; /* number of LUNs in a multi-LUN device */ 976 u8 redundant_paths; 977 u32 aio_handle; 978 }; 979 980 /* for device_flags field of struct report_phys_lun_extended_entry */ 981 #define CISS_REPORT_PHYS_DEV_FLAG_AIO_ENABLED 0x8 982 983 struct report_phys_lun_8byte_wwid_list { 984 struct report_lun_header header; 985 struct report_phys_lun_8byte_wwid lun_entries[1]; 986 }; 987 988 struct report_phys_lun_16byte_wwid_list { 989 struct report_lun_header header; 990 struct report_phys_lun_16byte_wwid lun_entries[1]; 991 }; 992 993 struct raid_map_disk_data { 994 u32 aio_handle; 995 u8 xor_mult[2]; 996 u8 reserved[2]; 997 }; 998 999 /* for flags field of RAID map */ 1000 #define RAID_MAP_ENCRYPTION_ENABLED 0x1 1001 1002 struct raid_map { 1003 __le32 structure_size; /* size of entire structure in bytes */ 1004 __le32 volume_blk_size; /* bytes / block in the volume */ 1005 __le64 volume_blk_cnt; /* logical blocks on the volume */ 1006 u8 phys_blk_shift; /* shift factor to convert between */ 1007 /* units of logical blocks and */ 1008 /* physical disk blocks */ 1009 u8 parity_rotation_shift; /* shift factor to convert between */ 1010 /* units of logical stripes and */ 1011 /* physical stripes */ 1012 __le16 strip_size; /* blocks used on each disk / stripe */ 1013 __le64 disk_starting_blk; /* first disk block used in volume */ 1014 __le64 disk_blk_cnt; /* disk blocks used by volume / disk */ 1015 __le16 data_disks_per_row; /* data disk entries / row in the map */ 1016 __le16 metadata_disks_per_row; /* mirror/parity disk entries / row */ 1017 /* in the map */ 1018 __le16 row_cnt; /* rows in each layout map */ 1019 __le16 layout_map_count; /* layout maps (1 map per */ 1020 /* mirror parity group) */ 1021 __le16 flags; 1022 __le16 data_encryption_key_index; 1023 u8 reserved[16]; 1024 struct raid_map_disk_data disk_data[RAID_MAP_MAX_ENTRIES]; 1025 }; 1026 1027 #pragma pack() 1028 1029 struct pqi_scsi_dev_raid_map_data { 1030 bool is_write; 1031 u8 raid_level; 1032 u32 map_index; 1033 u64 first_block; 1034 u64 last_block; 1035 u32 data_length; 1036 u32 block_cnt; 1037 u32 blocks_per_row; 1038 u64 first_row; 1039 u64 last_row; 1040 u32 first_row_offset; 1041 u32 last_row_offset; 1042 u32 first_column; 1043 u32 last_column; 1044 u64 r5or6_first_row; 1045 u64 r5or6_last_row; 1046 u32 r5or6_first_row_offset; 1047 u32 r5or6_last_row_offset; 1048 u32 r5or6_first_column; 1049 u32 r5or6_last_column; 1050 u16 data_disks_per_row; 1051 u32 total_disks_per_row; 1052 u16 layout_map_count; 1053 u32 stripesize; 1054 u16 strip_size; 1055 u32 first_group; 1056 u32 last_group; 1057 u32 map_row; 1058 u32 aio_handle; 1059 u64 disk_block; 1060 u32 disk_block_cnt; 1061 u8 cdb[16]; 1062 u8 cdb_length; 1063 1064 /* RAID 1 specific */ 1065 #define NUM_RAID1_MAP_ENTRIES 3 1066 u32 num_it_nexus_entries; 1067 u32 it_nexus[NUM_RAID1_MAP_ENTRIES]; 1068 1069 /* RAID 5 / RAID 6 specific */ 1070 u32 p_parity_it_nexus; /* aio_handle */ 1071 u32 q_parity_it_nexus; /* aio_handle */ 1072 u8 xor_mult; 1073 u64 row; 1074 u64 stripe_lba; 1075 u32 p_index; 1076 u32 q_index; 1077 }; 1078 1079 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 1080 1081 #define NUM_STREAMS_PER_LUN 8 1082 1083 struct pqi_stream_data { 1084 u64 next_lba; 1085 u32 last_accessed; 1086 }; 1087 1088 #define PQI_MAX_LUNS_PER_DEVICE 256 1089 1090 struct pqi_scsi_dev { 1091 int devtype; /* as reported by INQUIRY command */ 1092 u8 device_type; /* as reported by */ 1093 /* BMIC_IDENTIFY_PHYSICAL_DEVICE */ 1094 /* only valid for devtype = TYPE_DISK */ 1095 int bus; 1096 int target; 1097 int lun; 1098 u8 scsi3addr[8]; 1099 u8 wwid[16]; 1100 u8 volume_id[16]; 1101 u8 is_physical_device : 1; 1102 u8 is_external_raid_device : 1; 1103 u8 is_expander_smp_device : 1; 1104 u8 target_lun_valid : 1; 1105 u8 device_gone : 1; 1106 u8 new_device : 1; 1107 u8 keep_device : 1; 1108 u8 volume_offline : 1; 1109 u8 rescan : 1; 1110 u8 ignore_device : 1; 1111 bool aio_enabled; /* only valid for physical disks */ 1112 bool in_remove; 1113 bool device_offline; 1114 u8 vendor[8]; /* bytes 8-15 of inquiry data */ 1115 u8 model[16]; /* bytes 16-31 of inquiry data */ 1116 u64 sas_address; 1117 u8 raid_level; 1118 u16 queue_depth; /* max. queue_depth for this device */ 1119 u16 advertised_queue_depth; 1120 u32 aio_handle; 1121 u8 volume_status; 1122 u8 active_path_index; 1123 u8 path_map; 1124 u8 bay; 1125 u8 box_index; 1126 u8 phys_box_on_bus; 1127 u8 phy_connected_dev_type; 1128 u8 box[8]; 1129 u16 phys_connector[8]; 1130 u8 phy_id; 1131 u8 ncq_prio_enable; 1132 u8 ncq_prio_support; 1133 u8 multi_lun_device_lun_count; 1134 bool raid_bypass_configured; /* RAID bypass configured */ 1135 bool raid_bypass_enabled; /* RAID bypass enabled */ 1136 u32 next_bypass_group[RAID_MAP_MAX_DATA_DISKS_PER_ROW]; 1137 struct raid_map *raid_map; /* RAID bypass map */ 1138 u32 max_transfer_encrypted; 1139 1140 struct pqi_sas_port *sas_port; 1141 struct scsi_device *sdev; 1142 1143 struct list_head scsi_device_list_entry; 1144 struct list_head new_device_list_entry; 1145 struct list_head add_list_entry; 1146 struct list_head delete_list_entry; 1147 1148 struct pqi_stream_data stream_data[NUM_STREAMS_PER_LUN]; 1149 atomic_t scsi_cmds_outstanding[PQI_MAX_LUNS_PER_DEVICE]; 1150 atomic_t raid_bypass_cnt; 1151 }; 1152 1153 /* VPD inquiry pages */ 1154 #define CISS_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */ 1155 #define CISS_VPD_LV_BYPASS_STATUS 0xc2 /* vendor-specific page */ 1156 #define CISS_VPD_LV_STATUS 0xc3 /* vendor-specific page */ 1157 1158 #define VPD_PAGE (1 << 8) 1159 1160 #pragma pack(1) 1161 1162 /* structure for CISS_VPD_LV_STATUS */ 1163 struct ciss_vpd_logical_volume_status { 1164 u8 peripheral_info; 1165 u8 page_code; 1166 u8 reserved; 1167 u8 page_length; 1168 u8 volume_status; 1169 u8 reserved2[3]; 1170 __be32 flags; 1171 }; 1172 1173 #pragma pack() 1174 1175 /* constants for volume_status field of ciss_vpd_logical_volume_status */ 1176 #define CISS_LV_OK 0 1177 #define CISS_LV_FAILED 1 1178 #define CISS_LV_NOT_CONFIGURED 2 1179 #define CISS_LV_DEGRADED 3 1180 #define CISS_LV_READY_FOR_RECOVERY 4 1181 #define CISS_LV_UNDERGOING_RECOVERY 5 1182 #define CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED 6 1183 #define CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM 7 1184 #define CISS_LV_HARDWARE_OVERHEATING 8 1185 #define CISS_LV_HARDWARE_HAS_OVERHEATED 9 1186 #define CISS_LV_UNDERGOING_EXPANSION 10 1187 #define CISS_LV_NOT_AVAILABLE 11 1188 #define CISS_LV_QUEUED_FOR_EXPANSION 12 1189 #define CISS_LV_DISABLED_SCSI_ID_CONFLICT 13 1190 #define CISS_LV_EJECTED 14 1191 #define CISS_LV_UNDERGOING_ERASE 15 1192 /* state 16 not used */ 1193 #define CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD 17 1194 #define CISS_LV_UNDERGOING_RPI 18 1195 #define CISS_LV_PENDING_RPI 19 1196 #define CISS_LV_ENCRYPTED_NO_KEY 20 1197 /* state 21 not used */ 1198 #define CISS_LV_UNDERGOING_ENCRYPTION 22 1199 #define CISS_LV_UNDERGOING_ENCRYPTION_REKEYING 23 1200 #define CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 24 1201 #define CISS_LV_PENDING_ENCRYPTION 25 1202 #define CISS_LV_PENDING_ENCRYPTION_REKEYING 26 1203 #define CISS_LV_NOT_SUPPORTED 27 1204 #define CISS_LV_STATUS_UNAVAILABLE 255 1205 1206 /* constants for flags field of ciss_vpd_logical_volume_status */ 1207 #define CISS_LV_FLAGS_NO_HOST_IO 0x1 /* volume not available for */ 1208 /* host I/O */ 1209 1210 /* for SAS hosts and SAS expanders */ 1211 struct pqi_sas_node { 1212 struct device *parent_dev; 1213 struct list_head port_list_head; 1214 }; 1215 1216 struct pqi_sas_port { 1217 struct list_head port_list_entry; 1218 u64 sas_address; 1219 struct pqi_scsi_dev *device; 1220 struct sas_port *port; 1221 int next_phy_index; 1222 struct list_head phy_list_head; 1223 struct pqi_sas_node *parent_node; 1224 struct sas_rphy *rphy; 1225 }; 1226 1227 struct pqi_sas_phy { 1228 struct list_head phy_list_entry; 1229 struct sas_phy *phy; 1230 struct pqi_sas_port *parent_port; 1231 bool added_to_port; 1232 }; 1233 1234 struct pqi_io_request { 1235 atomic_t refcount; 1236 u16 index; 1237 void (*io_complete_callback)(struct pqi_io_request *io_request, 1238 void *context); 1239 void *context; 1240 u8 raid_bypass : 1; 1241 int status; 1242 struct pqi_queue_group *queue_group; 1243 struct scsi_cmnd *scmd; 1244 void *error_info; 1245 struct pqi_sg_descriptor *sg_chain_buffer; 1246 dma_addr_t sg_chain_buffer_dma_handle; 1247 void *iu; 1248 struct list_head request_list_entry; 1249 }; 1250 1251 #define PQI_NUM_SUPPORTED_EVENTS 7 1252 1253 struct pqi_event { 1254 bool pending; 1255 u8 event_type; 1256 u16 event_id; 1257 u32 additional_event_id; 1258 }; 1259 1260 #define PQI_RESERVED_IO_SLOTS_LUN_RESET 1 1261 #define PQI_RESERVED_IO_SLOTS_EVENT_ACK PQI_NUM_SUPPORTED_EVENTS 1262 #define PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS 3 1263 #define PQI_RESERVED_IO_SLOTS \ 1264 (PQI_RESERVED_IO_SLOTS_LUN_RESET + PQI_RESERVED_IO_SLOTS_EVENT_ACK + \ 1265 PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS) 1266 1267 #define PQI_CTRL_PRODUCT_ID_GEN1 0 1268 #define PQI_CTRL_PRODUCT_ID_GEN2 7 1269 #define PQI_CTRL_PRODUCT_REVISION_A 0 1270 #define PQI_CTRL_PRODUCT_REVISION_B 1 1271 1272 enum pqi_ctrl_removal_state { 1273 PQI_CTRL_PRESENT = 0, 1274 PQI_CTRL_GRACEFUL_REMOVAL, 1275 PQI_CTRL_SURPRISE_REMOVAL 1276 }; 1277 1278 struct pqi_ctrl_info { 1279 unsigned int ctrl_id; 1280 struct pci_dev *pci_dev; 1281 char firmware_version[32]; 1282 char serial_number[17]; 1283 char model[17]; 1284 char vendor[9]; 1285 u8 product_id; 1286 u8 product_revision; 1287 void __iomem *iomem_base; 1288 struct pqi_ctrl_registers __iomem *registers; 1289 struct pqi_device_registers __iomem *pqi_registers; 1290 u32 max_sg_entries; 1291 u32 config_table_offset; 1292 u32 config_table_length; 1293 u16 max_inbound_queues; 1294 u16 max_elements_per_iq; 1295 u16 max_iq_element_length; 1296 u16 max_outbound_queues; 1297 u16 max_elements_per_oq; 1298 u16 max_oq_element_length; 1299 u32 max_transfer_size; 1300 u32 max_outstanding_requests; 1301 u32 max_io_slots; 1302 unsigned int scsi_ml_can_queue; 1303 unsigned short sg_tablesize; 1304 unsigned int max_sectors; 1305 u32 error_buffer_length; 1306 void *error_buffer; 1307 dma_addr_t error_buffer_dma_handle; 1308 size_t sg_chain_buffer_length; 1309 unsigned int num_queue_groups; 1310 u16 max_hw_queue_index; 1311 u16 num_elements_per_iq; 1312 u16 num_elements_per_oq; 1313 u16 max_inbound_iu_length_per_firmware; 1314 u16 max_inbound_iu_length; 1315 unsigned int max_sg_per_iu; 1316 unsigned int max_sg_per_r56_iu; 1317 void *admin_queue_memory_base; 1318 u32 admin_queue_memory_length; 1319 dma_addr_t admin_queue_memory_base_dma_handle; 1320 void *queue_memory_base; 1321 u32 queue_memory_length; 1322 dma_addr_t queue_memory_base_dma_handle; 1323 struct pqi_admin_queues admin_queues; 1324 struct pqi_queue_group queue_groups[PQI_MAX_QUEUE_GROUPS]; 1325 struct pqi_event_queue event_queue; 1326 enum pqi_irq_mode irq_mode; 1327 int max_msix_vectors; 1328 int num_msix_vectors_enabled; 1329 int num_msix_vectors_initialized; 1330 int event_irq; 1331 struct Scsi_Host *scsi_host; 1332 1333 struct mutex scan_mutex; 1334 struct mutex lun_reset_mutex; 1335 bool controller_online; 1336 bool block_requests; 1337 bool scan_blocked; 1338 u8 logical_volume_rescan_needed : 1; 1339 u8 inbound_spanning_supported : 1; 1340 u8 outbound_spanning_supported : 1; 1341 u8 pqi_mode_enabled : 1; 1342 u8 pqi_reset_quiesce_supported : 1; 1343 u8 soft_reset_handshake_supported : 1; 1344 u8 raid_iu_timeout_supported : 1; 1345 u8 tmf_iu_timeout_supported : 1; 1346 u8 firmware_triage_supported : 1; 1347 u8 rpl_extended_format_4_5_supported : 1; 1348 u8 multi_lun_device_supported : 1; 1349 u8 enable_r1_writes : 1; 1350 u8 enable_r5_writes : 1; 1351 u8 enable_r6_writes : 1; 1352 u8 lv_drive_type_mix_valid : 1; 1353 u8 enable_stream_detection : 1; 1354 u8 disable_managed_interrupts : 1; 1355 u8 ciss_report_log_flags; 1356 u32 max_transfer_encrypted_sas_sata; 1357 u32 max_transfer_encrypted_nvme; 1358 u32 max_write_raid_5_6; 1359 u32 max_write_raid_1_10_2drive; 1360 u32 max_write_raid_1_10_3drive; 1361 1362 struct list_head scsi_device_list; 1363 spinlock_t scsi_device_list_lock; 1364 1365 struct delayed_work rescan_work; 1366 struct delayed_work update_time_work; 1367 1368 struct pqi_sas_node *sas_host; 1369 u64 sas_address; 1370 1371 struct pqi_io_request *io_request_pool; 1372 u16 next_io_request_slot; 1373 1374 struct pqi_event events[PQI_NUM_SUPPORTED_EVENTS]; 1375 struct work_struct event_work; 1376 1377 atomic_t num_interrupts; 1378 int previous_num_interrupts; 1379 u32 previous_heartbeat_count; 1380 __le32 __iomem *heartbeat_counter; 1381 u8 __iomem *soft_reset_status; 1382 struct timer_list heartbeat_timer; 1383 struct work_struct ctrl_offline_work; 1384 1385 struct semaphore sync_request_sem; 1386 atomic_t num_busy_threads; 1387 atomic_t num_blocked_threads; 1388 wait_queue_head_t block_requests_wait; 1389 1390 struct mutex ofa_mutex; 1391 struct pqi_ofa_memory *pqi_ofa_mem_virt_addr; 1392 dma_addr_t pqi_ofa_mem_dma_handle; 1393 void **pqi_ofa_chunk_virt_addr; 1394 struct work_struct ofa_memory_alloc_work; 1395 struct work_struct ofa_quiesce_work; 1396 u32 ofa_bytes_requested; 1397 u16 ofa_cancel_reason; 1398 enum pqi_ctrl_removal_state ctrl_removal_state; 1399 }; 1400 1401 enum pqi_ctrl_mode { 1402 SIS_MODE = 0, 1403 PQI_MODE 1404 }; 1405 1406 /* 1407 * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands 1408 */ 1409 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 1410 1411 /* CISS commands */ 1412 #define CISS_READ 0xc0 1413 #define CISS_REPORT_LOG 0xc2 /* Report Logical LUNs */ 1414 #define CISS_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 1415 #define CISS_GET_RAID_MAP 0xc8 1416 1417 /* BMIC commands */ 1418 #define BMIC_IDENTIFY_CONTROLLER 0x11 1419 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 1420 #define BMIC_READ 0x26 1421 #define BMIC_WRITE 0x27 1422 #define BMIC_SENSE_FEATURE 0x61 1423 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 1424 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 1425 #define BMIC_CSMI_PASSTHRU 0x68 1426 #define BMIC_WRITE_HOST_WELLNESS 0xa5 1427 #define BMIC_FLUSH_CACHE 0xc2 1428 #define BMIC_SET_DIAG_OPTIONS 0xf4 1429 #define BMIC_SENSE_DIAG_OPTIONS 0xf5 1430 1431 #define CSMI_CC_SAS_SMP_PASSTHRU 0x17 1432 1433 #define SA_FLUSH_CACHE 0x1 1434 1435 #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xc0) 1436 #define CISS_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3f) 1437 #define CISS_GET_LEVEL_2_TARGET(lunid) ((lunid)[6]) 1438 #define CISS_GET_DRIVE_NUMBER(lunid) \ 1439 (((CISS_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \ 1440 CISS_GET_LEVEL_2_TARGET((lunid))) 1441 1442 #define LV_GET_DRIVE_TYPE_MIX(lunid) ((lunid)[6]) 1443 1444 #define LV_DRIVE_TYPE_MIX_UNKNOWN 0 1445 #define LV_DRIVE_TYPE_MIX_NO_RESTRICTION 1 1446 #define LV_DRIVE_TYPE_MIX_SAS_HDD_ONLY 2 1447 #define LV_DRIVE_TYPE_MIX_SATA_HDD_ONLY 3 1448 #define LV_DRIVE_TYPE_MIX_SAS_OR_SATA_SSD_ONLY 4 1449 #define LV_DRIVE_TYPE_MIX_SAS_SSD_ONLY 5 1450 #define LV_DRIVE_TYPE_MIX_SATA_SSD_ONLY 6 1451 #define LV_DRIVE_TYPE_MIX_SAS_ONLY 7 1452 #define LV_DRIVE_TYPE_MIX_SATA_ONLY 8 1453 #define LV_DRIVE_TYPE_MIX_NVME_ONLY 9 1454 1455 #define NO_TIMEOUT ((unsigned long) -1) 1456 1457 #pragma pack(1) 1458 1459 struct bmic_identify_controller { 1460 u8 configured_logical_drive_count; 1461 __le32 configuration_signature; 1462 u8 firmware_version_short[4]; 1463 u8 reserved[145]; 1464 __le16 extended_logical_unit_count; 1465 u8 reserved1[34]; 1466 __le16 firmware_build_number; 1467 u8 reserved2[8]; 1468 u8 vendor_id[8]; 1469 u8 product_id[16]; 1470 u8 reserved3[62]; 1471 __le32 extra_controller_flags; 1472 u8 reserved4[2]; 1473 u8 controller_mode; 1474 u8 spare_part_number[32]; 1475 u8 firmware_version_long[32]; 1476 }; 1477 1478 /* constants for extra_controller_flags field of bmic_identify_controller */ 1479 #define BMIC_IDENTIFY_EXTRA_FLAGS_LONG_FW_VERSION_SUPPORTED 0x20000000 1480 1481 struct bmic_sense_subsystem_info { 1482 u8 reserved[44]; 1483 u8 ctrl_serial_number[16]; 1484 }; 1485 1486 /* constants for device_type field */ 1487 #define SA_DEVICE_TYPE_SATA 0x1 1488 #define SA_DEVICE_TYPE_SAS 0x2 1489 #define SA_DEVICE_TYPE_EXPANDER_SMP 0x5 1490 #define SA_DEVICE_TYPE_SES 0x6 1491 #define SA_DEVICE_TYPE_CONTROLLER 0x7 1492 #define SA_DEVICE_TYPE_NVME 0x9 1493 1494 struct bmic_identify_physical_device { 1495 u8 scsi_bus; /* SCSI Bus number on controller */ 1496 u8 scsi_id; /* SCSI ID on this bus */ 1497 __le16 block_size; /* sector size in bytes */ 1498 __le32 total_blocks; /* number for sectors on drive */ 1499 __le32 reserved_blocks; /* controller reserved (RIS) */ 1500 u8 model[40]; /* Physical Drive Model */ 1501 u8 serial_number[40]; /* Drive Serial Number */ 1502 u8 firmware_revision[8]; /* drive firmware revision */ 1503 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ 1504 u8 compaq_drive_stamp; /* 0 means drive not stamped */ 1505 u8 last_failure_reason; 1506 u8 flags; 1507 u8 more_flags; 1508 u8 scsi_lun; /* SCSI LUN for phys drive */ 1509 u8 yet_more_flags; 1510 u8 even_more_flags; 1511 __le32 spi_speed_rules; 1512 u8 phys_connector[2]; /* connector number on controller */ 1513 u8 phys_box_on_bus; /* phys enclosure this drive resides */ 1514 u8 phys_bay_in_box; /* phys drv bay this drive resides */ 1515 __le32 rpm; /* drive rotational speed in RPM */ 1516 u8 device_type; /* type of drive */ 1517 u8 sata_version; /* only valid when device_type = */ 1518 /* SA_DEVICE_TYPE_SATA */ 1519 __le64 big_total_block_count; 1520 __le64 ris_starting_lba; 1521 __le32 ris_size; 1522 u8 wwid[20]; 1523 u8 controller_phy_map[32]; 1524 __le16 phy_count; 1525 u8 phy_connected_dev_type[256]; 1526 u8 phy_to_drive_bay_num[256]; 1527 __le16 phy_to_attached_dev_index[256]; 1528 u8 box_index; 1529 u8 reserved; 1530 __le16 extra_physical_drive_flags; 1531 u8 negotiated_link_rate[256]; 1532 u8 phy_to_phy_map[256]; 1533 u8 redundant_path_present_map; 1534 u8 redundant_path_failure_map; 1535 u8 active_path_number; 1536 __le16 alternate_paths_phys_connector[8]; 1537 u8 alternate_paths_phys_box_on_port[8]; 1538 u8 multi_lun_device_lun_count; 1539 u8 minimum_good_fw_revision[8]; 1540 u8 unique_inquiry_bytes[20]; 1541 u8 current_temperature_degrees; 1542 u8 temperature_threshold_degrees; 1543 u8 max_temperature_degrees; 1544 u8 logical_blocks_per_phys_block_exp; 1545 __le16 current_queue_depth_limit; 1546 u8 switch_name[10]; 1547 __le16 switch_port; 1548 u8 alternate_paths_switch_name[40]; 1549 u8 alternate_paths_switch_port[8]; 1550 __le16 power_on_hours; 1551 __le16 percent_endurance_used; 1552 u8 drive_authentication; 1553 u8 smart_carrier_authentication; 1554 u8 smart_carrier_app_fw_version; 1555 u8 smart_carrier_bootloader_fw_version; 1556 u8 sanitize_flags; 1557 u8 encryption_key_flags; 1558 u8 encryption_key_name[64]; 1559 __le32 misc_drive_flags; 1560 __le16 dek_index; 1561 __le16 hba_drive_encryption_flags; 1562 __le16 max_overwrite_time; 1563 __le16 max_block_erase_time; 1564 __le16 max_crypto_erase_time; 1565 u8 connector_info[5]; 1566 u8 connector_name[8][8]; 1567 u8 page_83_identifier[16]; 1568 u8 maximum_link_rate[256]; 1569 u8 negotiated_physical_link_rate[256]; 1570 u8 box_connector_name[8]; 1571 u8 padding_to_multiple_of_512[9]; 1572 }; 1573 1574 #define BMIC_SENSE_FEATURE_IO_PAGE 0x8 1575 #define BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE 0x2 1576 1577 struct bmic_sense_feature_buffer_header { 1578 u8 page_code; 1579 u8 subpage_code; 1580 __le16 buffer_length; 1581 }; 1582 1583 struct bmic_sense_feature_page_header { 1584 u8 page_code; 1585 u8 subpage_code; 1586 __le16 page_length; 1587 }; 1588 1589 struct bmic_sense_feature_io_page_aio_subpage { 1590 struct bmic_sense_feature_page_header header; 1591 u8 firmware_read_support; 1592 u8 driver_read_support; 1593 u8 firmware_write_support; 1594 u8 driver_write_support; 1595 __le16 max_transfer_encrypted_sas_sata; 1596 __le16 max_transfer_encrypted_nvme; 1597 __le16 max_write_raid_5_6; 1598 __le16 max_write_raid_1_10_2drive; 1599 __le16 max_write_raid_1_10_3drive; 1600 }; 1601 1602 struct bmic_smp_request { 1603 u8 frame_type; 1604 u8 function; 1605 u8 allocated_response_length; 1606 u8 request_length; 1607 u8 additional_request_bytes[1016]; 1608 }; 1609 1610 struct bmic_smp_response { 1611 u8 frame_type; 1612 u8 function; 1613 u8 function_result; 1614 u8 response_length; 1615 u8 additional_response_bytes[1016]; 1616 }; 1617 1618 struct bmic_csmi_ioctl_header { 1619 __le32 header_length; 1620 u8 signature[8]; 1621 __le32 timeout; 1622 __le32 control_code; 1623 __le32 return_code; 1624 __le32 length; 1625 }; 1626 1627 struct bmic_csmi_smp_passthru { 1628 u8 phy_identifier; 1629 u8 port_identifier; 1630 u8 connection_rate; 1631 u8 reserved; 1632 __be64 destination_sas_address; 1633 __le32 request_length; 1634 struct bmic_smp_request request; 1635 u8 connection_status; 1636 u8 reserved1[3]; 1637 __le32 response_length; 1638 struct bmic_smp_response response; 1639 }; 1640 1641 struct bmic_csmi_smp_passthru_buffer { 1642 struct bmic_csmi_ioctl_header ioctl_header; 1643 struct bmic_csmi_smp_passthru parameters; 1644 }; 1645 1646 struct bmic_flush_cache { 1647 u8 disable_flag; 1648 u8 system_power_action; 1649 u8 ndu_flush; 1650 u8 shutdown_event; 1651 u8 reserved[28]; 1652 }; 1653 1654 /* for shutdown_event member of struct bmic_flush_cache */ 1655 enum bmic_flush_cache_shutdown_event { 1656 NONE_CACHE_FLUSH_ONLY = 0, 1657 SHUTDOWN = 1, 1658 HIBERNATE = 2, 1659 SUSPEND = 3, 1660 RESTART = 4 1661 }; 1662 1663 struct bmic_diag_options { 1664 __le32 options; 1665 }; 1666 1667 #pragma pack() 1668 shost_to_hba(struct Scsi_Host * shost)1669 static inline struct pqi_ctrl_info *shost_to_hba(struct Scsi_Host *shost) 1670 { 1671 void *hostdata = shost_priv(shost); 1672 1673 return *((struct pqi_ctrl_info **)hostdata); 1674 } 1675 1676 void pqi_sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost, 1677 struct sas_rphy *rphy); 1678 1679 int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info); 1680 void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info); 1681 int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node, 1682 struct pqi_scsi_dev *device); 1683 void pqi_remove_sas_device(struct pqi_scsi_dev *device); 1684 struct pqi_scsi_dev *pqi_find_device_by_sas_rphy( 1685 struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy); 1686 void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd); 1687 int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info, 1688 struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length, 1689 struct pqi_raid_error_info *error_info); 1690 1691 extern struct sas_function_template pqi_sas_transport_functions; 1692 1693 #endif /* _SMARTPQI_H */ 1694
