1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Hardware driver for DAQ-STC based boards
4  *
5  * COMEDI - Linux Control and Measurement Device Interface
6  * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7  * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8  */
9 
10 /*
11  * This file is meant to be included by another file, e.g.,
12  * ni_atmio.c or ni_pcimio.c.
13  *
14  * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
15  *
16  * References (ftp://ftp.natinst.com/support/manuals):
17  *   340747b.pdf  AT-MIO E series Register Level Programmer Manual
18  *   341079b.pdf  PCI E Series RLPM
19  *   340934b.pdf  DAQ-STC reference manual
20  *
21  * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
22  *   release_ni611x.pdf
23  *   release_ni67xx.pdf
24  *
25  * Other possibly relevant info:
26  *   320517c.pdf  User manual (obsolete)
27  *   320517f.pdf  User manual (new)
28  *   320889a.pdf  delete
29  *   320906c.pdf  maximum signal ratings
30  *   321066a.pdf  about 16x
31  *   321791a.pdf  discontinuation of at-mio-16e-10 rev. c
32  *   321808a.pdf  about at-mio-16e-10 rev P
33  *   321837a.pdf  discontinuation of at-mio-16de-10 rev d
34  *   321838a.pdf  about at-mio-16de-10 rev N
35  *
36  * ISSUES:
37  *   - the interrupt routine needs to be cleaned up
38  *
39  * 2006-02-07: S-Series PCI-6143: Support has been added but is not
40  * fully tested as yet. Terry Barnaby, BEAM Ltd.
41  */
42 
43 #include <linux/interrupt.h>
44 #include <linux/sched.h>
45 #include <linux/delay.h>
46 #include "8255.h"
47 #include "mite.h"
48 
49 /* A timeout count */
50 #define NI_TIMEOUT 1000
51 
52 /* Note: this table must match the ai_gain_* definitions */
53 static const short ni_gainlkup[][16] = {
54 	[ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
55 			0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
56 	[ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
57 	[ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
58 			0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
59 	[ai_gain_4] = {0, 1, 4, 7},
60 	[ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
61 			  0x003, 0x004, 0x005, 0x006},
62 	[ai_gain_622x] = {0, 1, 4, 5},
63 	[ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
64 	[ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
65 };
66 
67 static const struct comedi_lrange range_ni_E_ai = {
68 	16, {
69 		BIP_RANGE(10),
70 		BIP_RANGE(5),
71 		BIP_RANGE(2.5),
72 		BIP_RANGE(1),
73 		BIP_RANGE(0.5),
74 		BIP_RANGE(0.25),
75 		BIP_RANGE(0.1),
76 		BIP_RANGE(0.05),
77 		UNI_RANGE(20),
78 		UNI_RANGE(10),
79 		UNI_RANGE(5),
80 		UNI_RANGE(2),
81 		UNI_RANGE(1),
82 		UNI_RANGE(0.5),
83 		UNI_RANGE(0.2),
84 		UNI_RANGE(0.1)
85 	}
86 };
87 
88 static const struct comedi_lrange range_ni_E_ai_limited = {
89 	8, {
90 		BIP_RANGE(10),
91 		BIP_RANGE(5),
92 		BIP_RANGE(1),
93 		BIP_RANGE(0.1),
94 		UNI_RANGE(10),
95 		UNI_RANGE(5),
96 		UNI_RANGE(1),
97 		UNI_RANGE(0.1)
98 	}
99 };
100 
101 static const struct comedi_lrange range_ni_E_ai_limited14 = {
102 	14, {
103 		BIP_RANGE(10),
104 		BIP_RANGE(5),
105 		BIP_RANGE(2),
106 		BIP_RANGE(1),
107 		BIP_RANGE(0.5),
108 		BIP_RANGE(0.2),
109 		BIP_RANGE(0.1),
110 		UNI_RANGE(10),
111 		UNI_RANGE(5),
112 		UNI_RANGE(2),
113 		UNI_RANGE(1),
114 		UNI_RANGE(0.5),
115 		UNI_RANGE(0.2),
116 		UNI_RANGE(0.1)
117 	}
118 };
119 
120 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
121 	4, {
122 		BIP_RANGE(10),
123 		BIP_RANGE(5),
124 		BIP_RANGE(0.5),
125 		BIP_RANGE(0.05)
126 	}
127 };
128 
129 static const struct comedi_lrange range_ni_E_ai_611x = {
130 	8, {
131 		BIP_RANGE(50),
132 		BIP_RANGE(20),
133 		BIP_RANGE(10),
134 		BIP_RANGE(5),
135 		BIP_RANGE(2),
136 		BIP_RANGE(1),
137 		BIP_RANGE(0.5),
138 		BIP_RANGE(0.2)
139 	}
140 };
141 
142 static const struct comedi_lrange range_ni_M_ai_622x = {
143 	4, {
144 		BIP_RANGE(10),
145 		BIP_RANGE(5),
146 		BIP_RANGE(1),
147 		BIP_RANGE(0.2)
148 	}
149 };
150 
151 static const struct comedi_lrange range_ni_M_ai_628x = {
152 	7, {
153 		BIP_RANGE(10),
154 		BIP_RANGE(5),
155 		BIP_RANGE(2),
156 		BIP_RANGE(1),
157 		BIP_RANGE(0.5),
158 		BIP_RANGE(0.2),
159 		BIP_RANGE(0.1)
160 	}
161 };
162 
163 static const struct comedi_lrange range_ni_E_ao_ext = {
164 	4, {
165 		BIP_RANGE(10),
166 		UNI_RANGE(10),
167 		RANGE_ext(-1, 1),
168 		RANGE_ext(0, 1)
169 	}
170 };
171 
172 static const struct comedi_lrange *const ni_range_lkup[] = {
173 	[ai_gain_16] = &range_ni_E_ai,
174 	[ai_gain_8] = &range_ni_E_ai_limited,
175 	[ai_gain_14] = &range_ni_E_ai_limited14,
176 	[ai_gain_4] = &range_ni_E_ai_bipolar4,
177 	[ai_gain_611x] = &range_ni_E_ai_611x,
178 	[ai_gain_622x] = &range_ni_M_ai_622x,
179 	[ai_gain_628x] = &range_ni_M_ai_628x,
180 	[ai_gain_6143] = &range_bipolar5
181 };
182 
183 enum aimodes {
184 	AIMODE_NONE = 0,
185 	AIMODE_HALF_FULL = 1,
186 	AIMODE_SCAN = 2,
187 	AIMODE_SAMPLE = 3,
188 };
189 
190 enum ni_common_subdevices {
191 	NI_AI_SUBDEV,
192 	NI_AO_SUBDEV,
193 	NI_DIO_SUBDEV,
194 	NI_8255_DIO_SUBDEV,
195 	NI_UNUSED_SUBDEV,
196 	NI_CALIBRATION_SUBDEV,
197 	NI_EEPROM_SUBDEV,
198 	NI_PFI_DIO_SUBDEV,
199 	NI_CS5529_CALIBRATION_SUBDEV,
200 	NI_SERIAL_SUBDEV,
201 	NI_RTSI_SUBDEV,
202 	NI_GPCT0_SUBDEV,
203 	NI_GPCT1_SUBDEV,
204 	NI_FREQ_OUT_SUBDEV,
205 	NI_NUM_SUBDEVICES
206 };
207 
208 #define NI_GPCT_SUBDEV(x)	(NI_GPCT0_SUBDEV + (x))
209 
210 enum timebase_nanoseconds {
211 	TIMEBASE_1_NS = 50,
212 	TIMEBASE_2_NS = 10000
213 };
214 
215 #define SERIAL_DISABLED		0
216 #define SERIAL_600NS		600
217 #define SERIAL_1_2US		1200
218 #define SERIAL_10US			10000
219 
220 static const int num_adc_stages_611x = 3;
221 
ni_writel(struct comedi_device * dev,unsigned int data,int reg)222 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
223 {
224 	if (dev->mmio)
225 		writel(data, dev->mmio + reg);
226 	else
227 		outl(data, dev->iobase + reg);
228 }
229 
ni_writew(struct comedi_device * dev,unsigned int data,int reg)230 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
231 {
232 	if (dev->mmio)
233 		writew(data, dev->mmio + reg);
234 	else
235 		outw(data, dev->iobase + reg);
236 }
237 
ni_writeb(struct comedi_device * dev,unsigned int data,int reg)238 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
239 {
240 	if (dev->mmio)
241 		writeb(data, dev->mmio + reg);
242 	else
243 		outb(data, dev->iobase + reg);
244 }
245 
ni_readl(struct comedi_device * dev,int reg)246 static unsigned int ni_readl(struct comedi_device *dev, int reg)
247 {
248 	if (dev->mmio)
249 		return readl(dev->mmio + reg);
250 
251 	return inl(dev->iobase + reg);
252 }
253 
ni_readw(struct comedi_device * dev,int reg)254 static unsigned int ni_readw(struct comedi_device *dev, int reg)
255 {
256 	if (dev->mmio)
257 		return readw(dev->mmio + reg);
258 
259 	return inw(dev->iobase + reg);
260 }
261 
ni_readb(struct comedi_device * dev,int reg)262 static unsigned int ni_readb(struct comedi_device *dev, int reg)
263 {
264 	if (dev->mmio)
265 		return readb(dev->mmio + reg);
266 
267 	return inb(dev->iobase + reg);
268 }
269 
270 /*
271  * We automatically take advantage of STC registers that can be
272  * read/written directly in the I/O space of the board.
273  *
274  * The AT-MIO and DAQCard devices map the low 8 STC registers to
275  * iobase+reg*2.
276  *
277  * Most PCIMIO devices also map the low 8 STC registers but the
278  * 611x devices map the read registers to iobase+(addr-1)*2.
279  * For now non-windowed STC access is disabled if a PCIMIO device
280  * is detected (devpriv->mite has been initialized).
281  *
282  * The M series devices do not used windowed registers for the
283  * STC registers. The functions below handle the mapping of the
284  * windowed STC registers to the m series register offsets.
285  */
286 
287 struct mio_regmap {
288 	unsigned int mio_reg;
289 	int size;
290 };
291 
292 static const struct mio_regmap m_series_stc_write_regmap[] = {
293 	[NISTC_INTA_ACK_REG]		= { 0x104, 2 },
294 	[NISTC_INTB_ACK_REG]		= { 0x106, 2 },
295 	[NISTC_AI_CMD2_REG]		= { 0x108, 2 },
296 	[NISTC_AO_CMD2_REG]		= { 0x10a, 2 },
297 	[NISTC_G0_CMD_REG]		= { 0x10c, 2 },
298 	[NISTC_G1_CMD_REG]		= { 0x10e, 2 },
299 	[NISTC_AI_CMD1_REG]		= { 0x110, 2 },
300 	[NISTC_AO_CMD1_REG]		= { 0x112, 2 },
301 	/*
302 	 * NISTC_DIO_OUT_REG maps to:
303 	 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
304 	 */
305 	[NISTC_DIO_OUT_REG]		= { 0, 0 }, /* DOES NOT MAP CLEANLY */
306 	[NISTC_DIO_CTRL_REG]		= { 0, 0 }, /* DOES NOT MAP CLEANLY */
307 	[NISTC_AI_MODE1_REG]		= { 0x118, 2 },
308 	[NISTC_AI_MODE2_REG]		= { 0x11a, 2 },
309 	[NISTC_AI_SI_LOADA_REG]		= { 0x11c, 4 },
310 	[NISTC_AI_SI_LOADB_REG]		= { 0x120, 4 },
311 	[NISTC_AI_SC_LOADA_REG]		= { 0x124, 4 },
312 	[NISTC_AI_SC_LOADB_REG]		= { 0x128, 4 },
313 	[NISTC_AI_SI2_LOADA_REG]	= { 0x12c, 4 },
314 	[NISTC_AI_SI2_LOADB_REG]	= { 0x130, 4 },
315 	[NISTC_G0_MODE_REG]		= { 0x134, 2 },
316 	[NISTC_G1_MODE_REG]		= { 0x136, 2 },
317 	[NISTC_G0_LOADA_REG]		= { 0x138, 4 },
318 	[NISTC_G0_LOADB_REG]		= { 0x13c, 4 },
319 	[NISTC_G1_LOADA_REG]		= { 0x140, 4 },
320 	[NISTC_G1_LOADB_REG]		= { 0x144, 4 },
321 	[NISTC_G0_INPUT_SEL_REG]	= { 0x148, 2 },
322 	[NISTC_G1_INPUT_SEL_REG]	= { 0x14a, 2 },
323 	[NISTC_AO_MODE1_REG]		= { 0x14c, 2 },
324 	[NISTC_AO_MODE2_REG]		= { 0x14e, 2 },
325 	[NISTC_AO_UI_LOADA_REG]		= { 0x150, 4 },
326 	[NISTC_AO_UI_LOADB_REG]		= { 0x154, 4 },
327 	[NISTC_AO_BC_LOADA_REG]		= { 0x158, 4 },
328 	[NISTC_AO_BC_LOADB_REG]		= { 0x15c, 4 },
329 	[NISTC_AO_UC_LOADA_REG]		= { 0x160, 4 },
330 	[NISTC_AO_UC_LOADB_REG]		= { 0x164, 4 },
331 	[NISTC_CLK_FOUT_REG]		= { 0x170, 2 },
332 	[NISTC_IO_BIDIR_PIN_REG]	= { 0x172, 2 },
333 	[NISTC_RTSI_TRIG_DIR_REG]	= { 0x174, 2 },
334 	[NISTC_INT_CTRL_REG]		= { 0x176, 2 },
335 	[NISTC_AI_OUT_CTRL_REG]		= { 0x178, 2 },
336 	[NISTC_ATRIG_ETC_REG]		= { 0x17a, 2 },
337 	[NISTC_AI_START_STOP_REG]	= { 0x17c, 2 },
338 	[NISTC_AI_TRIG_SEL_REG]		= { 0x17e, 2 },
339 	[NISTC_AI_DIV_LOADA_REG]	= { 0x180, 4 },
340 	[NISTC_AO_START_SEL_REG]	= { 0x184, 2 },
341 	[NISTC_AO_TRIG_SEL_REG]		= { 0x186, 2 },
342 	[NISTC_G0_AUTOINC_REG]		= { 0x188, 2 },
343 	[NISTC_G1_AUTOINC_REG]		= { 0x18a, 2 },
344 	[NISTC_AO_MODE3_REG]		= { 0x18c, 2 },
345 	[NISTC_RESET_REG]		= { 0x190, 2 },
346 	[NISTC_INTA_ENA_REG]		= { 0x192, 2 },
347 	[NISTC_INTA2_ENA_REG]		= { 0, 0 }, /* E-Series only */
348 	[NISTC_INTB_ENA_REG]		= { 0x196, 2 },
349 	[NISTC_INTB2_ENA_REG]		= { 0, 0 }, /* E-Series only */
350 	[NISTC_AI_PERSONAL_REG]		= { 0x19a, 2 },
351 	[NISTC_AO_PERSONAL_REG]		= { 0x19c, 2 },
352 	[NISTC_RTSI_TRIGA_OUT_REG]	= { 0x19e, 2 },
353 	[NISTC_RTSI_TRIGB_OUT_REG]	= { 0x1a0, 2 },
354 	[NISTC_RTSI_BOARD_REG]		= { 0, 0 }, /* Unknown */
355 	[NISTC_CFG_MEM_CLR_REG]		= { 0x1a4, 2 },
356 	[NISTC_ADC_FIFO_CLR_REG]	= { 0x1a6, 2 },
357 	[NISTC_DAC_FIFO_CLR_REG]	= { 0x1a8, 2 },
358 	[NISTC_AO_OUT_CTRL_REG]		= { 0x1ac, 2 },
359 	[NISTC_AI_MODE3_REG]		= { 0x1ae, 2 },
360 };
361 
m_series_stc_write(struct comedi_device * dev,unsigned int data,unsigned int reg)362 static void m_series_stc_write(struct comedi_device *dev,
363 			       unsigned int data, unsigned int reg)
364 {
365 	const struct mio_regmap *regmap;
366 
367 	if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
368 		regmap = &m_series_stc_write_regmap[reg];
369 	} else {
370 		dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
371 			 __func__, reg);
372 		return;
373 	}
374 
375 	switch (regmap->size) {
376 	case 4:
377 		ni_writel(dev, data, regmap->mio_reg);
378 		break;
379 	case 2:
380 		ni_writew(dev, data, regmap->mio_reg);
381 		break;
382 	default:
383 		dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
384 			 __func__, reg);
385 		break;
386 	}
387 }
388 
389 static const struct mio_regmap m_series_stc_read_regmap[] = {
390 	[NISTC_AI_STATUS1_REG]		= { 0x104, 2 },
391 	[NISTC_AO_STATUS1_REG]		= { 0x106, 2 },
392 	[NISTC_G01_STATUS_REG]		= { 0x108, 2 },
393 	[NISTC_AI_STATUS2_REG]		= { 0, 0 }, /* Unknown */
394 	[NISTC_AO_STATUS2_REG]		= { 0x10c, 2 },
395 	[NISTC_DIO_IN_REG]		= { 0, 0 }, /* Unknown */
396 	[NISTC_G0_HW_SAVE_REG]		= { 0x110, 4 },
397 	[NISTC_G1_HW_SAVE_REG]		= { 0x114, 4 },
398 	[NISTC_G0_SAVE_REG]		= { 0x118, 4 },
399 	[NISTC_G1_SAVE_REG]		= { 0x11c, 4 },
400 	[NISTC_AO_UI_SAVE_REG]		= { 0x120, 4 },
401 	[NISTC_AO_BC_SAVE_REG]		= { 0x124, 4 },
402 	[NISTC_AO_UC_SAVE_REG]		= { 0x128, 4 },
403 	[NISTC_STATUS1_REG]		= { 0x136, 2 },
404 	[NISTC_DIO_SERIAL_IN_REG]	= { 0x009, 1 },
405 	[NISTC_STATUS2_REG]		= { 0x13a, 2 },
406 	[NISTC_AI_SI_SAVE_REG]		= { 0x180, 4 },
407 	[NISTC_AI_SC_SAVE_REG]		= { 0x184, 4 },
408 };
409 
m_series_stc_read(struct comedi_device * dev,unsigned int reg)410 static unsigned int m_series_stc_read(struct comedi_device *dev,
411 				      unsigned int reg)
412 {
413 	const struct mio_regmap *regmap;
414 
415 	if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
416 		regmap = &m_series_stc_read_regmap[reg];
417 	} else {
418 		dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
419 			 __func__, reg);
420 		return 0;
421 	}
422 
423 	switch (regmap->size) {
424 	case 4:
425 		return ni_readl(dev, regmap->mio_reg);
426 	case 2:
427 		return ni_readw(dev, regmap->mio_reg);
428 	case 1:
429 		return ni_readb(dev, regmap->mio_reg);
430 	default:
431 		dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
432 			 __func__, reg);
433 		return 0;
434 	}
435 }
436 
ni_stc_writew(struct comedi_device * dev,unsigned int data,int reg)437 static void ni_stc_writew(struct comedi_device *dev,
438 			  unsigned int data, int reg)
439 {
440 	struct ni_private *devpriv = dev->private;
441 	unsigned long flags;
442 
443 	if (devpriv->is_m_series) {
444 		m_series_stc_write(dev, data, reg);
445 	} else {
446 		spin_lock_irqsave(&devpriv->window_lock, flags);
447 		if (!devpriv->mite && reg < 8) {
448 			ni_writew(dev, data, reg * 2);
449 		} else {
450 			ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
451 			ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
452 		}
453 		spin_unlock_irqrestore(&devpriv->window_lock, flags);
454 	}
455 }
456 
ni_stc_writel(struct comedi_device * dev,unsigned int data,int reg)457 static void ni_stc_writel(struct comedi_device *dev,
458 			  unsigned int data, int reg)
459 {
460 	struct ni_private *devpriv = dev->private;
461 
462 	if (devpriv->is_m_series) {
463 		m_series_stc_write(dev, data, reg);
464 	} else {
465 		ni_stc_writew(dev, data >> 16, reg);
466 		ni_stc_writew(dev, data & 0xffff, reg + 1);
467 	}
468 }
469 
ni_stc_readw(struct comedi_device * dev,int reg)470 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
471 {
472 	struct ni_private *devpriv = dev->private;
473 	unsigned long flags;
474 	unsigned int val;
475 
476 	if (devpriv->is_m_series) {
477 		val = m_series_stc_read(dev, reg);
478 	} else {
479 		spin_lock_irqsave(&devpriv->window_lock, flags);
480 		if (!devpriv->mite && reg < 8) {
481 			val = ni_readw(dev, reg * 2);
482 		} else {
483 			ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
484 			val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
485 		}
486 		spin_unlock_irqrestore(&devpriv->window_lock, flags);
487 	}
488 	return val;
489 }
490 
ni_stc_readl(struct comedi_device * dev,int reg)491 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
492 {
493 	struct ni_private *devpriv = dev->private;
494 	unsigned int val;
495 
496 	if (devpriv->is_m_series) {
497 		val = m_series_stc_read(dev, reg);
498 	} else {
499 		val = ni_stc_readw(dev, reg) << 16;
500 		val |= ni_stc_readw(dev, reg + 1);
501 	}
502 	return val;
503 }
504 
ni_set_bitfield(struct comedi_device * dev,int reg,unsigned int bit_mask,unsigned int bit_values)505 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
506 				   unsigned int bit_mask,
507 				   unsigned int bit_values)
508 {
509 	struct ni_private *devpriv = dev->private;
510 	unsigned long flags;
511 
512 	spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
513 	switch (reg) {
514 	case NISTC_INTA_ENA_REG:
515 		devpriv->int_a_enable_reg &= ~bit_mask;
516 		devpriv->int_a_enable_reg |= bit_values & bit_mask;
517 		ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
518 		break;
519 	case NISTC_INTB_ENA_REG:
520 		devpriv->int_b_enable_reg &= ~bit_mask;
521 		devpriv->int_b_enable_reg |= bit_values & bit_mask;
522 		ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
523 		break;
524 	case NISTC_IO_BIDIR_PIN_REG:
525 		devpriv->io_bidirection_pin_reg &= ~bit_mask;
526 		devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
527 		ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
528 		break;
529 	case NI_E_DMA_AI_AO_SEL_REG:
530 		devpriv->ai_ao_select_reg &= ~bit_mask;
531 		devpriv->ai_ao_select_reg |= bit_values & bit_mask;
532 		ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
533 		break;
534 	case NI_E_DMA_G0_G1_SEL_REG:
535 		devpriv->g0_g1_select_reg &= ~bit_mask;
536 		devpriv->g0_g1_select_reg |= bit_values & bit_mask;
537 		ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
538 		break;
539 	case NI_M_CDIO_DMA_SEL_REG:
540 		devpriv->cdio_dma_select_reg &= ~bit_mask;
541 		devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
542 		ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
543 		break;
544 	default:
545 		dev_err(dev->class_dev, "called with invalid register %d\n",
546 			reg);
547 		break;
548 	}
549 	mmiowb();
550 	spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
551 }
552 
553 #ifdef PCIDMA
554 
555 /* selects the MITE channel to use for DMA */
556 #define NI_STC_DMA_CHAN_SEL(x)	(((x) < 4) ? BIT(x) :	\
557 				 ((x) == 4) ? 0x3 :	\
558 				 ((x) == 5) ? 0x5 : 0x0)
559 
560 /* DMA channel setup */
ni_request_ai_mite_channel(struct comedi_device * dev)561 static int ni_request_ai_mite_channel(struct comedi_device *dev)
562 {
563 	struct ni_private *devpriv = dev->private;
564 	struct mite_channel *mite_chan;
565 	unsigned long flags;
566 	unsigned int bits;
567 
568 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
569 	mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
570 	if (!mite_chan) {
571 		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
572 		dev_err(dev->class_dev,
573 			"failed to reserve mite dma channel for analog input\n");
574 		return -EBUSY;
575 	}
576 	mite_chan->dir = COMEDI_INPUT;
577 	devpriv->ai_mite_chan = mite_chan;
578 
579 	bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
580 	ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
581 			NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
582 
583 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
584 	return 0;
585 }
586 
ni_request_ao_mite_channel(struct comedi_device * dev)587 static int ni_request_ao_mite_channel(struct comedi_device *dev)
588 {
589 	struct ni_private *devpriv = dev->private;
590 	struct mite_channel *mite_chan;
591 	unsigned long flags;
592 	unsigned int bits;
593 
594 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
595 	mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
596 	if (!mite_chan) {
597 		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
598 		dev_err(dev->class_dev,
599 			"failed to reserve mite dma channel for analog outut\n");
600 		return -EBUSY;
601 	}
602 	mite_chan->dir = COMEDI_OUTPUT;
603 	devpriv->ao_mite_chan = mite_chan;
604 
605 	bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
606 	ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
607 			NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
608 
609 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
610 	return 0;
611 }
612 
ni_request_gpct_mite_channel(struct comedi_device * dev,unsigned int gpct_index,enum comedi_io_direction direction)613 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
614 					unsigned int gpct_index,
615 					enum comedi_io_direction direction)
616 {
617 	struct ni_private *devpriv = dev->private;
618 	struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
619 	struct mite_channel *mite_chan;
620 	unsigned long flags;
621 	unsigned int bits;
622 
623 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
624 	mite_chan = mite_request_channel(devpriv->mite,
625 					 devpriv->gpct_mite_ring[gpct_index]);
626 	if (!mite_chan) {
627 		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
628 		dev_err(dev->class_dev,
629 			"failed to reserve mite dma channel for counter\n");
630 		return -EBUSY;
631 	}
632 	mite_chan->dir = direction;
633 	ni_tio_set_mite_channel(counter, mite_chan);
634 
635 	bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
636 	ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
637 			NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
638 			NI_E_DMA_G0_G1_SEL(gpct_index, bits));
639 
640 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
641 	return 0;
642 }
643 
ni_request_cdo_mite_channel(struct comedi_device * dev)644 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
645 {
646 	struct ni_private *devpriv = dev->private;
647 	struct mite_channel *mite_chan;
648 	unsigned long flags;
649 	unsigned int bits;
650 
651 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
652 	mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
653 	if (!mite_chan) {
654 		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
655 		dev_err(dev->class_dev,
656 			"failed to reserve mite dma channel for correlated digital output\n");
657 		return -EBUSY;
658 	}
659 	mite_chan->dir = COMEDI_OUTPUT;
660 	devpriv->cdo_mite_chan = mite_chan;
661 
662 	/*
663 	 * XXX just guessing NI_STC_DMA_CHAN_SEL()
664 	 * returns the right bits, under the assumption the cdio dma
665 	 * selection works just like ai/ao/gpct.
666 	 * Definitely works for dma channels 0 and 1.
667 	 */
668 	bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
669 	ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
670 			NI_M_CDIO_DMA_SEL_CDO_MASK,
671 			NI_M_CDIO_DMA_SEL_CDO(bits));
672 
673 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
674 	return 0;
675 }
676 #endif /*  PCIDMA */
677 
ni_release_ai_mite_channel(struct comedi_device * dev)678 static void ni_release_ai_mite_channel(struct comedi_device *dev)
679 {
680 #ifdef PCIDMA
681 	struct ni_private *devpriv = dev->private;
682 	unsigned long flags;
683 
684 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
685 	if (devpriv->ai_mite_chan) {
686 		ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
687 				NI_E_DMA_AI_SEL_MASK, 0);
688 		mite_release_channel(devpriv->ai_mite_chan);
689 		devpriv->ai_mite_chan = NULL;
690 	}
691 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
692 #endif /*  PCIDMA */
693 }
694 
ni_release_ao_mite_channel(struct comedi_device * dev)695 static void ni_release_ao_mite_channel(struct comedi_device *dev)
696 {
697 #ifdef PCIDMA
698 	struct ni_private *devpriv = dev->private;
699 	unsigned long flags;
700 
701 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
702 	if (devpriv->ao_mite_chan) {
703 		ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
704 				NI_E_DMA_AO_SEL_MASK, 0);
705 		mite_release_channel(devpriv->ao_mite_chan);
706 		devpriv->ao_mite_chan = NULL;
707 	}
708 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
709 #endif /*  PCIDMA */
710 }
711 
712 #ifdef PCIDMA
ni_release_gpct_mite_channel(struct comedi_device * dev,unsigned int gpct_index)713 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
714 					 unsigned int gpct_index)
715 {
716 	struct ni_private *devpriv = dev->private;
717 	unsigned long flags;
718 
719 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
720 	if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
721 		struct mite_channel *mite_chan =
722 		    devpriv->counter_dev->counters[gpct_index].mite_chan;
723 
724 		ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
725 				NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
726 		ni_tio_set_mite_channel(&devpriv->
727 					counter_dev->counters[gpct_index],
728 					NULL);
729 		mite_release_channel(mite_chan);
730 	}
731 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
732 }
733 
ni_release_cdo_mite_channel(struct comedi_device * dev)734 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
735 {
736 	struct ni_private *devpriv = dev->private;
737 	unsigned long flags;
738 
739 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
740 	if (devpriv->cdo_mite_chan) {
741 		ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
742 				NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
743 		mite_release_channel(devpriv->cdo_mite_chan);
744 		devpriv->cdo_mite_chan = NULL;
745 	}
746 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
747 }
748 
ni_e_series_enable_second_irq(struct comedi_device * dev,unsigned int gpct_index,short enable)749 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
750 					  unsigned int gpct_index, short enable)
751 {
752 	struct ni_private *devpriv = dev->private;
753 	unsigned int val = 0;
754 	int reg;
755 
756 	if (devpriv->is_m_series || gpct_index > 1)
757 		return;
758 
759 	/*
760 	 * e-series boards use the second irq signals to generate
761 	 * dma requests for their counters
762 	 */
763 	if (gpct_index == 0) {
764 		reg = NISTC_INTA2_ENA_REG;
765 		if (enable)
766 			val = NISTC_INTA_ENA_G0_GATE;
767 	} else {
768 		reg = NISTC_INTB2_ENA_REG;
769 		if (enable)
770 			val = NISTC_INTB_ENA_G1_GATE;
771 	}
772 	ni_stc_writew(dev, val, reg);
773 }
774 #endif /*  PCIDMA */
775 
ni_clear_ai_fifo(struct comedi_device * dev)776 static void ni_clear_ai_fifo(struct comedi_device *dev)
777 {
778 	struct ni_private *devpriv = dev->private;
779 	static const int timeout = 10000;
780 	int i;
781 
782 	if (devpriv->is_6143) {
783 		/*  Flush the 6143 data FIFO */
784 		ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
785 		ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
786 		/*  Wait for complete */
787 		for (i = 0; i < timeout; i++) {
788 			if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
789 				break;
790 			udelay(1);
791 		}
792 		if (i == timeout)
793 			dev_err(dev->class_dev, "FIFO flush timeout\n");
794 	} else {
795 		ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
796 		if (devpriv->is_625x) {
797 			ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
798 			ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
799 #if 0
800 			/*
801 			 * The NI example code does 3 convert pulses for 625x
802 			 * boards, But that appears to be wrong in practice.
803 			 */
804 			ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
805 				      NISTC_AI_CMD1_REG);
806 			ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
807 				      NISTC_AI_CMD1_REG);
808 			ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
809 				      NISTC_AI_CMD1_REG);
810 #endif
811 		}
812 	}
813 }
814 
ni_ao_win_outw(struct comedi_device * dev,unsigned int data,int addr)815 static inline void ni_ao_win_outw(struct comedi_device *dev,
816 				  unsigned int data, int addr)
817 {
818 	struct ni_private *devpriv = dev->private;
819 	unsigned long flags;
820 
821 	spin_lock_irqsave(&devpriv->window_lock, flags);
822 	ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
823 	ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
824 	spin_unlock_irqrestore(&devpriv->window_lock, flags);
825 }
826 
ni_ao_win_outl(struct comedi_device * dev,unsigned int data,int addr)827 static inline void ni_ao_win_outl(struct comedi_device *dev,
828 				  unsigned int data, int addr)
829 {
830 	struct ni_private *devpriv = dev->private;
831 	unsigned long flags;
832 
833 	spin_lock_irqsave(&devpriv->window_lock, flags);
834 	ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
835 	ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
836 	spin_unlock_irqrestore(&devpriv->window_lock, flags);
837 }
838 
ni_ao_win_inw(struct comedi_device * dev,int addr)839 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
840 {
841 	struct ni_private *devpriv = dev->private;
842 	unsigned long flags;
843 	unsigned short data;
844 
845 	spin_lock_irqsave(&devpriv->window_lock, flags);
846 	ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
847 	data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
848 	spin_unlock_irqrestore(&devpriv->window_lock, flags);
849 	return data;
850 }
851 
852 /*
853  * ni_set_bits( ) allows different parts of the ni_mio_common driver to
854  * share registers (such as Interrupt_A_Register) without interfering with
855  * each other.
856  *
857  * NOTE: the switch/case statements are optimized out for a constant argument
858  * so this is actually quite fast---  If you must wrap another function around
859  * this make it inline to avoid a large speed penalty.
860  *
861  * value should only be 1 or 0.
862  */
ni_set_bits(struct comedi_device * dev,int reg,unsigned int bits,unsigned int value)863 static inline void ni_set_bits(struct comedi_device *dev, int reg,
864 			       unsigned int bits, unsigned int value)
865 {
866 	unsigned int bit_values;
867 
868 	if (value)
869 		bit_values = bits;
870 	else
871 		bit_values = 0;
872 	ni_set_bitfield(dev, reg, bits, bit_values);
873 }
874 
875 #ifdef PCIDMA
ni_sync_ai_dma(struct comedi_device * dev)876 static void ni_sync_ai_dma(struct comedi_device *dev)
877 {
878 	struct ni_private *devpriv = dev->private;
879 	struct comedi_subdevice *s = dev->read_subdev;
880 	unsigned long flags;
881 
882 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
883 	if (devpriv->ai_mite_chan)
884 		mite_sync_dma(devpriv->ai_mite_chan, s);
885 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
886 }
887 
ni_ai_drain_dma(struct comedi_device * dev)888 static int ni_ai_drain_dma(struct comedi_device *dev)
889 {
890 	struct ni_private *devpriv = dev->private;
891 	int i;
892 	static const int timeout = 10000;
893 	unsigned long flags;
894 	int retval = 0;
895 
896 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
897 	if (devpriv->ai_mite_chan) {
898 		for (i = 0; i < timeout; i++) {
899 			if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
900 			     NISTC_AI_STATUS1_FIFO_E) &&
901 			    mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
902 				break;
903 			udelay(5);
904 		}
905 		if (i == timeout) {
906 			dev_err(dev->class_dev, "timed out\n");
907 			dev_err(dev->class_dev,
908 				"mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
909 				mite_bytes_in_transit(devpriv->ai_mite_chan),
910 				ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
911 			retval = -1;
912 		}
913 	}
914 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
915 
916 	ni_sync_ai_dma(dev);
917 
918 	return retval;
919 }
920 
ni_ao_wait_for_dma_load(struct comedi_device * dev)921 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
922 {
923 	static const int timeout = 10000;
924 	int i;
925 
926 	for (i = 0; i < timeout; i++) {
927 		unsigned short b_status;
928 
929 		b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
930 		if (b_status & NISTC_AO_STATUS1_FIFO_HF)
931 			break;
932 		/*
933 		 * If we poll too often, the pci bus activity seems
934 		 * to slow the dma transfer down.
935 		 */
936 		usleep_range(10, 100);
937 	}
938 	if (i == timeout) {
939 		dev_err(dev->class_dev, "timed out waiting for dma load\n");
940 		return -EPIPE;
941 	}
942 	return 0;
943 }
944 #endif /* PCIDMA */
945 
946 #ifndef PCIDMA
947 
ni_ao_fifo_load(struct comedi_device * dev,struct comedi_subdevice * s,int n)948 static void ni_ao_fifo_load(struct comedi_device *dev,
949 			    struct comedi_subdevice *s, int n)
950 {
951 	struct ni_private *devpriv = dev->private;
952 	int i;
953 	unsigned short d;
954 	unsigned int packed_data;
955 
956 	for (i = 0; i < n; i++) {
957 		comedi_buf_read_samples(s, &d, 1);
958 
959 		if (devpriv->is_6xxx) {
960 			packed_data = d & 0xffff;
961 			/* 6711 only has 16 bit wide ao fifo */
962 			if (!devpriv->is_6711) {
963 				comedi_buf_read_samples(s, &d, 1);
964 				i++;
965 				packed_data |= (d << 16) & 0xffff0000;
966 			}
967 			ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
968 		} else {
969 			ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
970 		}
971 	}
972 }
973 
974 /*
975  *  There's a small problem if the FIFO gets really low and we
976  *  don't have the data to fill it.  Basically, if after we fill
977  *  the FIFO with all the data available, the FIFO is _still_
978  *  less than half full, we never clear the interrupt.  If the
979  *  IRQ is in edge mode, we never get another interrupt, because
980  *  this one wasn't cleared.  If in level mode, we get flooded
981  *  with interrupts that we can't fulfill, because nothing ever
982  *  gets put into the buffer.
983  *
984  *  This kind of situation is recoverable, but it is easier to
985  *  just pretend we had a FIFO underrun, since there is a good
986  *  chance it will happen anyway.  This is _not_ the case for
987  *  RT code, as RT code might purposely be running close to the
988  *  metal.  Needs to be fixed eventually.
989  */
ni_ao_fifo_half_empty(struct comedi_device * dev,struct comedi_subdevice * s)990 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
991 				 struct comedi_subdevice *s)
992 {
993 	const struct ni_board_struct *board = dev->board_ptr;
994 	unsigned int nbytes;
995 	unsigned int nsamples;
996 
997 	nbytes = comedi_buf_read_n_available(s);
998 	if (nbytes == 0) {
999 		s->async->events |= COMEDI_CB_OVERFLOW;
1000 		return 0;
1001 	}
1002 
1003 	nsamples = comedi_bytes_to_samples(s, nbytes);
1004 	if (nsamples > board->ao_fifo_depth / 2)
1005 		nsamples = board->ao_fifo_depth / 2;
1006 
1007 	ni_ao_fifo_load(dev, s, nsamples);
1008 
1009 	return 1;
1010 }
1011 
ni_ao_prep_fifo(struct comedi_device * dev,struct comedi_subdevice * s)1012 static int ni_ao_prep_fifo(struct comedi_device *dev,
1013 			   struct comedi_subdevice *s)
1014 {
1015 	const struct ni_board_struct *board = dev->board_ptr;
1016 	struct ni_private *devpriv = dev->private;
1017 	unsigned int nbytes;
1018 	unsigned int nsamples;
1019 
1020 	/* reset fifo */
1021 	ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1022 	if (devpriv->is_6xxx)
1023 		ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1024 
1025 	/* load some data */
1026 	nbytes = comedi_buf_read_n_available(s);
1027 	if (nbytes == 0)
1028 		return 0;
1029 
1030 	nsamples = comedi_bytes_to_samples(s, nbytes);
1031 	if (nsamples > board->ao_fifo_depth)
1032 		nsamples = board->ao_fifo_depth;
1033 
1034 	ni_ao_fifo_load(dev, s, nsamples);
1035 
1036 	return nsamples;
1037 }
1038 
ni_ai_fifo_read(struct comedi_device * dev,struct comedi_subdevice * s,int n)1039 static void ni_ai_fifo_read(struct comedi_device *dev,
1040 			    struct comedi_subdevice *s, int n)
1041 {
1042 	struct ni_private *devpriv = dev->private;
1043 	struct comedi_async *async = s->async;
1044 	unsigned int dl;
1045 	unsigned short data;
1046 	int i;
1047 
1048 	if (devpriv->is_611x) {
1049 		for (i = 0; i < n / 2; i++) {
1050 			dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1051 			/* This may get the hi/lo data in the wrong order */
1052 			data = (dl >> 16) & 0xffff;
1053 			comedi_buf_write_samples(s, &data, 1);
1054 			data = dl & 0xffff;
1055 			comedi_buf_write_samples(s, &data, 1);
1056 		}
1057 		/* Check if there's a single sample stuck in the FIFO */
1058 		if (n % 2) {
1059 			dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1060 			data = dl & 0xffff;
1061 			comedi_buf_write_samples(s, &data, 1);
1062 		}
1063 	} else if (devpriv->is_6143) {
1064 		/*
1065 		 * This just reads the FIFO assuming the data is present,
1066 		 * no checks on the FIFO status are performed.
1067 		 */
1068 		for (i = 0; i < n / 2; i++) {
1069 			dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1070 
1071 			data = (dl >> 16) & 0xffff;
1072 			comedi_buf_write_samples(s, &data, 1);
1073 			data = dl & 0xffff;
1074 			comedi_buf_write_samples(s, &data, 1);
1075 		}
1076 		if (n % 2) {
1077 			/* Assume there is a single sample stuck in the FIFO */
1078 			/* Get stranded sample into FIFO */
1079 			ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1080 			dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1081 			data = (dl >> 16) & 0xffff;
1082 			comedi_buf_write_samples(s, &data, 1);
1083 		}
1084 	} else {
1085 		if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1086 			dev_err(dev->class_dev,
1087 				"bug! ai_fifo_buffer too small\n");
1088 			async->events |= COMEDI_CB_ERROR;
1089 			return;
1090 		}
1091 		for (i = 0; i < n; i++) {
1092 			devpriv->ai_fifo_buffer[i] =
1093 			    ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1094 		}
1095 		comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1096 	}
1097 }
1098 
ni_handle_fifo_half_full(struct comedi_device * dev)1099 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1100 {
1101 	const struct ni_board_struct *board = dev->board_ptr;
1102 	struct comedi_subdevice *s = dev->read_subdev;
1103 	int n;
1104 
1105 	n = board->ai_fifo_depth / 2;
1106 
1107 	ni_ai_fifo_read(dev, s, n);
1108 }
1109 #endif
1110 
1111 /* Empties the AI fifo */
ni_handle_fifo_dregs(struct comedi_device * dev)1112 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1113 {
1114 	struct ni_private *devpriv = dev->private;
1115 	struct comedi_subdevice *s = dev->read_subdev;
1116 	unsigned int dl;
1117 	unsigned short data;
1118 	int i;
1119 
1120 	if (devpriv->is_611x) {
1121 		while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1122 			NISTC_AI_STATUS1_FIFO_E) == 0) {
1123 			dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1124 
1125 			/* This may get the hi/lo data in the wrong order */
1126 			data = dl >> 16;
1127 			comedi_buf_write_samples(s, &data, 1);
1128 			data = dl & 0xffff;
1129 			comedi_buf_write_samples(s, &data, 1);
1130 		}
1131 	} else if (devpriv->is_6143) {
1132 		i = 0;
1133 		while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1134 			dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1135 
1136 			/* This may get the hi/lo data in the wrong order */
1137 			data = dl >> 16;
1138 			comedi_buf_write_samples(s, &data, 1);
1139 			data = dl & 0xffff;
1140 			comedi_buf_write_samples(s, &data, 1);
1141 			i += 2;
1142 		}
1143 		/*  Check if stranded sample is present */
1144 		if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1145 			/* Get stranded sample into FIFO */
1146 			ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1147 			dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1148 			data = (dl >> 16) & 0xffff;
1149 			comedi_buf_write_samples(s, &data, 1);
1150 		}
1151 
1152 	} else {
1153 		unsigned short fe;	/* fifo empty */
1154 
1155 		fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1156 		     NISTC_AI_STATUS1_FIFO_E;
1157 		while (fe == 0) {
1158 			for (i = 0;
1159 			     i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1160 				fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1161 				     NISTC_AI_STATUS1_FIFO_E;
1162 				if (fe)
1163 					break;
1164 				devpriv->ai_fifo_buffer[i] =
1165 				    ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1166 			}
1167 			comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1168 		}
1169 	}
1170 }
1171 
get_last_sample_611x(struct comedi_device * dev)1172 static void get_last_sample_611x(struct comedi_device *dev)
1173 {
1174 	struct ni_private *devpriv = dev->private;
1175 	struct comedi_subdevice *s = dev->read_subdev;
1176 	unsigned short data;
1177 	unsigned int dl;
1178 
1179 	if (!devpriv->is_611x)
1180 		return;
1181 
1182 	/* Check if there's a single sample stuck in the FIFO */
1183 	if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1184 		dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1185 		data = dl & 0xffff;
1186 		comedi_buf_write_samples(s, &data, 1);
1187 	}
1188 }
1189 
get_last_sample_6143(struct comedi_device * dev)1190 static void get_last_sample_6143(struct comedi_device *dev)
1191 {
1192 	struct ni_private *devpriv = dev->private;
1193 	struct comedi_subdevice *s = dev->read_subdev;
1194 	unsigned short data;
1195 	unsigned int dl;
1196 
1197 	if (!devpriv->is_6143)
1198 		return;
1199 
1200 	/* Check if there's a single sample stuck in the FIFO */
1201 	if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1202 		/* Get stranded sample into FIFO */
1203 		ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1204 		dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1205 
1206 		/* This may get the hi/lo data in the wrong order */
1207 		data = (dl >> 16) & 0xffff;
1208 		comedi_buf_write_samples(s, &data, 1);
1209 	}
1210 }
1211 
shutdown_ai_command(struct comedi_device * dev)1212 static void shutdown_ai_command(struct comedi_device *dev)
1213 {
1214 	struct comedi_subdevice *s = dev->read_subdev;
1215 
1216 #ifdef PCIDMA
1217 	ni_ai_drain_dma(dev);
1218 #endif
1219 	ni_handle_fifo_dregs(dev);
1220 	get_last_sample_611x(dev);
1221 	get_last_sample_6143(dev);
1222 
1223 	s->async->events |= COMEDI_CB_EOA;
1224 }
1225 
ni_handle_eos(struct comedi_device * dev,struct comedi_subdevice * s)1226 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1227 {
1228 	struct ni_private *devpriv = dev->private;
1229 
1230 	if (devpriv->aimode == AIMODE_SCAN) {
1231 #ifdef PCIDMA
1232 		static const int timeout = 10;
1233 		int i;
1234 
1235 		for (i = 0; i < timeout; i++) {
1236 			ni_sync_ai_dma(dev);
1237 			if ((s->async->events & COMEDI_CB_EOS))
1238 				break;
1239 			udelay(1);
1240 		}
1241 #else
1242 		ni_handle_fifo_dregs(dev);
1243 		s->async->events |= COMEDI_CB_EOS;
1244 #endif
1245 	}
1246 	/* handle special case of single scan */
1247 	if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1248 		shutdown_ai_command(dev);
1249 }
1250 
handle_gpct_interrupt(struct comedi_device * dev,unsigned short counter_index)1251 static void handle_gpct_interrupt(struct comedi_device *dev,
1252 				  unsigned short counter_index)
1253 {
1254 #ifdef PCIDMA
1255 	struct ni_private *devpriv = dev->private;
1256 	struct comedi_subdevice *s;
1257 
1258 	s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1259 
1260 	ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1261 				s);
1262 	comedi_handle_events(dev, s);
1263 #endif
1264 }
1265 
ack_a_interrupt(struct comedi_device * dev,unsigned short a_status)1266 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1267 {
1268 	unsigned short ack = 0;
1269 
1270 	if (a_status & NISTC_AI_STATUS1_SC_TC)
1271 		ack |= NISTC_INTA_ACK_AI_SC_TC;
1272 	if (a_status & NISTC_AI_STATUS1_START1)
1273 		ack |= NISTC_INTA_ACK_AI_START1;
1274 	if (a_status & NISTC_AI_STATUS1_START)
1275 		ack |= NISTC_INTA_ACK_AI_START;
1276 	if (a_status & NISTC_AI_STATUS1_STOP)
1277 		ack |= NISTC_INTA_ACK_AI_STOP;
1278 	if (a_status & NISTC_AI_STATUS1_OVER)
1279 		ack |= NISTC_INTA_ACK_AI_ERR;
1280 	if (ack)
1281 		ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1282 }
1283 
handle_a_interrupt(struct comedi_device * dev,struct comedi_subdevice * s,unsigned short status)1284 static void handle_a_interrupt(struct comedi_device *dev,
1285 			       struct comedi_subdevice *s,
1286 			       unsigned short status)
1287 {
1288 	struct comedi_cmd *cmd = &s->async->cmd;
1289 
1290 	/* test for all uncommon interrupt events at the same time */
1291 	if (status & (NISTC_AI_STATUS1_ERR |
1292 		      NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1293 		if (status == 0xffff) {
1294 			dev_err(dev->class_dev, "Card removed?\n");
1295 			/*
1296 			 * We probably aren't even running a command now,
1297 			 * so it's a good idea to be careful.
1298 			 */
1299 			if (comedi_is_subdevice_running(s))
1300 				s->async->events |= COMEDI_CB_ERROR;
1301 			return;
1302 		}
1303 		if (status & NISTC_AI_STATUS1_ERR) {
1304 			dev_err(dev->class_dev, "ai error a_status=%04x\n",
1305 				status);
1306 
1307 			shutdown_ai_command(dev);
1308 
1309 			s->async->events |= COMEDI_CB_ERROR;
1310 			if (status & NISTC_AI_STATUS1_OVER)
1311 				s->async->events |= COMEDI_CB_OVERFLOW;
1312 			return;
1313 		}
1314 		if (status & NISTC_AI_STATUS1_SC_TC) {
1315 			if (cmd->stop_src == TRIG_COUNT)
1316 				shutdown_ai_command(dev);
1317 		}
1318 	}
1319 #ifndef PCIDMA
1320 	if (status & NISTC_AI_STATUS1_FIFO_HF) {
1321 		int i;
1322 		static const int timeout = 10;
1323 		/*
1324 		 * PCMCIA cards (at least 6036) seem to stop producing
1325 		 * interrupts if we fail to get the fifo less than half
1326 		 * full, so loop to be sure.
1327 		 */
1328 		for (i = 0; i < timeout; ++i) {
1329 			ni_handle_fifo_half_full(dev);
1330 			if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1331 			     NISTC_AI_STATUS1_FIFO_HF) == 0)
1332 				break;
1333 		}
1334 	}
1335 #endif /*  !PCIDMA */
1336 
1337 	if (status & NISTC_AI_STATUS1_STOP)
1338 		ni_handle_eos(dev, s);
1339 }
1340 
ack_b_interrupt(struct comedi_device * dev,unsigned short b_status)1341 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1342 {
1343 	unsigned short ack = 0;
1344 
1345 	if (b_status & NISTC_AO_STATUS1_BC_TC)
1346 		ack |= NISTC_INTB_ACK_AO_BC_TC;
1347 	if (b_status & NISTC_AO_STATUS1_OVERRUN)
1348 		ack |= NISTC_INTB_ACK_AO_ERR;
1349 	if (b_status & NISTC_AO_STATUS1_START)
1350 		ack |= NISTC_INTB_ACK_AO_START;
1351 	if (b_status & NISTC_AO_STATUS1_START1)
1352 		ack |= NISTC_INTB_ACK_AO_START1;
1353 	if (b_status & NISTC_AO_STATUS1_UC_TC)
1354 		ack |= NISTC_INTB_ACK_AO_UC_TC;
1355 	if (b_status & NISTC_AO_STATUS1_UI2_TC)
1356 		ack |= NISTC_INTB_ACK_AO_UI2_TC;
1357 	if (b_status & NISTC_AO_STATUS1_UPDATE)
1358 		ack |= NISTC_INTB_ACK_AO_UPDATE;
1359 	if (ack)
1360 		ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1361 }
1362 
handle_b_interrupt(struct comedi_device * dev,struct comedi_subdevice * s,unsigned short b_status)1363 static void handle_b_interrupt(struct comedi_device *dev,
1364 			       struct comedi_subdevice *s,
1365 			       unsigned short b_status)
1366 {
1367 	if (b_status == 0xffff)
1368 		return;
1369 	if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1370 		dev_err(dev->class_dev,
1371 			"AO FIFO underrun status=0x%04x status2=0x%04x\n",
1372 			b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1373 		s->async->events |= COMEDI_CB_OVERFLOW;
1374 	}
1375 
1376 	if (s->async->cmd.stop_src != TRIG_NONE &&
1377 	    b_status & NISTC_AO_STATUS1_BC_TC)
1378 		s->async->events |= COMEDI_CB_EOA;
1379 
1380 #ifndef PCIDMA
1381 	if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1382 		int ret;
1383 
1384 		ret = ni_ao_fifo_half_empty(dev, s);
1385 		if (!ret) {
1386 			dev_err(dev->class_dev, "AO buffer underrun\n");
1387 			ni_set_bits(dev, NISTC_INTB_ENA_REG,
1388 				    NISTC_INTB_ENA_AO_FIFO |
1389 				    NISTC_INTB_ENA_AO_ERR, 0);
1390 			s->async->events |= COMEDI_CB_OVERFLOW;
1391 		}
1392 	}
1393 #endif
1394 }
1395 
ni_ai_munge(struct comedi_device * dev,struct comedi_subdevice * s,void * data,unsigned int num_bytes,unsigned int chan_index)1396 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1397 			void *data, unsigned int num_bytes,
1398 			unsigned int chan_index)
1399 {
1400 	struct ni_private *devpriv = dev->private;
1401 	struct comedi_async *async = s->async;
1402 	struct comedi_cmd *cmd = &async->cmd;
1403 	unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1404 	unsigned short *array = data;
1405 	unsigned int *larray = data;
1406 	unsigned int i;
1407 #ifdef PCIDMA
1408 	__le16 *barray = data;
1409 	__le32 *blarray = data;
1410 #endif
1411 
1412 	for (i = 0; i < nsamples; i++) {
1413 #ifdef PCIDMA
1414 		if (s->subdev_flags & SDF_LSAMPL)
1415 			larray[i] = le32_to_cpu(blarray[i]);
1416 		else
1417 			array[i] = le16_to_cpu(barray[i]);
1418 #endif
1419 		if (s->subdev_flags & SDF_LSAMPL)
1420 			larray[i] += devpriv->ai_offset[chan_index];
1421 		else
1422 			array[i] += devpriv->ai_offset[chan_index];
1423 		chan_index++;
1424 		chan_index %= cmd->chanlist_len;
1425 	}
1426 }
1427 
1428 #ifdef PCIDMA
1429 
ni_ai_setup_MITE_dma(struct comedi_device * dev)1430 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1431 {
1432 	struct ni_private *devpriv = dev->private;
1433 	struct comedi_subdevice *s = dev->read_subdev;
1434 	int retval;
1435 	unsigned long flags;
1436 
1437 	retval = ni_request_ai_mite_channel(dev);
1438 	if (retval)
1439 		return retval;
1440 
1441 	/* write alloc the entire buffer */
1442 	comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1443 
1444 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1445 	if (!devpriv->ai_mite_chan) {
1446 		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1447 		return -EIO;
1448 	}
1449 
1450 	if (devpriv->is_611x || devpriv->is_6143)
1451 		mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1452 	else if (devpriv->is_628x)
1453 		mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1454 	else
1455 		mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1456 
1457 	/*start the MITE */
1458 	mite_dma_arm(devpriv->ai_mite_chan);
1459 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1460 
1461 	return 0;
1462 }
1463 
ni_ao_setup_MITE_dma(struct comedi_device * dev)1464 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1465 {
1466 	struct ni_private *devpriv = dev->private;
1467 	struct comedi_subdevice *s = dev->write_subdev;
1468 	int retval;
1469 	unsigned long flags;
1470 
1471 	retval = ni_request_ao_mite_channel(dev);
1472 	if (retval)
1473 		return retval;
1474 
1475 	/* read alloc the entire buffer */
1476 	comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1477 
1478 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1479 	if (devpriv->ao_mite_chan) {
1480 		if (devpriv->is_611x || devpriv->is_6713) {
1481 			mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1482 		} else {
1483 			/*
1484 			 * Doing 32 instead of 16 bit wide transfers from
1485 			 * memory makes the mite do 32 bit pci transfers,
1486 			 * doubling pci bandwidth.
1487 			 */
1488 			mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1489 		}
1490 		mite_dma_arm(devpriv->ao_mite_chan);
1491 	} else {
1492 		retval = -EIO;
1493 	}
1494 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1495 
1496 	return retval;
1497 }
1498 
1499 #endif /*  PCIDMA */
1500 
1501 /*
1502  * used for both cancel ioctl and board initialization
1503  *
1504  * this is pretty harsh for a cancel, but it works...
1505  */
ni_ai_reset(struct comedi_device * dev,struct comedi_subdevice * s)1506 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1507 {
1508 	struct ni_private *devpriv = dev->private;
1509 	unsigned int ai_personal;
1510 	unsigned int ai_out_ctrl;
1511 
1512 	ni_release_ai_mite_channel(dev);
1513 	/* ai configuration */
1514 	ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1515 		      NISTC_RESET_REG);
1516 
1517 	ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1518 
1519 	ni_clear_ai_fifo(dev);
1520 
1521 	if (!devpriv->is_6143)
1522 		ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1523 
1524 	ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1525 	ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1526 			   NISTC_AI_MODE1_RSVD
1527 			    /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1528 		      NISTC_AI_MODE1_REG);
1529 	ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1530 	/* generate FIFO interrupts on non-empty */
1531 	ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1532 		      NISTC_AI_MODE3_REG);
1533 
1534 	ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1535 		      NISTC_AI_PERSONAL_SOC_POLARITY |
1536 		      NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1537 	ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1538 		      NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1539 		      NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1540 		      NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1541 	if (devpriv->is_611x) {
1542 		ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1543 	} else if (devpriv->is_6143) {
1544 		ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1545 	} else {
1546 		ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1547 		if (devpriv->is_622x)
1548 			ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1549 		else
1550 			ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1551 	}
1552 	ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1553 	ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1554 
1555 	/* the following registers should not be changed, because there
1556 	 * are no backup registers in devpriv.  If you want to change
1557 	 * any of these, add a backup register and other appropriate code:
1558 	 *      NISTC_AI_MODE1_REG
1559 	 *      NISTC_AI_MODE3_REG
1560 	 *      NISTC_AI_PERSONAL_REG
1561 	 *      NISTC_AI_OUT_CTRL_REG
1562 	 */
1563 
1564 	/* clear interrupts */
1565 	ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1566 
1567 	ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1568 
1569 	return 0;
1570 }
1571 
ni_ai_poll(struct comedi_device * dev,struct comedi_subdevice * s)1572 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1573 {
1574 	unsigned long flags;
1575 	int count;
1576 
1577 	/*  lock to avoid race with interrupt handler */
1578 	spin_lock_irqsave(&dev->spinlock, flags);
1579 #ifndef PCIDMA
1580 	ni_handle_fifo_dregs(dev);
1581 #else
1582 	ni_sync_ai_dma(dev);
1583 #endif
1584 	count = comedi_buf_n_bytes_ready(s);
1585 	spin_unlock_irqrestore(&dev->spinlock, flags);
1586 
1587 	return count;
1588 }
1589 
ni_prime_channelgain_list(struct comedi_device * dev)1590 static void ni_prime_channelgain_list(struct comedi_device *dev)
1591 {
1592 	int i;
1593 
1594 	ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1595 	for (i = 0; i < NI_TIMEOUT; ++i) {
1596 		if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1597 		      NISTC_AI_STATUS1_FIFO_E)) {
1598 			ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1599 			return;
1600 		}
1601 		udelay(1);
1602 	}
1603 	dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1604 }
1605 
ni_m_series_load_channelgain_list(struct comedi_device * dev,unsigned int n_chan,unsigned int * list)1606 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1607 					      unsigned int n_chan,
1608 					      unsigned int *list)
1609 {
1610 	const struct ni_board_struct *board = dev->board_ptr;
1611 	struct ni_private *devpriv = dev->private;
1612 	unsigned int chan, range, aref;
1613 	unsigned int i;
1614 	unsigned int dither;
1615 	unsigned int range_code;
1616 
1617 	ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1618 
1619 	if ((list[0] & CR_ALT_SOURCE)) {
1620 		unsigned int bypass_bits;
1621 
1622 		chan = CR_CHAN(list[0]);
1623 		range = CR_RANGE(list[0]);
1624 		range_code = ni_gainlkup[board->gainlkup][range];
1625 		dither = (list[0] & CR_ALT_FILTER) != 0;
1626 		bypass_bits = NI_M_CFG_BYPASS_FIFO |
1627 			      NI_M_CFG_BYPASS_AI_CHAN(chan) |
1628 			      NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1629 			      devpriv->ai_calib_source;
1630 		if (dither)
1631 			bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1632 		/*  don't use 2's complement encoding */
1633 		bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1634 		ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1635 	} else {
1636 		ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1637 	}
1638 	for (i = 0; i < n_chan; i++) {
1639 		unsigned int config_bits = 0;
1640 
1641 		chan = CR_CHAN(list[i]);
1642 		aref = CR_AREF(list[i]);
1643 		range = CR_RANGE(list[i]);
1644 		dither = (list[i] & CR_ALT_FILTER) != 0;
1645 
1646 		range_code = ni_gainlkup[board->gainlkup][range];
1647 		devpriv->ai_offset[i] = 0;
1648 		switch (aref) {
1649 		case AREF_DIFF:
1650 			config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1651 			break;
1652 		case AREF_COMMON:
1653 			config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1654 			break;
1655 		case AREF_GROUND:
1656 			config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1657 			break;
1658 		case AREF_OTHER:
1659 			break;
1660 		}
1661 		config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1662 		config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1663 		config_bits |= NI_M_AI_CFG_GAIN(range_code);
1664 		if (i == n_chan - 1)
1665 			config_bits |= NI_M_AI_CFG_LAST_CHAN;
1666 		if (dither)
1667 			config_bits |= NI_M_AI_CFG_DITHER;
1668 		/*  don't use 2's complement encoding */
1669 		config_bits |= NI_M_AI_CFG_POLARITY;
1670 		ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1671 	}
1672 	ni_prime_channelgain_list(dev);
1673 }
1674 
1675 /*
1676  * Notes on the 6110 and 6111:
1677  * These boards a slightly different than the rest of the series, since
1678  * they have multiple A/D converters.
1679  * From the driver side, the configuration memory is a
1680  * little different.
1681  * Configuration Memory Low:
1682  *   bits 15-9: same
1683  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1684  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1685  *       1001 gain=0.1 (+/- 50)
1686  *       1010 0.2
1687  *       1011 0.1
1688  *       0001 1
1689  *       0010 2
1690  *       0011 5
1691  *       0100 10
1692  *       0101 20
1693  *       0110 50
1694  * Configuration Memory High:
1695  *   bits 12-14: Channel Type
1696  *       001 for differential
1697  *       000 for calibration
1698  *   bit 11: coupling  (this is not currently handled)
1699  *       1 AC coupling
1700  *       0 DC coupling
1701  *   bits 0-2: channel
1702  *       valid channels are 0-3
1703  */
ni_load_channelgain_list(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int n_chan,unsigned int * list)1704 static void ni_load_channelgain_list(struct comedi_device *dev,
1705 				     struct comedi_subdevice *s,
1706 				     unsigned int n_chan, unsigned int *list)
1707 {
1708 	const struct ni_board_struct *board = dev->board_ptr;
1709 	struct ni_private *devpriv = dev->private;
1710 	unsigned int offset = (s->maxdata + 1) >> 1;
1711 	unsigned int chan, range, aref;
1712 	unsigned int i;
1713 	unsigned int hi, lo;
1714 	unsigned int dither;
1715 
1716 	if (devpriv->is_m_series) {
1717 		ni_m_series_load_channelgain_list(dev, n_chan, list);
1718 		return;
1719 	}
1720 	if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1721 		if (devpriv->changain_state &&
1722 		    devpriv->changain_spec == list[0]) {
1723 			/*  ready to go. */
1724 			return;
1725 		}
1726 		devpriv->changain_state = 1;
1727 		devpriv->changain_spec = list[0];
1728 	} else {
1729 		devpriv->changain_state = 0;
1730 	}
1731 
1732 	ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1733 
1734 	/*  Set up Calibration mode if required */
1735 	if (devpriv->is_6143) {
1736 		if ((list[0] & CR_ALT_SOURCE) &&
1737 		    !devpriv->ai_calib_source_enabled) {
1738 			/*  Strobe Relay enable bit */
1739 			ni_writew(dev, devpriv->ai_calib_source |
1740 				       NI6143_CALIB_CHAN_RELAY_ON,
1741 				  NI6143_CALIB_CHAN_REG);
1742 			ni_writew(dev, devpriv->ai_calib_source,
1743 				  NI6143_CALIB_CHAN_REG);
1744 			devpriv->ai_calib_source_enabled = 1;
1745 			/* Allow relays to change */
1746 			msleep_interruptible(100);
1747 		} else if (!(list[0] & CR_ALT_SOURCE) &&
1748 			   devpriv->ai_calib_source_enabled) {
1749 			/*  Strobe Relay disable bit */
1750 			ni_writew(dev, devpriv->ai_calib_source |
1751 				       NI6143_CALIB_CHAN_RELAY_OFF,
1752 				  NI6143_CALIB_CHAN_REG);
1753 			ni_writew(dev, devpriv->ai_calib_source,
1754 				  NI6143_CALIB_CHAN_REG);
1755 			devpriv->ai_calib_source_enabled = 0;
1756 			/* Allow relays to change */
1757 			msleep_interruptible(100);
1758 		}
1759 	}
1760 
1761 	for (i = 0; i < n_chan; i++) {
1762 		if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1763 			chan = devpriv->ai_calib_source;
1764 		else
1765 			chan = CR_CHAN(list[i]);
1766 		aref = CR_AREF(list[i]);
1767 		range = CR_RANGE(list[i]);
1768 		dither = (list[i] & CR_ALT_FILTER) != 0;
1769 
1770 		/* fix the external/internal range differences */
1771 		range = ni_gainlkup[board->gainlkup][range];
1772 		if (devpriv->is_611x)
1773 			devpriv->ai_offset[i] = offset;
1774 		else
1775 			devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1776 
1777 		hi = 0;
1778 		if ((list[i] & CR_ALT_SOURCE)) {
1779 			if (devpriv->is_611x)
1780 				ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1781 					  NI611X_CALIB_CHAN_SEL_REG);
1782 		} else {
1783 			if (devpriv->is_611x)
1784 				aref = AREF_DIFF;
1785 			else if (devpriv->is_6143)
1786 				aref = AREF_OTHER;
1787 			switch (aref) {
1788 			case AREF_DIFF:
1789 				hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1790 				break;
1791 			case AREF_COMMON:
1792 				hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1793 				break;
1794 			case AREF_GROUND:
1795 				hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1796 				break;
1797 			case AREF_OTHER:
1798 				break;
1799 			}
1800 		}
1801 		hi |= NI_E_AI_CFG_HI_CHAN(chan);
1802 
1803 		ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1804 
1805 		if (!devpriv->is_6143) {
1806 			lo = NI_E_AI_CFG_LO_GAIN(range);
1807 
1808 			if (i == n_chan - 1)
1809 				lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1810 			if (dither)
1811 				lo |= NI_E_AI_CFG_LO_DITHER;
1812 
1813 			ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1814 		}
1815 	}
1816 
1817 	/* prime the channel/gain list */
1818 	if (!devpriv->is_611x && !devpriv->is_6143)
1819 		ni_prime_channelgain_list(dev);
1820 }
1821 
ni_ai_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)1822 static int ni_ai_insn_read(struct comedi_device *dev,
1823 			   struct comedi_subdevice *s,
1824 			   struct comedi_insn *insn,
1825 			   unsigned int *data)
1826 {
1827 	struct ni_private *devpriv = dev->private;
1828 	unsigned int mask = s->maxdata;
1829 	int i, n;
1830 	unsigned int signbits;
1831 	unsigned int d;
1832 
1833 	ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1834 
1835 	ni_clear_ai_fifo(dev);
1836 
1837 	signbits = devpriv->ai_offset[0];
1838 	if (devpriv->is_611x) {
1839 		for (n = 0; n < num_adc_stages_611x; n++) {
1840 			ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1841 				      NISTC_AI_CMD1_REG);
1842 			udelay(1);
1843 		}
1844 		for (n = 0; n < insn->n; n++) {
1845 			ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1846 				      NISTC_AI_CMD1_REG);
1847 			/* The 611x has screwy 32-bit FIFOs. */
1848 			d = 0;
1849 			for (i = 0; i < NI_TIMEOUT; i++) {
1850 				if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1851 					d = ni_readl(dev,
1852 						     NI611X_AI_FIFO_DATA_REG);
1853 					d >>= 16;
1854 					d &= 0xffff;
1855 					break;
1856 				}
1857 				if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1858 				      NISTC_AI_STATUS1_FIFO_E)) {
1859 					d = ni_readl(dev,
1860 						     NI611X_AI_FIFO_DATA_REG);
1861 					d &= 0xffff;
1862 					break;
1863 				}
1864 			}
1865 			if (i == NI_TIMEOUT) {
1866 				dev_err(dev->class_dev, "timeout\n");
1867 				return -ETIME;
1868 			}
1869 			d += signbits;
1870 			data[n] = d & 0xffff;
1871 		}
1872 	} else if (devpriv->is_6143) {
1873 		for (n = 0; n < insn->n; n++) {
1874 			ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1875 				      NISTC_AI_CMD1_REG);
1876 
1877 			/*
1878 			 * The 6143 has 32-bit FIFOs. You need to strobe a
1879 			 * bit to move a single 16bit stranded sample into
1880 			 * the FIFO.
1881 			 */
1882 			d = 0;
1883 			for (i = 0; i < NI_TIMEOUT; i++) {
1884 				if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1885 				    0x01) {
1886 					/* Get stranded sample into FIFO */
1887 					ni_writel(dev, 0x01,
1888 						  NI6143_AI_FIFO_CTRL_REG);
1889 					d = ni_readl(dev,
1890 						     NI6143_AI_FIFO_DATA_REG);
1891 					break;
1892 				}
1893 			}
1894 			if (i == NI_TIMEOUT) {
1895 				dev_err(dev->class_dev, "timeout\n");
1896 				return -ETIME;
1897 			}
1898 			data[n] = (((d >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1899 		}
1900 	} else {
1901 		for (n = 0; n < insn->n; n++) {
1902 			ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1903 				      NISTC_AI_CMD1_REG);
1904 			for (i = 0; i < NI_TIMEOUT; i++) {
1905 				if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1906 				      NISTC_AI_STATUS1_FIFO_E))
1907 					break;
1908 			}
1909 			if (i == NI_TIMEOUT) {
1910 				dev_err(dev->class_dev, "timeout\n");
1911 				return -ETIME;
1912 			}
1913 			if (devpriv->is_m_series) {
1914 				d = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1915 				d &= mask;
1916 				data[n] = d;
1917 			} else {
1918 				d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1919 				d += signbits;
1920 				data[n] = d & 0xffff;
1921 			}
1922 		}
1923 	}
1924 	return insn->n;
1925 }
1926 
ni_ns_to_timer(const struct comedi_device * dev,unsigned int nanosec,unsigned int flags)1927 static int ni_ns_to_timer(const struct comedi_device *dev,
1928 			  unsigned int nanosec, unsigned int flags)
1929 {
1930 	struct ni_private *devpriv = dev->private;
1931 	int divider;
1932 
1933 	switch (flags & CMDF_ROUND_MASK) {
1934 	case CMDF_ROUND_NEAREST:
1935 	default:
1936 		divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1937 		break;
1938 	case CMDF_ROUND_DOWN:
1939 		divider = (nanosec) / devpriv->clock_ns;
1940 		break;
1941 	case CMDF_ROUND_UP:
1942 		divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1943 		break;
1944 	}
1945 	return divider - 1;
1946 }
1947 
ni_timer_to_ns(const struct comedi_device * dev,int timer)1948 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1949 {
1950 	struct ni_private *devpriv = dev->private;
1951 
1952 	return devpriv->clock_ns * (timer + 1);
1953 }
1954 
ni_cmd_set_mite_transfer(struct mite_ring * ring,struct comedi_subdevice * sdev,const struct comedi_cmd * cmd,unsigned int max_count)1955 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1956 				     struct comedi_subdevice *sdev,
1957 				     const struct comedi_cmd *cmd,
1958 				     unsigned int max_count)
1959 {
1960 #ifdef PCIDMA
1961 	unsigned int nbytes = max_count;
1962 
1963 	if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1964 		nbytes = cmd->stop_arg;
1965 	nbytes *= comedi_bytes_per_scan(sdev);
1966 
1967 	if (nbytes > sdev->async->prealloc_bufsz) {
1968 		if (cmd->stop_arg > 0)
1969 			dev_err(sdev->device->class_dev,
1970 				"%s: tried exact data transfer limits greater than buffer size\n",
1971 				__func__);
1972 
1973 		/*
1974 		 * we can only transfer up to the size of the buffer.  In this
1975 		 * case, the user is expected to continue to write into the
1976 		 * comedi buffer (already implemented as a ring buffer).
1977 		 */
1978 		nbytes = sdev->async->prealloc_bufsz;
1979 	}
1980 
1981 	mite_init_ring_descriptors(ring, sdev, nbytes);
1982 #else
1983 	dev_err(sdev->device->class_dev,
1984 		"%s: exact data transfer limits not implemented yet without DMA\n",
1985 		__func__);
1986 #endif
1987 }
1988 
ni_min_ai_scan_period_ns(struct comedi_device * dev,unsigned int num_channels)1989 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
1990 					     unsigned int num_channels)
1991 {
1992 	const struct ni_board_struct *board = dev->board_ptr;
1993 	struct ni_private *devpriv = dev->private;
1994 
1995 	/* simultaneously-sampled inputs */
1996 	if (devpriv->is_611x || devpriv->is_6143)
1997 		return board->ai_speed;
1998 
1999 	/* multiplexed inputs */
2000 	return board->ai_speed * num_channels;
2001 }
2002 
ni_ai_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)2003 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2004 			 struct comedi_cmd *cmd)
2005 {
2006 	const struct ni_board_struct *board = dev->board_ptr;
2007 	struct ni_private *devpriv = dev->private;
2008 	int err = 0;
2009 	unsigned int tmp;
2010 	unsigned int sources;
2011 
2012 	/* Step 1 : check if triggers are trivially valid */
2013 
2014 	err |= comedi_check_trigger_src(&cmd->start_src,
2015 					TRIG_NOW | TRIG_INT | TRIG_EXT);
2016 	err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2017 					TRIG_TIMER | TRIG_EXT);
2018 
2019 	sources = TRIG_TIMER | TRIG_EXT;
2020 	if (devpriv->is_611x || devpriv->is_6143)
2021 		sources |= TRIG_NOW;
2022 	err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2023 
2024 	err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2025 	err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2026 
2027 	if (err)
2028 		return 1;
2029 
2030 	/* Step 2a : make sure trigger sources are unique */
2031 
2032 	err |= comedi_check_trigger_is_unique(cmd->start_src);
2033 	err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2034 	err |= comedi_check_trigger_is_unique(cmd->convert_src);
2035 	err |= comedi_check_trigger_is_unique(cmd->stop_src);
2036 
2037 	/* Step 2b : and mutually compatible */
2038 
2039 	if (err)
2040 		return 2;
2041 
2042 	/* Step 3: check if arguments are trivially valid */
2043 
2044 	switch (cmd->start_src) {
2045 	case TRIG_NOW:
2046 	case TRIG_INT:
2047 		err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2048 		break;
2049 	case TRIG_EXT:
2050 		tmp = CR_CHAN(cmd->start_arg);
2051 
2052 		if (tmp > 16)
2053 			tmp = 16;
2054 		tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2055 		err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2056 		break;
2057 	}
2058 
2059 	if (cmd->scan_begin_src == TRIG_TIMER) {
2060 		err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2061 			ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2062 		err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2063 						    devpriv->clock_ns *
2064 						    0xffffff);
2065 	} else if (cmd->scan_begin_src == TRIG_EXT) {
2066 		/* external trigger */
2067 		unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2068 
2069 		if (tmp > 16)
2070 			tmp = 16;
2071 		tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2072 		err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2073 	} else {		/* TRIG_OTHER */
2074 		err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2075 	}
2076 
2077 	if (cmd->convert_src == TRIG_TIMER) {
2078 		if (devpriv->is_611x || devpriv->is_6143) {
2079 			err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2080 							   0);
2081 		} else {
2082 			err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2083 							    board->ai_speed);
2084 			err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2085 							    devpriv->clock_ns *
2086 							    0xffff);
2087 		}
2088 	} else if (cmd->convert_src == TRIG_EXT) {
2089 		/* external trigger */
2090 		unsigned int tmp = CR_CHAN(cmd->convert_arg);
2091 
2092 		if (tmp > 16)
2093 			tmp = 16;
2094 		tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2095 		err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2096 	} else if (cmd->convert_src == TRIG_NOW) {
2097 		err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2098 	}
2099 
2100 	err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2101 					   cmd->chanlist_len);
2102 
2103 	if (cmd->stop_src == TRIG_COUNT) {
2104 		unsigned int max_count = 0x01000000;
2105 
2106 		if (devpriv->is_611x)
2107 			max_count -= num_adc_stages_611x;
2108 		err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2109 		err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2110 	} else {
2111 		/* TRIG_NONE */
2112 		err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2113 	}
2114 
2115 	if (err)
2116 		return 3;
2117 
2118 	/* step 4: fix up any arguments */
2119 
2120 	if (cmd->scan_begin_src == TRIG_TIMER) {
2121 		tmp = cmd->scan_begin_arg;
2122 		cmd->scan_begin_arg =
2123 		    ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2124 						       cmd->scan_begin_arg,
2125 						       cmd->flags));
2126 		if (tmp != cmd->scan_begin_arg)
2127 			err++;
2128 	}
2129 	if (cmd->convert_src == TRIG_TIMER) {
2130 		if (!devpriv->is_611x && !devpriv->is_6143) {
2131 			tmp = cmd->convert_arg;
2132 			cmd->convert_arg =
2133 			    ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2134 							       cmd->convert_arg,
2135 							       cmd->flags));
2136 			if (tmp != cmd->convert_arg)
2137 				err++;
2138 			if (cmd->scan_begin_src == TRIG_TIMER &&
2139 			    cmd->scan_begin_arg <
2140 			    cmd->convert_arg * cmd->scan_end_arg) {
2141 				cmd->scan_begin_arg =
2142 				    cmd->convert_arg * cmd->scan_end_arg;
2143 				err++;
2144 			}
2145 		}
2146 	}
2147 
2148 	if (err)
2149 		return 4;
2150 
2151 	return 0;
2152 }
2153 
ni_ai_inttrig(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int trig_num)2154 static int ni_ai_inttrig(struct comedi_device *dev,
2155 			 struct comedi_subdevice *s,
2156 			 unsigned int trig_num)
2157 {
2158 	struct ni_private *devpriv = dev->private;
2159 	struct comedi_cmd *cmd = &s->async->cmd;
2160 
2161 	if (trig_num != cmd->start_arg)
2162 		return -EINVAL;
2163 
2164 	ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2165 		      NISTC_AI_CMD2_REG);
2166 	s->async->inttrig = NULL;
2167 
2168 	return 1;
2169 }
2170 
ni_ai_cmd(struct comedi_device * dev,struct comedi_subdevice * s)2171 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2172 {
2173 	struct ni_private *devpriv = dev->private;
2174 	const struct comedi_cmd *cmd = &s->async->cmd;
2175 	int timer;
2176 	int mode1 = 0;		/* mode1 is needed for both stop and convert */
2177 	int mode2 = 0;
2178 	int start_stop_select = 0;
2179 	unsigned int stop_count;
2180 	int interrupt_a_enable = 0;
2181 	unsigned int ai_trig;
2182 
2183 	if (dev->irq == 0) {
2184 		dev_err(dev->class_dev, "cannot run command without an irq\n");
2185 		return -EIO;
2186 	}
2187 	ni_clear_ai_fifo(dev);
2188 
2189 	ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2190 
2191 	/* start configuration */
2192 	ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2193 
2194 	/*
2195 	 * Disable analog triggering for now, since it interferes
2196 	 * with the use of pfi0.
2197 	 */
2198 	devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2199 	ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2200 
2201 	ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2202 	switch (cmd->start_src) {
2203 	case TRIG_INT:
2204 	case TRIG_NOW:
2205 		ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2206 			   NISTC_AI_TRIG_START1_SEL(0);
2207 		break;
2208 	case TRIG_EXT:
2209 		ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2210 						    1);
2211 
2212 		if (cmd->start_arg & CR_INVERT)
2213 			ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2214 		if (cmd->start_arg & CR_EDGE)
2215 			ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2216 		break;
2217 	}
2218 	ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2219 
2220 	mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2221 	mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2222 	mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2223 	ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2224 
2225 	if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2226 		/* logic low */
2227 		start_stop_select |= NISTC_AI_STOP_POLARITY |
2228 				     NISTC_AI_STOP_SEL(31) |
2229 				     NISTC_AI_STOP_SYNC;
2230 	} else {
2231 		/*  ai configuration memory */
2232 		start_stop_select |= NISTC_AI_STOP_SEL(19);
2233 	}
2234 	ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2235 
2236 	devpriv->ai_cmd2 = 0;
2237 	switch (cmd->stop_src) {
2238 	case TRIG_COUNT:
2239 		stop_count = cmd->stop_arg - 1;
2240 
2241 		if (devpriv->is_611x) {
2242 			/*  have to take 3 stage adc pipeline into account */
2243 			stop_count += num_adc_stages_611x;
2244 		}
2245 		/* stage number of scans */
2246 		ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2247 
2248 		mode1 |= NISTC_AI_MODE1_START_STOP |
2249 			 NISTC_AI_MODE1_RSVD |
2250 			 NISTC_AI_MODE1_TRIGGER_ONCE;
2251 		ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2252 		/* load SC (Scan Count) */
2253 		ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2254 
2255 		if (stop_count == 0) {
2256 			devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2257 			interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2258 			/*
2259 			 * This is required to get the last sample for
2260 			 * chanlist_len > 1, not sure why.
2261 			 */
2262 			if (cmd->chanlist_len > 1)
2263 				start_stop_select |= NISTC_AI_STOP_POLARITY |
2264 						     NISTC_AI_STOP_EDGE;
2265 		}
2266 		break;
2267 	case TRIG_NONE:
2268 		/* stage number of scans */
2269 		ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2270 
2271 		mode1 |= NISTC_AI_MODE1_START_STOP |
2272 			 NISTC_AI_MODE1_RSVD |
2273 			 NISTC_AI_MODE1_CONTINUOUS;
2274 		ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2275 
2276 		/* load SC (Scan Count) */
2277 		ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2278 		break;
2279 	}
2280 
2281 	switch (cmd->scan_begin_src) {
2282 	case TRIG_TIMER:
2283 		/*
2284 		 * stop bits for non 611x boards
2285 		 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2286 		 * NISTC_AI_MODE2_PRE_TRIGGER=0
2287 		 * NISTC_AI_START_STOP_REG:
2288 		 * NISTC_AI_START_POLARITY=0	(?) rising edge
2289 		 * NISTC_AI_START_EDGE=1	edge triggered
2290 		 * NISTC_AI_START_SYNC=1	(?)
2291 		 * NISTC_AI_START_SEL=0		SI_TC
2292 		 * NISTC_AI_STOP_POLARITY=0	rising edge
2293 		 * NISTC_AI_STOP_EDGE=0		level
2294 		 * NISTC_AI_STOP_SYNC=1
2295 		 * NISTC_AI_STOP_SEL=19		external pin (configuration mem)
2296 		 */
2297 		start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2298 		ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2299 
2300 		mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;	/* A */
2301 		mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2302 		/* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2303 		ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2304 
2305 		/* load SI */
2306 		timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2307 				       CMDF_ROUND_NEAREST);
2308 		ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2309 		ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2310 		break;
2311 	case TRIG_EXT:
2312 		if (cmd->scan_begin_arg & CR_EDGE)
2313 			start_stop_select |= NISTC_AI_START_EDGE;
2314 		if (cmd->scan_begin_arg & CR_INVERT)	/* falling edge */
2315 			start_stop_select |= NISTC_AI_START_POLARITY;
2316 		if (cmd->scan_begin_src != cmd->convert_src ||
2317 		    (cmd->scan_begin_arg & ~CR_EDGE) !=
2318 		    (cmd->convert_arg & ~CR_EDGE))
2319 			start_stop_select |= NISTC_AI_START_SYNC;
2320 		start_stop_select |=
2321 		    NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2322 		ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2323 		break;
2324 	}
2325 
2326 	switch (cmd->convert_src) {
2327 	case TRIG_TIMER:
2328 	case TRIG_NOW:
2329 		if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2330 			timer = 1;
2331 		else
2332 			timer = ni_ns_to_timer(dev, cmd->convert_arg,
2333 					       CMDF_ROUND_NEAREST);
2334 		/* 0,0 does not work */
2335 		ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2336 		ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2337 
2338 		mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;	/* A */
2339 		mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;	/* alternate */
2340 		ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2341 
2342 		ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2343 
2344 		mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;	/* B */
2345 		mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;	/* alternate */
2346 		ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2347 		break;
2348 	case TRIG_EXT:
2349 		mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 +
2350 						    CR_CHAN(cmd->convert_arg));
2351 		if ((cmd->convert_arg & CR_INVERT) == 0)
2352 			mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2353 		ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2354 
2355 		mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2356 			 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2357 		ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2358 
2359 		break;
2360 	}
2361 
2362 	if (dev->irq) {
2363 		/* interrupt on FIFO, errors, SC_TC */
2364 		interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2365 				      NISTC_INTA_ENA_AI_SC_TC;
2366 
2367 #ifndef PCIDMA
2368 		interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2369 #endif
2370 
2371 		if ((cmd->flags & CMDF_WAKE_EOS) ||
2372 		    (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2373 			/* wake on end-of-scan */
2374 			devpriv->aimode = AIMODE_SCAN;
2375 		} else {
2376 			devpriv->aimode = AIMODE_HALF_FULL;
2377 		}
2378 
2379 		switch (devpriv->aimode) {
2380 		case AIMODE_HALF_FULL:
2381 			/* FIFO interrupts and DMA requests on half-full */
2382 #ifdef PCIDMA
2383 			ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2384 				      NISTC_AI_MODE3_REG);
2385 #else
2386 			ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2387 				      NISTC_AI_MODE3_REG);
2388 #endif
2389 			break;
2390 		case AIMODE_SAMPLE:
2391 			/*generate FIFO interrupts on non-empty */
2392 			ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2393 				      NISTC_AI_MODE3_REG);
2394 			break;
2395 		case AIMODE_SCAN:
2396 #ifdef PCIDMA
2397 			ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2398 				      NISTC_AI_MODE3_REG);
2399 #else
2400 			ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2401 				      NISTC_AI_MODE3_REG);
2402 #endif
2403 			interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2404 			break;
2405 		default:
2406 			break;
2407 		}
2408 
2409 		/* clear interrupts */
2410 		ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2411 
2412 		ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2413 	} else {
2414 		/* interrupt on nothing */
2415 		ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2416 
2417 		/* XXX start polling if necessary */
2418 	}
2419 
2420 	/* end configuration */
2421 	ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2422 
2423 	switch (cmd->scan_begin_src) {
2424 	case TRIG_TIMER:
2425 		ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2426 				   NISTC_AI_CMD1_SI_ARM |
2427 				   NISTC_AI_CMD1_DIV_ARM |
2428 				   NISTC_AI_CMD1_SC_ARM,
2429 			      NISTC_AI_CMD1_REG);
2430 		break;
2431 	case TRIG_EXT:
2432 		ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2433 				   NISTC_AI_CMD1_SI_ARM |	/* XXX ? */
2434 				   NISTC_AI_CMD1_DIV_ARM |
2435 				   NISTC_AI_CMD1_SC_ARM,
2436 			      NISTC_AI_CMD1_REG);
2437 		break;
2438 	}
2439 
2440 #ifdef PCIDMA
2441 	{
2442 		int retval = ni_ai_setup_MITE_dma(dev);
2443 
2444 		if (retval)
2445 			return retval;
2446 	}
2447 #endif
2448 
2449 	if (cmd->start_src == TRIG_NOW) {
2450 		ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2451 				   devpriv->ai_cmd2,
2452 			      NISTC_AI_CMD2_REG);
2453 		s->async->inttrig = NULL;
2454 	} else if (cmd->start_src == TRIG_EXT) {
2455 		s->async->inttrig = NULL;
2456 	} else {	/* TRIG_INT */
2457 		s->async->inttrig = ni_ai_inttrig;
2458 	}
2459 
2460 	return 0;
2461 }
2462 
ni_ai_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)2463 static int ni_ai_insn_config(struct comedi_device *dev,
2464 			     struct comedi_subdevice *s,
2465 			     struct comedi_insn *insn, unsigned int *data)
2466 {
2467 	struct ni_private *devpriv = dev->private;
2468 
2469 	if (insn->n < 1)
2470 		return -EINVAL;
2471 
2472 	switch (data[0]) {
2473 	case INSN_CONFIG_ALT_SOURCE:
2474 		if (devpriv->is_m_series) {
2475 			if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2476 				return -EINVAL;
2477 			devpriv->ai_calib_source = data[1];
2478 		} else if (devpriv->is_6143) {
2479 			unsigned int calib_source;
2480 
2481 			calib_source = data[1] & 0xf;
2482 
2483 			devpriv->ai_calib_source = calib_source;
2484 			ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2485 		} else {
2486 			unsigned int calib_source;
2487 			unsigned int calib_source_adjust;
2488 
2489 			calib_source = data[1] & 0xf;
2490 			calib_source_adjust = (data[1] >> 4) & 0xff;
2491 
2492 			if (calib_source >= 8)
2493 				return -EINVAL;
2494 			devpriv->ai_calib_source = calib_source;
2495 			if (devpriv->is_611x) {
2496 				ni_writeb(dev, calib_source_adjust,
2497 					  NI611X_CAL_GAIN_SEL_REG);
2498 			}
2499 		}
2500 		return 2;
2501 	default:
2502 		break;
2503 	}
2504 
2505 	return -EINVAL;
2506 }
2507 
ni_ao_munge(struct comedi_device * dev,struct comedi_subdevice * s,void * data,unsigned int num_bytes,unsigned int chan_index)2508 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2509 			void *data, unsigned int num_bytes,
2510 			unsigned int chan_index)
2511 {
2512 	struct comedi_cmd *cmd = &s->async->cmd;
2513 	unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2514 	unsigned short *array = data;
2515 	unsigned int i;
2516 #ifdef PCIDMA
2517 	__le16 buf, *barray = data;
2518 #endif
2519 
2520 	for (i = 0; i < nsamples; i++) {
2521 		unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2522 		unsigned short val = array[i];
2523 
2524 		/*
2525 		 * Munge data from unsigned to two's complement for
2526 		 * bipolar ranges.
2527 		 */
2528 		if (comedi_range_is_bipolar(s, range))
2529 			val = comedi_offset_munge(s, val);
2530 #ifdef PCIDMA
2531 		buf = cpu_to_le16(val);
2532 		barray[i] = buf;
2533 #else
2534 		array[i] = val;
2535 #endif
2536 		chan_index++;
2537 		chan_index %= cmd->chanlist_len;
2538 	}
2539 }
2540 
ni_m_series_ao_config_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int chanspec[],unsigned int n_chans,int timed)2541 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2542 					  struct comedi_subdevice *s,
2543 					  unsigned int chanspec[],
2544 					  unsigned int n_chans, int timed)
2545 {
2546 	struct ni_private *devpriv = dev->private;
2547 	unsigned int range;
2548 	unsigned int chan;
2549 	unsigned int conf;
2550 	int i;
2551 	int invert = 0;
2552 
2553 	if (timed) {
2554 		for (i = 0; i < s->n_chan; ++i) {
2555 			devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2556 			ni_writeb(dev, devpriv->ao_conf[i],
2557 				  NI_M_AO_CFG_BANK_REG(i));
2558 			ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2559 		}
2560 	}
2561 	for (i = 0; i < n_chans; i++) {
2562 		const struct comedi_krange *krange;
2563 
2564 		chan = CR_CHAN(chanspec[i]);
2565 		range = CR_RANGE(chanspec[i]);
2566 		krange = s->range_table->range + range;
2567 		invert = 0;
2568 		conf = 0;
2569 		switch (krange->max - krange->min) {
2570 		case 20000000:
2571 			conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2572 			ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2573 			break;
2574 		case 10000000:
2575 			conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2576 			ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2577 			break;
2578 		case 4000000:
2579 			conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2580 			ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2581 				  NI_M_AO_REF_ATTENUATION_REG(chan));
2582 			break;
2583 		case 2000000:
2584 			conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2585 			ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2586 				  NI_M_AO_REF_ATTENUATION_REG(chan));
2587 			break;
2588 		default:
2589 			dev_err(dev->class_dev,
2590 				"bug! unhandled ao reference voltage\n");
2591 			break;
2592 		}
2593 		switch (krange->max + krange->min) {
2594 		case 0:
2595 			conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2596 			break;
2597 		case 10000000:
2598 			conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2599 			break;
2600 		default:
2601 			dev_err(dev->class_dev,
2602 				"bug! unhandled ao offset voltage\n");
2603 			break;
2604 		}
2605 		if (timed)
2606 			conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2607 		ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2608 		devpriv->ao_conf[chan] = conf;
2609 		ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2610 	}
2611 	return invert;
2612 }
2613 
ni_old_ao_config_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int chanspec[],unsigned int n_chans)2614 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2615 				     struct comedi_subdevice *s,
2616 				     unsigned int chanspec[],
2617 				     unsigned int n_chans)
2618 {
2619 	struct ni_private *devpriv = dev->private;
2620 	unsigned int range;
2621 	unsigned int chan;
2622 	unsigned int conf;
2623 	int i;
2624 	int invert = 0;
2625 
2626 	for (i = 0; i < n_chans; i++) {
2627 		chan = CR_CHAN(chanspec[i]);
2628 		range = CR_RANGE(chanspec[i]);
2629 		conf = NI_E_AO_DACSEL(chan);
2630 
2631 		if (comedi_range_is_bipolar(s, range)) {
2632 			conf |= NI_E_AO_CFG_BIP;
2633 			invert = (s->maxdata + 1) >> 1;
2634 		} else {
2635 			invert = 0;
2636 		}
2637 		if (comedi_range_is_external(s, range))
2638 			conf |= NI_E_AO_EXT_REF;
2639 
2640 		/* not all boards can deglitch, but this shouldn't hurt */
2641 		if (chanspec[i] & CR_DEGLITCH)
2642 			conf |= NI_E_AO_DEGLITCH;
2643 
2644 		/* analog reference */
2645 		/* AREF_OTHER connects AO ground to AI ground, i think */
2646 		if (CR_AREF(chanspec[i]) == AREF_OTHER)
2647 			conf |= NI_E_AO_GROUND_REF;
2648 
2649 		ni_writew(dev, conf, NI_E_AO_CFG_REG);
2650 		devpriv->ao_conf[chan] = conf;
2651 	}
2652 	return invert;
2653 }
2654 
ni_ao_config_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int chanspec[],unsigned int n_chans,int timed)2655 static int ni_ao_config_chanlist(struct comedi_device *dev,
2656 				 struct comedi_subdevice *s,
2657 				 unsigned int chanspec[], unsigned int n_chans,
2658 				 int timed)
2659 {
2660 	struct ni_private *devpriv = dev->private;
2661 
2662 	if (devpriv->is_m_series)
2663 		return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2664 						      timed);
2665 	else
2666 		return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2667 }
2668 
ni_ao_insn_write(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)2669 static int ni_ao_insn_write(struct comedi_device *dev,
2670 			    struct comedi_subdevice *s,
2671 			    struct comedi_insn *insn,
2672 			    unsigned int *data)
2673 {
2674 	struct ni_private *devpriv = dev->private;
2675 	unsigned int chan = CR_CHAN(insn->chanspec);
2676 	unsigned int range = CR_RANGE(insn->chanspec);
2677 	int reg;
2678 	int i;
2679 
2680 	if (devpriv->is_6xxx) {
2681 		ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2682 
2683 		reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2684 	} else if (devpriv->is_m_series) {
2685 		reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2686 	} else {
2687 		reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2688 	}
2689 
2690 	ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2691 
2692 	for (i = 0; i < insn->n; i++) {
2693 		unsigned int val = data[i];
2694 
2695 		s->readback[chan] = val;
2696 
2697 		if (devpriv->is_6xxx) {
2698 			/*
2699 			 * 6xxx boards have bipolar outputs, munge the
2700 			 * unsigned comedi values to 2's complement
2701 			 */
2702 			val = comedi_offset_munge(s, val);
2703 
2704 			ni_ao_win_outw(dev, val, reg);
2705 		} else if (devpriv->is_m_series) {
2706 			/*
2707 			 * M-series boards use offset binary values for
2708 			 * bipolar and uinpolar outputs
2709 			 */
2710 			ni_writew(dev, val, reg);
2711 		} else {
2712 			/*
2713 			 * Non-M series boards need two's complement values
2714 			 * for bipolar ranges.
2715 			 */
2716 			if (comedi_range_is_bipolar(s, range))
2717 				val = comedi_offset_munge(s, val);
2718 
2719 			ni_writew(dev, val, reg);
2720 		}
2721 	}
2722 
2723 	return insn->n;
2724 }
2725 
2726 /*
2727  * Arms the AO device in preparation for a trigger event.
2728  * This function also allocates and prepares a DMA channel (or FIFO if DMA is
2729  * not used).  As a part of this preparation, this function preloads the DAC
2730  * registers with the first values of the output stream.  This ensures that the
2731  * first clock cycle after the trigger can be used for output.
2732  *
2733  * Note that this function _must_ happen after a user has written data to the
2734  * output buffers via either mmap or write(fileno,...).
2735  */
ni_ao_arm(struct comedi_device * dev,struct comedi_subdevice * s)2736 static int ni_ao_arm(struct comedi_device *dev,
2737 		     struct comedi_subdevice *s)
2738 {
2739 	struct ni_private *devpriv = dev->private;
2740 	int ret;
2741 	int interrupt_b_bits;
2742 	int i;
2743 	static const int timeout = 1000;
2744 
2745 	/*
2746 	 * Prevent ao from doing things like trying to allocate the ao dma
2747 	 * channel multiple times.
2748 	 */
2749 	if (!devpriv->ao_needs_arming) {
2750 		dev_dbg(dev->class_dev, "%s: device does not need arming!\n",
2751 			__func__);
2752 		return -EINVAL;
2753 	}
2754 
2755 	devpriv->ao_needs_arming = 0;
2756 
2757 	ni_set_bits(dev, NISTC_INTB_ENA_REG,
2758 		    NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2759 	interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2760 #ifdef PCIDMA
2761 	ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2762 	if (devpriv->is_6xxx)
2763 		ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2764 	ret = ni_ao_setup_MITE_dma(dev);
2765 	if (ret)
2766 		return ret;
2767 	ret = ni_ao_wait_for_dma_load(dev);
2768 	if (ret < 0)
2769 		return ret;
2770 #else
2771 	ret = ni_ao_prep_fifo(dev, s);
2772 	if (ret == 0)
2773 		return -EPIPE;
2774 
2775 	interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2776 #endif
2777 
2778 	ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2779 		      NISTC_AO_MODE3_REG);
2780 	ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2781 	/* wait for DACs to be loaded */
2782 	for (i = 0; i < timeout; i++) {
2783 		udelay(1);
2784 		if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2785 		     NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2786 			break;
2787 	}
2788 	if (i == timeout) {
2789 		dev_err(dev->class_dev,
2790 			"timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2791 		return -EIO;
2792 	}
2793 	/*
2794 	 * stc manual says we are need to clear error interrupt after
2795 	 * AO_TMRDACWRs_In_Progress_St clears
2796 	 */
2797 	ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2798 
2799 	ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2800 
2801 	ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2802 			   NISTC_AO_CMD1_UC_ARM |
2803 			   NISTC_AO_CMD1_BC_ARM |
2804 			   devpriv->ao_cmd1,
2805 		      NISTC_AO_CMD1_REG);
2806 
2807 	return 0;
2808 }
2809 
ni_ao_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)2810 static int ni_ao_insn_config(struct comedi_device *dev,
2811 			     struct comedi_subdevice *s,
2812 			     struct comedi_insn *insn, unsigned int *data)
2813 {
2814 	const struct ni_board_struct *board = dev->board_ptr;
2815 	struct ni_private *devpriv = dev->private;
2816 	unsigned int nbytes;
2817 
2818 	switch (data[0]) {
2819 	case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2820 		switch (data[1]) {
2821 		case COMEDI_OUTPUT:
2822 			nbytes = comedi_samples_to_bytes(s,
2823 							 board->ao_fifo_depth);
2824 			data[2] = 1 + nbytes;
2825 			if (devpriv->mite)
2826 				data[2] += devpriv->mite->fifo_size;
2827 			break;
2828 		case COMEDI_INPUT:
2829 			data[2] = 0;
2830 			break;
2831 		default:
2832 			return -EINVAL;
2833 		}
2834 		return 0;
2835 	case INSN_CONFIG_ARM:
2836 		return ni_ao_arm(dev, s);
2837 	default:
2838 		break;
2839 	}
2840 
2841 	return -EINVAL;
2842 }
2843 
ni_ao_inttrig(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int trig_num)2844 static int ni_ao_inttrig(struct comedi_device *dev,
2845 			 struct comedi_subdevice *s,
2846 			 unsigned int trig_num)
2847 {
2848 	struct ni_private *devpriv = dev->private;
2849 	struct comedi_cmd *cmd = &s->async->cmd;
2850 	int ret;
2851 
2852 	/*
2853 	 * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2854 	 * For backwards compatibility, also allow trig_num == 0 when
2855 	 * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2856 	 * in that case, the internal trigger is being used as a pre-trigger
2857 	 * before the external trigger.
2858 	 */
2859 	if (!(trig_num == cmd->start_arg ||
2860 	      (trig_num == 0 && cmd->start_src != TRIG_INT)))
2861 		return -EINVAL;
2862 
2863 	/*
2864 	 * Null trig at beginning prevent ao start trigger from executing more
2865 	 * than once per command.
2866 	 */
2867 	s->async->inttrig = NULL;
2868 
2869 	if (devpriv->ao_needs_arming) {
2870 		/* only arm this device if it still needs arming */
2871 		ret = ni_ao_arm(dev, s);
2872 		if (ret)
2873 			return ret;
2874 	}
2875 
2876 	ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2877 		      NISTC_AO_CMD2_REG);
2878 
2879 	return 0;
2880 }
2881 
2882 /*
2883  * begin ni_ao_cmd.
2884  * Organized similar to NI-STC and MHDDK examples.
2885  * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2886  */
2887 
ni_ao_cmd_personalize(struct comedi_device * dev,const struct comedi_cmd * cmd)2888 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2889 				  const struct comedi_cmd *cmd)
2890 {
2891 	const struct ni_board_struct *board = dev->board_ptr;
2892 	unsigned int bits;
2893 
2894 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2895 
2896 	bits =
2897 	  /* fast CPU interface--only eseries */
2898 	  /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2899 	  NISTC_AO_PERSONAL_BC_SRC_SEL  |
2900 	  0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2901 	  /*
2902 	   * FIXME:  start setting following bit when appropriate.  Need to
2903 	   * determine whether board is E4 or E1.
2904 	   * FROM MHHDK:
2905 	   * if board is E4 or E1
2906 	   *   Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2907 	   * else
2908 	   *   set it to 1
2909 	   */
2910 	  NISTC_AO_PERSONAL_UPDATE_PW   |
2911 	  /* FIXME:  when should we set following bit to zero? */
2912 	  NISTC_AO_PERSONAL_TMRDACWR_PW |
2913 	  (board->ao_fifo_depth ?
2914 	    NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2915 	  ;
2916 #if 0
2917 	/*
2918 	 * FIXME:
2919 	 * add something like ".has_individual_dacs = 0" to ni_board_struct
2920 	 * since, as F Hess pointed out, not all in m series have singles.  not
2921 	 * sure if e-series all have duals...
2922 	 */
2923 
2924 	/*
2925 	 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2926 	 * 6281, verified with bus analyzer.
2927 	 */
2928 	if (devpriv->is_m_series)
2929 		bits |= NISTC_AO_PERSONAL_NUM_DAC;
2930 #endif
2931 	ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2932 
2933 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2934 }
2935 
ni_ao_cmd_set_trigger(struct comedi_device * dev,const struct comedi_cmd * cmd)2936 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2937 				  const struct comedi_cmd *cmd)
2938 {
2939 	struct ni_private *devpriv = dev->private;
2940 	unsigned int trigsel;
2941 
2942 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2943 
2944 	/* sync */
2945 	if (cmd->stop_src == TRIG_NONE) {
2946 		devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2947 		devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2948 	} else {
2949 		devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2950 		devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2951 	}
2952 	ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2953 
2954 	if (cmd->start_src == TRIG_INT) {
2955 		trigsel = NISTC_AO_TRIG_START1_EDGE |
2956 			  NISTC_AO_TRIG_START1_SYNC;
2957 	} else { /* TRIG_EXT */
2958 		trigsel = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2959 		/* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2960 		if (cmd->start_arg & CR_INVERT)
2961 			trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2962 		/* 0=edge detection disabled, 1=enabled */
2963 		if (cmd->start_arg & CR_EDGE)
2964 			trigsel |= NISTC_AO_TRIG_START1_EDGE;
2965 	}
2966 	ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
2967 
2968 	/* AO_Delayed_START1 = 0, we do not support delayed start...yet */
2969 
2970 	/* sync */
2971 	/* select DA_START1 as PFI6/AO_START1 when configured as an output */
2972 	devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2973 	ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2974 
2975 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2976 }
2977 
ni_ao_cmd_set_counters(struct comedi_device * dev,const struct comedi_cmd * cmd)2978 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
2979 				   const struct comedi_cmd *cmd)
2980 {
2981 	struct ni_private *devpriv = dev->private;
2982 	/* Not supporting 'waveform staging' or 'local buffer with pauses' */
2983 
2984 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2985 	/*
2986 	 * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
2987 	 * set_trigger above.  It is unclear whether we really need to re-write
2988 	 * this register with these values.  The mhddk examples for e-series
2989 	 * show writing this in both places, but the examples for m-series show
2990 	 * a single write in the set_counters function (here).
2991 	 */
2992 	ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2993 
2994 	/* sync (upload number of buffer iterations -1) */
2995 	/* indicate that we want to use BC_Load_A_Register as the source */
2996 	devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2997 	ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2998 
2999 	/*
3000 	 * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3001 	 * ignoring BC_TC, then we will need to find a way to ignore that
3002 	 * interrupt in continuous mode.
3003 	 */
3004 	ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3005 
3006 	/* sync (issue command to load number of buffer iterations -1) */
3007 	ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3008 
3009 	/* sync (upload number of updates in buffer) */
3010 	/* indicate that we want to use UC_Load_A_Register as the source */
3011 	devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3012 	ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3013 
3014 	/*
3015 	 * if a user specifies '0', this automatically assumes the entire 24bit
3016 	 * address space is available for the (multiple iterations of single
3017 	 * buffer) MISB.  Otherwise, stop_arg specifies the MISB length that
3018 	 * will be used, regardless of whether we are in continuous mode or not.
3019 	 * In continuous mode, the output will just iterate indefinitely over
3020 	 * the MISB.
3021 	 */
3022 	{
3023 		unsigned int stop_arg = cmd->stop_arg > 0 ?
3024 			(cmd->stop_arg & 0xffffff) : 0xffffff;
3025 
3026 		if (devpriv->is_m_series) {
3027 			/*
3028 			 * this is how the NI example code does it for m-series
3029 			 * boards, verified correct with 6259
3030 			 */
3031 			ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3032 
3033 			/* sync (issue cmd to load number of updates in MISB) */
3034 			ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3035 				      NISTC_AO_CMD1_REG);
3036 		} else {
3037 			ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3038 
3039 			/* sync (issue cmd to load number of updates in MISB) */
3040 			ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3041 				      NISTC_AO_CMD1_REG);
3042 
3043 			/*
3044 			 * sync (upload number of updates-1 in MISB)
3045 			 * --eseries only?
3046 			 */
3047 			ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3048 		}
3049 	}
3050 
3051 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3052 }
3053 
ni_ao_cmd_set_update(struct comedi_device * dev,const struct comedi_cmd * cmd)3054 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3055 				 const struct comedi_cmd *cmd)
3056 {
3057 	struct ni_private *devpriv = dev->private;
3058 
3059 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3060 
3061 	/*
3062 	 * zero out these bit fields to be set below. Does an ao-reset do this
3063 	 * automatically?
3064 	 */
3065 	devpriv->ao_mode1 &= ~(
3066 	  NISTC_AO_MODE1_UI_SRC_MASK         |
3067 	  NISTC_AO_MODE1_UI_SRC_POLARITY     |
3068 	  NISTC_AO_MODE1_UPDATE_SRC_MASK     |
3069 	  NISTC_AO_MODE1_UPDATE_SRC_POLARITY
3070 	);
3071 
3072 	if (cmd->scan_begin_src == TRIG_TIMER) {
3073 		unsigned int trigvar;
3074 
3075 		devpriv->ao_cmd2  &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3076 
3077 		/*
3078 		 * NOTE: there are several other ways of configuring internal
3079 		 * updates, but we'll only support one for now:  using
3080 		 * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3081 		 * START1 and first update, and also w/o local buffer mode w/
3082 		 * pauses.
3083 		 */
3084 
3085 		/*
3086 		 * This is already done above:
3087 		 * devpriv->ao_mode1 &= ~(
3088 		 *   // set UPDATE_Source to UI_TC:
3089 		 *   NISTC_AO_MODE1_UPDATE_SRC_MASK |
3090 		 *   // set UPDATE_Source_Polarity to rising (required?)
3091 		 *   NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3092 		 *   // set UI_Source to AO_IN_TIMEBASE1:
3093 		 *   NISTC_AO_MODE1_UI_SRC_MASK     |
3094 		 *   // set UI_Source_Polarity to rising (required?)
3095 		 *   NISTC_AO_MODE1_UI_SRC_POLARITY
3096 		 * );
3097 		 */
3098 
3099 		/*
3100 		 * TODO:  use ao_ui_clock_source to allow all possible signals
3101 		 * to be routed to UI_Source_Select.  See tSTC.h for
3102 		 * eseries/ni67xx and tMSeries.h for mseries.
3103 		 */
3104 
3105 		trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3106 					 CMDF_ROUND_NEAREST);
3107 
3108 		/*
3109 		 * Wait N TB3 ticks after the start trigger before
3110 		 * clocking (N must be >=2).
3111 		 */
3112 		/* following line: 2-1 per STC */
3113 		ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3114 		ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3115 		ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3116 	} else { /* TRIG_EXT */
3117 		/* FIXME:  assert scan_begin_arg != 0, ret failure otherwise */
3118 		devpriv->ao_cmd2  |= NISTC_AO_CMD2_BC_GATE_ENA;
3119 		devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3120 					CR_CHAN(cmd->scan_begin_arg));
3121 		if (cmd->scan_begin_arg & CR_INVERT)
3122 			devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3123 	}
3124 
3125 	ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3126 	ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3127 	devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3128 			       NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3129 	ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3130 
3131 	/* Configure DAQ-STC for Timed update mode */
3132 	devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3133 			    NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3134 	/* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3135 	ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3136 
3137 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3138 }
3139 
ni_ao_cmd_set_channels(struct comedi_device * dev,struct comedi_subdevice * s)3140 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3141 				   struct comedi_subdevice *s)
3142 {
3143 	struct ni_private *devpriv = dev->private;
3144 	const struct comedi_cmd *cmd = &s->async->cmd;
3145 	unsigned int bits = 0;
3146 
3147 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3148 
3149 	if (devpriv->is_6xxx) {
3150 		unsigned int i;
3151 
3152 		bits = 0;
3153 		for (i = 0; i < cmd->chanlist_len; ++i) {
3154 			int chan = CR_CHAN(cmd->chanlist[i]);
3155 
3156 			bits |= 1 << chan;
3157 			ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3158 		}
3159 		ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3160 	}
3161 
3162 	ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3163 
3164 	if (cmd->scan_end_arg > 1) {
3165 		devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3166 		bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3167 				 | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3168 
3169 	} else {
3170 		devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3171 		bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3172 		if (devpriv->is_m_series | devpriv->is_6xxx)
3173 			bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3174 		else
3175 			bits |= NISTC_AO_OUT_CTRL_CHANS(
3176 					CR_CHAN(cmd->chanlist[0]));
3177 	}
3178 
3179 	ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3180 	ni_stc_writew(dev, bits,              NISTC_AO_OUT_CTRL_REG);
3181 
3182 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3183 }
3184 
ni_ao_cmd_set_stop_conditions(struct comedi_device * dev,const struct comedi_cmd * cmd)3185 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3186 					  const struct comedi_cmd *cmd)
3187 {
3188 	struct ni_private *devpriv = dev->private;
3189 
3190 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3191 
3192 	devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3193 	ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3194 
3195 	/*
3196 	 * Since we are not supporting waveform staging, we ignore these errors:
3197 	 * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3198 	 * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3199 	 */
3200 
3201 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3202 }
3203 
ni_ao_cmd_set_fifo_mode(struct comedi_device * dev)3204 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3205 {
3206 	struct ni_private *devpriv = dev->private;
3207 
3208 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3209 
3210 	devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3211 #ifdef PCIDMA
3212 	devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3213 #else
3214 	devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3215 #endif
3216 	/* NOTE:  this is where use_onboard_memory=True would be implemented */
3217 	devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3218 	ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3219 
3220 	/* enable sending of ao fifo requests (dma request) */
3221 	ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3222 
3223 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3224 
3225 	/* we are not supporting boards with virtual fifos */
3226 }
3227 
ni_ao_cmd_set_interrupts(struct comedi_device * dev,struct comedi_subdevice * s)3228 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3229 				     struct comedi_subdevice *s)
3230 {
3231 	if (s->async->cmd.stop_src == TRIG_COUNT)
3232 		ni_set_bits(dev, NISTC_INTB_ENA_REG,
3233 			    NISTC_INTB_ENA_AO_BC_TC, 1);
3234 
3235 	s->async->inttrig = ni_ao_inttrig;
3236 }
3237 
ni_ao_cmd(struct comedi_device * dev,struct comedi_subdevice * s)3238 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3239 {
3240 	struct ni_private *devpriv = dev->private;
3241 	const struct comedi_cmd *cmd = &s->async->cmd;
3242 
3243 	if (dev->irq == 0) {
3244 		dev_err(dev->class_dev, "cannot run command without an irq");
3245 		return -EIO;
3246 	}
3247 
3248 	/* ni_ao_reset should have already been done */
3249 	ni_ao_cmd_personalize(dev, cmd);
3250 	/* clearing fifo and preload happens elsewhere */
3251 
3252 	ni_ao_cmd_set_trigger(dev, cmd);
3253 	ni_ao_cmd_set_counters(dev, cmd);
3254 	ni_ao_cmd_set_update(dev, cmd);
3255 	ni_ao_cmd_set_channels(dev, s);
3256 	ni_ao_cmd_set_stop_conditions(dev, cmd);
3257 	ni_ao_cmd_set_fifo_mode(dev);
3258 	ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3259 	ni_ao_cmd_set_interrupts(dev, s);
3260 
3261 	/*
3262 	 * arm(ing) must happen later so that DMA can be setup and DACs
3263 	 * preloaded with the actual output buffer before starting.
3264 	 *
3265 	 * start(ing) must happen _after_ arming is completed.  Starting can be
3266 	 * done either via ni_ao_inttrig, or via an external trigger.
3267 	 *
3268 	 * **Currently, ni_ao_inttrig will automatically attempt a call to
3269 	 * ni_ao_arm if the device still needs arming at that point.  This
3270 	 * allows backwards compatibility.
3271 	 */
3272 	devpriv->ao_needs_arming = 1;
3273 	return 0;
3274 }
3275 
3276 /* end ni_ao_cmd */
3277 
ni_ao_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)3278 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3279 			 struct comedi_cmd *cmd)
3280 {
3281 	const struct ni_board_struct *board = dev->board_ptr;
3282 	struct ni_private *devpriv = dev->private;
3283 	int err = 0;
3284 	unsigned int tmp;
3285 
3286 	/* Step 1 : check if triggers are trivially valid */
3287 
3288 	err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3289 	err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3290 					TRIG_TIMER | TRIG_EXT);
3291 	err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3292 	err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3293 	err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3294 
3295 	if (err)
3296 		return 1;
3297 
3298 	/* Step 2a : make sure trigger sources are unique */
3299 
3300 	err |= comedi_check_trigger_is_unique(cmd->start_src);
3301 	err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3302 	err |= comedi_check_trigger_is_unique(cmd->stop_src);
3303 
3304 	/* Step 2b : and mutually compatible */
3305 
3306 	if (err)
3307 		return 2;
3308 
3309 	/* Step 3: check if arguments are trivially valid */
3310 
3311 	switch (cmd->start_src) {
3312 	case TRIG_INT:
3313 		err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3314 		break;
3315 	case TRIG_EXT:
3316 		tmp = CR_CHAN(cmd->start_arg);
3317 
3318 		if (tmp > 18)
3319 			tmp = 18;
3320 		tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3321 		err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3322 		break;
3323 	}
3324 
3325 	if (cmd->scan_begin_src == TRIG_TIMER) {
3326 		err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3327 						    board->ao_speed);
3328 		err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3329 						    devpriv->clock_ns *
3330 						    0xffffff);
3331 	}
3332 
3333 	err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3334 	err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3335 					   cmd->chanlist_len);
3336 	err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3337 
3338 	if (err)
3339 		return 3;
3340 
3341 	/* step 4: fix up any arguments */
3342 	if (cmd->scan_begin_src == TRIG_TIMER) {
3343 		tmp = cmd->scan_begin_arg;
3344 		cmd->scan_begin_arg =
3345 		    ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3346 						       cmd->scan_begin_arg,
3347 						       cmd->flags));
3348 		if (tmp != cmd->scan_begin_arg)
3349 			err++;
3350 	}
3351 	if (err)
3352 		return 4;
3353 
3354 	return 0;
3355 }
3356 
ni_ao_reset(struct comedi_device * dev,struct comedi_subdevice * s)3357 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3358 {
3359 	/* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3360 
3361 	/*
3362 	 * In the following, the "--sync" comments are meant to denote
3363 	 * asynchronous boundaries for setting the registers as described in the
3364 	 * DAQ-STC mostly in the order also described in the DAQ-STC.
3365 	 */
3366 
3367 	struct ni_private *devpriv = dev->private;
3368 
3369 	ni_release_ao_mite_channel(dev);
3370 
3371 	/* --sync (reset AO) */
3372 	if (devpriv->is_m_series)
3373 		/* following example in mhddk for m-series */
3374 		ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3375 
3376 	/*--sync (start config) */
3377 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3378 
3379 	/*--sync (Disarm) */
3380 	ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3381 
3382 	/*
3383 	 * --sync
3384 	 * (clear bunch of registers--mseries mhddk examples do not include
3385 	 * this)
3386 	 */
3387 	devpriv->ao_cmd1  = 0;
3388 	devpriv->ao_cmd2  = 0;
3389 	devpriv->ao_mode1 = 0;
3390 	devpriv->ao_mode2 = 0;
3391 	if (devpriv->is_m_series)
3392 		devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3393 	else
3394 		devpriv->ao_mode3 = 0;
3395 
3396 	ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3397 	ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3398 	ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3399 	ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3400 	ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3401 	ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3402 	ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3403 	ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3404 	ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3405 
3406 	/*--sync (disable interrupts) */
3407 	ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3408 
3409 	/*--sync (ack) */
3410 	ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3411 	ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3412 
3413 	/*--not in DAQ-STC.  which doc? */
3414 	if (devpriv->is_6xxx) {
3415 		ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3416 			       NI671X_AO_IMMEDIATE_REG);
3417 		ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3418 			       NI611X_AO_MISC_REG);
3419 	}
3420 	ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3421 	/*--end */
3422 
3423 	return 0;
3424 }
3425 
3426 /* digital io */
3427 
ni_dio_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3428 static int ni_dio_insn_config(struct comedi_device *dev,
3429 			      struct comedi_subdevice *s,
3430 			      struct comedi_insn *insn,
3431 			      unsigned int *data)
3432 {
3433 	struct ni_private *devpriv = dev->private;
3434 	int ret;
3435 
3436 	ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3437 	if (ret)
3438 		return ret;
3439 
3440 	devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3441 	devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3442 	ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3443 
3444 	return insn->n;
3445 }
3446 
ni_dio_insn_bits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3447 static int ni_dio_insn_bits(struct comedi_device *dev,
3448 			    struct comedi_subdevice *s,
3449 			    struct comedi_insn *insn,
3450 			    unsigned int *data)
3451 {
3452 	struct ni_private *devpriv = dev->private;
3453 
3454 	/* Make sure we're not using the serial part of the dio */
3455 	if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3456 	    devpriv->serial_interval_ns)
3457 		return -EBUSY;
3458 
3459 	if (comedi_dio_update_state(s, data)) {
3460 		devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3461 		devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3462 		ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3463 	}
3464 
3465 	data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3466 
3467 	return insn->n;
3468 }
3469 
3470 #ifdef PCIDMA
ni_m_series_dio_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3471 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3472 				       struct comedi_subdevice *s,
3473 				       struct comedi_insn *insn,
3474 				       unsigned int *data)
3475 {
3476 	int ret;
3477 
3478 	ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3479 	if (ret)
3480 		return ret;
3481 
3482 	ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3483 
3484 	return insn->n;
3485 }
3486 
ni_m_series_dio_insn_bits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3487 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3488 				     struct comedi_subdevice *s,
3489 				     struct comedi_insn *insn,
3490 				     unsigned int *data)
3491 {
3492 	if (comedi_dio_update_state(s, data))
3493 		ni_writel(dev, s->state, NI_M_DIO_REG);
3494 
3495 	data[1] = ni_readl(dev, NI_M_DIO_REG);
3496 
3497 	return insn->n;
3498 }
3499 
ni_cdio_check_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)3500 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3501 				  struct comedi_subdevice *s,
3502 				  struct comedi_cmd *cmd)
3503 {
3504 	int i;
3505 
3506 	for (i = 0; i < cmd->chanlist_len; ++i) {
3507 		unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3508 
3509 		if (chan != i)
3510 			return -EINVAL;
3511 	}
3512 
3513 	return 0;
3514 }
3515 
ni_cdio_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)3516 static int ni_cdio_cmdtest(struct comedi_device *dev,
3517 			   struct comedi_subdevice *s, struct comedi_cmd *cmd)
3518 {
3519 	int err = 0;
3520 	int tmp;
3521 
3522 	/* Step 1 : check if triggers are trivially valid */
3523 
3524 	err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3525 	err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3526 	err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3527 	err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3528 	err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3529 
3530 	if (err)
3531 		return 1;
3532 
3533 	/* Step 2a : make sure trigger sources are unique */
3534 	/* Step 2b : and mutually compatible */
3535 
3536 	/* Step 3: check if arguments are trivially valid */
3537 
3538 	err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3539 
3540 	tmp = cmd->scan_begin_arg;
3541 	tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3542 	if (tmp != cmd->scan_begin_arg)
3543 		err |= -EINVAL;
3544 
3545 	err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3546 	err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3547 					   cmd->chanlist_len);
3548 	err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3549 					    s->async->prealloc_bufsz /
3550 					    comedi_bytes_per_scan(s));
3551 
3552 	if (err)
3553 		return 3;
3554 
3555 	/* Step 4: fix up any arguments */
3556 
3557 	/* Step 5: check channel list if it exists */
3558 
3559 	if (cmd->chanlist && cmd->chanlist_len > 0)
3560 		err |= ni_cdio_check_chanlist(dev, s, cmd);
3561 
3562 	if (err)
3563 		return 5;
3564 
3565 	return 0;
3566 }
3567 
ni_cdo_inttrig(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int trig_num)3568 static int ni_cdo_inttrig(struct comedi_device *dev,
3569 			  struct comedi_subdevice *s,
3570 			  unsigned int trig_num)
3571 {
3572 	struct comedi_cmd *cmd = &s->async->cmd;
3573 	const unsigned int timeout = 1000;
3574 	int retval = 0;
3575 	unsigned int i;
3576 	struct ni_private *devpriv = dev->private;
3577 	unsigned long flags;
3578 
3579 	if (trig_num != cmd->start_arg)
3580 		return -EINVAL;
3581 
3582 	s->async->inttrig = NULL;
3583 
3584 	/* read alloc the entire buffer */
3585 	comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3586 
3587 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3588 	if (devpriv->cdo_mite_chan) {
3589 		mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3590 		mite_dma_arm(devpriv->cdo_mite_chan);
3591 	} else {
3592 		dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3593 		retval = -EIO;
3594 	}
3595 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3596 	if (retval < 0)
3597 		return retval;
3598 
3599 	/*
3600 	 * XXX not sure what interrupt C group does
3601 	 * wait for dma to fill output fifo
3602 	 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3603 	 */
3604 	for (i = 0; i < timeout; ++i) {
3605 		if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3606 		    NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3607 			break;
3608 		usleep_range(10, 100);
3609 	}
3610 	if (i == timeout) {
3611 		dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3612 		s->cancel(dev, s);
3613 		return -EIO;
3614 	}
3615 	ni_writel(dev, NI_M_CDO_CMD_ARM |
3616 		       NI_M_CDO_CMD_ERR_INT_ENA_SET |
3617 		       NI_M_CDO_CMD_F_E_INT_ENA_SET,
3618 		  NI_M_CDIO_CMD_REG);
3619 	return retval;
3620 }
3621 
ni_cdio_cmd(struct comedi_device * dev,struct comedi_subdevice * s)3622 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3623 {
3624 	struct ni_private *devpriv = dev->private;
3625 	const struct comedi_cmd *cmd = &s->async->cmd;
3626 	unsigned int cdo_mode_bits;
3627 	int retval;
3628 
3629 	ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3630 	cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3631 			NI_M_CDO_MODE_HALT_ON_ERROR |
3632 			NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3633 	if (cmd->scan_begin_arg & CR_INVERT)
3634 		cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3635 	ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3636 	if (s->io_bits) {
3637 		ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3638 		ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3639 		ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3640 	} else {
3641 		dev_err(dev->class_dev,
3642 			"attempted to run digital output command with no lines configured as outputs\n");
3643 		return -EIO;
3644 	}
3645 	retval = ni_request_cdo_mite_channel(dev);
3646 	if (retval < 0)
3647 		return retval;
3648 
3649 	ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3650 				 s->async->prealloc_bufsz /
3651 				 comedi_bytes_per_scan(s));
3652 
3653 	s->async->inttrig = ni_cdo_inttrig;
3654 
3655 	return 0;
3656 }
3657 
ni_cdio_cancel(struct comedi_device * dev,struct comedi_subdevice * s)3658 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3659 {
3660 	ni_writel(dev, NI_M_CDO_CMD_DISARM |
3661 		       NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3662 		       NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3663 		       NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3664 		  NI_M_CDIO_CMD_REG);
3665 	/*
3666 	 * XXX not sure what interrupt C group does
3667 	 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3668 	 */
3669 	ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3670 	ni_release_cdo_mite_channel(dev);
3671 	return 0;
3672 }
3673 
handle_cdio_interrupt(struct comedi_device * dev)3674 static void handle_cdio_interrupt(struct comedi_device *dev)
3675 {
3676 	struct ni_private *devpriv = dev->private;
3677 	unsigned int cdio_status;
3678 	struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3679 	unsigned long flags;
3680 
3681 	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3682 	if (devpriv->cdo_mite_chan)
3683 		mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3684 	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3685 
3686 	cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3687 	if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3688 		/* XXX just guessing this is needed and does something useful */
3689 		ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3690 			  NI_M_CDIO_CMD_REG);
3691 		s->async->events |= COMEDI_CB_OVERFLOW;
3692 	}
3693 	if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3694 		ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3695 			  NI_M_CDIO_CMD_REG);
3696 		/* s->async->events |= COMEDI_CB_EOA; */
3697 	}
3698 	comedi_handle_events(dev, s);
3699 }
3700 #endif /*  PCIDMA */
3701 
ni_serial_hw_readwrite8(struct comedi_device * dev,struct comedi_subdevice * s,unsigned char data_out,unsigned char * data_in)3702 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3703 				   struct comedi_subdevice *s,
3704 				   unsigned char data_out,
3705 				   unsigned char *data_in)
3706 {
3707 	struct ni_private *devpriv = dev->private;
3708 	unsigned int status1;
3709 	int err = 0, count = 20;
3710 
3711 	devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3712 	devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3713 	ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3714 
3715 	status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3716 	if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3717 		err = -EBUSY;
3718 		goto error;
3719 	}
3720 
3721 	devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3722 	ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3723 	devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3724 
3725 	/* Wait until STC says we're done, but don't loop infinitely. */
3726 	while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3727 	       NISTC_STATUS1_SERIO_IN_PROG) {
3728 		/* Delay one bit per loop */
3729 		udelay((devpriv->serial_interval_ns + 999) / 1000);
3730 		if (--count < 0) {
3731 			dev_err(dev->class_dev,
3732 				"SPI serial I/O didn't finish in time!\n");
3733 			err = -ETIME;
3734 			goto error;
3735 		}
3736 	}
3737 
3738 	/*
3739 	 * Delay for last bit. This delay is absolutely necessary, because
3740 	 * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3741 	 */
3742 	udelay((devpriv->serial_interval_ns + 999) / 1000);
3743 
3744 	if (data_in)
3745 		*data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3746 
3747 error:
3748 	ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3749 
3750 	return err;
3751 }
3752 
ni_serial_sw_readwrite8(struct comedi_device * dev,struct comedi_subdevice * s,unsigned char data_out,unsigned char * data_in)3753 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3754 				   struct comedi_subdevice *s,
3755 				   unsigned char data_out,
3756 				   unsigned char *data_in)
3757 {
3758 	struct ni_private *devpriv = dev->private;
3759 	unsigned char mask, input = 0;
3760 
3761 	/* Wait for one bit before transfer */
3762 	udelay((devpriv->serial_interval_ns + 999) / 1000);
3763 
3764 	for (mask = 0x80; mask; mask >>= 1) {
3765 		/*
3766 		 * Output current bit; note that we cannot touch s->state
3767 		 * because it is a per-subdevice field, and serial is
3768 		 * a separate subdevice from DIO.
3769 		 */
3770 		devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3771 		if (data_out & mask)
3772 			devpriv->dio_output |= NISTC_DIO_SDOUT;
3773 		ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3774 
3775 		/*
3776 		 * Assert SDCLK (active low, inverted), wait for half of
3777 		 * the delay, deassert SDCLK, and wait for the other half.
3778 		 */
3779 		devpriv->dio_control |= NISTC_DIO_SDCLK;
3780 		ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3781 
3782 		udelay((devpriv->serial_interval_ns + 999) / 2000);
3783 
3784 		devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3785 		ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3786 
3787 		udelay((devpriv->serial_interval_ns + 999) / 2000);
3788 
3789 		/* Input current bit */
3790 		if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3791 			input |= mask;
3792 	}
3793 
3794 	if (data_in)
3795 		*data_in = input;
3796 
3797 	return 0;
3798 }
3799 
ni_serial_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3800 static int ni_serial_insn_config(struct comedi_device *dev,
3801 				 struct comedi_subdevice *s,
3802 				 struct comedi_insn *insn,
3803 				 unsigned int *data)
3804 {
3805 	struct ni_private *devpriv = dev->private;
3806 	unsigned int clk_fout = devpriv->clock_and_fout;
3807 	int err = insn->n;
3808 	unsigned char byte_out, byte_in = 0;
3809 
3810 	if (insn->n != 2)
3811 		return -EINVAL;
3812 
3813 	switch (data[0]) {
3814 	case INSN_CONFIG_SERIAL_CLOCK:
3815 		devpriv->serial_hw_mode = 1;
3816 		devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3817 
3818 		if (data[1] == SERIAL_DISABLED) {
3819 			devpriv->serial_hw_mode = 0;
3820 			devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3821 						  NISTC_DIO_SDCLK);
3822 			data[1] = SERIAL_DISABLED;
3823 			devpriv->serial_interval_ns = data[1];
3824 		} else if (data[1] <= SERIAL_600NS) {
3825 			/*
3826 			 * Warning: this clock speed is too fast to reliably
3827 			 * control SCXI.
3828 			 */
3829 			devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3830 			clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3831 			clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3832 			data[1] = SERIAL_600NS;
3833 			devpriv->serial_interval_ns = data[1];
3834 		} else if (data[1] <= SERIAL_1_2US) {
3835 			devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3836 			clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3837 				    NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3838 			data[1] = SERIAL_1_2US;
3839 			devpriv->serial_interval_ns = data[1];
3840 		} else if (data[1] <= SERIAL_10US) {
3841 			devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3842 			clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3843 				    NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3844 			/*
3845 			 * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3846 			 * 600ns/1.2us. If you turn divide_by_2 off with the
3847 			 * slow clock, you will still get 10us, except then
3848 			 * all your delays are wrong.
3849 			 */
3850 			data[1] = SERIAL_10US;
3851 			devpriv->serial_interval_ns = data[1];
3852 		} else {
3853 			devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3854 						  NISTC_DIO_SDCLK);
3855 			devpriv->serial_hw_mode = 0;
3856 			data[1] = (data[1] / 1000) * 1000;
3857 			devpriv->serial_interval_ns = data[1];
3858 		}
3859 		devpriv->clock_and_fout = clk_fout;
3860 
3861 		ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3862 		ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3863 		return 1;
3864 
3865 	case INSN_CONFIG_BIDIRECTIONAL_DATA:
3866 
3867 		if (devpriv->serial_interval_ns == 0)
3868 			return -EINVAL;
3869 
3870 		byte_out = data[1] & 0xFF;
3871 
3872 		if (devpriv->serial_hw_mode) {
3873 			err = ni_serial_hw_readwrite8(dev, s, byte_out,
3874 						      &byte_in);
3875 		} else if (devpriv->serial_interval_ns > 0) {
3876 			err = ni_serial_sw_readwrite8(dev, s, byte_out,
3877 						      &byte_in);
3878 		} else {
3879 			dev_err(dev->class_dev, "serial disabled!\n");
3880 			return -EINVAL;
3881 		}
3882 		if (err < 0)
3883 			return err;
3884 		data[1] = byte_in & 0xFF;
3885 		return insn->n;
3886 
3887 		break;
3888 	default:
3889 		return -EINVAL;
3890 	}
3891 }
3892 
init_ao_67xx(struct comedi_device * dev,struct comedi_subdevice * s)3893 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3894 {
3895 	int i;
3896 
3897 	for (i = 0; i < s->n_chan; i++) {
3898 		ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3899 			       NI67XX_AO_CFG2_REG);
3900 	}
3901 	ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3902 }
3903 
3904 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3905 	[NITIO_G0_AUTO_INC]	= { NISTC_G0_AUTOINC_REG, 2 },
3906 	[NITIO_G1_AUTO_INC]	= { NISTC_G1_AUTOINC_REG, 2 },
3907 	[NITIO_G0_CMD]		= { NISTC_G0_CMD_REG, 2 },
3908 	[NITIO_G1_CMD]		= { NISTC_G1_CMD_REG, 2 },
3909 	[NITIO_G0_HW_SAVE]	= { NISTC_G0_HW_SAVE_REG, 4 },
3910 	[NITIO_G1_HW_SAVE]	= { NISTC_G1_HW_SAVE_REG, 4 },
3911 	[NITIO_G0_SW_SAVE]	= { NISTC_G0_SAVE_REG, 4 },
3912 	[NITIO_G1_SW_SAVE]	= { NISTC_G1_SAVE_REG, 4 },
3913 	[NITIO_G0_MODE]		= { NISTC_G0_MODE_REG, 2 },
3914 	[NITIO_G1_MODE]		= { NISTC_G1_MODE_REG, 2 },
3915 	[NITIO_G0_LOADA]	= { NISTC_G0_LOADA_REG, 4 },
3916 	[NITIO_G1_LOADA]	= { NISTC_G1_LOADA_REG, 4 },
3917 	[NITIO_G0_LOADB]	= { NISTC_G0_LOADB_REG, 4 },
3918 	[NITIO_G1_LOADB]	= { NISTC_G1_LOADB_REG, 4 },
3919 	[NITIO_G0_INPUT_SEL]	= { NISTC_G0_INPUT_SEL_REG, 2 },
3920 	[NITIO_G1_INPUT_SEL]	= { NISTC_G1_INPUT_SEL_REG, 2 },
3921 	[NITIO_G0_CNT_MODE]	= { 0x1b0, 2 },	/* M-Series only */
3922 	[NITIO_G1_CNT_MODE]	= { 0x1b2, 2 },	/* M-Series only */
3923 	[NITIO_G0_GATE2]	= { 0x1b4, 2 },	/* M-Series only */
3924 	[NITIO_G1_GATE2]	= { 0x1b6, 2 },	/* M-Series only */
3925 	[NITIO_G01_STATUS]	= { NISTC_G01_STATUS_REG, 2 },
3926 	[NITIO_G01_RESET]	= { NISTC_RESET_REG, 2 },
3927 	[NITIO_G01_STATUS1]	= { NISTC_STATUS1_REG, 2 },
3928 	[NITIO_G01_STATUS2]	= { NISTC_STATUS2_REG, 2 },
3929 	[NITIO_G0_DMA_CFG]	= { 0x1b8, 2 },	/* M-Series only */
3930 	[NITIO_G1_DMA_CFG]	= { 0x1ba, 2 },	/* M-Series only */
3931 	[NITIO_G0_DMA_STATUS]	= { 0x1b8, 2 },	/* M-Series only */
3932 	[NITIO_G1_DMA_STATUS]	= { 0x1ba, 2 },	/* M-Series only */
3933 	[NITIO_G0_ABZ]		= { 0x1c0, 2 },	/* M-Series only */
3934 	[NITIO_G1_ABZ]		= { 0x1c2, 2 },	/* M-Series only */
3935 	[NITIO_G0_INT_ACK]	= { NISTC_INTA_ACK_REG, 2 },
3936 	[NITIO_G1_INT_ACK]	= { NISTC_INTB_ACK_REG, 2 },
3937 	[NITIO_G0_STATUS]	= { NISTC_AI_STATUS1_REG, 2 },
3938 	[NITIO_G1_STATUS]	= { NISTC_AO_STATUS1_REG, 2 },
3939 	[NITIO_G0_INT_ENA]	= { NISTC_INTA_ENA_REG, 2 },
3940 	[NITIO_G1_INT_ENA]	= { NISTC_INTB_ENA_REG, 2 },
3941 };
3942 
ni_gpct_to_stc_register(struct comedi_device * dev,enum ni_gpct_register reg)3943 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3944 					    enum ni_gpct_register reg)
3945 {
3946 	const struct mio_regmap *regmap;
3947 
3948 	if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3949 		regmap = &ni_gpct_to_stc_regmap[reg];
3950 	} else {
3951 		dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3952 			 __func__, reg);
3953 		return 0;
3954 	}
3955 
3956 	return regmap->mio_reg;
3957 }
3958 
ni_gpct_write_register(struct ni_gpct * counter,unsigned int bits,enum ni_gpct_register reg)3959 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
3960 				   enum ni_gpct_register reg)
3961 {
3962 	struct comedi_device *dev = counter->counter_dev->dev;
3963 	unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3964 
3965 	if (stc_register == 0)
3966 		return;
3967 
3968 	switch (reg) {
3969 		/* m-series only registers */
3970 	case NITIO_G0_CNT_MODE:
3971 	case NITIO_G1_CNT_MODE:
3972 	case NITIO_G0_GATE2:
3973 	case NITIO_G1_GATE2:
3974 	case NITIO_G0_DMA_CFG:
3975 	case NITIO_G1_DMA_CFG:
3976 	case NITIO_G0_ABZ:
3977 	case NITIO_G1_ABZ:
3978 		ni_writew(dev, bits, stc_register);
3979 		break;
3980 
3981 		/* 32 bit registers */
3982 	case NITIO_G0_LOADA:
3983 	case NITIO_G1_LOADA:
3984 	case NITIO_G0_LOADB:
3985 	case NITIO_G1_LOADB:
3986 		ni_stc_writel(dev, bits, stc_register);
3987 		break;
3988 
3989 		/* 16 bit registers */
3990 	case NITIO_G0_INT_ENA:
3991 		ni_set_bitfield(dev, stc_register,
3992 				NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
3993 				bits);
3994 		break;
3995 	case NITIO_G1_INT_ENA:
3996 		ni_set_bitfield(dev, stc_register,
3997 				NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
3998 				bits);
3999 		break;
4000 	default:
4001 		ni_stc_writew(dev, bits, stc_register);
4002 	}
4003 }
4004 
ni_gpct_read_register(struct ni_gpct * counter,enum ni_gpct_register reg)4005 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
4006 					  enum ni_gpct_register reg)
4007 {
4008 	struct comedi_device *dev = counter->counter_dev->dev;
4009 	unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4010 
4011 	if (stc_register == 0)
4012 		return 0;
4013 
4014 	switch (reg) {
4015 		/* m-series only registers */
4016 	case NITIO_G0_DMA_STATUS:
4017 	case NITIO_G1_DMA_STATUS:
4018 		return ni_readw(dev, stc_register);
4019 
4020 		/* 32 bit registers */
4021 	case NITIO_G0_HW_SAVE:
4022 	case NITIO_G1_HW_SAVE:
4023 	case NITIO_G0_SW_SAVE:
4024 	case NITIO_G1_SW_SAVE:
4025 		return ni_stc_readl(dev, stc_register);
4026 
4027 		/* 16 bit registers */
4028 	default:
4029 		return ni_stc_readw(dev, stc_register);
4030 	}
4031 }
4032 
ni_freq_out_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4033 static int ni_freq_out_insn_read(struct comedi_device *dev,
4034 				 struct comedi_subdevice *s,
4035 				 struct comedi_insn *insn,
4036 				 unsigned int *data)
4037 {
4038 	struct ni_private *devpriv = dev->private;
4039 	unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4040 	int i;
4041 
4042 	for (i = 0; i < insn->n; i++)
4043 		data[i] = val;
4044 
4045 	return insn->n;
4046 }
4047 
ni_freq_out_insn_write(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4048 static int ni_freq_out_insn_write(struct comedi_device *dev,
4049 				  struct comedi_subdevice *s,
4050 				  struct comedi_insn *insn,
4051 				  unsigned int *data)
4052 {
4053 	struct ni_private *devpriv = dev->private;
4054 
4055 	if (insn->n) {
4056 		unsigned int val = data[insn->n - 1];
4057 
4058 		devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4059 		ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4060 		devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4061 
4062 		/* use the last data value to set the fout divider */
4063 		devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4064 
4065 		devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4066 		ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4067 	}
4068 	return insn->n;
4069 }
4070 
ni_freq_out_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4071 static int ni_freq_out_insn_config(struct comedi_device *dev,
4072 				   struct comedi_subdevice *s,
4073 				   struct comedi_insn *insn,
4074 				   unsigned int *data)
4075 {
4076 	struct ni_private *devpriv = dev->private;
4077 
4078 	switch (data[0]) {
4079 	case INSN_CONFIG_SET_CLOCK_SRC:
4080 		switch (data[1]) {
4081 		case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4082 			devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4083 			break;
4084 		case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4085 			devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4086 			break;
4087 		default:
4088 			return -EINVAL;
4089 		}
4090 		ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4091 		break;
4092 	case INSN_CONFIG_GET_CLOCK_SRC:
4093 		if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4094 			data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4095 			data[2] = TIMEBASE_2_NS;
4096 		} else {
4097 			data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4098 			data[2] = TIMEBASE_1_NS * 2;
4099 		}
4100 		break;
4101 	default:
4102 		return -EINVAL;
4103 	}
4104 	return insn->n;
4105 }
4106 
ni_8255_callback(struct comedi_device * dev,int dir,int port,int data,unsigned long iobase)4107 static int ni_8255_callback(struct comedi_device *dev,
4108 			    int dir, int port, int data, unsigned long iobase)
4109 {
4110 	if (dir) {
4111 		ni_writeb(dev, data, iobase + 2 * port);
4112 		return 0;
4113 	}
4114 
4115 	return ni_readb(dev, iobase + 2 * port);
4116 }
4117 
ni_get_pwm_config(struct comedi_device * dev,unsigned int * data)4118 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4119 {
4120 	struct ni_private *devpriv = dev->private;
4121 
4122 	data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4123 	data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4124 	return 3;
4125 }
4126 
ni_m_series_pwm_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4127 static int ni_m_series_pwm_config(struct comedi_device *dev,
4128 				  struct comedi_subdevice *s,
4129 				  struct comedi_insn *insn,
4130 				  unsigned int *data)
4131 {
4132 	struct ni_private *devpriv = dev->private;
4133 	unsigned int up_count, down_count;
4134 
4135 	switch (data[0]) {
4136 	case INSN_CONFIG_PWM_OUTPUT:
4137 		switch (data[1]) {
4138 		case CMDF_ROUND_NEAREST:
4139 			up_count = DIV_ROUND_CLOSEST(data[2],
4140 						     devpriv->clock_ns);
4141 			break;
4142 		case CMDF_ROUND_DOWN:
4143 			up_count = data[2] / devpriv->clock_ns;
4144 			break;
4145 		case CMDF_ROUND_UP:
4146 			up_count =
4147 			    DIV_ROUND_UP(data[2], devpriv->clock_ns);
4148 			break;
4149 		default:
4150 			return -EINVAL;
4151 		}
4152 		switch (data[3]) {
4153 		case CMDF_ROUND_NEAREST:
4154 			down_count = DIV_ROUND_CLOSEST(data[4],
4155 						       devpriv->clock_ns);
4156 			break;
4157 		case CMDF_ROUND_DOWN:
4158 			down_count = data[4] / devpriv->clock_ns;
4159 			break;
4160 		case CMDF_ROUND_UP:
4161 			down_count =
4162 			    DIV_ROUND_UP(data[4], devpriv->clock_ns);
4163 			break;
4164 		default:
4165 			return -EINVAL;
4166 		}
4167 		if (up_count * devpriv->clock_ns != data[2] ||
4168 		    down_count * devpriv->clock_ns != data[4]) {
4169 			data[2] = up_count * devpriv->clock_ns;
4170 			data[4] = down_count * devpriv->clock_ns;
4171 			return -EAGAIN;
4172 		}
4173 		ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4174 			       NI_M_CAL_PWM_LOW_TIME(down_count),
4175 			  NI_M_CAL_PWM_REG);
4176 		devpriv->pwm_up_count = up_count;
4177 		devpriv->pwm_down_count = down_count;
4178 		return 5;
4179 	case INSN_CONFIG_GET_PWM_OUTPUT:
4180 		return ni_get_pwm_config(dev, data);
4181 	default:
4182 		return -EINVAL;
4183 	}
4184 	return 0;
4185 }
4186 
ni_6143_pwm_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4187 static int ni_6143_pwm_config(struct comedi_device *dev,
4188 			      struct comedi_subdevice *s,
4189 			      struct comedi_insn *insn,
4190 			      unsigned int *data)
4191 {
4192 	struct ni_private *devpriv = dev->private;
4193 	unsigned int up_count, down_count;
4194 
4195 	switch (data[0]) {
4196 	case INSN_CONFIG_PWM_OUTPUT:
4197 		switch (data[1]) {
4198 		case CMDF_ROUND_NEAREST:
4199 			up_count = DIV_ROUND_CLOSEST(data[2],
4200 						     devpriv->clock_ns);
4201 			break;
4202 		case CMDF_ROUND_DOWN:
4203 			up_count = data[2] / devpriv->clock_ns;
4204 			break;
4205 		case CMDF_ROUND_UP:
4206 			up_count =
4207 			    DIV_ROUND_UP(data[2], devpriv->clock_ns);
4208 			break;
4209 		default:
4210 			return -EINVAL;
4211 		}
4212 		switch (data[3]) {
4213 		case CMDF_ROUND_NEAREST:
4214 			down_count = DIV_ROUND_CLOSEST(data[4],
4215 						       devpriv->clock_ns);
4216 			break;
4217 		case CMDF_ROUND_DOWN:
4218 			down_count = data[4] / devpriv->clock_ns;
4219 			break;
4220 		case CMDF_ROUND_UP:
4221 			down_count =
4222 			    DIV_ROUND_UP(data[4], devpriv->clock_ns);
4223 			break;
4224 		default:
4225 			return -EINVAL;
4226 		}
4227 		if (up_count * devpriv->clock_ns != data[2] ||
4228 		    down_count * devpriv->clock_ns != data[4]) {
4229 			data[2] = up_count * devpriv->clock_ns;
4230 			data[4] = down_count * devpriv->clock_ns;
4231 			return -EAGAIN;
4232 		}
4233 		ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4234 		devpriv->pwm_up_count = up_count;
4235 		ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4236 		devpriv->pwm_down_count = down_count;
4237 		return 5;
4238 	case INSN_CONFIG_GET_PWM_OUTPUT:
4239 		return ni_get_pwm_config(dev, data);
4240 	default:
4241 		return -EINVAL;
4242 	}
4243 	return 0;
4244 }
4245 
pack_mb88341(int addr,int val,int * bitstring)4246 static int pack_mb88341(int addr, int val, int *bitstring)
4247 {
4248 	/*
4249 	 * Fujitsu MB 88341
4250 	 * Note that address bits are reversed.  Thanks to
4251 	 * Ingo Keen for noticing this.
4252 	 *
4253 	 * Note also that the 88341 expects address values from
4254 	 * 1-12, whereas we use channel numbers 0-11.  The NI
4255 	 * docs use 1-12, also, so be careful here.
4256 	 */
4257 	addr++;
4258 	*bitstring = ((addr & 0x1) << 11) |
4259 	    ((addr & 0x2) << 9) |
4260 	    ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4261 	return 12;
4262 }
4263 
pack_dac8800(int addr,int val,int * bitstring)4264 static int pack_dac8800(int addr, int val, int *bitstring)
4265 {
4266 	*bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4267 	return 11;
4268 }
4269 
pack_dac8043(int addr,int val,int * bitstring)4270 static int pack_dac8043(int addr, int val, int *bitstring)
4271 {
4272 	*bitstring = val & 0xfff;
4273 	return 12;
4274 }
4275 
pack_ad8522(int addr,int val,int * bitstring)4276 static int pack_ad8522(int addr, int val, int *bitstring)
4277 {
4278 	*bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4279 	return 16;
4280 }
4281 
pack_ad8804(int addr,int val,int * bitstring)4282 static int pack_ad8804(int addr, int val, int *bitstring)
4283 {
4284 	*bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4285 	return 12;
4286 }
4287 
pack_ad8842(int addr,int val,int * bitstring)4288 static int pack_ad8842(int addr, int val, int *bitstring)
4289 {
4290 	*bitstring = ((addr + 1) << 8) | (val & 0xff);
4291 	return 12;
4292 }
4293 
4294 struct caldac_struct {
4295 	int n_chans;
4296 	int n_bits;
4297 	int (*packbits)(int address, int value, int *bitstring);
4298 };
4299 
4300 static struct caldac_struct caldacs[] = {
4301 	[mb88341] = {12, 8, pack_mb88341},
4302 	[dac8800] = {8, 8, pack_dac8800},
4303 	[dac8043] = {1, 12, pack_dac8043},
4304 	[ad8522] = {2, 12, pack_ad8522},
4305 	[ad8804] = {12, 8, pack_ad8804},
4306 	[ad8842] = {8, 8, pack_ad8842},
4307 	[ad8804_debug] = {16, 8, pack_ad8804},
4308 };
4309 
ni_write_caldac(struct comedi_device * dev,int addr,int val)4310 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4311 {
4312 	const struct ni_board_struct *board = dev->board_ptr;
4313 	struct ni_private *devpriv = dev->private;
4314 	unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4315 	unsigned int cmd;
4316 	int i;
4317 	int type;
4318 
4319 	if (devpriv->caldacs[addr] == val)
4320 		return;
4321 	devpriv->caldacs[addr] = val;
4322 
4323 	for (i = 0; i < 3; i++) {
4324 		type = board->caldac[i];
4325 		if (type == caldac_none)
4326 			break;
4327 		if (addr < caldacs[type].n_chans) {
4328 			bits = caldacs[type].packbits(addr, val, &bitstring);
4329 			loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4330 			break;
4331 		}
4332 		addr -= caldacs[type].n_chans;
4333 	}
4334 
4335 	/* bits will be 0 if there is no caldac for the given addr */
4336 	if (bits == 0)
4337 		return;
4338 
4339 	for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4340 		cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4341 		ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4342 		udelay(1);
4343 		ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4344 		udelay(1);
4345 	}
4346 	ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4347 	udelay(1);
4348 	ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4349 }
4350 
ni_calib_insn_write(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4351 static int ni_calib_insn_write(struct comedi_device *dev,
4352 			       struct comedi_subdevice *s,
4353 			       struct comedi_insn *insn,
4354 			       unsigned int *data)
4355 {
4356 	ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4357 
4358 	return 1;
4359 }
4360 
ni_calib_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4361 static int ni_calib_insn_read(struct comedi_device *dev,
4362 			      struct comedi_subdevice *s,
4363 			      struct comedi_insn *insn,
4364 			      unsigned int *data)
4365 {
4366 	struct ni_private *devpriv = dev->private;
4367 
4368 	data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4369 
4370 	return 1;
4371 }
4372 
caldac_setup(struct comedi_device * dev,struct comedi_subdevice * s)4373 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4374 {
4375 	const struct ni_board_struct *board = dev->board_ptr;
4376 	struct ni_private *devpriv = dev->private;
4377 	int i, j;
4378 	int n_dacs;
4379 	int n_chans = 0;
4380 	int n_bits;
4381 	int diffbits = 0;
4382 	int type;
4383 	int chan;
4384 
4385 	type = board->caldac[0];
4386 	if (type == caldac_none)
4387 		return;
4388 	n_bits = caldacs[type].n_bits;
4389 	for (i = 0; i < 3; i++) {
4390 		type = board->caldac[i];
4391 		if (type == caldac_none)
4392 			break;
4393 		if (caldacs[type].n_bits != n_bits)
4394 			diffbits = 1;
4395 		n_chans += caldacs[type].n_chans;
4396 	}
4397 	n_dacs = i;
4398 	s->n_chan = n_chans;
4399 
4400 	if (diffbits) {
4401 		unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4402 
4403 		if (n_chans > MAX_N_CALDACS)
4404 			dev_err(dev->class_dev,
4405 				"BUG! MAX_N_CALDACS too small\n");
4406 		s->maxdata_list = maxdata_list;
4407 		chan = 0;
4408 		for (i = 0; i < n_dacs; i++) {
4409 			type = board->caldac[i];
4410 			for (j = 0; j < caldacs[type].n_chans; j++) {
4411 				maxdata_list[chan] =
4412 				    (1 << caldacs[type].n_bits) - 1;
4413 				chan++;
4414 			}
4415 		}
4416 
4417 		for (chan = 0; chan < s->n_chan; chan++)
4418 			ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4419 	} else {
4420 		type = board->caldac[0];
4421 		s->maxdata = (1 << caldacs[type].n_bits) - 1;
4422 
4423 		for (chan = 0; chan < s->n_chan; chan++)
4424 			ni_write_caldac(dev, i, s->maxdata / 2);
4425 	}
4426 }
4427 
ni_read_eeprom(struct comedi_device * dev,int addr)4428 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4429 {
4430 	unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4431 	int bit;
4432 	int bitstring;
4433 
4434 	bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4435 	ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4436 	for (bit = 0x8000; bit; bit >>= 1) {
4437 		if (bit & bitstring)
4438 			cmd |= NI_E_SERIAL_CMD_SDATA;
4439 		else
4440 			cmd &= ~NI_E_SERIAL_CMD_SDATA;
4441 
4442 		ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4443 		ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4444 	}
4445 	cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4446 	bitstring = 0;
4447 	for (bit = 0x80; bit; bit >>= 1) {
4448 		ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4449 		ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4450 		if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4451 			bitstring |= bit;
4452 	}
4453 	ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4454 
4455 	return bitstring;
4456 }
4457 
ni_eeprom_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4458 static int ni_eeprom_insn_read(struct comedi_device *dev,
4459 			       struct comedi_subdevice *s,
4460 			       struct comedi_insn *insn,
4461 			       unsigned int *data)
4462 {
4463 	data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4464 
4465 	return 1;
4466 }
4467 
ni_m_series_eeprom_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4468 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4469 					struct comedi_subdevice *s,
4470 					struct comedi_insn *insn,
4471 					unsigned int *data)
4472 {
4473 	struct ni_private *devpriv = dev->private;
4474 
4475 	data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4476 
4477 	return 1;
4478 }
4479 
ni_old_get_pfi_routing(struct comedi_device * dev,unsigned int chan)4480 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4481 					   unsigned int chan)
4482 {
4483 	/*  pre-m-series boards have fixed signals on pfi pins */
4484 	switch (chan) {
4485 	case 0:
4486 		return NI_PFI_OUTPUT_AI_START1;
4487 	case 1:
4488 		return NI_PFI_OUTPUT_AI_START2;
4489 	case 2:
4490 		return NI_PFI_OUTPUT_AI_CONVERT;
4491 	case 3:
4492 		return NI_PFI_OUTPUT_G_SRC1;
4493 	case 4:
4494 		return NI_PFI_OUTPUT_G_GATE1;
4495 	case 5:
4496 		return NI_PFI_OUTPUT_AO_UPDATE_N;
4497 	case 6:
4498 		return NI_PFI_OUTPUT_AO_START1;
4499 	case 7:
4500 		return NI_PFI_OUTPUT_AI_START_PULSE;
4501 	case 8:
4502 		return NI_PFI_OUTPUT_G_SRC0;
4503 	case 9:
4504 		return NI_PFI_OUTPUT_G_GATE0;
4505 	default:
4506 		dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4507 		break;
4508 	}
4509 	return 0;
4510 }
4511 
ni_old_set_pfi_routing(struct comedi_device * dev,unsigned int chan,unsigned int source)4512 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4513 				  unsigned int chan, unsigned int source)
4514 {
4515 	/*  pre-m-series boards have fixed signals on pfi pins */
4516 	if (source != ni_old_get_pfi_routing(dev, chan))
4517 		return -EINVAL;
4518 	return 2;
4519 }
4520 
ni_m_series_get_pfi_routing(struct comedi_device * dev,unsigned int chan)4521 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4522 						unsigned int chan)
4523 {
4524 	struct ni_private *devpriv = dev->private;
4525 	const unsigned int array_offset = chan / 3;
4526 
4527 	return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4528 				devpriv->pfi_output_select_reg[array_offset]);
4529 }
4530 
ni_m_series_set_pfi_routing(struct comedi_device * dev,unsigned int chan,unsigned int source)4531 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4532 				       unsigned int chan, unsigned int source)
4533 {
4534 	struct ni_private *devpriv = dev->private;
4535 	unsigned int index = chan / 3;
4536 	unsigned short val = devpriv->pfi_output_select_reg[index];
4537 
4538 	if ((source & 0x1f) != source)
4539 		return -EINVAL;
4540 
4541 	val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4542 	val |= NI_M_PFI_OUT_SEL(chan, source);
4543 	ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4544 	devpriv->pfi_output_select_reg[index] = val;
4545 
4546 	return 2;
4547 }
4548 
ni_get_pfi_routing(struct comedi_device * dev,unsigned int chan)4549 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4550 				       unsigned int chan)
4551 {
4552 	struct ni_private *devpriv = dev->private;
4553 
4554 	return (devpriv->is_m_series)
4555 			? ni_m_series_get_pfi_routing(dev, chan)
4556 			: ni_old_get_pfi_routing(dev, chan);
4557 }
4558 
ni_set_pfi_routing(struct comedi_device * dev,unsigned int chan,unsigned int source)4559 static int ni_set_pfi_routing(struct comedi_device *dev,
4560 			      unsigned int chan, unsigned int source)
4561 {
4562 	struct ni_private *devpriv = dev->private;
4563 
4564 	return (devpriv->is_m_series)
4565 			? ni_m_series_set_pfi_routing(dev, chan, source)
4566 			: ni_old_set_pfi_routing(dev, chan, source);
4567 }
4568 
ni_config_filter(struct comedi_device * dev,unsigned int pfi_channel,enum ni_pfi_filter_select filter)4569 static int ni_config_filter(struct comedi_device *dev,
4570 			    unsigned int pfi_channel,
4571 			    enum ni_pfi_filter_select filter)
4572 {
4573 	struct ni_private *devpriv = dev->private;
4574 	unsigned int bits;
4575 
4576 	if (!devpriv->is_m_series)
4577 		return -ENOTSUPP;
4578 
4579 	bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4580 	bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4581 	bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4582 	ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4583 	return 0;
4584 }
4585 
ni_pfi_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4586 static int ni_pfi_insn_config(struct comedi_device *dev,
4587 			      struct comedi_subdevice *s,
4588 			      struct comedi_insn *insn,
4589 			      unsigned int *data)
4590 {
4591 	struct ni_private *devpriv = dev->private;
4592 	unsigned int chan;
4593 
4594 	if (insn->n < 1)
4595 		return -EINVAL;
4596 
4597 	chan = CR_CHAN(insn->chanspec);
4598 
4599 	switch (data[0]) {
4600 	case COMEDI_OUTPUT:
4601 		ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4602 		break;
4603 	case COMEDI_INPUT:
4604 		ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4605 		break;
4606 	case INSN_CONFIG_DIO_QUERY:
4607 		data[1] =
4608 		    (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4609 		    COMEDI_OUTPUT : COMEDI_INPUT;
4610 		return 0;
4611 	case INSN_CONFIG_SET_ROUTING:
4612 		return ni_set_pfi_routing(dev, chan, data[1]);
4613 	case INSN_CONFIG_GET_ROUTING:
4614 		data[1] = ni_get_pfi_routing(dev, chan);
4615 		break;
4616 	case INSN_CONFIG_FILTER:
4617 		return ni_config_filter(dev, chan, data[1]);
4618 	default:
4619 		return -EINVAL;
4620 	}
4621 	return 0;
4622 }
4623 
ni_pfi_insn_bits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4624 static int ni_pfi_insn_bits(struct comedi_device *dev,
4625 			    struct comedi_subdevice *s,
4626 			    struct comedi_insn *insn,
4627 			    unsigned int *data)
4628 {
4629 	struct ni_private *devpriv = dev->private;
4630 
4631 	if (!devpriv->is_m_series)
4632 		return -ENOTSUPP;
4633 
4634 	if (comedi_dio_update_state(s, data))
4635 		ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4636 
4637 	data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4638 
4639 	return insn->n;
4640 }
4641 
cs5529_wait_for_idle(struct comedi_device * dev)4642 static int cs5529_wait_for_idle(struct comedi_device *dev)
4643 {
4644 	unsigned short status;
4645 	const int timeout = HZ;
4646 	int i;
4647 
4648 	for (i = 0; i < timeout; i++) {
4649 		status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4650 		if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4651 			break;
4652 		set_current_state(TASK_INTERRUPTIBLE);
4653 		if (schedule_timeout(1))
4654 			return -EIO;
4655 	}
4656 	if (i == timeout) {
4657 		dev_err(dev->class_dev, "timeout\n");
4658 		return -ETIME;
4659 	}
4660 	return 0;
4661 }
4662 
cs5529_command(struct comedi_device * dev,unsigned short value)4663 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4664 {
4665 	static const int timeout = 100;
4666 	int i;
4667 
4668 	ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4669 	/* give time for command to start being serially clocked into cs5529.
4670 	 * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4671 	 * set before we exit this function.
4672 	 */
4673 	for (i = 0; i < timeout; i++) {
4674 		if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4675 		    NI67XX_CAL_STATUS_BUSY)
4676 			break;
4677 		udelay(1);
4678 	}
4679 	if (i == timeout)
4680 		dev_err(dev->class_dev,
4681 			"possible problem - never saw adc go busy?\n");
4682 }
4683 
cs5529_do_conversion(struct comedi_device * dev,unsigned short * data)4684 static int cs5529_do_conversion(struct comedi_device *dev,
4685 				unsigned short *data)
4686 {
4687 	int retval;
4688 	unsigned short status;
4689 
4690 	cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4691 	retval = cs5529_wait_for_idle(dev);
4692 	if (retval) {
4693 		dev_err(dev->class_dev,
4694 			"timeout or signal in %s()\n", __func__);
4695 		return -ETIME;
4696 	}
4697 	status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4698 	if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4699 		dev_err(dev->class_dev,
4700 			"cs5529 conversion error, status CSS_OSC_DETECT\n");
4701 		return -EIO;
4702 	}
4703 	if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4704 		dev_err(dev->class_dev,
4705 			"cs5529 conversion error, overrange (ignoring)\n");
4706 	}
4707 	if (data) {
4708 		*data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4709 		/* cs5529 returns 16 bit signed data in bipolar mode */
4710 		*data ^= (1 << 15);
4711 	}
4712 	return 0;
4713 }
4714 
cs5529_ai_insn_read(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)4715 static int cs5529_ai_insn_read(struct comedi_device *dev,
4716 			       struct comedi_subdevice *s,
4717 			       struct comedi_insn *insn,
4718 			       unsigned int *data)
4719 {
4720 	int n, retval;
4721 	unsigned short sample;
4722 	unsigned int channel_select;
4723 	const unsigned int INTERNAL_REF = 0x1000;
4724 
4725 	/*
4726 	 * Set calibration adc source.  Docs lie, reference select bits 8 to 11
4727 	 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4728 	 * 13 causes the adc input to go overrange (maybe reads external
4729 	 * reference?)
4730 	 */
4731 	if (insn->chanspec & CR_ALT_SOURCE)
4732 		channel_select = INTERNAL_REF;
4733 	else
4734 		channel_select = CR_CHAN(insn->chanspec);
4735 	ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4736 
4737 	for (n = 0; n < insn->n; n++) {
4738 		retval = cs5529_do_conversion(dev, &sample);
4739 		if (retval < 0)
4740 			return retval;
4741 		data[n] = sample;
4742 	}
4743 	return insn->n;
4744 }
4745 
cs5529_config_write(struct comedi_device * dev,unsigned int value,unsigned int reg_select_bits)4746 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4747 				unsigned int reg_select_bits)
4748 {
4749 	ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4750 	ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4751 	reg_select_bits &= CS5529_CMD_REG_MASK;
4752 	cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4753 	if (cs5529_wait_for_idle(dev))
4754 		dev_err(dev->class_dev,
4755 			"timeout or signal in %s\n", __func__);
4756 }
4757 
init_cs5529(struct comedi_device * dev)4758 static int init_cs5529(struct comedi_device *dev)
4759 {
4760 	unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4761 				   CS5529_CFG_WORD_RATE_2180;
4762 
4763 #if 1
4764 	/* do self-calibration */
4765 	cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4766 			    CS5529_CFG_REG);
4767 	/* need to force a conversion for calibration to run */
4768 	cs5529_do_conversion(dev, NULL);
4769 #else
4770 	/* force gain calibration to 1 */
4771 	cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4772 	cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4773 			    CS5529_CFG_REG);
4774 	if (cs5529_wait_for_idle(dev))
4775 		dev_err(dev->class_dev,
4776 			"timeout or signal in %s\n", __func__);
4777 #endif
4778 	return 0;
4779 }
4780 
4781 /*
4782  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4783  * given an arbitrary frequency input clock.
4784  */
ni_mseries_get_pll_parameters(unsigned int reference_period_ns,unsigned int * freq_divider,unsigned int * freq_multiplier,unsigned int * actual_period_ns)4785 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4786 					 unsigned int *freq_divider,
4787 					 unsigned int *freq_multiplier,
4788 					 unsigned int *actual_period_ns)
4789 {
4790 	unsigned int div;
4791 	unsigned int best_div = 1;
4792 	unsigned int mult;
4793 	unsigned int best_mult = 1;
4794 	static const unsigned int pico_per_nano = 1000;
4795 	const unsigned int reference_picosec = reference_period_ns *
4796 					       pico_per_nano;
4797 	/*
4798 	 * m-series wants the phased-locked loop to output 80MHz, which is
4799 	 * divided by 4 to 20 MHz for most timing clocks
4800 	 */
4801 	static const unsigned int target_picosec = 12500;
4802 	int best_period_picosec = 0;
4803 
4804 	for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4805 		for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4806 			unsigned int new_period_ps =
4807 			    (reference_picosec * div) / mult;
4808 			if (abs(new_period_ps - target_picosec) <
4809 			    abs(best_period_picosec - target_picosec)) {
4810 				best_period_picosec = new_period_ps;
4811 				best_div = div;
4812 				best_mult = mult;
4813 			}
4814 		}
4815 	}
4816 	if (best_period_picosec == 0)
4817 		return -EIO;
4818 
4819 	*freq_divider = best_div;
4820 	*freq_multiplier = best_mult;
4821 	/* return the actual period (* fudge factor for 80 to 20 MHz) */
4822 	*actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4823 					      pico_per_nano);
4824 	return 0;
4825 }
4826 
ni_mseries_set_pll_master_clock(struct comedi_device * dev,unsigned int source,unsigned int period_ns)4827 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4828 					   unsigned int source,
4829 					   unsigned int period_ns)
4830 {
4831 	struct ni_private *devpriv = dev->private;
4832 	static const unsigned int min_period_ns = 50;
4833 	static const unsigned int max_period_ns = 1000;
4834 	static const unsigned int timeout = 1000;
4835 	unsigned int pll_control_bits;
4836 	unsigned int freq_divider;
4837 	unsigned int freq_multiplier;
4838 	unsigned int rtsi;
4839 	unsigned int i;
4840 	int retval;
4841 
4842 	if (source == NI_MIO_PLL_PXI10_CLOCK)
4843 		period_ns = 100;
4844 	/*
4845 	 * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4846 	 * range so we'll use that.
4847 	 */
4848 	if (period_ns < min_period_ns || period_ns > max_period_ns) {
4849 		dev_err(dev->class_dev,
4850 			"%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4851 			__func__, min_period_ns, max_period_ns);
4852 		return -EINVAL;
4853 	}
4854 	devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4855 	ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4856 		      NISTC_RTSI_TRIG_DIR_REG);
4857 	pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4858 	devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4859 				    NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4860 	devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4861 	switch (source) {
4862 	case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4863 		devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4864 		break;
4865 	case NI_MIO_PLL_PXI10_CLOCK:
4866 		/* pxi clock is 10MHz */
4867 		devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4868 		break;
4869 	default:
4870 		for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4871 			if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4872 				devpriv->clock_and_fout2 |=
4873 					NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4874 				break;
4875 			}
4876 		}
4877 		if (rtsi > NI_M_MAX_RTSI_CHAN)
4878 			return -EINVAL;
4879 		break;
4880 	}
4881 	retval = ni_mseries_get_pll_parameters(period_ns,
4882 					       &freq_divider,
4883 					       &freq_multiplier,
4884 					       &devpriv->clock_ns);
4885 	if (retval < 0) {
4886 		dev_err(dev->class_dev,
4887 			"bug, failed to find pll parameters\n");
4888 		return retval;
4889 	}
4890 
4891 	ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4892 	pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4893 			    NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4894 
4895 	ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4896 	devpriv->clock_source = source;
4897 	/* it takes a few hundred microseconds for PLL to lock */
4898 	for (i = 0; i < timeout; ++i) {
4899 		if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4900 			break;
4901 		udelay(1);
4902 	}
4903 	if (i == timeout) {
4904 		dev_err(dev->class_dev,
4905 			"%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4906 			__func__, source, period_ns);
4907 		return -ETIMEDOUT;
4908 	}
4909 	return 3;
4910 }
4911 
ni_set_master_clock(struct comedi_device * dev,unsigned int source,unsigned int period_ns)4912 static int ni_set_master_clock(struct comedi_device *dev,
4913 			       unsigned int source, unsigned int period_ns)
4914 {
4915 	struct ni_private *devpriv = dev->private;
4916 
4917 	if (source == NI_MIO_INTERNAL_CLOCK) {
4918 		devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4919 		ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4920 			      NISTC_RTSI_TRIG_DIR_REG);
4921 		devpriv->clock_ns = TIMEBASE_1_NS;
4922 		if (devpriv->is_m_series) {
4923 			devpriv->clock_and_fout2 &=
4924 			    ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4925 			      NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4926 			ni_writew(dev, devpriv->clock_and_fout2,
4927 				  NI_M_CLK_FOUT2_REG);
4928 			ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4929 		}
4930 		devpriv->clock_source = source;
4931 	} else {
4932 		if (devpriv->is_m_series) {
4933 			return ni_mseries_set_pll_master_clock(dev, source,
4934 							       period_ns);
4935 		} else {
4936 			if (source == NI_MIO_RTSI_CLOCK) {
4937 				devpriv->rtsi_trig_direction_reg |=
4938 				    NISTC_RTSI_TRIG_USE_CLK;
4939 				ni_stc_writew(dev,
4940 					      devpriv->rtsi_trig_direction_reg,
4941 					      NISTC_RTSI_TRIG_DIR_REG);
4942 				if (period_ns == 0) {
4943 					dev_err(dev->class_dev,
4944 						"we don't handle an unspecified clock period correctly yet, returning error\n");
4945 					return -EINVAL;
4946 				}
4947 				devpriv->clock_ns = period_ns;
4948 				devpriv->clock_source = source;
4949 			} else {
4950 				return -EINVAL;
4951 			}
4952 		}
4953 	}
4954 	return 3;
4955 }
4956 
ni_valid_rtsi_output_source(struct comedi_device * dev,unsigned int chan,unsigned int source)4957 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4958 				       unsigned int chan, unsigned int source)
4959 {
4960 	struct ni_private *devpriv = dev->private;
4961 
4962 	if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4963 		if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4964 			if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4965 				return 1;
4966 
4967 			dev_err(dev->class_dev,
4968 				"%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4969 				__func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4970 			return 0;
4971 		}
4972 		return 0;
4973 	}
4974 	switch (source) {
4975 	case NI_RTSI_OUTPUT_ADR_START1:
4976 	case NI_RTSI_OUTPUT_ADR_START2:
4977 	case NI_RTSI_OUTPUT_SCLKG:
4978 	case NI_RTSI_OUTPUT_DACUPDN:
4979 	case NI_RTSI_OUTPUT_DA_START1:
4980 	case NI_RTSI_OUTPUT_G_SRC0:
4981 	case NI_RTSI_OUTPUT_G_GATE0:
4982 	case NI_RTSI_OUTPUT_RGOUT0:
4983 	case NI_RTSI_OUTPUT_RTSI_BRD_0:
4984 		return 1;
4985 	case NI_RTSI_OUTPUT_RTSI_OSC:
4986 		return (devpriv->is_m_series) ? 1 : 0;
4987 	default:
4988 		return 0;
4989 	}
4990 }
4991 
ni_set_rtsi_routing(struct comedi_device * dev,unsigned int chan,unsigned int src)4992 static int ni_set_rtsi_routing(struct comedi_device *dev,
4993 			       unsigned int chan, unsigned int src)
4994 {
4995 	struct ni_private *devpriv = dev->private;
4996 
4997 	if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
4998 		return -EINVAL;
4999 	if (chan < 4) {
5000 		devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5001 		devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5002 		ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5003 			      NISTC_RTSI_TRIGA_OUT_REG);
5004 	} else if (chan < 8) {
5005 		devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5006 		devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5007 		ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5008 			      NISTC_RTSI_TRIGB_OUT_REG);
5009 	}
5010 	return 2;
5011 }
5012 
ni_get_rtsi_routing(struct comedi_device * dev,unsigned int chan)5013 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
5014 					unsigned int chan)
5015 {
5016 	struct ni_private *devpriv = dev->private;
5017 
5018 	if (chan < 4) {
5019 		return NISTC_RTSI_TRIG_TO_SRC(chan,
5020 					      devpriv->rtsi_trig_a_output_reg);
5021 	} else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5022 		return NISTC_RTSI_TRIG_TO_SRC(chan,
5023 					      devpriv->rtsi_trig_b_output_reg);
5024 	} else {
5025 		if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
5026 			return NI_RTSI_OUTPUT_RTSI_OSC;
5027 		dev_err(dev->class_dev, "bug! should never get here?\n");
5028 		return 0;
5029 	}
5030 }
5031 
ni_rtsi_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)5032 static int ni_rtsi_insn_config(struct comedi_device *dev,
5033 			       struct comedi_subdevice *s,
5034 			       struct comedi_insn *insn,
5035 			       unsigned int *data)
5036 {
5037 	struct ni_private *devpriv = dev->private;
5038 	unsigned int chan = CR_CHAN(insn->chanspec);
5039 	unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5040 
5041 	switch (data[0]) {
5042 	case INSN_CONFIG_DIO_OUTPUT:
5043 		if (chan < max_chan) {
5044 			devpriv->rtsi_trig_direction_reg |=
5045 			    NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5046 		} else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5047 			devpriv->rtsi_trig_direction_reg |=
5048 			    NISTC_RTSI_TRIG_DRV_CLK;
5049 		}
5050 		ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5051 			      NISTC_RTSI_TRIG_DIR_REG);
5052 		break;
5053 	case INSN_CONFIG_DIO_INPUT:
5054 		if (chan < max_chan) {
5055 			devpriv->rtsi_trig_direction_reg &=
5056 			    ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5057 		} else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5058 			devpriv->rtsi_trig_direction_reg &=
5059 			    ~NISTC_RTSI_TRIG_DRV_CLK;
5060 		}
5061 		ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5062 			      NISTC_RTSI_TRIG_DIR_REG);
5063 		break;
5064 	case INSN_CONFIG_DIO_QUERY:
5065 		if (chan < max_chan) {
5066 			data[1] =
5067 			    (devpriv->rtsi_trig_direction_reg &
5068 			     NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5069 				? INSN_CONFIG_DIO_OUTPUT
5070 				: INSN_CONFIG_DIO_INPUT;
5071 		} else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5072 			data[1] = (devpriv->rtsi_trig_direction_reg &
5073 				   NISTC_RTSI_TRIG_DRV_CLK)
5074 				  ? INSN_CONFIG_DIO_OUTPUT
5075 				  : INSN_CONFIG_DIO_INPUT;
5076 		}
5077 		return 2;
5078 	case INSN_CONFIG_SET_CLOCK_SRC:
5079 		return ni_set_master_clock(dev, data[1], data[2]);
5080 	case INSN_CONFIG_GET_CLOCK_SRC:
5081 		data[1] = devpriv->clock_source;
5082 		data[2] = devpriv->clock_ns;
5083 		return 3;
5084 	case INSN_CONFIG_SET_ROUTING:
5085 		return ni_set_rtsi_routing(dev, chan, data[1]);
5086 	case INSN_CONFIG_GET_ROUTING:
5087 		data[1] = ni_get_rtsi_routing(dev, chan);
5088 		return 2;
5089 	default:
5090 		return -EINVAL;
5091 	}
5092 	return 1;
5093 }
5094 
ni_rtsi_insn_bits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)5095 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5096 			     struct comedi_subdevice *s,
5097 			     struct comedi_insn *insn,
5098 			     unsigned int *data)
5099 {
5100 	data[1] = 0;
5101 
5102 	return insn->n;
5103 }
5104 
ni_rtsi_init(struct comedi_device * dev)5105 static void ni_rtsi_init(struct comedi_device *dev)
5106 {
5107 	struct ni_private *devpriv = dev->private;
5108 
5109 	/*  Initialises the RTSI bus signal switch to a default state */
5110 
5111 	/*
5112 	 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5113 	 * to have no effect, at least on pxi-6281, which always uses
5114 	 * 20MHz rtsi clock frequency
5115 	 */
5116 	devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5117 	/*  Set clock mode to internal */
5118 	if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5119 		dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5120 	/*  default internal lines routing to RTSI bus lines */
5121 	devpriv->rtsi_trig_a_output_reg =
5122 	    NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
5123 	    NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
5124 	    NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
5125 	    NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
5126 	ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5127 		      NISTC_RTSI_TRIGA_OUT_REG);
5128 	devpriv->rtsi_trig_b_output_reg =
5129 	    NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
5130 	    NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
5131 	    NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
5132 	if (devpriv->is_m_series)
5133 		devpriv->rtsi_trig_b_output_reg |=
5134 		    NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
5135 	ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5136 		      NISTC_RTSI_TRIGB_OUT_REG);
5137 
5138 	/*
5139 	 * Sets the source and direction of the 4 on board lines
5140 	 * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
5141 	 */
5142 }
5143 
5144 #ifdef PCIDMA
ni_gpct_cmd(struct comedi_device * dev,struct comedi_subdevice * s)5145 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5146 {
5147 	struct ni_gpct *counter = s->private;
5148 	int retval;
5149 
5150 	retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5151 					      COMEDI_INPUT);
5152 	if (retval) {
5153 		dev_err(dev->class_dev,
5154 			"no dma channel available for use by counter\n");
5155 		return retval;
5156 	}
5157 	ni_tio_acknowledge(counter);
5158 	ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5159 
5160 	return ni_tio_cmd(dev, s);
5161 }
5162 
ni_gpct_cancel(struct comedi_device * dev,struct comedi_subdevice * s)5163 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5164 {
5165 	struct ni_gpct *counter = s->private;
5166 	int retval;
5167 
5168 	retval = ni_tio_cancel(counter);
5169 	ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5170 	ni_release_gpct_mite_channel(dev, counter->counter_index);
5171 	return retval;
5172 }
5173 #endif
5174 
ni_E_interrupt(int irq,void * d)5175 static irqreturn_t ni_E_interrupt(int irq, void *d)
5176 {
5177 	struct comedi_device *dev = d;
5178 	struct comedi_subdevice *s_ai = dev->read_subdev;
5179 	struct comedi_subdevice *s_ao = dev->write_subdev;
5180 	unsigned short a_status;
5181 	unsigned short b_status;
5182 	unsigned long flags;
5183 #ifdef PCIDMA
5184 	struct ni_private *devpriv = dev->private;
5185 #endif
5186 
5187 	if (!dev->attached)
5188 		return IRQ_NONE;
5189 	smp_mb();		/* make sure dev->attached is checked */
5190 
5191 	/*  lock to avoid race with comedi_poll */
5192 	spin_lock_irqsave(&dev->spinlock, flags);
5193 	a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5194 	b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5195 #ifdef PCIDMA
5196 	if (devpriv->mite) {
5197 		unsigned long flags_too;
5198 
5199 		spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5200 		if (s_ai && devpriv->ai_mite_chan)
5201 			mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5202 		if (s_ao && devpriv->ao_mite_chan)
5203 			mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5204 		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5205 	}
5206 #endif
5207 	ack_a_interrupt(dev, a_status);
5208 	ack_b_interrupt(dev, b_status);
5209 	if (s_ai) {
5210 		if (a_status & NISTC_AI_STATUS1_INTA)
5211 			handle_a_interrupt(dev, s_ai, a_status);
5212 		/* handle any interrupt or dma events */
5213 		comedi_handle_events(dev, s_ai);
5214 	}
5215 	if (s_ao) {
5216 		if (b_status & NISTC_AO_STATUS1_INTB)
5217 			handle_b_interrupt(dev, s_ao, b_status);
5218 		/* handle any interrupt or dma events */
5219 		comedi_handle_events(dev, s_ao);
5220 	}
5221 	handle_gpct_interrupt(dev, 0);
5222 	handle_gpct_interrupt(dev, 1);
5223 #ifdef PCIDMA
5224 	if (devpriv->is_m_series)
5225 		handle_cdio_interrupt(dev);
5226 #endif
5227 
5228 	spin_unlock_irqrestore(&dev->spinlock, flags);
5229 	return IRQ_HANDLED;
5230 }
5231 
ni_alloc_private(struct comedi_device * dev)5232 static int ni_alloc_private(struct comedi_device *dev)
5233 {
5234 	struct ni_private *devpriv;
5235 
5236 	devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5237 	if (!devpriv)
5238 		return -ENOMEM;
5239 
5240 	spin_lock_init(&devpriv->window_lock);
5241 	spin_lock_init(&devpriv->soft_reg_copy_lock);
5242 	spin_lock_init(&devpriv->mite_channel_lock);
5243 
5244 	return 0;
5245 }
5246 
ni_E_init(struct comedi_device * dev,unsigned int interrupt_pin,unsigned int irq_polarity)5247 static int ni_E_init(struct comedi_device *dev,
5248 		     unsigned int interrupt_pin, unsigned int irq_polarity)
5249 {
5250 	const struct ni_board_struct *board = dev->board_ptr;
5251 	struct ni_private *devpriv = dev->private;
5252 	struct comedi_subdevice *s;
5253 	int ret;
5254 	int i;
5255 
5256 	if (board->n_aochan > MAX_N_AO_CHAN) {
5257 		dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5258 		return -EINVAL;
5259 	}
5260 
5261 	/* initialize clock dividers */
5262 	devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5263 				  NISTC_CLK_FOUT_SLOW_TIMEBASE |
5264 				  NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5265 				  NISTC_CLK_FOUT_TO_BOARD;
5266 	if (!devpriv->is_6xxx) {
5267 		/* BEAM is this needed for PCI-6143 ?? */
5268 		devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5269 					    NISTC_CLK_FOUT_AO_OUT_DIV2);
5270 	}
5271 	ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5272 
5273 	ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5274 	if (ret)
5275 		return ret;
5276 
5277 	/* Analog Input subdevice */
5278 	s = &dev->subdevices[NI_AI_SUBDEV];
5279 	if (board->n_adchan) {
5280 		s->type		= COMEDI_SUBD_AI;
5281 		s->subdev_flags	= SDF_READABLE | SDF_DIFF | SDF_DITHER;
5282 		if (!devpriv->is_611x)
5283 			s->subdev_flags	|= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5284 		if (board->ai_maxdata > 0xffff)
5285 			s->subdev_flags	|= SDF_LSAMPL;
5286 		if (devpriv->is_m_series)
5287 			s->subdev_flags	|= SDF_SOFT_CALIBRATED;
5288 		s->n_chan	= board->n_adchan;
5289 		s->maxdata	= board->ai_maxdata;
5290 		s->range_table	= ni_range_lkup[board->gainlkup];
5291 		s->insn_read	= ni_ai_insn_read;
5292 		s->insn_config	= ni_ai_insn_config;
5293 		if (dev->irq) {
5294 			dev->read_subdev = s;
5295 			s->subdev_flags	|= SDF_CMD_READ;
5296 			s->len_chanlist	= 512;
5297 			s->do_cmdtest	= ni_ai_cmdtest;
5298 			s->do_cmd	= ni_ai_cmd;
5299 			s->cancel	= ni_ai_reset;
5300 			s->poll		= ni_ai_poll;
5301 			s->munge	= ni_ai_munge;
5302 
5303 			if (devpriv->mite)
5304 				s->async_dma_dir = DMA_FROM_DEVICE;
5305 		}
5306 
5307 		/* reset the analog input configuration */
5308 		ni_ai_reset(dev, s);
5309 	} else {
5310 		s->type		= COMEDI_SUBD_UNUSED;
5311 	}
5312 
5313 	/* Analog Output subdevice */
5314 	s = &dev->subdevices[NI_AO_SUBDEV];
5315 	if (board->n_aochan) {
5316 		s->type		= COMEDI_SUBD_AO;
5317 		s->subdev_flags	= SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5318 		if (devpriv->is_m_series)
5319 			s->subdev_flags	|= SDF_SOFT_CALIBRATED;
5320 		s->n_chan	= board->n_aochan;
5321 		s->maxdata	= board->ao_maxdata;
5322 		s->range_table	= board->ao_range_table;
5323 		s->insn_config	= ni_ao_insn_config;
5324 		s->insn_write	= ni_ao_insn_write;
5325 
5326 		ret = comedi_alloc_subdev_readback(s);
5327 		if (ret)
5328 			return ret;
5329 
5330 		/*
5331 		 * Along with the IRQ we need either a FIFO or DMA for
5332 		 * async command support.
5333 		 */
5334 		if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5335 			dev->write_subdev = s;
5336 			s->subdev_flags	|= SDF_CMD_WRITE;
5337 			s->len_chanlist	= s->n_chan;
5338 			s->do_cmdtest	= ni_ao_cmdtest;
5339 			s->do_cmd	= ni_ao_cmd;
5340 			s->cancel	= ni_ao_reset;
5341 			if (!devpriv->is_m_series)
5342 				s->munge	= ni_ao_munge;
5343 
5344 			if (devpriv->mite)
5345 				s->async_dma_dir = DMA_TO_DEVICE;
5346 		}
5347 
5348 		if (devpriv->is_67xx)
5349 			init_ao_67xx(dev, s);
5350 
5351 		/* reset the analog output configuration */
5352 		ni_ao_reset(dev, s);
5353 	} else {
5354 		s->type		= COMEDI_SUBD_UNUSED;
5355 	}
5356 
5357 	/* Digital I/O subdevice */
5358 	s = &dev->subdevices[NI_DIO_SUBDEV];
5359 	s->type		= COMEDI_SUBD_DIO;
5360 	s->subdev_flags	= SDF_WRITABLE | SDF_READABLE;
5361 	s->n_chan	= board->has_32dio_chan ? 32 : 8;
5362 	s->maxdata	= 1;
5363 	s->range_table	= &range_digital;
5364 	if (devpriv->is_m_series) {
5365 #ifdef PCIDMA
5366 		s->subdev_flags	|= SDF_LSAMPL;
5367 		s->insn_bits	= ni_m_series_dio_insn_bits;
5368 		s->insn_config	= ni_m_series_dio_insn_config;
5369 		if (dev->irq) {
5370 			s->subdev_flags	|= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5371 			s->len_chanlist	= s->n_chan;
5372 			s->do_cmdtest	= ni_cdio_cmdtest;
5373 			s->do_cmd	= ni_cdio_cmd;
5374 			s->cancel	= ni_cdio_cancel;
5375 
5376 			/* M-series boards use DMA */
5377 			s->async_dma_dir = DMA_BIDIRECTIONAL;
5378 		}
5379 
5380 		/* reset DIO and set all channels to inputs */
5381 		ni_writel(dev, NI_M_CDO_CMD_RESET |
5382 			       NI_M_CDI_CMD_RESET,
5383 			  NI_M_CDIO_CMD_REG);
5384 		ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5385 #endif /* PCIDMA */
5386 	} else {
5387 		s->insn_bits	= ni_dio_insn_bits;
5388 		s->insn_config	= ni_dio_insn_config;
5389 
5390 		/* set all channels to inputs */
5391 		devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5392 		ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5393 	}
5394 
5395 	/* 8255 device */
5396 	s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5397 	if (board->has_8255) {
5398 		ret = subdev_8255_init(dev, s, ni_8255_callback,
5399 				       NI_E_8255_BASE);
5400 		if (ret)
5401 			return ret;
5402 	} else {
5403 		s->type = COMEDI_SUBD_UNUSED;
5404 	}
5405 
5406 	/* formerly general purpose counter/timer device, but no longer used */
5407 	s = &dev->subdevices[NI_UNUSED_SUBDEV];
5408 	s->type = COMEDI_SUBD_UNUSED;
5409 
5410 	/* Calibration subdevice */
5411 	s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5412 	s->type		= COMEDI_SUBD_CALIB;
5413 	s->subdev_flags	= SDF_INTERNAL;
5414 	s->n_chan	= 1;
5415 	s->maxdata	= 0;
5416 	if (devpriv->is_m_series) {
5417 		/* internal PWM output used for AI nonlinearity calibration */
5418 		s->insn_config	= ni_m_series_pwm_config;
5419 
5420 		ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5421 	} else if (devpriv->is_6143) {
5422 		/* internal PWM output used for AI nonlinearity calibration */
5423 		s->insn_config	= ni_6143_pwm_config;
5424 	} else {
5425 		s->subdev_flags	|= SDF_WRITABLE;
5426 		s->insn_read	= ni_calib_insn_read;
5427 		s->insn_write	= ni_calib_insn_write;
5428 
5429 		/* setup the caldacs and find the real n_chan and maxdata */
5430 		caldac_setup(dev, s);
5431 	}
5432 
5433 	/* EEPROM subdevice */
5434 	s = &dev->subdevices[NI_EEPROM_SUBDEV];
5435 	s->type		= COMEDI_SUBD_MEMORY;
5436 	s->subdev_flags	= SDF_READABLE | SDF_INTERNAL;
5437 	s->maxdata	= 0xff;
5438 	if (devpriv->is_m_series) {
5439 		s->n_chan	= M_SERIES_EEPROM_SIZE;
5440 		s->insn_read	= ni_m_series_eeprom_insn_read;
5441 	} else {
5442 		s->n_chan	= 512;
5443 		s->insn_read	= ni_eeprom_insn_read;
5444 	}
5445 
5446 	/* Digital I/O (PFI) subdevice */
5447 	s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5448 	s->type		= COMEDI_SUBD_DIO;
5449 	s->maxdata	= 1;
5450 	if (devpriv->is_m_series) {
5451 		s->n_chan	= 16;
5452 		s->insn_bits	= ni_pfi_insn_bits;
5453 		s->subdev_flags	= SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5454 
5455 		ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5456 		for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5457 			ni_writew(dev, devpriv->pfi_output_select_reg[i],
5458 				  NI_M_PFI_OUT_SEL_REG(i));
5459 		}
5460 	} else {
5461 		s->n_chan	= 10;
5462 		s->subdev_flags	= SDF_INTERNAL;
5463 	}
5464 	s->insn_config	= ni_pfi_insn_config;
5465 
5466 	ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5467 
5468 	/* cs5529 calibration adc */
5469 	s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5470 	if (devpriv->is_67xx) {
5471 		s->type = COMEDI_SUBD_AI;
5472 		s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5473 		/*  one channel for each analog output channel */
5474 		s->n_chan = board->n_aochan;
5475 		s->maxdata = (1 << 16) - 1;
5476 		s->range_table = &range_unknown;	/* XXX */
5477 		s->insn_read = cs5529_ai_insn_read;
5478 		s->insn_config = NULL;
5479 		init_cs5529(dev);
5480 	} else {
5481 		s->type = COMEDI_SUBD_UNUSED;
5482 	}
5483 
5484 	/* Serial */
5485 	s = &dev->subdevices[NI_SERIAL_SUBDEV];
5486 	s->type = COMEDI_SUBD_SERIAL;
5487 	s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5488 	s->n_chan = 1;
5489 	s->maxdata = 0xff;
5490 	s->insn_config = ni_serial_insn_config;
5491 	devpriv->serial_interval_ns = 0;
5492 	devpriv->serial_hw_mode = 0;
5493 
5494 	/* RTSI */
5495 	s = &dev->subdevices[NI_RTSI_SUBDEV];
5496 	s->type = COMEDI_SUBD_DIO;
5497 	s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5498 	s->n_chan = 8;
5499 	s->maxdata = 1;
5500 	s->insn_bits = ni_rtsi_insn_bits;
5501 	s->insn_config = ni_rtsi_insn_config;
5502 	ni_rtsi_init(dev);
5503 
5504 	/* allocate and initialize the gpct counter device */
5505 	devpriv->counter_dev = ni_gpct_device_construct(dev,
5506 					ni_gpct_write_register,
5507 					ni_gpct_read_register,
5508 					(devpriv->is_m_series)
5509 						? ni_gpct_variant_m_series
5510 						: ni_gpct_variant_e_series,
5511 					NUM_GPCT);
5512 	if (!devpriv->counter_dev)
5513 		return -ENOMEM;
5514 
5515 	/* Counter (gpct) subdevices */
5516 	for (i = 0; i < NUM_GPCT; ++i) {
5517 		struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5518 
5519 		/* setup and initialize the counter */
5520 		gpct->chip_index = 0;
5521 		gpct->counter_index = i;
5522 		ni_tio_init_counter(gpct);
5523 
5524 		s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5525 		s->type		= COMEDI_SUBD_COUNTER;
5526 		s->subdev_flags	= SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5527 		s->n_chan	= 3;
5528 		s->maxdata	= (devpriv->is_m_series) ? 0xffffffff
5529 							 : 0x00ffffff;
5530 		s->insn_read	= ni_tio_insn_read;
5531 		s->insn_write	= ni_tio_insn_write;
5532 		s->insn_config	= ni_tio_insn_config;
5533 #ifdef PCIDMA
5534 		if (dev->irq && devpriv->mite) {
5535 			s->subdev_flags	|= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5536 			s->len_chanlist	= 1;
5537 			s->do_cmdtest	= ni_tio_cmdtest;
5538 			s->do_cmd	= ni_gpct_cmd;
5539 			s->cancel	= ni_gpct_cancel;
5540 
5541 			s->async_dma_dir = DMA_BIDIRECTIONAL;
5542 		}
5543 #endif
5544 		s->private	= gpct;
5545 	}
5546 
5547 	/* Frequency output subdevice */
5548 	s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5549 	s->type		= COMEDI_SUBD_COUNTER;
5550 	s->subdev_flags	= SDF_READABLE | SDF_WRITABLE;
5551 	s->n_chan	= 1;
5552 	s->maxdata	= 0xf;
5553 	s->insn_read	= ni_freq_out_insn_read;
5554 	s->insn_write	= ni_freq_out_insn_write;
5555 	s->insn_config	= ni_freq_out_insn_config;
5556 
5557 	if (dev->irq) {
5558 		ni_stc_writew(dev,
5559 			      (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5560 			      (NISTC_INT_CTRL_3PIN_INT & 0) |
5561 			      NISTC_INT_CTRL_INTA_ENA |
5562 			      NISTC_INT_CTRL_INTB_ENA |
5563 			      NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5564 			      NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5565 			      NISTC_INT_CTRL_REG);
5566 	}
5567 
5568 	/* DMA setup */
5569 	ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5570 	ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5571 
5572 	if (devpriv->is_6xxx) {
5573 		ni_writeb(dev, 0, NI611X_MAGIC_REG);
5574 	} else if (devpriv->is_m_series) {
5575 		int channel;
5576 
5577 		for (channel = 0; channel < board->n_aochan; ++channel) {
5578 			ni_writeb(dev, 0xf,
5579 				  NI_M_AO_WAVEFORM_ORDER_REG(channel));
5580 			ni_writeb(dev, 0x0,
5581 				  NI_M_AO_REF_ATTENUATION_REG(channel));
5582 		}
5583 		ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5584 	}
5585 
5586 	return 0;
5587 }
5588 
mio_common_detach(struct comedi_device * dev)5589 static void mio_common_detach(struct comedi_device *dev)
5590 {
5591 	struct ni_private *devpriv = dev->private;
5592 
5593 	if (devpriv)
5594 		ni_gpct_device_destroy(devpriv->counter_dev);
5595 }
5596