1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * nicstar.c
4 *
5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
6 *
7 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
8 * It was taken from the frle-0.22 device driver.
9 * As the file doesn't have a copyright notice, in the file
10 * nicstarmac.copyright I put the copyright notice from the
11 * frle-0.22 device driver.
12 * Some code is based on the nicstar driver by M. Welsh.
13 *
14 * Author: Rui Prior (rprior@inescn.pt)
15 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
16 *
17 *
18 * (C) INESC 1999
19 */
20
21 /*
22 * IMPORTANT INFORMATION
23 *
24 * There are currently three types of spinlocks:
25 *
26 * 1 - Per card interrupt spinlock (to protect structures and such)
27 * 2 - Per SCQ scq spinlock
28 * 3 - Per card resource spinlock (to access registers, etc.)
29 *
30 * These must NEVER be grabbed in reverse order.
31 *
32 */
33
34 /* Header files */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/skbuff.h>
39 #include <linux/atmdev.h>
40 #include <linux/atm.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/types.h>
44 #include <linux/string.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/sched.h>
48 #include <linux/timer.h>
49 #include <linux/interrupt.h>
50 #include <linux/bitops.h>
51 #include <linux/slab.h>
52 #include <linux/idr.h>
53 #include <asm/io.h>
54 #include <linux/uaccess.h>
55 #include <linux/atomic.h>
56 #include <linux/etherdevice.h>
57 #include "nicstar.h"
58 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
59 #include "suni.h"
60 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
61 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
62 #include "idt77105.h"
63 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
64
65 /* Additional code */
66
67 #include "nicstarmac.c"
68
69 /* Configurable parameters */
70
71 #undef PHY_LOOPBACK
72 #undef TX_DEBUG
73 #undef RX_DEBUG
74 #undef GENERAL_DEBUG
75 #undef EXTRA_DEBUG
76
77 /* Do not touch these */
78
79 #ifdef TX_DEBUG
80 #define TXPRINTK(args...) printk(args)
81 #else
82 #define TXPRINTK(args...)
83 #endif /* TX_DEBUG */
84
85 #ifdef RX_DEBUG
86 #define RXPRINTK(args...) printk(args)
87 #else
88 #define RXPRINTK(args...)
89 #endif /* RX_DEBUG */
90
91 #ifdef GENERAL_DEBUG
92 #define PRINTK(args...) printk(args)
93 #else
94 #define PRINTK(args...) do {} while (0)
95 #endif /* GENERAL_DEBUG */
96
97 #ifdef EXTRA_DEBUG
98 #define XPRINTK(args...) printk(args)
99 #else
100 #define XPRINTK(args...)
101 #endif /* EXTRA_DEBUG */
102
103 /* Macros */
104
105 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
106
107 #define NS_DELAY mdelay(1)
108
109 #define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
110
111 #ifndef ATM_SKB
112 #define ATM_SKB(s) (&(s)->atm)
113 #endif
114
115 #define scq_virt_to_bus(scq, p) \
116 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
117
118 /* Function declarations */
119
120 static u32 ns_read_sram(ns_dev * card, u32 sram_address);
121 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
122 int count);
123 static int ns_init_card(int i, struct pci_dev *pcidev);
124 static void ns_init_card_error(ns_dev * card, int error);
125 static scq_info *get_scq(ns_dev *card, int size, u32 scd);
126 static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
127 static void push_rxbufs(ns_dev *, struct sk_buff *);
128 static irqreturn_t ns_irq_handler(int irq, void *dev_id);
129 static int ns_open(struct atm_vcc *vcc);
130 static void ns_close(struct atm_vcc *vcc);
131 static void fill_tst(ns_dev * card, int n, vc_map * vc);
132 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
133 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
134 struct sk_buff *skb);
135 static void process_tsq(ns_dev * card);
136 static void drain_scq(ns_dev * card, scq_info * scq, int pos);
137 static void process_rsq(ns_dev * card);
138 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
139 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
140 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
141 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
142 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
143 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
144 static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
145 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
146 #ifdef EXTRA_DEBUG
147 static void which_list(ns_dev * card, struct sk_buff *skb);
148 #endif
149 static void ns_poll(struct timer_list *unused);
150 static void ns_phy_put(struct atm_dev *dev, unsigned char value,
151 unsigned long addr);
152 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
153
154 /* Global variables */
155
156 static struct ns_dev *cards[NS_MAX_CARDS];
157 static unsigned num_cards;
158 static const struct atmdev_ops atm_ops = {
159 .open = ns_open,
160 .close = ns_close,
161 .ioctl = ns_ioctl,
162 .send = ns_send,
163 .phy_put = ns_phy_put,
164 .phy_get = ns_phy_get,
165 .proc_read = ns_proc_read,
166 .owner = THIS_MODULE,
167 };
168
169 static struct timer_list ns_timer;
170 static char *mac[NS_MAX_CARDS];
171 module_param_array(mac, charp, NULL, 0);
172 MODULE_LICENSE("GPL");
173
174 /* Functions */
175
nicstar_init_one(struct pci_dev * pcidev,const struct pci_device_id * ent)176 static int nicstar_init_one(struct pci_dev *pcidev,
177 const struct pci_device_id *ent)
178 {
179 static int index = -1;
180 unsigned int error;
181
182 index++;
183 cards[index] = NULL;
184
185 error = ns_init_card(index, pcidev);
186 if (error) {
187 cards[index--] = NULL; /* don't increment index */
188 goto err_out;
189 }
190
191 return 0;
192 err_out:
193 return -ENODEV;
194 }
195
nicstar_remove_one(struct pci_dev * pcidev)196 static void nicstar_remove_one(struct pci_dev *pcidev)
197 {
198 int i, j;
199 ns_dev *card = pci_get_drvdata(pcidev);
200 struct sk_buff *hb;
201 struct sk_buff *iovb;
202 struct sk_buff *lb;
203 struct sk_buff *sb;
204
205 i = card->index;
206
207 if (cards[i] == NULL)
208 return;
209
210 if (card->atmdev->phy && card->atmdev->phy->stop)
211 card->atmdev->phy->stop(card->atmdev);
212
213 /* Stop everything */
214 writel(0x00000000, card->membase + CFG);
215
216 /* De-register device */
217 atm_dev_deregister(card->atmdev);
218
219 /* Disable PCI device */
220 pci_disable_device(pcidev);
221
222 /* Free up resources */
223 j = 0;
224 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
225 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
226 dev_kfree_skb_any(hb);
227 j++;
228 }
229 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
230 j = 0;
231 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
232 card->iovpool.count);
233 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
234 dev_kfree_skb_any(iovb);
235 j++;
236 }
237 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
238 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
239 dev_kfree_skb_any(lb);
240 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
241 dev_kfree_skb_any(sb);
242 free_scq(card, card->scq0, NULL);
243 for (j = 0; j < NS_FRSCD_NUM; j++) {
244 if (card->scd2vc[j] != NULL)
245 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
246 }
247 idr_destroy(&card->idr);
248 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
249 card->rsq.org, card->rsq.dma);
250 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
251 card->tsq.org, card->tsq.dma);
252 free_irq(card->pcidev->irq, card);
253 iounmap(card->membase);
254 kfree(card);
255 }
256
257 static const struct pci_device_id nicstar_pci_tbl[] = {
258 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
259 {0,} /* terminate list */
260 };
261
262 MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
263
264 static struct pci_driver nicstar_driver = {
265 .name = "nicstar",
266 .id_table = nicstar_pci_tbl,
267 .probe = nicstar_init_one,
268 .remove = nicstar_remove_one,
269 };
270
nicstar_init(void)271 static int __init nicstar_init(void)
272 {
273 unsigned error = 0; /* Initialized to remove compile warning */
274
275 XPRINTK("nicstar: nicstar_init() called.\n");
276
277 error = pci_register_driver(&nicstar_driver);
278
279 TXPRINTK("nicstar: TX debug enabled.\n");
280 RXPRINTK("nicstar: RX debug enabled.\n");
281 PRINTK("nicstar: General debug enabled.\n");
282 #ifdef PHY_LOOPBACK
283 printk("nicstar: using PHY loopback.\n");
284 #endif /* PHY_LOOPBACK */
285 XPRINTK("nicstar: nicstar_init() returned.\n");
286
287 if (!error) {
288 timer_setup(&ns_timer, ns_poll, 0);
289 ns_timer.expires = jiffies + NS_POLL_PERIOD;
290 add_timer(&ns_timer);
291 }
292
293 return error;
294 }
295
nicstar_cleanup(void)296 static void __exit nicstar_cleanup(void)
297 {
298 XPRINTK("nicstar: nicstar_cleanup() called.\n");
299
300 del_timer(&ns_timer);
301
302 pci_unregister_driver(&nicstar_driver);
303
304 XPRINTK("nicstar: nicstar_cleanup() returned.\n");
305 }
306
ns_read_sram(ns_dev * card,u32 sram_address)307 static u32 ns_read_sram(ns_dev * card, u32 sram_address)
308 {
309 unsigned long flags;
310 u32 data;
311 sram_address <<= 2;
312 sram_address &= 0x0007FFFC; /* address must be dword aligned */
313 sram_address |= 0x50000000; /* SRAM read command */
314 spin_lock_irqsave(&card->res_lock, flags);
315 while (CMD_BUSY(card)) ;
316 writel(sram_address, card->membase + CMD);
317 while (CMD_BUSY(card)) ;
318 data = readl(card->membase + DR0);
319 spin_unlock_irqrestore(&card->res_lock, flags);
320 return data;
321 }
322
ns_write_sram(ns_dev * card,u32 sram_address,u32 * value,int count)323 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
324 int count)
325 {
326 unsigned long flags;
327 int i, c;
328 count--; /* count range now is 0..3 instead of 1..4 */
329 c = count;
330 c <<= 2; /* to use increments of 4 */
331 spin_lock_irqsave(&card->res_lock, flags);
332 while (CMD_BUSY(card)) ;
333 for (i = 0; i <= c; i += 4)
334 writel(*(value++), card->membase + i);
335 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
336 so card->membase + DR0 == card->membase */
337 sram_address <<= 2;
338 sram_address &= 0x0007FFFC;
339 sram_address |= (0x40000000 | count);
340 writel(sram_address, card->membase + CMD);
341 spin_unlock_irqrestore(&card->res_lock, flags);
342 }
343
ns_init_card(int i,struct pci_dev * pcidev)344 static int ns_init_card(int i, struct pci_dev *pcidev)
345 {
346 int j;
347 struct ns_dev *card = NULL;
348 unsigned char pci_latency;
349 unsigned error;
350 u32 data;
351 u32 u32d[4];
352 u32 ns_cfg_rctsize;
353 int bcount;
354 unsigned long membase;
355
356 error = 0;
357
358 if (pci_enable_device(pcidev)) {
359 printk("nicstar%d: can't enable PCI device\n", i);
360 error = 2;
361 ns_init_card_error(card, error);
362 return error;
363 }
364 if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) {
365 printk(KERN_WARNING
366 "nicstar%d: No suitable DMA available.\n", i);
367 error = 2;
368 ns_init_card_error(card, error);
369 return error;
370 }
371
372 card = kmalloc(sizeof(*card), GFP_KERNEL);
373 if (!card) {
374 printk
375 ("nicstar%d: can't allocate memory for device structure.\n",
376 i);
377 error = 2;
378 ns_init_card_error(card, error);
379 return error;
380 }
381 cards[i] = card;
382 spin_lock_init(&card->int_lock);
383 spin_lock_init(&card->res_lock);
384
385 pci_set_drvdata(pcidev, card);
386
387 card->index = i;
388 card->atmdev = NULL;
389 card->pcidev = pcidev;
390 membase = pci_resource_start(pcidev, 1);
391 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
392 if (!card->membase) {
393 printk("nicstar%d: can't ioremap() membase.\n", i);
394 error = 3;
395 ns_init_card_error(card, error);
396 return error;
397 }
398 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
399
400 pci_set_master(pcidev);
401
402 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
403 printk("nicstar%d: can't read PCI latency timer.\n", i);
404 error = 6;
405 ns_init_card_error(card, error);
406 return error;
407 }
408 #ifdef NS_PCI_LATENCY
409 if (pci_latency < NS_PCI_LATENCY) {
410 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
411 NS_PCI_LATENCY);
412 for (j = 1; j < 4; j++) {
413 if (pci_write_config_byte
414 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
415 break;
416 }
417 if (j == 4) {
418 printk
419 ("nicstar%d: can't set PCI latency timer to %d.\n",
420 i, NS_PCI_LATENCY);
421 error = 7;
422 ns_init_card_error(card, error);
423 return error;
424 }
425 }
426 #endif /* NS_PCI_LATENCY */
427
428 /* Clear timer overflow */
429 data = readl(card->membase + STAT);
430 if (data & NS_STAT_TMROF)
431 writel(NS_STAT_TMROF, card->membase + STAT);
432
433 /* Software reset */
434 writel(NS_CFG_SWRST, card->membase + CFG);
435 NS_DELAY;
436 writel(0x00000000, card->membase + CFG);
437
438 /* PHY reset */
439 writel(0x00000008, card->membase + GP);
440 NS_DELAY;
441 writel(0x00000001, card->membase + GP);
442 NS_DELAY;
443 while (CMD_BUSY(card)) ;
444 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
445 NS_DELAY;
446
447 /* Detect PHY type */
448 while (CMD_BUSY(card)) ;
449 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
450 while (CMD_BUSY(card)) ;
451 data = readl(card->membase + DR0);
452 switch (data) {
453 case 0x00000009:
454 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
455 card->max_pcr = ATM_25_PCR;
456 while (CMD_BUSY(card)) ;
457 writel(0x00000008, card->membase + DR0);
458 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
459 /* Clear an eventual pending interrupt */
460 writel(NS_STAT_SFBQF, card->membase + STAT);
461 #ifdef PHY_LOOPBACK
462 while (CMD_BUSY(card)) ;
463 writel(0x00000022, card->membase + DR0);
464 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
465 #endif /* PHY_LOOPBACK */
466 break;
467 case 0x00000030:
468 case 0x00000031:
469 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
470 card->max_pcr = ATM_OC3_PCR;
471 #ifdef PHY_LOOPBACK
472 while (CMD_BUSY(card)) ;
473 writel(0x00000002, card->membase + DR0);
474 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
475 #endif /* PHY_LOOPBACK */
476 break;
477 default:
478 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
479 error = 8;
480 ns_init_card_error(card, error);
481 return error;
482 }
483 writel(0x00000000, card->membase + GP);
484
485 /* Determine SRAM size */
486 data = 0x76543210;
487 ns_write_sram(card, 0x1C003, &data, 1);
488 data = 0x89ABCDEF;
489 ns_write_sram(card, 0x14003, &data, 1);
490 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
491 ns_read_sram(card, 0x1C003) == 0x76543210)
492 card->sram_size = 128;
493 else
494 card->sram_size = 32;
495 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
496
497 card->rct_size = NS_MAX_RCTSIZE;
498
499 #if (NS_MAX_RCTSIZE == 4096)
500 if (card->sram_size == 128)
501 printk
502 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
503 i);
504 #elif (NS_MAX_RCTSIZE == 16384)
505 if (card->sram_size == 32) {
506 printk
507 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
508 i);
509 card->rct_size = 4096;
510 }
511 #else
512 #error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
513 #endif
514
515 card->vpibits = NS_VPIBITS;
516 if (card->rct_size == 4096)
517 card->vcibits = 12 - NS_VPIBITS;
518 else /* card->rct_size == 16384 */
519 card->vcibits = 14 - NS_VPIBITS;
520
521 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
522 if (mac[i] == NULL)
523 nicstar_init_eprom(card->membase);
524
525 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
526 writel(0x00000000, card->membase + VPM);
527
528 /* Initialize TSQ */
529 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
530 NS_TSQSIZE + NS_TSQ_ALIGNMENT,
531 &card->tsq.dma, GFP_KERNEL);
532 if (card->tsq.org == NULL) {
533 printk("nicstar%d: can't allocate TSQ.\n", i);
534 error = 10;
535 ns_init_card_error(card, error);
536 return error;
537 }
538 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
539 card->tsq.next = card->tsq.base;
540 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
541 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
542 ns_tsi_init(card->tsq.base + j);
543 writel(0x00000000, card->membase + TSQH);
544 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
545 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
546
547 /* Initialize RSQ */
548 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev,
549 NS_RSQSIZE + NS_RSQ_ALIGNMENT,
550 &card->rsq.dma, GFP_KERNEL);
551 if (card->rsq.org == NULL) {
552 printk("nicstar%d: can't allocate RSQ.\n", i);
553 error = 11;
554 ns_init_card_error(card, error);
555 return error;
556 }
557 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
558 card->rsq.next = card->rsq.base;
559 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
560 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
561 ns_rsqe_init(card->rsq.base + j);
562 writel(0x00000000, card->membase + RSQH);
563 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
564 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
565
566 /* Initialize SCQ0, the only VBR SCQ used */
567 card->scq1 = NULL;
568 card->scq2 = NULL;
569 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
570 if (card->scq0 == NULL) {
571 printk("nicstar%d: can't get SCQ0.\n", i);
572 error = 12;
573 ns_init_card_error(card, error);
574 return error;
575 }
576 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
577 u32d[1] = (u32) 0x00000000;
578 u32d[2] = (u32) 0xffffffff;
579 u32d[3] = (u32) 0x00000000;
580 ns_write_sram(card, NS_VRSCD0, u32d, 4);
581 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
582 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
583 card->scq0->scd = NS_VRSCD0;
584 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
585
586 /* Initialize TSTs */
587 card->tst_addr = NS_TST0;
588 card->tst_free_entries = NS_TST_NUM_ENTRIES;
589 data = NS_TST_OPCODE_VARIABLE;
590 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
591 ns_write_sram(card, NS_TST0 + j, &data, 1);
592 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
593 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
594 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
595 ns_write_sram(card, NS_TST1 + j, &data, 1);
596 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
597 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
598 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
599 card->tste2vc[j] = NULL;
600 writel(NS_TST0 << 2, card->membase + TSTB);
601
602 /* Initialize RCT. AAL type is set on opening the VC. */
603 #ifdef RCQ_SUPPORT
604 u32d[0] = NS_RCTE_RAWCELLINTEN;
605 #else
606 u32d[0] = 0x00000000;
607 #endif /* RCQ_SUPPORT */
608 u32d[1] = 0x00000000;
609 u32d[2] = 0x00000000;
610 u32d[3] = 0xFFFFFFFF;
611 for (j = 0; j < card->rct_size; j++)
612 ns_write_sram(card, j * 4, u32d, 4);
613
614 memset(card->vcmap, 0, sizeof(card->vcmap));
615
616 for (j = 0; j < NS_FRSCD_NUM; j++)
617 card->scd2vc[j] = NULL;
618
619 /* Initialize buffer levels */
620 card->sbnr.min = MIN_SB;
621 card->sbnr.init = NUM_SB;
622 card->sbnr.max = MAX_SB;
623 card->lbnr.min = MIN_LB;
624 card->lbnr.init = NUM_LB;
625 card->lbnr.max = MAX_LB;
626 card->iovnr.min = MIN_IOVB;
627 card->iovnr.init = NUM_IOVB;
628 card->iovnr.max = MAX_IOVB;
629 card->hbnr.min = MIN_HB;
630 card->hbnr.init = NUM_HB;
631 card->hbnr.max = MAX_HB;
632
633 card->sm_handle = NULL;
634 card->sm_addr = 0x00000000;
635 card->lg_handle = NULL;
636 card->lg_addr = 0x00000000;
637
638 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
639
640 idr_init(&card->idr);
641
642 /* Pre-allocate some huge buffers */
643 skb_queue_head_init(&card->hbpool.queue);
644 card->hbpool.count = 0;
645 for (j = 0; j < NUM_HB; j++) {
646 struct sk_buff *hb;
647 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
648 if (hb == NULL) {
649 printk
650 ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
651 i, j, NUM_HB);
652 error = 13;
653 ns_init_card_error(card, error);
654 return error;
655 }
656 NS_PRV_BUFTYPE(hb) = BUF_NONE;
657 skb_queue_tail(&card->hbpool.queue, hb);
658 card->hbpool.count++;
659 }
660
661 /* Allocate large buffers */
662 skb_queue_head_init(&card->lbpool.queue);
663 card->lbpool.count = 0; /* Not used */
664 for (j = 0; j < NUM_LB; j++) {
665 struct sk_buff *lb;
666 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
667 if (lb == NULL) {
668 printk
669 ("nicstar%d: can't allocate %dth of %d large buffers.\n",
670 i, j, NUM_LB);
671 error = 14;
672 ns_init_card_error(card, error);
673 return error;
674 }
675 NS_PRV_BUFTYPE(lb) = BUF_LG;
676 skb_queue_tail(&card->lbpool.queue, lb);
677 skb_reserve(lb, NS_SMBUFSIZE);
678 push_rxbufs(card, lb);
679 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
680 if (j == 1) {
681 card->rcbuf = lb;
682 card->rawcell = (struct ns_rcqe *) lb->data;
683 card->rawch = NS_PRV_DMA(lb);
684 }
685 }
686 /* Test for strange behaviour which leads to crashes */
687 if ((bcount =
688 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
689 printk
690 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
691 i, j, bcount);
692 error = 14;
693 ns_init_card_error(card, error);
694 return error;
695 }
696
697 /* Allocate small buffers */
698 skb_queue_head_init(&card->sbpool.queue);
699 card->sbpool.count = 0; /* Not used */
700 for (j = 0; j < NUM_SB; j++) {
701 struct sk_buff *sb;
702 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
703 if (sb == NULL) {
704 printk
705 ("nicstar%d: can't allocate %dth of %d small buffers.\n",
706 i, j, NUM_SB);
707 error = 15;
708 ns_init_card_error(card, error);
709 return error;
710 }
711 NS_PRV_BUFTYPE(sb) = BUF_SM;
712 skb_queue_tail(&card->sbpool.queue, sb);
713 skb_reserve(sb, NS_AAL0_HEADER);
714 push_rxbufs(card, sb);
715 }
716 /* Test for strange behaviour which leads to crashes */
717 if ((bcount =
718 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
719 printk
720 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
721 i, j, bcount);
722 error = 15;
723 ns_init_card_error(card, error);
724 return error;
725 }
726
727 /* Allocate iovec buffers */
728 skb_queue_head_init(&card->iovpool.queue);
729 card->iovpool.count = 0;
730 for (j = 0; j < NUM_IOVB; j++) {
731 struct sk_buff *iovb;
732 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
733 if (iovb == NULL) {
734 printk
735 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
736 i, j, NUM_IOVB);
737 error = 16;
738 ns_init_card_error(card, error);
739 return error;
740 }
741 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
742 skb_queue_tail(&card->iovpool.queue, iovb);
743 card->iovpool.count++;
744 }
745
746 /* Configure NICStAR */
747 if (card->rct_size == 4096)
748 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
749 else /* (card->rct_size == 16384) */
750 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
751
752 card->efbie = 1;
753
754 card->intcnt = 0;
755 if (request_irq
756 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
757 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
758 error = 9;
759 ns_init_card_error(card, error);
760 return error;
761 }
762
763 /* Register device */
764 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
765 -1, NULL);
766 if (card->atmdev == NULL) {
767 printk("nicstar%d: can't register device.\n", i);
768 error = 17;
769 ns_init_card_error(card, error);
770 return error;
771 }
772
773 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
774 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
775 card->atmdev->esi, 6);
776 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
777 nicstar_read_eprom(card->membase,
778 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
779 card->atmdev->esi, 6);
780 }
781 }
782
783 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
784
785 card->atmdev->dev_data = card;
786 card->atmdev->ci_range.vpi_bits = card->vpibits;
787 card->atmdev->ci_range.vci_bits = card->vcibits;
788 card->atmdev->link_rate = card->max_pcr;
789 card->atmdev->phy = NULL;
790
791 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
792 if (card->max_pcr == ATM_OC3_PCR)
793 suni_init(card->atmdev);
794 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
795
796 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
797 if (card->max_pcr == ATM_25_PCR)
798 idt77105_init(card->atmdev);
799 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
800
801 if (card->atmdev->phy && card->atmdev->phy->start)
802 card->atmdev->phy->start(card->atmdev);
803
804 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
805 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
806 NS_CFG_PHYIE, card->membase + CFG);
807
808 num_cards++;
809
810 return error;
811 }
812
ns_init_card_error(ns_dev * card,int error)813 static void ns_init_card_error(ns_dev *card, int error)
814 {
815 if (error >= 17) {
816 writel(0x00000000, card->membase + CFG);
817 }
818 if (error >= 16) {
819 struct sk_buff *iovb;
820 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
821 dev_kfree_skb_any(iovb);
822 }
823 if (error >= 15) {
824 struct sk_buff *sb;
825 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
826 dev_kfree_skb_any(sb);
827 free_scq(card, card->scq0, NULL);
828 }
829 if (error >= 14) {
830 struct sk_buff *lb;
831 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
832 dev_kfree_skb_any(lb);
833 }
834 if (error >= 13) {
835 struct sk_buff *hb;
836 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
837 dev_kfree_skb_any(hb);
838 }
839 if (error >= 12) {
840 kfree(card->rsq.org);
841 }
842 if (error >= 11) {
843 kfree(card->tsq.org);
844 }
845 if (error >= 10) {
846 free_irq(card->pcidev->irq, card);
847 }
848 if (error >= 4) {
849 iounmap(card->membase);
850 }
851 if (error >= 3) {
852 pci_disable_device(card->pcidev);
853 kfree(card);
854 }
855 }
856
get_scq(ns_dev * card,int size,u32 scd)857 static scq_info *get_scq(ns_dev *card, int size, u32 scd)
858 {
859 scq_info *scq;
860 int i;
861
862 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
863 return NULL;
864
865 scq = kmalloc(sizeof(*scq), GFP_KERNEL);
866 if (!scq)
867 return NULL;
868 scq->org = dma_alloc_coherent(&card->pcidev->dev,
869 2 * size, &scq->dma, GFP_KERNEL);
870 if (!scq->org) {
871 kfree(scq);
872 return NULL;
873 }
874 scq->skb = kmalloc_array(size / NS_SCQE_SIZE,
875 sizeof(*scq->skb),
876 GFP_KERNEL);
877 if (!scq->skb) {
878 dma_free_coherent(&card->pcidev->dev,
879 2 * size, scq->org, scq->dma);
880 kfree(scq);
881 return NULL;
882 }
883 scq->num_entries = size / NS_SCQE_SIZE;
884 scq->base = PTR_ALIGN(scq->org, size);
885 scq->next = scq->base;
886 scq->last = scq->base + (scq->num_entries - 1);
887 scq->tail = scq->last;
888 scq->scd = scd;
889 scq->num_entries = size / NS_SCQE_SIZE;
890 scq->tbd_count = 0;
891 init_waitqueue_head(&scq->scqfull_waitq);
892 scq->full = 0;
893 spin_lock_init(&scq->lock);
894
895 for (i = 0; i < scq->num_entries; i++)
896 scq->skb[i] = NULL;
897
898 return scq;
899 }
900
901 /* For variable rate SCQ vcc must be NULL */
free_scq(ns_dev * card,scq_info * scq,struct atm_vcc * vcc)902 static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
903 {
904 int i;
905
906 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
907 for (i = 0; i < scq->num_entries; i++) {
908 if (scq->skb[i] != NULL) {
909 vcc = ATM_SKB(scq->skb[i])->vcc;
910 if (vcc->pop != NULL)
911 vcc->pop(vcc, scq->skb[i]);
912 else
913 dev_kfree_skb_any(scq->skb[i]);
914 }
915 } else { /* vcc must be != NULL */
916
917 if (vcc == NULL) {
918 printk
919 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
920 for (i = 0; i < scq->num_entries; i++)
921 dev_kfree_skb_any(scq->skb[i]);
922 } else
923 for (i = 0; i < scq->num_entries; i++) {
924 if (scq->skb[i] != NULL) {
925 if (vcc->pop != NULL)
926 vcc->pop(vcc, scq->skb[i]);
927 else
928 dev_kfree_skb_any(scq->skb[i]);
929 }
930 }
931 }
932 kfree(scq->skb);
933 dma_free_coherent(&card->pcidev->dev,
934 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
935 VBR_SCQSIZE : CBR_SCQSIZE),
936 scq->org, scq->dma);
937 kfree(scq);
938 }
939
940 /* The handles passed must be pointers to the sk_buff containing the small
941 or large buffer(s) cast to u32. */
push_rxbufs(ns_dev * card,struct sk_buff * skb)942 static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
943 {
944 struct sk_buff *handle1, *handle2;
945 int id1, id2;
946 u32 addr1, addr2;
947 u32 stat;
948 unsigned long flags;
949
950 /* *BARF* */
951 handle2 = NULL;
952 addr2 = 0;
953 handle1 = skb;
954 addr1 = dma_map_single(&card->pcidev->dev,
955 skb->data,
956 (NS_PRV_BUFTYPE(skb) == BUF_SM
957 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
958 DMA_TO_DEVICE);
959 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
960
961 #ifdef GENERAL_DEBUG
962 if (!addr1)
963 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
964 card->index);
965 #endif /* GENERAL_DEBUG */
966
967 stat = readl(card->membase + STAT);
968 card->sbfqc = ns_stat_sfbqc_get(stat);
969 card->lbfqc = ns_stat_lfbqc_get(stat);
970 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
971 if (!addr2) {
972 if (card->sm_addr) {
973 addr2 = card->sm_addr;
974 handle2 = card->sm_handle;
975 card->sm_addr = 0x00000000;
976 card->sm_handle = NULL;
977 } else { /* (!sm_addr) */
978
979 card->sm_addr = addr1;
980 card->sm_handle = handle1;
981 }
982 }
983 } else { /* buf_type == BUF_LG */
984
985 if (!addr2) {
986 if (card->lg_addr) {
987 addr2 = card->lg_addr;
988 handle2 = card->lg_handle;
989 card->lg_addr = 0x00000000;
990 card->lg_handle = NULL;
991 } else { /* (!lg_addr) */
992
993 card->lg_addr = addr1;
994 card->lg_handle = handle1;
995 }
996 }
997 }
998
999 if (addr2) {
1000 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
1001 if (card->sbfqc >= card->sbnr.max) {
1002 skb_unlink(handle1, &card->sbpool.queue);
1003 dev_kfree_skb_any(handle1);
1004 skb_unlink(handle2, &card->sbpool.queue);
1005 dev_kfree_skb_any(handle2);
1006 return;
1007 } else
1008 card->sbfqc += 2;
1009 } else { /* (buf_type == BUF_LG) */
1010
1011 if (card->lbfqc >= card->lbnr.max) {
1012 skb_unlink(handle1, &card->lbpool.queue);
1013 dev_kfree_skb_any(handle1);
1014 skb_unlink(handle2, &card->lbpool.queue);
1015 dev_kfree_skb_any(handle2);
1016 return;
1017 } else
1018 card->lbfqc += 2;
1019 }
1020
1021 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
1022 if (id1 < 0)
1023 goto out;
1024
1025 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
1026 if (id2 < 0)
1027 goto out;
1028
1029 spin_lock_irqsave(&card->res_lock, flags);
1030 while (CMD_BUSY(card)) ;
1031 writel(addr2, card->membase + DR3);
1032 writel(id2, card->membase + DR2);
1033 writel(addr1, card->membase + DR1);
1034 writel(id1, card->membase + DR0);
1035 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
1036 card->membase + CMD);
1037 spin_unlock_irqrestore(&card->res_lock, flags);
1038
1039 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1040 card->index,
1041 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
1042 addr1, addr2);
1043 }
1044
1045 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1046 card->lbfqc >= card->lbnr.min) {
1047 card->efbie = 1;
1048 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1049 card->membase + CFG);
1050 }
1051
1052 out:
1053 return;
1054 }
1055
ns_irq_handler(int irq,void * dev_id)1056 static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1057 {
1058 u32 stat_r;
1059 ns_dev *card;
1060 struct atm_dev *dev;
1061 unsigned long flags;
1062
1063 card = (ns_dev *) dev_id;
1064 dev = card->atmdev;
1065 card->intcnt++;
1066
1067 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1068
1069 spin_lock_irqsave(&card->int_lock, flags);
1070
1071 stat_r = readl(card->membase + STAT);
1072
1073 /* Transmit Status Indicator has been written to T. S. Queue */
1074 if (stat_r & NS_STAT_TSIF) {
1075 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1076 process_tsq(card);
1077 writel(NS_STAT_TSIF, card->membase + STAT);
1078 }
1079
1080 /* Incomplete CS-PDU has been transmitted */
1081 if (stat_r & NS_STAT_TXICP) {
1082 writel(NS_STAT_TXICP, card->membase + STAT);
1083 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1084 card->index);
1085 }
1086
1087 /* Transmit Status Queue 7/8 full */
1088 if (stat_r & NS_STAT_TSQF) {
1089 writel(NS_STAT_TSQF, card->membase + STAT);
1090 PRINTK("nicstar%d: TSQ full.\n", card->index);
1091 process_tsq(card);
1092 }
1093
1094 /* Timer overflow */
1095 if (stat_r & NS_STAT_TMROF) {
1096 writel(NS_STAT_TMROF, card->membase + STAT);
1097 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1098 }
1099
1100 /* PHY device interrupt signal active */
1101 if (stat_r & NS_STAT_PHYI) {
1102 writel(NS_STAT_PHYI, card->membase + STAT);
1103 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1104 if (dev->phy && dev->phy->interrupt) {
1105 dev->phy->interrupt(dev);
1106 }
1107 }
1108
1109 /* Small Buffer Queue is full */
1110 if (stat_r & NS_STAT_SFBQF) {
1111 writel(NS_STAT_SFBQF, card->membase + STAT);
1112 printk("nicstar%d: Small free buffer queue is full.\n",
1113 card->index);
1114 }
1115
1116 /* Large Buffer Queue is full */
1117 if (stat_r & NS_STAT_LFBQF) {
1118 writel(NS_STAT_LFBQF, card->membase + STAT);
1119 printk("nicstar%d: Large free buffer queue is full.\n",
1120 card->index);
1121 }
1122
1123 /* Receive Status Queue is full */
1124 if (stat_r & NS_STAT_RSQF) {
1125 writel(NS_STAT_RSQF, card->membase + STAT);
1126 printk("nicstar%d: RSQ full.\n", card->index);
1127 process_rsq(card);
1128 }
1129
1130 /* Complete CS-PDU received */
1131 if (stat_r & NS_STAT_EOPDU) {
1132 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1133 process_rsq(card);
1134 writel(NS_STAT_EOPDU, card->membase + STAT);
1135 }
1136
1137 /* Raw cell received */
1138 if (stat_r & NS_STAT_RAWCF) {
1139 writel(NS_STAT_RAWCF, card->membase + STAT);
1140 #ifndef RCQ_SUPPORT
1141 printk("nicstar%d: Raw cell received and no support yet...\n",
1142 card->index);
1143 #endif /* RCQ_SUPPORT */
1144 /* NOTE: the following procedure may keep a raw cell pending until the
1145 next interrupt. As this preliminary support is only meant to
1146 avoid buffer leakage, this is not an issue. */
1147 while (readl(card->membase + RAWCT) != card->rawch) {
1148
1149 if (ns_rcqe_islast(card->rawcell)) {
1150 struct sk_buff *oldbuf;
1151
1152 oldbuf = card->rcbuf;
1153 card->rcbuf = idr_find(&card->idr,
1154 ns_rcqe_nextbufhandle(card->rawcell));
1155 card->rawch = NS_PRV_DMA(card->rcbuf);
1156 card->rawcell = (struct ns_rcqe *)
1157 card->rcbuf->data;
1158 recycle_rx_buf(card, oldbuf);
1159 } else {
1160 card->rawch += NS_RCQE_SIZE;
1161 card->rawcell++;
1162 }
1163 }
1164 }
1165
1166 /* Small buffer queue is empty */
1167 if (stat_r & NS_STAT_SFBQE) {
1168 int i;
1169 struct sk_buff *sb;
1170
1171 writel(NS_STAT_SFBQE, card->membase + STAT);
1172 printk("nicstar%d: Small free buffer queue empty.\n",
1173 card->index);
1174 for (i = 0; i < card->sbnr.min; i++) {
1175 sb = dev_alloc_skb(NS_SMSKBSIZE);
1176 if (sb == NULL) {
1177 writel(readl(card->membase + CFG) &
1178 ~NS_CFG_EFBIE, card->membase + CFG);
1179 card->efbie = 0;
1180 break;
1181 }
1182 NS_PRV_BUFTYPE(sb) = BUF_SM;
1183 skb_queue_tail(&card->sbpool.queue, sb);
1184 skb_reserve(sb, NS_AAL0_HEADER);
1185 push_rxbufs(card, sb);
1186 }
1187 card->sbfqc = i;
1188 process_rsq(card);
1189 }
1190
1191 /* Large buffer queue empty */
1192 if (stat_r & NS_STAT_LFBQE) {
1193 int i;
1194 struct sk_buff *lb;
1195
1196 writel(NS_STAT_LFBQE, card->membase + STAT);
1197 printk("nicstar%d: Large free buffer queue empty.\n",
1198 card->index);
1199 for (i = 0; i < card->lbnr.min; i++) {
1200 lb = dev_alloc_skb(NS_LGSKBSIZE);
1201 if (lb == NULL) {
1202 writel(readl(card->membase + CFG) &
1203 ~NS_CFG_EFBIE, card->membase + CFG);
1204 card->efbie = 0;
1205 break;
1206 }
1207 NS_PRV_BUFTYPE(lb) = BUF_LG;
1208 skb_queue_tail(&card->lbpool.queue, lb);
1209 skb_reserve(lb, NS_SMBUFSIZE);
1210 push_rxbufs(card, lb);
1211 }
1212 card->lbfqc = i;
1213 process_rsq(card);
1214 }
1215
1216 /* Receive Status Queue is 7/8 full */
1217 if (stat_r & NS_STAT_RSQAF) {
1218 writel(NS_STAT_RSQAF, card->membase + STAT);
1219 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1220 process_rsq(card);
1221 }
1222
1223 spin_unlock_irqrestore(&card->int_lock, flags);
1224 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1225 return IRQ_HANDLED;
1226 }
1227
ns_open(struct atm_vcc * vcc)1228 static int ns_open(struct atm_vcc *vcc)
1229 {
1230 ns_dev *card;
1231 vc_map *vc;
1232 unsigned long tmpl, modl;
1233 int tcr, tcra; /* target cell rate, and absolute value */
1234 int n = 0; /* Number of entries in the TST. Initialized to remove
1235 the compiler warning. */
1236 u32 u32d[4];
1237 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1238 warning. How I wish compilers were clever enough to
1239 tell which variables can truly be used
1240 uninitialized... */
1241 int inuse; /* tx or rx vc already in use by another vcc */
1242 short vpi = vcc->vpi;
1243 int vci = vcc->vci;
1244
1245 card = (ns_dev *) vcc->dev->dev_data;
1246 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1247 vci);
1248 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1249 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1250 return -EINVAL;
1251 }
1252
1253 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1254 vcc->dev_data = vc;
1255
1256 inuse = 0;
1257 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1258 inuse = 1;
1259 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1260 inuse += 2;
1261 if (inuse) {
1262 printk("nicstar%d: %s vci already in use.\n", card->index,
1263 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1264 return -EINVAL;
1265 }
1266
1267 set_bit(ATM_VF_ADDR, &vcc->flags);
1268
1269 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1270 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1271 needed to do that. */
1272 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1273 scq_info *scq;
1274
1275 set_bit(ATM_VF_PARTIAL, &vcc->flags);
1276 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1277 /* Check requested cell rate and availability of SCD */
1278 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1279 && vcc->qos.txtp.min_pcr == 0) {
1280 PRINTK
1281 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1282 card->index);
1283 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1284 clear_bit(ATM_VF_ADDR, &vcc->flags);
1285 return -EINVAL;
1286 }
1287
1288 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1289 tcra = tcr >= 0 ? tcr : -tcr;
1290
1291 PRINTK("nicstar%d: target cell rate = %d.\n",
1292 card->index, vcc->qos.txtp.max_pcr);
1293
1294 tmpl =
1295 (unsigned long)tcra *(unsigned long)
1296 NS_TST_NUM_ENTRIES;
1297 modl = tmpl % card->max_pcr;
1298
1299 n = (int)(tmpl / card->max_pcr);
1300 if (tcr > 0) {
1301 if (modl > 0)
1302 n++;
1303 } else if (tcr == 0) {
1304 if ((n =
1305 (card->tst_free_entries -
1306 NS_TST_RESERVED)) <= 0) {
1307 PRINTK
1308 ("nicstar%d: no CBR bandwidth free.\n",
1309 card->index);
1310 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1311 clear_bit(ATM_VF_ADDR, &vcc->flags);
1312 return -EINVAL;
1313 }
1314 }
1315
1316 if (n == 0) {
1317 printk
1318 ("nicstar%d: selected bandwidth < granularity.\n",
1319 card->index);
1320 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1321 clear_bit(ATM_VF_ADDR, &vcc->flags);
1322 return -EINVAL;
1323 }
1324
1325 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1326 PRINTK
1327 ("nicstar%d: not enough free CBR bandwidth.\n",
1328 card->index);
1329 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1330 clear_bit(ATM_VF_ADDR, &vcc->flags);
1331 return -EINVAL;
1332 } else
1333 card->tst_free_entries -= n;
1334
1335 XPRINTK("nicstar%d: writing %d tst entries.\n",
1336 card->index, n);
1337 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1338 if (card->scd2vc[frscdi] == NULL) {
1339 card->scd2vc[frscdi] = vc;
1340 break;
1341 }
1342 }
1343 if (frscdi == NS_FRSCD_NUM) {
1344 PRINTK
1345 ("nicstar%d: no SCD available for CBR channel.\n",
1346 card->index);
1347 card->tst_free_entries += n;
1348 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1349 clear_bit(ATM_VF_ADDR, &vcc->flags);
1350 return -EBUSY;
1351 }
1352
1353 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1354
1355 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1356 if (scq == NULL) {
1357 PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1358 card->index);
1359 card->scd2vc[frscdi] = NULL;
1360 card->tst_free_entries += n;
1361 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1362 clear_bit(ATM_VF_ADDR, &vcc->flags);
1363 return -ENOMEM;
1364 }
1365 vc->scq = scq;
1366 u32d[0] = scq_virt_to_bus(scq, scq->base);
1367 u32d[1] = (u32) 0x00000000;
1368 u32d[2] = (u32) 0xffffffff;
1369 u32d[3] = (u32) 0x00000000;
1370 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1371
1372 fill_tst(card, n, vc);
1373 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1374 vc->cbr_scd = 0x00000000;
1375 vc->scq = card->scq0;
1376 }
1377
1378 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1379 vc->tx = 1;
1380 vc->tx_vcc = vcc;
1381 vc->tbd_count = 0;
1382 }
1383 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1384 u32 status;
1385
1386 vc->rx = 1;
1387 vc->rx_vcc = vcc;
1388 vc->rx_iov = NULL;
1389
1390 /* Open the connection in hardware */
1391 if (vcc->qos.aal == ATM_AAL5)
1392 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1393 else /* vcc->qos.aal == ATM_AAL0 */
1394 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1395 #ifdef RCQ_SUPPORT
1396 status |= NS_RCTE_RAWCELLINTEN;
1397 #endif /* RCQ_SUPPORT */
1398 ns_write_sram(card,
1399 NS_RCT +
1400 (vpi << card->vcibits | vci) *
1401 NS_RCT_ENTRY_SIZE, &status, 1);
1402 }
1403
1404 }
1405
1406 set_bit(ATM_VF_READY, &vcc->flags);
1407 return 0;
1408 }
1409
ns_close(struct atm_vcc * vcc)1410 static void ns_close(struct atm_vcc *vcc)
1411 {
1412 vc_map *vc;
1413 ns_dev *card;
1414 u32 data;
1415 int i;
1416
1417 vc = vcc->dev_data;
1418 card = vcc->dev->dev_data;
1419 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1420 (int)vcc->vpi, vcc->vci);
1421
1422 clear_bit(ATM_VF_READY, &vcc->flags);
1423
1424 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1425 u32 addr;
1426 unsigned long flags;
1427
1428 addr =
1429 NS_RCT +
1430 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1431 spin_lock_irqsave(&card->res_lock, flags);
1432 while (CMD_BUSY(card)) ;
1433 writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1434 card->membase + CMD);
1435 spin_unlock_irqrestore(&card->res_lock, flags);
1436
1437 vc->rx = 0;
1438 if (vc->rx_iov != NULL) {
1439 struct sk_buff *iovb;
1440 u32 stat;
1441
1442 stat = readl(card->membase + STAT);
1443 card->sbfqc = ns_stat_sfbqc_get(stat);
1444 card->lbfqc = ns_stat_lfbqc_get(stat);
1445
1446 PRINTK
1447 ("nicstar%d: closing a VC with pending rx buffers.\n",
1448 card->index);
1449 iovb = vc->rx_iov;
1450 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1451 NS_PRV_IOVCNT(iovb));
1452 NS_PRV_IOVCNT(iovb) = 0;
1453 spin_lock_irqsave(&card->int_lock, flags);
1454 recycle_iov_buf(card, iovb);
1455 spin_unlock_irqrestore(&card->int_lock, flags);
1456 vc->rx_iov = NULL;
1457 }
1458 }
1459
1460 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1461 vc->tx = 0;
1462 }
1463
1464 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1465 unsigned long flags;
1466 ns_scqe *scqep;
1467 scq_info *scq;
1468
1469 scq = vc->scq;
1470
1471 for (;;) {
1472 spin_lock_irqsave(&scq->lock, flags);
1473 scqep = scq->next;
1474 if (scqep == scq->base)
1475 scqep = scq->last;
1476 else
1477 scqep--;
1478 if (scqep == scq->tail) {
1479 spin_unlock_irqrestore(&scq->lock, flags);
1480 break;
1481 }
1482 /* If the last entry is not a TSR, place one in the SCQ in order to
1483 be able to completely drain it and then close. */
1484 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1485 ns_scqe tsr;
1486 u32 scdi, scqi;
1487 u32 data;
1488 int index;
1489
1490 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1491 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1492 scqi = scq->next - scq->base;
1493 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1494 tsr.word_3 = 0x00000000;
1495 tsr.word_4 = 0x00000000;
1496 *scq->next = tsr;
1497 index = (int)scqi;
1498 scq->skb[index] = NULL;
1499 if (scq->next == scq->last)
1500 scq->next = scq->base;
1501 else
1502 scq->next++;
1503 data = scq_virt_to_bus(scq, scq->next);
1504 ns_write_sram(card, scq->scd, &data, 1);
1505 }
1506 spin_unlock_irqrestore(&scq->lock, flags);
1507 schedule();
1508 }
1509
1510 /* Free all TST entries */
1511 data = NS_TST_OPCODE_VARIABLE;
1512 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1513 if (card->tste2vc[i] == vc) {
1514 ns_write_sram(card, card->tst_addr + i, &data,
1515 1);
1516 card->tste2vc[i] = NULL;
1517 card->tst_free_entries++;
1518 }
1519 }
1520
1521 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1522 free_scq(card, vc->scq, vcc);
1523 }
1524
1525 /* remove all references to vcc before deleting it */
1526 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1527 unsigned long flags;
1528 scq_info *scq = card->scq0;
1529
1530 spin_lock_irqsave(&scq->lock, flags);
1531
1532 for (i = 0; i < scq->num_entries; i++) {
1533 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1534 ATM_SKB(scq->skb[i])->vcc = NULL;
1535 atm_return(vcc, scq->skb[i]->truesize);
1536 PRINTK
1537 ("nicstar: deleted pending vcc mapping\n");
1538 }
1539 }
1540
1541 spin_unlock_irqrestore(&scq->lock, flags);
1542 }
1543
1544 vcc->dev_data = NULL;
1545 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1546 clear_bit(ATM_VF_ADDR, &vcc->flags);
1547
1548 #ifdef RX_DEBUG
1549 {
1550 u32 stat, cfg;
1551 stat = readl(card->membase + STAT);
1552 cfg = readl(card->membase + CFG);
1553 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1554 printk
1555 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
1556 card->tsq.base, card->tsq.next,
1557 card->tsq.last, readl(card->membase + TSQT));
1558 printk
1559 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
1560 card->rsq.base, card->rsq.next,
1561 card->rsq.last, readl(card->membase + RSQT));
1562 printk("Empty free buffer queue interrupt %s \n",
1563 card->efbie ? "enabled" : "disabled");
1564 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1565 ns_stat_sfbqc_get(stat), card->sbpool.count,
1566 ns_stat_lfbqc_get(stat), card->lbpool.count);
1567 printk("hbpool.count = %d iovpool.count = %d \n",
1568 card->hbpool.count, card->iovpool.count);
1569 }
1570 #endif /* RX_DEBUG */
1571 }
1572
fill_tst(ns_dev * card,int n,vc_map * vc)1573 static void fill_tst(ns_dev * card, int n, vc_map * vc)
1574 {
1575 u32 new_tst;
1576 unsigned long cl;
1577 int e, r;
1578 u32 data;
1579
1580 /* It would be very complicated to keep the two TSTs synchronized while
1581 assuring that writes are only made to the inactive TST. So, for now I
1582 will use only one TST. If problems occur, I will change this again */
1583
1584 new_tst = card->tst_addr;
1585
1586 /* Fill procedure */
1587
1588 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1589 if (card->tste2vc[e] == NULL)
1590 break;
1591 }
1592 if (e == NS_TST_NUM_ENTRIES) {
1593 printk("nicstar%d: No free TST entries found. \n", card->index);
1594 return;
1595 }
1596
1597 r = n;
1598 cl = NS_TST_NUM_ENTRIES;
1599 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1600
1601 while (r > 0) {
1602 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1603 card->tste2vc[e] = vc;
1604 ns_write_sram(card, new_tst + e, &data, 1);
1605 cl -= NS_TST_NUM_ENTRIES;
1606 r--;
1607 }
1608
1609 if (++e == NS_TST_NUM_ENTRIES) {
1610 e = 0;
1611 }
1612 cl += n;
1613 }
1614
1615 /* End of fill procedure */
1616
1617 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1618 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1619 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1620 card->tst_addr = new_tst;
1621 }
1622
ns_send(struct atm_vcc * vcc,struct sk_buff * skb)1623 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1624 {
1625 ns_dev *card;
1626 vc_map *vc;
1627 scq_info *scq;
1628 unsigned long buflen;
1629 ns_scqe scqe;
1630 u32 flags; /* TBD flags, not CPU flags */
1631
1632 card = vcc->dev->dev_data;
1633 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1634 if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1635 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1636 card->index);
1637 atomic_inc(&vcc->stats->tx_err);
1638 dev_kfree_skb_any(skb);
1639 return -EINVAL;
1640 }
1641
1642 if (!vc->tx) {
1643 printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1644 card->index);
1645 atomic_inc(&vcc->stats->tx_err);
1646 dev_kfree_skb_any(skb);
1647 return -EINVAL;
1648 }
1649
1650 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1651 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1652 card->index);
1653 atomic_inc(&vcc->stats->tx_err);
1654 dev_kfree_skb_any(skb);
1655 return -EINVAL;
1656 }
1657
1658 if (skb_shinfo(skb)->nr_frags != 0) {
1659 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1660 atomic_inc(&vcc->stats->tx_err);
1661 dev_kfree_skb_any(skb);
1662 return -EINVAL;
1663 }
1664
1665 ATM_SKB(skb)->vcc = vcc;
1666
1667 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
1668 skb->len, DMA_TO_DEVICE);
1669
1670 if (vcc->qos.aal == ATM_AAL5) {
1671 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1672 flags = NS_TBD_AAL5;
1673 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
1674 scqe.word_3 = cpu_to_le32(skb->len);
1675 scqe.word_4 =
1676 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1677 ATM_SKB(skb)->
1678 atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1679 flags |= NS_TBD_EOPDU;
1680 } else { /* (vcc->qos.aal == ATM_AAL0) */
1681
1682 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1683 flags = NS_TBD_AAL0;
1684 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
1685 scqe.word_3 = cpu_to_le32(0x00000000);
1686 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1687 flags |= NS_TBD_EOPDU;
1688 scqe.word_4 =
1689 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1690 /* Force the VPI/VCI to be the same as in VCC struct */
1691 scqe.word_4 |=
1692 cpu_to_le32((((u32) vcc->
1693 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1694 vci) <<
1695 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1696 }
1697
1698 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1699 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1700 scq = ((vc_map *) vcc->dev_data)->scq;
1701 } else {
1702 scqe.word_1 =
1703 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1704 scq = card->scq0;
1705 }
1706
1707 if (push_scqe(card, vc, scq, &scqe, skb) != 0) {
1708 atomic_inc(&vcc->stats->tx_err);
1709 dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
1710 DMA_TO_DEVICE);
1711 dev_kfree_skb_any(skb);
1712 return -EIO;
1713 }
1714 atomic_inc(&vcc->stats->tx);
1715
1716 return 0;
1717 }
1718
push_scqe(ns_dev * card,vc_map * vc,scq_info * scq,ns_scqe * tbd,struct sk_buff * skb)1719 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1720 struct sk_buff *skb)
1721 {
1722 unsigned long flags;
1723 ns_scqe tsr;
1724 u32 scdi, scqi;
1725 int scq_is_vbr;
1726 u32 data;
1727 int index;
1728
1729 spin_lock_irqsave(&scq->lock, flags);
1730 while (scq->tail == scq->next) {
1731 if (in_interrupt()) {
1732 spin_unlock_irqrestore(&scq->lock, flags);
1733 printk("nicstar%d: Error pushing TBD.\n", card->index);
1734 return 1;
1735 }
1736
1737 scq->full = 1;
1738 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1739 scq->tail != scq->next,
1740 scq->lock,
1741 SCQFULL_TIMEOUT);
1742
1743 if (scq->full) {
1744 spin_unlock_irqrestore(&scq->lock, flags);
1745 printk("nicstar%d: Timeout pushing TBD.\n",
1746 card->index);
1747 return 1;
1748 }
1749 }
1750 *scq->next = *tbd;
1751 index = (int)(scq->next - scq->base);
1752 scq->skb[index] = skb;
1753 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
1754 card->index, skb, index);
1755 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1756 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1757 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1758 scq->next);
1759 if (scq->next == scq->last)
1760 scq->next = scq->base;
1761 else
1762 scq->next++;
1763
1764 vc->tbd_count++;
1765 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1766 scq->tbd_count++;
1767 scq_is_vbr = 1;
1768 } else
1769 scq_is_vbr = 0;
1770
1771 if (vc->tbd_count >= MAX_TBD_PER_VC
1772 || scq->tbd_count >= MAX_TBD_PER_SCQ) {
1773 int has_run = 0;
1774
1775 while (scq->tail == scq->next) {
1776 if (in_interrupt()) {
1777 data = scq_virt_to_bus(scq, scq->next);
1778 ns_write_sram(card, scq->scd, &data, 1);
1779 spin_unlock_irqrestore(&scq->lock, flags);
1780 printk("nicstar%d: Error pushing TSR.\n",
1781 card->index);
1782 return 0;
1783 }
1784
1785 scq->full = 1;
1786 if (has_run++)
1787 break;
1788 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1789 scq->tail != scq->next,
1790 scq->lock,
1791 SCQFULL_TIMEOUT);
1792 }
1793
1794 if (!scq->full) {
1795 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1796 if (scq_is_vbr)
1797 scdi = NS_TSR_SCDISVBR;
1798 else
1799 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1800 scqi = scq->next - scq->base;
1801 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1802 tsr.word_3 = 0x00000000;
1803 tsr.word_4 = 0x00000000;
1804
1805 *scq->next = tsr;
1806 index = (int)scqi;
1807 scq->skb[index] = NULL;
1808 XPRINTK
1809 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1810 card->index, le32_to_cpu(tsr.word_1),
1811 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1812 le32_to_cpu(tsr.word_4), scq->next);
1813 if (scq->next == scq->last)
1814 scq->next = scq->base;
1815 else
1816 scq->next++;
1817 vc->tbd_count = 0;
1818 scq->tbd_count = 0;
1819 } else
1820 PRINTK("nicstar%d: Timeout pushing TSR.\n",
1821 card->index);
1822 }
1823 data = scq_virt_to_bus(scq, scq->next);
1824 ns_write_sram(card, scq->scd, &data, 1);
1825
1826 spin_unlock_irqrestore(&scq->lock, flags);
1827
1828 return 0;
1829 }
1830
process_tsq(ns_dev * card)1831 static void process_tsq(ns_dev * card)
1832 {
1833 u32 scdi;
1834 scq_info *scq;
1835 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
1836 int serviced_entries; /* flag indicating at least on entry was serviced */
1837
1838 serviced_entries = 0;
1839
1840 if (card->tsq.next == card->tsq.last)
1841 one_ahead = card->tsq.base;
1842 else
1843 one_ahead = card->tsq.next + 1;
1844
1845 if (one_ahead == card->tsq.last)
1846 two_ahead = card->tsq.base;
1847 else
1848 two_ahead = one_ahead + 1;
1849
1850 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1851 !ns_tsi_isempty(two_ahead))
1852 /* At most two empty, as stated in the 77201 errata */
1853 {
1854 serviced_entries = 1;
1855
1856 /* Skip the one or two possible empty entries */
1857 while (ns_tsi_isempty(card->tsq.next)) {
1858 if (card->tsq.next == card->tsq.last)
1859 card->tsq.next = card->tsq.base;
1860 else
1861 card->tsq.next++;
1862 }
1863
1864 if (!ns_tsi_tmrof(card->tsq.next)) {
1865 scdi = ns_tsi_getscdindex(card->tsq.next);
1866 if (scdi == NS_TSI_SCDISVBR)
1867 scq = card->scq0;
1868 else {
1869 if (card->scd2vc[scdi] == NULL) {
1870 printk
1871 ("nicstar%d: could not find VC from SCD index.\n",
1872 card->index);
1873 ns_tsi_init(card->tsq.next);
1874 return;
1875 }
1876 scq = card->scd2vc[scdi]->scq;
1877 }
1878 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1879 scq->full = 0;
1880 wake_up_interruptible(&(scq->scqfull_waitq));
1881 }
1882
1883 ns_tsi_init(card->tsq.next);
1884 previous = card->tsq.next;
1885 if (card->tsq.next == card->tsq.last)
1886 card->tsq.next = card->tsq.base;
1887 else
1888 card->tsq.next++;
1889
1890 if (card->tsq.next == card->tsq.last)
1891 one_ahead = card->tsq.base;
1892 else
1893 one_ahead = card->tsq.next + 1;
1894
1895 if (one_ahead == card->tsq.last)
1896 two_ahead = card->tsq.base;
1897 else
1898 two_ahead = one_ahead + 1;
1899 }
1900
1901 if (serviced_entries)
1902 writel(PTR_DIFF(previous, card->tsq.base),
1903 card->membase + TSQH);
1904 }
1905
drain_scq(ns_dev * card,scq_info * scq,int pos)1906 static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1907 {
1908 struct atm_vcc *vcc;
1909 struct sk_buff *skb;
1910 int i;
1911 unsigned long flags;
1912
1913 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
1914 card->index, scq, pos);
1915 if (pos >= scq->num_entries) {
1916 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1917 return;
1918 }
1919
1920 spin_lock_irqsave(&scq->lock, flags);
1921 i = (int)(scq->tail - scq->base);
1922 if (++i == scq->num_entries)
1923 i = 0;
1924 while (i != pos) {
1925 skb = scq->skb[i];
1926 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
1927 card->index, skb, i);
1928 if (skb != NULL) {
1929 dma_unmap_single(&card->pcidev->dev,
1930 NS_PRV_DMA(skb),
1931 skb->len,
1932 DMA_TO_DEVICE);
1933 vcc = ATM_SKB(skb)->vcc;
1934 if (vcc && vcc->pop != NULL) {
1935 vcc->pop(vcc, skb);
1936 } else {
1937 dev_kfree_skb_irq(skb);
1938 }
1939 scq->skb[i] = NULL;
1940 }
1941 if (++i == scq->num_entries)
1942 i = 0;
1943 }
1944 scq->tail = scq->base + pos;
1945 spin_unlock_irqrestore(&scq->lock, flags);
1946 }
1947
process_rsq(ns_dev * card)1948 static void process_rsq(ns_dev * card)
1949 {
1950 ns_rsqe *previous;
1951
1952 if (!ns_rsqe_valid(card->rsq.next))
1953 return;
1954 do {
1955 dequeue_rx(card, card->rsq.next);
1956 ns_rsqe_init(card->rsq.next);
1957 previous = card->rsq.next;
1958 if (card->rsq.next == card->rsq.last)
1959 card->rsq.next = card->rsq.base;
1960 else
1961 card->rsq.next++;
1962 } while (ns_rsqe_valid(card->rsq.next));
1963 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1964 }
1965
dequeue_rx(ns_dev * card,ns_rsqe * rsqe)1966 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1967 {
1968 u32 vpi, vci;
1969 vc_map *vc;
1970 struct sk_buff *iovb;
1971 struct iovec *iov;
1972 struct atm_vcc *vcc;
1973 struct sk_buff *skb;
1974 unsigned short aal5_len;
1975 int len;
1976 u32 stat;
1977 u32 id;
1978
1979 stat = readl(card->membase + STAT);
1980 card->sbfqc = ns_stat_sfbqc_get(stat);
1981 card->lbfqc = ns_stat_lfbqc_get(stat);
1982
1983 id = le32_to_cpu(rsqe->buffer_handle);
1984 skb = idr_remove(&card->idr, id);
1985 if (!skb) {
1986 RXPRINTK(KERN_ERR
1987 "nicstar%d: skb not found!\n", card->index);
1988 return;
1989 }
1990 dma_sync_single_for_cpu(&card->pcidev->dev,
1991 NS_PRV_DMA(skb),
1992 (NS_PRV_BUFTYPE(skb) == BUF_SM
1993 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
1994 DMA_FROM_DEVICE);
1995 dma_unmap_single(&card->pcidev->dev,
1996 NS_PRV_DMA(skb),
1997 (NS_PRV_BUFTYPE(skb) == BUF_SM
1998 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
1999 DMA_FROM_DEVICE);
2000 vpi = ns_rsqe_vpi(rsqe);
2001 vci = ns_rsqe_vci(rsqe);
2002 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2003 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2004 card->index, vpi, vci);
2005 recycle_rx_buf(card, skb);
2006 return;
2007 }
2008
2009 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2010 if (!vc->rx) {
2011 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2012 card->index, vpi, vci);
2013 recycle_rx_buf(card, skb);
2014 return;
2015 }
2016
2017 vcc = vc->rx_vcc;
2018
2019 if (vcc->qos.aal == ATM_AAL0) {
2020 struct sk_buff *sb;
2021 unsigned char *cell;
2022 int i;
2023
2024 cell = skb->data;
2025 for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2026 sb = dev_alloc_skb(NS_SMSKBSIZE);
2027 if (!sb) {
2028 printk
2029 ("nicstar%d: Can't allocate buffers for aal0.\n",
2030 card->index);
2031 atomic_add(i, &vcc->stats->rx_drop);
2032 break;
2033 }
2034 if (!atm_charge(vcc, sb->truesize)) {
2035 RXPRINTK
2036 ("nicstar%d: atm_charge() dropped aal0 packets.\n",
2037 card->index);
2038 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
2039 dev_kfree_skb_any(sb);
2040 break;
2041 }
2042 /* Rebuild the header */
2043 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2044 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2045 if (i == 1 && ns_rsqe_eopdu(rsqe))
2046 *((u32 *) sb->data) |= 0x00000002;
2047 skb_put(sb, NS_AAL0_HEADER);
2048 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2049 skb_put(sb, ATM_CELL_PAYLOAD);
2050 ATM_SKB(sb)->vcc = vcc;
2051 __net_timestamp(sb);
2052 vcc->push(vcc, sb);
2053 atomic_inc(&vcc->stats->rx);
2054 cell += ATM_CELL_PAYLOAD;
2055 }
2056
2057 recycle_rx_buf(card, skb);
2058 return;
2059 }
2060
2061 /* To reach this point, the AAL layer can only be AAL5 */
2062
2063 if ((iovb = vc->rx_iov) == NULL) {
2064 iovb = skb_dequeue(&(card->iovpool.queue));
2065 if (iovb == NULL) { /* No buffers in the queue */
2066 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2067 if (iovb == NULL) {
2068 printk("nicstar%d: Out of iovec buffers.\n",
2069 card->index);
2070 atomic_inc(&vcc->stats->rx_drop);
2071 recycle_rx_buf(card, skb);
2072 return;
2073 }
2074 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2075 } else if (--card->iovpool.count < card->iovnr.min) {
2076 struct sk_buff *new_iovb;
2077 if ((new_iovb =
2078 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2079 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2080 skb_queue_tail(&card->iovpool.queue, new_iovb);
2081 card->iovpool.count++;
2082 }
2083 }
2084 vc->rx_iov = iovb;
2085 NS_PRV_IOVCNT(iovb) = 0;
2086 iovb->len = 0;
2087 iovb->data = iovb->head;
2088 skb_reset_tail_pointer(iovb);
2089 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2090 buffer is stored as iovec base, NOT a pointer to the
2091 small or large buffer itself. */
2092 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
2093 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2094 atomic_inc(&vcc->stats->rx_err);
2095 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2096 NS_MAX_IOVECS);
2097 NS_PRV_IOVCNT(iovb) = 0;
2098 iovb->len = 0;
2099 iovb->data = iovb->head;
2100 skb_reset_tail_pointer(iovb);
2101 }
2102 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
2103 iov->iov_base = (void *)skb;
2104 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2105 iovb->len += iov->iov_len;
2106
2107 #ifdef EXTRA_DEBUG
2108 if (NS_PRV_IOVCNT(iovb) == 1) {
2109 if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
2110 printk
2111 ("nicstar%d: Expected a small buffer, and this is not one.\n",
2112 card->index);
2113 which_list(card, skb);
2114 atomic_inc(&vcc->stats->rx_err);
2115 recycle_rx_buf(card, skb);
2116 vc->rx_iov = NULL;
2117 recycle_iov_buf(card, iovb);
2118 return;
2119 }
2120 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
2121
2122 if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
2123 printk
2124 ("nicstar%d: Expected a large buffer, and this is not one.\n",
2125 card->index);
2126 which_list(card, skb);
2127 atomic_inc(&vcc->stats->rx_err);
2128 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2129 NS_PRV_IOVCNT(iovb));
2130 vc->rx_iov = NULL;
2131 recycle_iov_buf(card, iovb);
2132 return;
2133 }
2134 }
2135 #endif /* EXTRA_DEBUG */
2136
2137 if (ns_rsqe_eopdu(rsqe)) {
2138 /* This works correctly regardless of the endianness of the host */
2139 unsigned char *L1L2 = (unsigned char *)
2140 (skb->data + iov->iov_len - 6);
2141 aal5_len = L1L2[0] << 8 | L1L2[1];
2142 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2143 if (ns_rsqe_crcerr(rsqe) ||
2144 len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2145 printk("nicstar%d: AAL5 CRC error", card->index);
2146 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2147 printk(" - PDU size mismatch.\n");
2148 else
2149 printk(".\n");
2150 atomic_inc(&vcc->stats->rx_err);
2151 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2152 NS_PRV_IOVCNT(iovb));
2153 vc->rx_iov = NULL;
2154 recycle_iov_buf(card, iovb);
2155 return;
2156 }
2157
2158 /* By this point we (hopefully) have a complete SDU without errors. */
2159
2160 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
2161 /* skb points to a small buffer */
2162 if (!atm_charge(vcc, skb->truesize)) {
2163 push_rxbufs(card, skb);
2164 atomic_inc(&vcc->stats->rx_drop);
2165 } else {
2166 skb_put(skb, len);
2167 dequeue_sm_buf(card, skb);
2168 ATM_SKB(skb)->vcc = vcc;
2169 __net_timestamp(skb);
2170 vcc->push(vcc, skb);
2171 atomic_inc(&vcc->stats->rx);
2172 }
2173 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
2174 struct sk_buff *sb;
2175
2176 sb = (struct sk_buff *)(iov - 1)->iov_base;
2177 /* skb points to a large buffer */
2178
2179 if (len <= NS_SMBUFSIZE) {
2180 if (!atm_charge(vcc, sb->truesize)) {
2181 push_rxbufs(card, sb);
2182 atomic_inc(&vcc->stats->rx_drop);
2183 } else {
2184 skb_put(sb, len);
2185 dequeue_sm_buf(card, sb);
2186 ATM_SKB(sb)->vcc = vcc;
2187 __net_timestamp(sb);
2188 vcc->push(vcc, sb);
2189 atomic_inc(&vcc->stats->rx);
2190 }
2191
2192 push_rxbufs(card, skb);
2193
2194 } else { /* len > NS_SMBUFSIZE, the usual case */
2195
2196 if (!atm_charge(vcc, skb->truesize)) {
2197 push_rxbufs(card, skb);
2198 atomic_inc(&vcc->stats->rx_drop);
2199 } else {
2200 dequeue_lg_buf(card, skb);
2201 skb_push(skb, NS_SMBUFSIZE);
2202 skb_copy_from_linear_data(sb, skb->data,
2203 NS_SMBUFSIZE);
2204 skb_put(skb, len - NS_SMBUFSIZE);
2205 ATM_SKB(skb)->vcc = vcc;
2206 __net_timestamp(skb);
2207 vcc->push(vcc, skb);
2208 atomic_inc(&vcc->stats->rx);
2209 }
2210
2211 push_rxbufs(card, sb);
2212
2213 }
2214
2215 } else { /* Must push a huge buffer */
2216
2217 struct sk_buff *hb, *sb, *lb;
2218 int remaining, tocopy;
2219 int j;
2220
2221 hb = skb_dequeue(&(card->hbpool.queue));
2222 if (hb == NULL) { /* No buffers in the queue */
2223
2224 hb = dev_alloc_skb(NS_HBUFSIZE);
2225 if (hb == NULL) {
2226 printk
2227 ("nicstar%d: Out of huge buffers.\n",
2228 card->index);
2229 atomic_inc(&vcc->stats->rx_drop);
2230 recycle_iovec_rx_bufs(card,
2231 (struct iovec *)
2232 iovb->data,
2233 NS_PRV_IOVCNT(iovb));
2234 vc->rx_iov = NULL;
2235 recycle_iov_buf(card, iovb);
2236 return;
2237 } else if (card->hbpool.count < card->hbnr.min) {
2238 struct sk_buff *new_hb;
2239 if ((new_hb =
2240 dev_alloc_skb(NS_HBUFSIZE)) !=
2241 NULL) {
2242 skb_queue_tail(&card->hbpool.
2243 queue, new_hb);
2244 card->hbpool.count++;
2245 }
2246 }
2247 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2248 } else if (--card->hbpool.count < card->hbnr.min) {
2249 struct sk_buff *new_hb;
2250 if ((new_hb =
2251 dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2252 NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
2253 skb_queue_tail(&card->hbpool.queue,
2254 new_hb);
2255 card->hbpool.count++;
2256 }
2257 if (card->hbpool.count < card->hbnr.min) {
2258 if ((new_hb =
2259 dev_alloc_skb(NS_HBUFSIZE)) !=
2260 NULL) {
2261 NS_PRV_BUFTYPE(new_hb) =
2262 BUF_NONE;
2263 skb_queue_tail(&card->hbpool.
2264 queue, new_hb);
2265 card->hbpool.count++;
2266 }
2267 }
2268 }
2269
2270 iov = (struct iovec *)iovb->data;
2271
2272 if (!atm_charge(vcc, hb->truesize)) {
2273 recycle_iovec_rx_bufs(card, iov,
2274 NS_PRV_IOVCNT(iovb));
2275 if (card->hbpool.count < card->hbnr.max) {
2276 skb_queue_tail(&card->hbpool.queue, hb);
2277 card->hbpool.count++;
2278 } else
2279 dev_kfree_skb_any(hb);
2280 atomic_inc(&vcc->stats->rx_drop);
2281 } else {
2282 /* Copy the small buffer to the huge buffer */
2283 sb = (struct sk_buff *)iov->iov_base;
2284 skb_copy_from_linear_data(sb, hb->data,
2285 iov->iov_len);
2286 skb_put(hb, iov->iov_len);
2287 remaining = len - iov->iov_len;
2288 iov++;
2289 /* Free the small buffer */
2290 push_rxbufs(card, sb);
2291
2292 /* Copy all large buffers to the huge buffer and free them */
2293 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
2294 lb = (struct sk_buff *)iov->iov_base;
2295 tocopy =
2296 min_t(int, remaining, iov->iov_len);
2297 skb_copy_from_linear_data(lb,
2298 skb_tail_pointer
2299 (hb), tocopy);
2300 skb_put(hb, tocopy);
2301 iov++;
2302 remaining -= tocopy;
2303 push_rxbufs(card, lb);
2304 }
2305 #ifdef EXTRA_DEBUG
2306 if (remaining != 0 || hb->len != len)
2307 printk
2308 ("nicstar%d: Huge buffer len mismatch.\n",
2309 card->index);
2310 #endif /* EXTRA_DEBUG */
2311 ATM_SKB(hb)->vcc = vcc;
2312 __net_timestamp(hb);
2313 vcc->push(vcc, hb);
2314 atomic_inc(&vcc->stats->rx);
2315 }
2316 }
2317
2318 vc->rx_iov = NULL;
2319 recycle_iov_buf(card, iovb);
2320 }
2321
2322 }
2323
recycle_rx_buf(ns_dev * card,struct sk_buff * skb)2324 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2325 {
2326 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
2327 printk("nicstar%d: What kind of rx buffer is this?\n",
2328 card->index);
2329 dev_kfree_skb_any(skb);
2330 } else
2331 push_rxbufs(card, skb);
2332 }
2333
recycle_iovec_rx_bufs(ns_dev * card,struct iovec * iov,int count)2334 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2335 {
2336 while (count-- > 0)
2337 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2338 }
2339
recycle_iov_buf(ns_dev * card,struct sk_buff * iovb)2340 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2341 {
2342 if (card->iovpool.count < card->iovnr.max) {
2343 skb_queue_tail(&card->iovpool.queue, iovb);
2344 card->iovpool.count++;
2345 } else
2346 dev_kfree_skb_any(iovb);
2347 }
2348
dequeue_sm_buf(ns_dev * card,struct sk_buff * sb)2349 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2350 {
2351 skb_unlink(sb, &card->sbpool.queue);
2352 if (card->sbfqc < card->sbnr.init) {
2353 struct sk_buff *new_sb;
2354 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2355 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2356 skb_queue_tail(&card->sbpool.queue, new_sb);
2357 skb_reserve(new_sb, NS_AAL0_HEADER);
2358 push_rxbufs(card, new_sb);
2359 }
2360 }
2361 if (card->sbfqc < card->sbnr.init)
2362 {
2363 struct sk_buff *new_sb;
2364 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2365 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2366 skb_queue_tail(&card->sbpool.queue, new_sb);
2367 skb_reserve(new_sb, NS_AAL0_HEADER);
2368 push_rxbufs(card, new_sb);
2369 }
2370 }
2371 }
2372
dequeue_lg_buf(ns_dev * card,struct sk_buff * lb)2373 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2374 {
2375 skb_unlink(lb, &card->lbpool.queue);
2376 if (card->lbfqc < card->lbnr.init) {
2377 struct sk_buff *new_lb;
2378 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2379 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2380 skb_queue_tail(&card->lbpool.queue, new_lb);
2381 skb_reserve(new_lb, NS_SMBUFSIZE);
2382 push_rxbufs(card, new_lb);
2383 }
2384 }
2385 if (card->lbfqc < card->lbnr.init)
2386 {
2387 struct sk_buff *new_lb;
2388 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2389 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2390 skb_queue_tail(&card->lbpool.queue, new_lb);
2391 skb_reserve(new_lb, NS_SMBUFSIZE);
2392 push_rxbufs(card, new_lb);
2393 }
2394 }
2395 }
2396
ns_proc_read(struct atm_dev * dev,loff_t * pos,char * page)2397 static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2398 {
2399 u32 stat;
2400 ns_dev *card;
2401 int left;
2402
2403 left = (int)*pos;
2404 card = (ns_dev *) dev->dev_data;
2405 stat = readl(card->membase + STAT);
2406 if (!left--)
2407 return sprintf(page, "Pool count min init max \n");
2408 if (!left--)
2409 return sprintf(page, "Small %5d %5d %5d %5d \n",
2410 ns_stat_sfbqc_get(stat), card->sbnr.min,
2411 card->sbnr.init, card->sbnr.max);
2412 if (!left--)
2413 return sprintf(page, "Large %5d %5d %5d %5d \n",
2414 ns_stat_lfbqc_get(stat), card->lbnr.min,
2415 card->lbnr.init, card->lbnr.max);
2416 if (!left--)
2417 return sprintf(page, "Huge %5d %5d %5d %5d \n",
2418 card->hbpool.count, card->hbnr.min,
2419 card->hbnr.init, card->hbnr.max);
2420 if (!left--)
2421 return sprintf(page, "Iovec %5d %5d %5d %5d \n",
2422 card->iovpool.count, card->iovnr.min,
2423 card->iovnr.init, card->iovnr.max);
2424 if (!left--) {
2425 int retval;
2426 retval =
2427 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2428 card->intcnt = 0;
2429 return retval;
2430 }
2431 #if 0
2432 /* Dump 25.6 Mbps PHY registers */
2433 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2434 here just in case it's needed for debugging. */
2435 if (card->max_pcr == ATM_25_PCR && !left--) {
2436 u32 phy_regs[4];
2437 u32 i;
2438
2439 for (i = 0; i < 4; i++) {
2440 while (CMD_BUSY(card)) ;
2441 writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2442 card->membase + CMD);
2443 while (CMD_BUSY(card)) ;
2444 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2445 }
2446
2447 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2448 phy_regs[0], phy_regs[1], phy_regs[2],
2449 phy_regs[3]);
2450 }
2451 #endif /* 0 - Dump 25.6 Mbps PHY registers */
2452 #if 0
2453 /* Dump TST */
2454 if (left-- < NS_TST_NUM_ENTRIES) {
2455 if (card->tste2vc[left + 1] == NULL)
2456 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2457 else
2458 return sprintf(page, "%5d - %d %d \n", left + 1,
2459 card->tste2vc[left + 1]->tx_vcc->vpi,
2460 card->tste2vc[left + 1]->tx_vcc->vci);
2461 }
2462 #endif /* 0 */
2463 return 0;
2464 }
2465
ns_ioctl(struct atm_dev * dev,unsigned int cmd,void __user * arg)2466 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2467 {
2468 ns_dev *card;
2469 pool_levels pl;
2470 long btype;
2471 unsigned long flags;
2472
2473 card = dev->dev_data;
2474 switch (cmd) {
2475 case NS_GETPSTAT:
2476 if (get_user
2477 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2478 return -EFAULT;
2479 switch (pl.buftype) {
2480 case NS_BUFTYPE_SMALL:
2481 pl.count =
2482 ns_stat_sfbqc_get(readl(card->membase + STAT));
2483 pl.level.min = card->sbnr.min;
2484 pl.level.init = card->sbnr.init;
2485 pl.level.max = card->sbnr.max;
2486 break;
2487
2488 case NS_BUFTYPE_LARGE:
2489 pl.count =
2490 ns_stat_lfbqc_get(readl(card->membase + STAT));
2491 pl.level.min = card->lbnr.min;
2492 pl.level.init = card->lbnr.init;
2493 pl.level.max = card->lbnr.max;
2494 break;
2495
2496 case NS_BUFTYPE_HUGE:
2497 pl.count = card->hbpool.count;
2498 pl.level.min = card->hbnr.min;
2499 pl.level.init = card->hbnr.init;
2500 pl.level.max = card->hbnr.max;
2501 break;
2502
2503 case NS_BUFTYPE_IOVEC:
2504 pl.count = card->iovpool.count;
2505 pl.level.min = card->iovnr.min;
2506 pl.level.init = card->iovnr.init;
2507 pl.level.max = card->iovnr.max;
2508 break;
2509
2510 default:
2511 return -ENOIOCTLCMD;
2512
2513 }
2514 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
2515 return (sizeof(pl));
2516 else
2517 return -EFAULT;
2518
2519 case NS_SETBUFLEV:
2520 if (!capable(CAP_NET_ADMIN))
2521 return -EPERM;
2522 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
2523 return -EFAULT;
2524 if (pl.level.min >= pl.level.init
2525 || pl.level.init >= pl.level.max)
2526 return -EINVAL;
2527 if (pl.level.min == 0)
2528 return -EINVAL;
2529 switch (pl.buftype) {
2530 case NS_BUFTYPE_SMALL:
2531 if (pl.level.max > TOP_SB)
2532 return -EINVAL;
2533 card->sbnr.min = pl.level.min;
2534 card->sbnr.init = pl.level.init;
2535 card->sbnr.max = pl.level.max;
2536 break;
2537
2538 case NS_BUFTYPE_LARGE:
2539 if (pl.level.max > TOP_LB)
2540 return -EINVAL;
2541 card->lbnr.min = pl.level.min;
2542 card->lbnr.init = pl.level.init;
2543 card->lbnr.max = pl.level.max;
2544 break;
2545
2546 case NS_BUFTYPE_HUGE:
2547 if (pl.level.max > TOP_HB)
2548 return -EINVAL;
2549 card->hbnr.min = pl.level.min;
2550 card->hbnr.init = pl.level.init;
2551 card->hbnr.max = pl.level.max;
2552 break;
2553
2554 case NS_BUFTYPE_IOVEC:
2555 if (pl.level.max > TOP_IOVB)
2556 return -EINVAL;
2557 card->iovnr.min = pl.level.min;
2558 card->iovnr.init = pl.level.init;
2559 card->iovnr.max = pl.level.max;
2560 break;
2561
2562 default:
2563 return -EINVAL;
2564
2565 }
2566 return 0;
2567
2568 case NS_ADJBUFLEV:
2569 if (!capable(CAP_NET_ADMIN))
2570 return -EPERM;
2571 btype = (long)arg; /* a long is the same size as a pointer or bigger */
2572 switch (btype) {
2573 case NS_BUFTYPE_SMALL:
2574 while (card->sbfqc < card->sbnr.init) {
2575 struct sk_buff *sb;
2576
2577 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2578 if (sb == NULL)
2579 return -ENOMEM;
2580 NS_PRV_BUFTYPE(sb) = BUF_SM;
2581 skb_queue_tail(&card->sbpool.queue, sb);
2582 skb_reserve(sb, NS_AAL0_HEADER);
2583 push_rxbufs(card, sb);
2584 }
2585 break;
2586
2587 case NS_BUFTYPE_LARGE:
2588 while (card->lbfqc < card->lbnr.init) {
2589 struct sk_buff *lb;
2590
2591 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2592 if (lb == NULL)
2593 return -ENOMEM;
2594 NS_PRV_BUFTYPE(lb) = BUF_LG;
2595 skb_queue_tail(&card->lbpool.queue, lb);
2596 skb_reserve(lb, NS_SMBUFSIZE);
2597 push_rxbufs(card, lb);
2598 }
2599 break;
2600
2601 case NS_BUFTYPE_HUGE:
2602 while (card->hbpool.count > card->hbnr.init) {
2603 struct sk_buff *hb;
2604
2605 spin_lock_irqsave(&card->int_lock, flags);
2606 hb = skb_dequeue(&card->hbpool.queue);
2607 card->hbpool.count--;
2608 spin_unlock_irqrestore(&card->int_lock, flags);
2609 if (hb == NULL)
2610 printk
2611 ("nicstar%d: huge buffer count inconsistent.\n",
2612 card->index);
2613 else
2614 dev_kfree_skb_any(hb);
2615
2616 }
2617 while (card->hbpool.count < card->hbnr.init) {
2618 struct sk_buff *hb;
2619
2620 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2621 if (hb == NULL)
2622 return -ENOMEM;
2623 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2624 spin_lock_irqsave(&card->int_lock, flags);
2625 skb_queue_tail(&card->hbpool.queue, hb);
2626 card->hbpool.count++;
2627 spin_unlock_irqrestore(&card->int_lock, flags);
2628 }
2629 break;
2630
2631 case NS_BUFTYPE_IOVEC:
2632 while (card->iovpool.count > card->iovnr.init) {
2633 struct sk_buff *iovb;
2634
2635 spin_lock_irqsave(&card->int_lock, flags);
2636 iovb = skb_dequeue(&card->iovpool.queue);
2637 card->iovpool.count--;
2638 spin_unlock_irqrestore(&card->int_lock, flags);
2639 if (iovb == NULL)
2640 printk
2641 ("nicstar%d: iovec buffer count inconsistent.\n",
2642 card->index);
2643 else
2644 dev_kfree_skb_any(iovb);
2645
2646 }
2647 while (card->iovpool.count < card->iovnr.init) {
2648 struct sk_buff *iovb;
2649
2650 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2651 if (iovb == NULL)
2652 return -ENOMEM;
2653 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2654 spin_lock_irqsave(&card->int_lock, flags);
2655 skb_queue_tail(&card->iovpool.queue, iovb);
2656 card->iovpool.count++;
2657 spin_unlock_irqrestore(&card->int_lock, flags);
2658 }
2659 break;
2660
2661 default:
2662 return -EINVAL;
2663
2664 }
2665 return 0;
2666
2667 default:
2668 if (dev->phy && dev->phy->ioctl) {
2669 return dev->phy->ioctl(dev, cmd, arg);
2670 } else {
2671 printk("nicstar%d: %s == NULL \n", card->index,
2672 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2673 return -ENOIOCTLCMD;
2674 }
2675 }
2676 }
2677
2678 #ifdef EXTRA_DEBUG
which_list(ns_dev * card,struct sk_buff * skb)2679 static void which_list(ns_dev * card, struct sk_buff *skb)
2680 {
2681 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
2682 }
2683 #endif /* EXTRA_DEBUG */
2684
ns_poll(struct timer_list * unused)2685 static void ns_poll(struct timer_list *unused)
2686 {
2687 int i;
2688 ns_dev *card;
2689 unsigned long flags;
2690 u32 stat_r, stat_w;
2691
2692 PRINTK("nicstar: Entering ns_poll().\n");
2693 for (i = 0; i < num_cards; i++) {
2694 card = cards[i];
2695 if (!spin_trylock_irqsave(&card->int_lock, flags)) {
2696 /* Probably it isn't worth spinning */
2697 continue;
2698 }
2699
2700 stat_w = 0;
2701 stat_r = readl(card->membase + STAT);
2702 if (stat_r & NS_STAT_TSIF)
2703 stat_w |= NS_STAT_TSIF;
2704 if (stat_r & NS_STAT_EOPDU)
2705 stat_w |= NS_STAT_EOPDU;
2706
2707 process_tsq(card);
2708 process_rsq(card);
2709
2710 writel(stat_w, card->membase + STAT);
2711 spin_unlock_irqrestore(&card->int_lock, flags);
2712 }
2713 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
2714 PRINTK("nicstar: Leaving ns_poll().\n");
2715 }
2716
ns_phy_put(struct atm_dev * dev,unsigned char value,unsigned long addr)2717 static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2718 unsigned long addr)
2719 {
2720 ns_dev *card;
2721 unsigned long flags;
2722
2723 card = dev->dev_data;
2724 spin_lock_irqsave(&card->res_lock, flags);
2725 while (CMD_BUSY(card)) ;
2726 writel((u32) value, card->membase + DR0);
2727 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2728 card->membase + CMD);
2729 spin_unlock_irqrestore(&card->res_lock, flags);
2730 }
2731
ns_phy_get(struct atm_dev * dev,unsigned long addr)2732 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2733 {
2734 ns_dev *card;
2735 unsigned long flags;
2736 u32 data;
2737
2738 card = dev->dev_data;
2739 spin_lock_irqsave(&card->res_lock, flags);
2740 while (CMD_BUSY(card)) ;
2741 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
2742 card->membase + CMD);
2743 while (CMD_BUSY(card)) ;
2744 data = readl(card->membase + DR0) & 0x000000FF;
2745 spin_unlock_irqrestore(&card->res_lock, flags);
2746 return (unsigned char)data;
2747 }
2748
2749 module_init(nicstar_init);
2750 module_exit(nicstar_cleanup);
2751
