1 /*
2 * cimax2.c
3 *
4 * CIMax2(R) SP2 driver in conjunction with NetUp Dual DVB-S2 CI card
5 *
6 * Copyright (C) 2009 NetUP Inc.
7 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
8 * Copyright (C) 2009 Abylay Ospan <aospan@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 */
21
22 #include "cx23885.h"
23 #include "cimax2.h"
24 #include <media/dvb_ca_en50221.h>
25
26 /* Max transfer size done by I2C transfer functions */
27 #define MAX_XFER_SIZE 64
28
29 /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
30 bits 31-16
31 +-----------+
32 | Reserved |
33 +-----------+
34 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
35 +-------+-------+-------+-------+-------+-------+-------+-------+
36 | WR# | RD# | | ACK# | ADHI | ADLO | CS1# | CS0# |
37 +-------+-------+-------+-------+-------+-------+-------+-------+
38 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
39 +-------+-------+-------+-------+-------+-------+-------+-------+
40 | DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0|
41 +-------+-------+-------+-------+-------+-------+-------+-------+
42 ***/
43 /* MC417 */
44 #define NETUP_DATA 0x000000ff
45 #define NETUP_WR 0x00008000
46 #define NETUP_RD 0x00004000
47 #define NETUP_ACK 0x00001000
48 #define NETUP_ADHI 0x00000800
49 #define NETUP_ADLO 0x00000400
50 #define NETUP_CS1 0x00000200
51 #define NETUP_CS0 0x00000100
52 #define NETUP_EN_ALL 0x00001000
53 #define NETUP_CTRL_OFF (NETUP_CS1 | NETUP_CS0 | NETUP_WR | NETUP_RD)
54 #define NETUP_CI_CTL 0x04
55 #define NETUP_CI_RD 1
56
57 #define NETUP_IRQ_DETAM 0x1
58 #define NETUP_IRQ_IRQAM 0x4
59
60 static unsigned int ci_dbg;
61 module_param(ci_dbg, int, 0644);
62 MODULE_PARM_DESC(ci_dbg, "Enable CI debugging");
63
64 static unsigned int ci_irq_enable;
65 module_param(ci_irq_enable, int, 0644);
66 MODULE_PARM_DESC(ci_irq_enable, "Enable IRQ from CAM");
67
68 #define ci_dbg_print(fmt, args...) \
69 do { \
70 if (ci_dbg) \
71 printk(KERN_DEBUG pr_fmt("%s: " fmt), \
72 __func__, ##args); \
73 } while (0)
74
75 #define ci_irq_flags() (ci_irq_enable ? NETUP_IRQ_IRQAM : 0)
76
77 /* stores all private variables for communication with CI */
78 struct netup_ci_state {
79 struct dvb_ca_en50221 ca;
80 struct mutex ca_mutex;
81 struct i2c_adapter *i2c_adap;
82 u8 ci_i2c_addr;
83 int status;
84 struct work_struct work;
85 void *priv;
86 u8 current_irq_mode;
87 int current_ci_flag;
88 unsigned long next_status_checked_time;
89 };
90
91
netup_read_i2c(struct i2c_adapter * i2c_adap,u8 addr,u8 reg,u8 * buf,int len)92 static int netup_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
93 u8 *buf, int len)
94 {
95 int ret;
96 struct i2c_msg msg[] = {
97 {
98 .addr = addr,
99 .flags = 0,
100 .buf = ®,
101 .len = 1
102 }, {
103 .addr = addr,
104 .flags = I2C_M_RD,
105 .buf = buf,
106 .len = len
107 }
108 };
109
110 ret = i2c_transfer(i2c_adap, msg, 2);
111
112 if (ret != 2) {
113 ci_dbg_print("%s: i2c read error, Reg = 0x%02x, Status = %d\n",
114 __func__, reg, ret);
115
116 return -1;
117 }
118
119 ci_dbg_print("%s: i2c read Addr=0x%04x, Reg = 0x%02x, data = %02x\n",
120 __func__, addr, reg, buf[0]);
121
122 return 0;
123 }
124
netup_write_i2c(struct i2c_adapter * i2c_adap,u8 addr,u8 reg,u8 * buf,int len)125 static int netup_write_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
126 u8 *buf, int len)
127 {
128 int ret;
129 u8 buffer[MAX_XFER_SIZE];
130
131 struct i2c_msg msg = {
132 .addr = addr,
133 .flags = 0,
134 .buf = &buffer[0],
135 .len = len + 1
136 };
137
138 if (1 + len > sizeof(buffer)) {
139 pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n",
140 KBUILD_MODNAME, reg, len);
141 return -EINVAL;
142 }
143
144 buffer[0] = reg;
145 memcpy(&buffer[1], buf, len);
146
147 ret = i2c_transfer(i2c_adap, &msg, 1);
148
149 if (ret != 1) {
150 ci_dbg_print("%s: i2c write error, Reg=[0x%02x], Status=%d\n",
151 __func__, reg, ret);
152 return -1;
153 }
154
155 return 0;
156 }
157
netup_ci_get_mem(struct cx23885_dev * dev)158 static int netup_ci_get_mem(struct cx23885_dev *dev)
159 {
160 int mem;
161 unsigned long timeout = jiffies + msecs_to_jiffies(1);
162
163 for (;;) {
164 mem = cx_read(MC417_RWD);
165 if ((mem & NETUP_ACK) == 0)
166 break;
167 if (time_after(jiffies, timeout))
168 break;
169 udelay(1);
170 }
171
172 cx_set(MC417_RWD, NETUP_CTRL_OFF);
173
174 return mem & 0xff;
175 }
176
netup_ci_op_cam(struct dvb_ca_en50221 * en50221,int slot,u8 flag,u8 read,int addr,u8 data)177 static int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
178 u8 flag, u8 read, int addr, u8 data)
179 {
180 struct netup_ci_state *state = en50221->data;
181 struct cx23885_tsport *port = state->priv;
182 struct cx23885_dev *dev = port->dev;
183
184 u8 store;
185 int mem;
186 int ret;
187
188 if (0 != slot)
189 return -EINVAL;
190
191 if (state->current_ci_flag != flag) {
192 ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
193 0, &store, 1);
194 if (ret != 0)
195 return ret;
196
197 store &= ~0x0c;
198 store |= flag;
199
200 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
201 0, &store, 1);
202 if (ret != 0)
203 return ret;
204 }
205 state->current_ci_flag = flag;
206
207 mutex_lock(&dev->gpio_lock);
208
209 /* write addr */
210 cx_write(MC417_OEN, NETUP_EN_ALL);
211 cx_write(MC417_RWD, NETUP_CTRL_OFF |
212 NETUP_ADLO | (0xff & addr));
213 cx_clear(MC417_RWD, NETUP_ADLO);
214 cx_write(MC417_RWD, NETUP_CTRL_OFF |
215 NETUP_ADHI | (0xff & (addr >> 8)));
216 cx_clear(MC417_RWD, NETUP_ADHI);
217
218 if (read) { /* data in */
219 cx_write(MC417_OEN, NETUP_EN_ALL | NETUP_DATA);
220 } else /* data out */
221 cx_write(MC417_RWD, NETUP_CTRL_OFF | data);
222
223 /* choose chip */
224 cx_clear(MC417_RWD,
225 (state->ci_i2c_addr == 0x40) ? NETUP_CS0 : NETUP_CS1);
226 /* read/write */
227 cx_clear(MC417_RWD, (read) ? NETUP_RD : NETUP_WR);
228 mem = netup_ci_get_mem(dev);
229
230 mutex_unlock(&dev->gpio_lock);
231
232 if (!read)
233 if (mem < 0)
234 return -EREMOTEIO;
235
236 ci_dbg_print("%s: %s: chipaddr=[0x%x] addr=[0x%02x], %s=%x\n", __func__,
237 (read) ? "read" : "write", state->ci_i2c_addr, addr,
238 (flag == NETUP_CI_CTL) ? "ctl" : "mem",
239 (read) ? mem : data);
240
241 if (read)
242 return mem;
243
244 return 0;
245 }
246
netup_ci_read_attribute_mem(struct dvb_ca_en50221 * en50221,int slot,int addr)247 int netup_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
248 int slot, int addr)
249 {
250 return netup_ci_op_cam(en50221, slot, 0, NETUP_CI_RD, addr, 0);
251 }
252
netup_ci_write_attribute_mem(struct dvb_ca_en50221 * en50221,int slot,int addr,u8 data)253 int netup_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
254 int slot, int addr, u8 data)
255 {
256 return netup_ci_op_cam(en50221, slot, 0, 0, addr, data);
257 }
258
netup_ci_read_cam_ctl(struct dvb_ca_en50221 * en50221,int slot,u8 addr)259 int netup_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
260 u8 addr)
261 {
262 return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL,
263 NETUP_CI_RD, addr, 0);
264 }
265
netup_ci_write_cam_ctl(struct dvb_ca_en50221 * en50221,int slot,u8 addr,u8 data)266 int netup_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
267 u8 addr, u8 data)
268 {
269 return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL, 0, addr, data);
270 }
271
netup_ci_slot_reset(struct dvb_ca_en50221 * en50221,int slot)272 int netup_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
273 {
274 struct netup_ci_state *state = en50221->data;
275 u8 buf = 0x80;
276 int ret;
277
278 if (0 != slot)
279 return -EINVAL;
280
281 udelay(500);
282 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
283 0, &buf, 1);
284
285 if (ret != 0)
286 return ret;
287
288 udelay(500);
289
290 buf = 0x00;
291 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
292 0, &buf, 1);
293
294 msleep(1000);
295 dvb_ca_en50221_camready_irq(&state->ca, 0);
296
297 return 0;
298
299 }
300
netup_ci_slot_shutdown(struct dvb_ca_en50221 * en50221,int slot)301 int netup_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
302 {
303 /* not implemented */
304 return 0;
305 }
306
netup_ci_set_irq(struct dvb_ca_en50221 * en50221,u8 irq_mode)307 static int netup_ci_set_irq(struct dvb_ca_en50221 *en50221, u8 irq_mode)
308 {
309 struct netup_ci_state *state = en50221->data;
310 int ret;
311
312 if (irq_mode == state->current_irq_mode)
313 return 0;
314
315 ci_dbg_print("%s: chipaddr=[0x%x] setting ci IRQ to [0x%x] \n",
316 __func__, state->ci_i2c_addr, irq_mode);
317 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
318 0x1b, &irq_mode, 1);
319
320 if (ret != 0)
321 return ret;
322
323 state->current_irq_mode = irq_mode;
324
325 return 0;
326 }
327
netup_ci_slot_ts_ctl(struct dvb_ca_en50221 * en50221,int slot)328 int netup_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
329 {
330 struct netup_ci_state *state = en50221->data;
331 u8 buf;
332
333 if (0 != slot)
334 return -EINVAL;
335
336 netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
337 0, &buf, 1);
338 buf |= 0x60;
339
340 return netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
341 0, &buf, 1);
342 }
343
344 /* work handler */
netup_read_ci_status(struct work_struct * work)345 static void netup_read_ci_status(struct work_struct *work)
346 {
347 struct netup_ci_state *state =
348 container_of(work, struct netup_ci_state, work);
349 u8 buf[33];
350 int ret;
351
352 /* CAM module IRQ processing. fast operation */
353 dvb_ca_en50221_frda_irq(&state->ca, 0);
354
355 /* CAM module INSERT/REMOVE processing. slow operation because of i2c
356 * transfers */
357 if (time_after(jiffies, state->next_status_checked_time)
358 || !state->status) {
359 ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
360 0, &buf[0], 33);
361
362 state->next_status_checked_time = jiffies
363 + msecs_to_jiffies(1000);
364
365 if (ret != 0)
366 return;
367
368 ci_dbg_print("%s: Slot Status Addr=[0x%04x], Reg=[0x%02x], data=%02x, TS config = %02x\n",
369 __func__, state->ci_i2c_addr, 0, buf[0], buf[0]);
370
371
372 if (buf[0] & 1)
373 state->status = DVB_CA_EN50221_POLL_CAM_PRESENT |
374 DVB_CA_EN50221_POLL_CAM_READY;
375 else
376 state->status = 0;
377 }
378 }
379
380 /* CI irq handler */
netup_ci_slot_status(struct cx23885_dev * dev,u32 pci_status)381 int netup_ci_slot_status(struct cx23885_dev *dev, u32 pci_status)
382 {
383 struct cx23885_tsport *port = NULL;
384 struct netup_ci_state *state = NULL;
385
386 ci_dbg_print("%s:\n", __func__);
387
388 if (0 == (pci_status & (PCI_MSK_GPIO0 | PCI_MSK_GPIO1)))
389 return 0;
390
391 if (pci_status & PCI_MSK_GPIO0) {
392 port = &dev->ts1;
393 state = port->port_priv;
394 schedule_work(&state->work);
395 ci_dbg_print("%s: Wakeup CI0\n", __func__);
396 }
397
398 if (pci_status & PCI_MSK_GPIO1) {
399 port = &dev->ts2;
400 state = port->port_priv;
401 schedule_work(&state->work);
402 ci_dbg_print("%s: Wakeup CI1\n", __func__);
403 }
404
405 return 1;
406 }
407
netup_poll_ci_slot_status(struct dvb_ca_en50221 * en50221,int slot,int open)408 int netup_poll_ci_slot_status(struct dvb_ca_en50221 *en50221,
409 int slot, int open)
410 {
411 struct netup_ci_state *state = en50221->data;
412
413 if (0 != slot)
414 return -EINVAL;
415
416 netup_ci_set_irq(en50221, open ? (NETUP_IRQ_DETAM | ci_irq_flags())
417 : NETUP_IRQ_DETAM);
418
419 return state->status;
420 }
421
netup_ci_init(struct cx23885_tsport * port)422 int netup_ci_init(struct cx23885_tsport *port)
423 {
424 struct netup_ci_state *state;
425 u8 cimax_init[34] = {
426 0x00, /* module A control*/
427 0x00, /* auto select mask high A */
428 0x00, /* auto select mask low A */
429 0x00, /* auto select pattern high A */
430 0x00, /* auto select pattern low A */
431 0x44, /* memory access time A */
432 0x00, /* invert input A */
433 0x00, /* RFU */
434 0x00, /* RFU */
435 0x00, /* module B control*/
436 0x00, /* auto select mask high B */
437 0x00, /* auto select mask low B */
438 0x00, /* auto select pattern high B */
439 0x00, /* auto select pattern low B */
440 0x44, /* memory access time B */
441 0x00, /* invert input B */
442 0x00, /* RFU */
443 0x00, /* RFU */
444 0x00, /* auto select mask high Ext */
445 0x00, /* auto select mask low Ext */
446 0x00, /* auto select pattern high Ext */
447 0x00, /* auto select pattern low Ext */
448 0x00, /* RFU */
449 0x02, /* destination - module A */
450 0x01, /* power on (use it like store place) */
451 0x00, /* RFU */
452 0x00, /* int status read only */
453 ci_irq_flags() | NETUP_IRQ_DETAM, /* DETAM, IRQAM unmasked */
454 0x05, /* EXTINT=active-high, INT=push-pull */
455 0x00, /* USCG1 */
456 0x04, /* ack active low */
457 0x00, /* LOCK = 0 */
458 0x33, /* serial mode, rising in, rising out, MSB first*/
459 0x31, /* synchronization */
460 };
461 int ret;
462
463 ci_dbg_print("%s\n", __func__);
464 state = kzalloc(sizeof(struct netup_ci_state), GFP_KERNEL);
465 if (!state) {
466 ci_dbg_print("%s: Unable create CI structure!\n", __func__);
467 ret = -ENOMEM;
468 goto err;
469 }
470
471 port->port_priv = state;
472
473 switch (port->nr) {
474 case 1:
475 state->ci_i2c_addr = 0x40;
476 break;
477 case 2:
478 state->ci_i2c_addr = 0x41;
479 break;
480 }
481
482 state->i2c_adap = &port->dev->i2c_bus[0].i2c_adap;
483 state->ca.owner = THIS_MODULE;
484 state->ca.read_attribute_mem = netup_ci_read_attribute_mem;
485 state->ca.write_attribute_mem = netup_ci_write_attribute_mem;
486 state->ca.read_cam_control = netup_ci_read_cam_ctl;
487 state->ca.write_cam_control = netup_ci_write_cam_ctl;
488 state->ca.slot_reset = netup_ci_slot_reset;
489 state->ca.slot_shutdown = netup_ci_slot_shutdown;
490 state->ca.slot_ts_enable = netup_ci_slot_ts_ctl;
491 state->ca.poll_slot_status = netup_poll_ci_slot_status;
492 state->ca.data = state;
493 state->priv = port;
494 state->current_irq_mode = ci_irq_flags() | NETUP_IRQ_DETAM;
495
496 ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
497 0, &cimax_init[0], 34);
498 /* lock registers */
499 ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
500 0x1f, &cimax_init[0x18], 1);
501 /* power on slots */
502 ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
503 0x18, &cimax_init[0x18], 1);
504
505 if (0 != ret)
506 goto err;
507
508 ret = dvb_ca_en50221_init(&port->frontends.adapter,
509 &state->ca,
510 /* flags */ 0,
511 /* n_slots */ 1);
512 if (0 != ret)
513 goto err;
514
515 INIT_WORK(&state->work, netup_read_ci_status);
516 schedule_work(&state->work);
517
518 ci_dbg_print("%s: CI initialized!\n", __func__);
519
520 return 0;
521 err:
522 ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
523 kfree(state);
524 return ret;
525 }
526
netup_ci_exit(struct cx23885_tsport * port)527 void netup_ci_exit(struct cx23885_tsport *port)
528 {
529 struct netup_ci_state *state;
530
531 if (NULL == port)
532 return;
533
534 state = (struct netup_ci_state *)port->port_priv;
535 if (NULL == state)
536 return;
537
538 if (NULL == state->ca.data)
539 return;
540
541 dvb_ca_en50221_release(&state->ca);
542 kfree(state);
543 }
544
