1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2020-2021 NXP
4 */
5
6 #include <linux/init.h>
7 #include <linux/interconnect.h>
8 #include <linux/ioctl.h>
9 #include <linux/list.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/of_address.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/rational.h>
17 #include <linux/time64.h>
18 #include <media/videobuf2-v4l2.h>
19 #include <media/videobuf2-dma-contig.h>
20 #include <linux/videodev2.h>
21 #include "vpu.h"
22 #include "vpu_rpc.h"
23 #include "vpu_defs.h"
24 #include "vpu_helpers.h"
25 #include "vpu_v4l2.h"
26 #include "vpu_cmds.h"
27 #include "vpu_imx8q.h"
28 #include "vpu_malone.h"
29
30 #define CMD_SIZE 25600
31 #define MSG_SIZE 25600
32 #define CODEC_SIZE 0x1000
33 #define JPEG_SIZE 0x1000
34 #define SEQ_SIZE 0x1000
35 #define GOP_SIZE 0x1000
36 #define PIC_SIZE 0x1000
37 #define QMETER_SIZE 0x1000
38 #define DBGLOG_SIZE 0x10000
39 #define DEBUG_SIZE 0x80000
40 #define ENG_SIZE 0x1000
41 #define MALONE_SKIPPED_FRAME_ID 0x555
42
43 #define MALONE_ALIGN_MBI 0x800
44 #define MALONE_DCP_CHUNK_BIT 16
45 #define MALONE_DCP_SIZE_MAX 0x3000000
46 #define MALONE_DCP_SIZE_MIN 0x100000
47 #define MALONE_DCP_FIXED_MB_ALLOC 250
48
49 #define CONFIG_SET(val, cfg, pos, mask) \
50 (*(cfg) |= (((val) << (pos)) & (mask)))
51 //x means source data , y means destination data
52 #define STREAM_CONFIG_FORMAT_SET(x, y) CONFIG_SET(x, y, 0, 0x0000000F)
53 #define STREAM_CONFIG_STRBUFIDX_SET(x, y) CONFIG_SET(x, y, 8, 0x00000300)
54 #define STREAM_CONFIG_NOSEQ_SET(x, y) CONFIG_SET(x, y, 10, 0x00000400)
55 #define STREAM_CONFIG_DEBLOCK_SET(x, y) CONFIG_SET(x, y, 11, 0x00000800)
56 #define STREAM_CONFIG_DERING_SET(x, y) CONFIG_SET(x, y, 12, 0x00001000)
57 #define STREAM_CONFIG_IBWAIT_SET(x, y) CONFIG_SET(x, y, 13, 0x00002000)
58 #define STREAM_CONFIG_FBC_SET(x, y) CONFIG_SET(x, y, 14, 0x00004000)
59 #define STREAM_CONFIG_PLAY_MODE_SET(x, y) CONFIG_SET(x, y, 16, 0x00030000)
60 #define STREAM_CONFIG_ENABLE_DCP_SET(x, y) CONFIG_SET(x, y, 20, 0x00100000)
61 #define STREAM_CONFIG_NUM_STR_BUF_SET(x, y) CONFIG_SET(x, y, 21, 0x00600000)
62 #define STREAM_CONFIG_MALONE_USAGE_SET(x, y) CONFIG_SET(x, y, 23, 0x01800000)
63 #define STREAM_CONFIG_MULTI_VID_SET(x, y) CONFIG_SET(x, y, 25, 0x02000000)
64 #define STREAM_CONFIG_OBFUSC_EN_SET(x, y) CONFIG_SET(x, y, 26, 0x04000000)
65 #define STREAM_CONFIG_RC4_EN_SET(x, y) CONFIG_SET(x, y, 27, 0x08000000)
66 #define STREAM_CONFIG_MCX_SET(x, y) CONFIG_SET(x, y, 28, 0x10000000)
67 #define STREAM_CONFIG_PES_SET(x, y) CONFIG_SET(x, y, 29, 0x20000000)
68 #define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000)
69 #define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000)
70
71 enum vpu_malone_stream_input_mode {
72 INVALID_MODE = 0,
73 FRAME_LVL,
74 NON_FRAME_LVL
75 };
76
77 enum vpu_malone_format {
78 MALONE_FMT_NULL = 0x0,
79 MALONE_FMT_AVC = 0x1,
80 MALONE_FMT_MP2 = 0x2,
81 MALONE_FMT_VC1 = 0x3,
82 MALONE_FMT_AVS = 0x4,
83 MALONE_FMT_ASP = 0x5,
84 MALONE_FMT_JPG = 0x6,
85 MALONE_FMT_RV = 0x7,
86 MALONE_FMT_VP6 = 0x8,
87 MALONE_FMT_SPK = 0x9,
88 MALONE_FMT_VP8 = 0xA,
89 MALONE_FMT_HEVC = 0xB,
90 MALONE_FMT_LAST = MALONE_FMT_HEVC
91 };
92
93 enum {
94 VID_API_CMD_NULL = 0x00,
95 VID_API_CMD_PARSE_NEXT_SEQ = 0x01,
96 VID_API_CMD_PARSE_NEXT_I = 0x02,
97 VID_API_CMD_PARSE_NEXT_IP = 0x03,
98 VID_API_CMD_PARSE_NEXT_ANY = 0x04,
99 VID_API_CMD_DEC_PIC = 0x05,
100 VID_API_CMD_UPDATE_ES_WR_PTR = 0x06,
101 VID_API_CMD_UPDATE_ES_RD_PTR = 0x07,
102 VID_API_CMD_UPDATE_UDATA = 0x08,
103 VID_API_CMD_GET_FSINFO = 0x09,
104 VID_API_CMD_SKIP_PIC = 0x0a,
105 VID_API_CMD_DEC_CHUNK = 0x0b,
106 VID_API_CMD_START = 0x10,
107 VID_API_CMD_STOP = 0x11,
108 VID_API_CMD_ABORT = 0x12,
109 VID_API_CMD_RST_BUF = 0x13,
110 VID_API_CMD_FS_RELEASE = 0x15,
111 VID_API_CMD_MEM_REGION_ATTACH = 0x16,
112 VID_API_CMD_MEM_REGION_DETACH = 0x17,
113 VID_API_CMD_MVC_VIEW_SELECT = 0x18,
114 VID_API_CMD_FS_ALLOC = 0x19,
115 VID_API_CMD_DBG_GET_STATUS = 0x1C,
116 VID_API_CMD_DBG_START_LOG = 0x1D,
117 VID_API_CMD_DBG_STOP_LOG = 0x1E,
118 VID_API_CMD_DBG_DUMP_LOG = 0x1F,
119 VID_API_CMD_YUV_READY = 0x20,
120 VID_API_CMD_TS = 0x21,
121
122 VID_API_CMD_FIRM_RESET = 0x40,
123
124 VID_API_CMD_SNAPSHOT = 0xAA,
125 VID_API_CMD_ROLL_SNAPSHOT = 0xAB,
126 VID_API_CMD_LOCK_SCHEDULER = 0xAC,
127 VID_API_CMD_UNLOCK_SCHEDULER = 0xAD,
128 VID_API_CMD_CQ_FIFO_DUMP = 0xAE,
129 VID_API_CMD_DBG_FIFO_DUMP = 0xAF,
130 VID_API_CMD_SVC_ILP = 0xBB,
131 VID_API_CMD_FW_STATUS = 0xF0,
132 VID_API_CMD_INVALID = 0xFF
133 };
134
135 enum {
136 VID_API_EVENT_NULL = 0x00,
137 VID_API_EVENT_RESET_DONE = 0x01,
138 VID_API_EVENT_SEQ_HDR_FOUND = 0x02,
139 VID_API_EVENT_PIC_HDR_FOUND = 0x03,
140 VID_API_EVENT_PIC_DECODED = 0x04,
141 VID_API_EVENT_FIFO_LOW = 0x05,
142 VID_API_EVENT_FIFO_HIGH = 0x06,
143 VID_API_EVENT_FIFO_EMPTY = 0x07,
144 VID_API_EVENT_FIFO_FULL = 0x08,
145 VID_API_EVENT_BS_ERROR = 0x09,
146 VID_API_EVENT_UDATA_FIFO_UPTD = 0x0A,
147 VID_API_EVENT_RES_CHANGE = 0x0B,
148 VID_API_EVENT_FIFO_OVF = 0x0C,
149 VID_API_EVENT_CHUNK_DECODED = 0x0D,
150 VID_API_EVENT_REQ_FRAME_BUFF = 0x10,
151 VID_API_EVENT_FRAME_BUFF_RDY = 0x11,
152 VID_API_EVENT_REL_FRAME_BUFF = 0x12,
153 VID_API_EVENT_STR_BUF_RST = 0x13,
154 VID_API_EVENT_RET_PING = 0x14,
155 VID_API_EVENT_QMETER = 0x15,
156 VID_API_EVENT_STR_FMT_CHANGE = 0x16,
157 VID_API_EVENT_FIRMWARE_XCPT = 0x17,
158 VID_API_EVENT_START_DONE = 0x18,
159 VID_API_EVENT_STOPPED = 0x19,
160 VID_API_EVENT_ABORT_DONE = 0x1A,
161 VID_API_EVENT_FINISHED = 0x1B,
162 VID_API_EVENT_DBG_STAT_UPDATE = 0x1C,
163 VID_API_EVENT_DBG_LOG_STARTED = 0x1D,
164 VID_API_EVENT_DBG_LOG_STOPPED = 0x1E,
165 VID_API_EVENT_DBG_LOG_UPDATED = 0x1F,
166 VID_API_EVENT_DBG_MSG_DEC = 0x20,
167 VID_API_EVENT_DEC_SC_ERR = 0x21,
168 VID_API_EVENT_CQ_FIFO_DUMP = 0x22,
169 VID_API_EVENT_DBG_FIFO_DUMP = 0x23,
170 VID_API_EVENT_DEC_CHECK_RES = 0x24,
171 VID_API_EVENT_DEC_CFG_INFO = 0x25,
172 VID_API_EVENT_UNSUPPORTED_STREAM = 0x26,
173 VID_API_EVENT_PIC_SKIPPED = 0x27,
174 VID_API_EVENT_STR_SUSPENDED = 0x30,
175 VID_API_EVENT_SNAPSHOT_DONE = 0x40,
176 VID_API_EVENT_FW_STATUS = 0xF0,
177 VID_API_EVENT_INVALID = 0xFF
178 };
179
180 struct vpu_malone_buffer_desc {
181 struct vpu_rpc_buffer_desc buffer;
182 u32 low;
183 u32 high;
184 };
185
186 struct vpu_malone_str_buffer {
187 u32 wptr;
188 u32 rptr;
189 u32 start;
190 u32 end;
191 u32 lwm;
192 };
193
194 struct vpu_malone_picth_info {
195 u32 frame_pitch;
196 };
197
198 struct vpu_malone_table_desc {
199 u32 array_base;
200 u32 size;
201 };
202
203 struct vpu_malone_dbglog_desc {
204 u32 addr;
205 u32 size;
206 u32 level;
207 u32 reserved;
208 };
209
210 struct vpu_malone_frame_buffer {
211 u32 addr;
212 u32 size;
213 };
214
215 struct vpu_malone_udata {
216 u32 base;
217 u32 total_size;
218 u32 slot_size;
219 };
220
221 struct vpu_malone_buffer_info {
222 u32 stream_input_mode;
223 u32 stream_pic_input_count;
224 u32 stream_pic_parsed_count;
225 u32 stream_buffer_threshold;
226 u32 stream_pic_end_flag;
227 };
228
229 struct vpu_malone_encrypt_info {
230 u32 rec4key[8];
231 u32 obfusc;
232 };
233
234 struct malone_iface {
235 u32 exec_base_addr;
236 u32 exec_area_size;
237 struct vpu_malone_buffer_desc cmd_buffer_desc;
238 struct vpu_malone_buffer_desc msg_buffer_desc;
239 u32 cmd_int_enable[VID_API_NUM_STREAMS];
240 struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS];
241 u32 stream_config[VID_API_NUM_STREAMS];
242 struct vpu_malone_table_desc codec_param_tab_desc;
243 struct vpu_malone_table_desc jpeg_param_tab_desc;
244 u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR];
245 struct vpu_malone_table_desc seq_info_tab_desc;
246 struct vpu_malone_table_desc pic_info_tab_desc;
247 struct vpu_malone_table_desc gop_info_tab_desc;
248 struct vpu_malone_table_desc qmeter_info_tab_desc;
249 u32 stream_error[VID_API_NUM_STREAMS];
250 u32 fw_version;
251 u32 fw_offset;
252 u32 max_streams;
253 struct vpu_malone_dbglog_desc dbglog_desc;
254 struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS];
255 struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS];
256 struct vpu_malone_buffer_desc debug_buffer_desc;
257 struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS];
258 u32 encrypt_info[VID_API_NUM_STREAMS];
259 struct vpu_rpc_system_config system_cfg;
260 u32 api_version;
261 struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS];
262 };
263
264 struct malone_jpg_params {
265 u32 rotation_angle;
266 u32 horiz_scale_factor;
267 u32 vert_scale_factor;
268 u32 rotation_mode;
269 u32 rgb_mode;
270 u32 chunk_mode; /* 0 ~ 1 */
271 u32 last_chunk; /* 0 ~ 1 */
272 u32 chunk_rows; /* 0 ~ 255 */
273 u32 num_bytes;
274 u32 jpg_crop_x;
275 u32 jpg_crop_y;
276 u32 jpg_crop_width;
277 u32 jpg_crop_height;
278 u32 jpg_mjpeg_mode;
279 u32 jpg_mjpeg_interlaced;
280 };
281
282 struct malone_codec_params {
283 u32 disp_imm;
284 u32 fourcc;
285 u32 codec_version;
286 u32 frame_rate;
287 u32 dbglog_enable;
288 u32 bsdma_lwm;
289 u32 bbd_coring;
290 u32 bbd_s_thr_row;
291 u32 bbd_p_thr_row;
292 u32 bbd_s_thr_logo_row;
293 u32 bbd_p_thr_logo_row;
294 u32 bbd_s_thr_col;
295 u32 bbd_p_thr_col;
296 u32 bbd_chr_thr_row;
297 u32 bbd_chr_thr_col;
298 u32 bbd_uv_mid_level;
299 u32 bbd_excl_win_mb_left;
300 u32 bbd_excl_win_mb_right;
301 };
302
303 struct malone_padding_scode {
304 u32 scode_type;
305 u32 pixelformat;
306 u32 data[2];
307 };
308
309 struct malone_fmt_mapping {
310 u32 pixelformat;
311 enum vpu_malone_format malone_format;
312 u32 is_disabled;
313 };
314
315 struct malone_scode_t {
316 struct vpu_inst *inst;
317 struct vb2_buffer *vb;
318 u32 wptr;
319 u32 need_data;
320 };
321
322 struct malone_scode_handler {
323 u32 pixelformat;
324 int (*insert_scode_seq)(struct malone_scode_t *scode);
325 int (*insert_scode_pic)(struct malone_scode_t *scode);
326 };
327
328 struct vpu_dec_ctrl {
329 struct malone_codec_params *codec_param;
330 struct malone_jpg_params *jpg;
331 void *seq_mem;
332 void *pic_mem;
333 void *gop_mem;
334 void *qmeter_mem;
335 void *dbglog_mem;
336 struct vpu_malone_str_buffer __iomem *str_buf[VID_API_NUM_STREAMS];
337 u32 buf_addr[VID_API_NUM_STREAMS];
338 };
339
vpu_malone_get_data_size(void)340 u32 vpu_malone_get_data_size(void)
341 {
342 return sizeof(struct vpu_dec_ctrl);
343 }
344
vpu_malone_init_rpc(struct vpu_shared_addr * shared,struct vpu_buffer * rpc,dma_addr_t boot_addr)345 void vpu_malone_init_rpc(struct vpu_shared_addr *shared,
346 struct vpu_buffer *rpc, dma_addr_t boot_addr)
347 {
348 struct malone_iface *iface;
349 struct vpu_dec_ctrl *hc;
350 unsigned long base_phy_addr;
351 unsigned long phy_addr;
352 unsigned long offset;
353 unsigned int i;
354
355 if (rpc->phys < boot_addr)
356 return;
357
358 iface = rpc->virt;
359 base_phy_addr = rpc->phys - boot_addr;
360 hc = shared->priv;
361
362 shared->iface = iface;
363 shared->boot_addr = boot_addr;
364
365 iface->exec_base_addr = base_phy_addr;
366 iface->exec_area_size = rpc->length;
367
368 offset = sizeof(struct malone_iface);
369 phy_addr = base_phy_addr + offset;
370
371 shared->cmd_desc = &iface->cmd_buffer_desc.buffer;
372 shared->cmd_mem_vir = rpc->virt + offset;
373 iface->cmd_buffer_desc.buffer.start =
374 iface->cmd_buffer_desc.buffer.rptr =
375 iface->cmd_buffer_desc.buffer.wptr = phy_addr;
376 iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE;
377 offset += CMD_SIZE;
378 phy_addr = base_phy_addr + offset;
379
380 shared->msg_desc = &iface->msg_buffer_desc.buffer;
381 shared->msg_mem_vir = rpc->virt + offset;
382 iface->msg_buffer_desc.buffer.start =
383 iface->msg_buffer_desc.buffer.wptr =
384 iface->msg_buffer_desc.buffer.rptr = phy_addr;
385 iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE;
386 offset += MSG_SIZE;
387 phy_addr = base_phy_addr + offset;
388
389 iface->codec_param_tab_desc.array_base = phy_addr;
390 hc->codec_param = rpc->virt + offset;
391 offset += CODEC_SIZE;
392 phy_addr = base_phy_addr + offset;
393
394 iface->jpeg_param_tab_desc.array_base = phy_addr;
395 hc->jpg = rpc->virt + offset;
396 offset += JPEG_SIZE;
397 phy_addr = base_phy_addr + offset;
398
399 iface->seq_info_tab_desc.array_base = phy_addr;
400 hc->seq_mem = rpc->virt + offset;
401 offset += SEQ_SIZE;
402 phy_addr = base_phy_addr + offset;
403
404 iface->pic_info_tab_desc.array_base = phy_addr;
405 hc->pic_mem = rpc->virt + offset;
406 offset += PIC_SIZE;
407 phy_addr = base_phy_addr + offset;
408
409 iface->gop_info_tab_desc.array_base = phy_addr;
410 hc->gop_mem = rpc->virt + offset;
411 offset += GOP_SIZE;
412 phy_addr = base_phy_addr + offset;
413
414 iface->qmeter_info_tab_desc.array_base = phy_addr;
415 hc->qmeter_mem = rpc->virt + offset;
416 offset += QMETER_SIZE;
417 phy_addr = base_phy_addr + offset;
418
419 iface->dbglog_desc.addr = phy_addr;
420 iface->dbglog_desc.size = DBGLOG_SIZE;
421 hc->dbglog_mem = rpc->virt + offset;
422 offset += DBGLOG_SIZE;
423 phy_addr = base_phy_addr + offset;
424
425 for (i = 0; i < VID_API_NUM_STREAMS; i++) {
426 iface->eng_access_buff_desc[i].buffer.start =
427 iface->eng_access_buff_desc[i].buffer.wptr =
428 iface->eng_access_buff_desc[i].buffer.rptr = phy_addr;
429 iface->eng_access_buff_desc[i].buffer.end =
430 iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE;
431 offset += ENG_SIZE;
432 phy_addr = base_phy_addr + offset;
433 }
434
435 for (i = 0; i < VID_API_NUM_STREAMS; i++) {
436 iface->encrypt_info[i] = phy_addr;
437 offset += sizeof(struct vpu_malone_encrypt_info);
438 phy_addr = base_phy_addr + offset;
439 }
440
441 rpc->bytesused = offset;
442 }
443
vpu_malone_set_log_buf(struct vpu_shared_addr * shared,struct vpu_buffer * log)444 void vpu_malone_set_log_buf(struct vpu_shared_addr *shared,
445 struct vpu_buffer *log)
446 {
447 struct malone_iface *iface = shared->iface;
448
449 iface->debug_buffer_desc.buffer.start =
450 iface->debug_buffer_desc.buffer.wptr =
451 iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr;
452 iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length;
453 }
454
get_str_buffer_offset(u32 instance)455 static u32 get_str_buffer_offset(u32 instance)
456 {
457 return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance;
458 }
459
vpu_malone_set_system_cfg(struct vpu_shared_addr * shared,u32 regs_base,void __iomem * regs,u32 core_id)460 void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared,
461 u32 regs_base, void __iomem *regs, u32 core_id)
462 {
463 struct malone_iface *iface = shared->iface;
464 struct vpu_rpc_system_config *config = &iface->system_cfg;
465 struct vpu_dec_ctrl *hc = shared->priv;
466 int i;
467
468 vpu_imx8q_set_system_cfg_common(config, regs_base, core_id);
469 for (i = 0; i < VID_API_NUM_STREAMS; i++) {
470 u32 offset = get_str_buffer_offset(i);
471
472 hc->buf_addr[i] = regs_base + offset;
473 hc->str_buf[i] = regs + offset;
474 }
475 }
476
vpu_malone_get_version(struct vpu_shared_addr * shared)477 u32 vpu_malone_get_version(struct vpu_shared_addr *shared)
478 {
479 struct malone_iface *iface = shared->iface;
480
481 return iface->fw_version;
482 }
483
vpu_malone_get_stream_buffer_size(struct vpu_shared_addr * shared)484 int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared)
485 {
486 return 0xc00000;
487 }
488
vpu_malone_config_stream_buffer(struct vpu_shared_addr * shared,u32 instance,struct vpu_buffer * buf)489 int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared,
490 u32 instance,
491 struct vpu_buffer *buf)
492 {
493 struct malone_iface *iface = shared->iface;
494 struct vpu_dec_ctrl *hc = shared->priv;
495 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
496
497 writel(buf->phys, &str_buf->start);
498 writel(buf->phys, &str_buf->rptr);
499 writel(buf->phys, &str_buf->wptr);
500 writel(buf->phys + buf->length, &str_buf->end);
501 writel(0x1, &str_buf->lwm);
502
503 iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance];
504
505 return 0;
506 }
507
vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr * shared,u32 instance,struct vpu_rpc_buffer_desc * desc)508 int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared,
509 u32 instance,
510 struct vpu_rpc_buffer_desc *desc)
511 {
512 struct vpu_dec_ctrl *hc = shared->priv;
513 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
514
515 if (desc) {
516 desc->wptr = readl(&str_buf->wptr);
517 desc->rptr = readl(&str_buf->rptr);
518 desc->start = readl(&str_buf->start);
519 desc->end = readl(&str_buf->end);
520 }
521
522 return 0;
523 }
524
vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem * str_buf,u32 wptr)525 static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr)
526 {
527 /*update wptr after data is written*/
528 mb();
529 writel(wptr, &str_buf->wptr);
530 }
531
vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem * str_buf,u32 rptr)532 static void vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 rptr)
533 {
534 /*update rptr after data is read*/
535 mb();
536 writel(rptr, &str_buf->rptr);
537 }
538
vpu_malone_update_stream_buffer(struct vpu_shared_addr * shared,u32 instance,u32 ptr,bool write)539 int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared,
540 u32 instance, u32 ptr, bool write)
541 {
542 struct vpu_dec_ctrl *hc = shared->priv;
543 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
544
545 if (write)
546 vpu_malone_update_wptr(str_buf, ptr);
547 else
548 vpu_malone_update_rptr(str_buf, ptr);
549
550 return 0;
551 }
552
553 static struct malone_fmt_mapping fmt_mappings[] = {
554 {V4L2_PIX_FMT_H264, MALONE_FMT_AVC},
555 {V4L2_PIX_FMT_H264_MVC, MALONE_FMT_AVC},
556 {V4L2_PIX_FMT_HEVC, MALONE_FMT_HEVC},
557 {V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1},
558 {V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1},
559 {V4L2_PIX_FMT_MPEG2, MALONE_FMT_MP2},
560 {V4L2_PIX_FMT_MPEG4, MALONE_FMT_ASP},
561 {V4L2_PIX_FMT_XVID, MALONE_FMT_ASP},
562 {V4L2_PIX_FMT_H263, MALONE_FMT_ASP},
563 {V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG},
564 {V4L2_PIX_FMT_VP8, MALONE_FMT_VP8},
565 };
566
vpu_malone_format_remap(u32 pixelformat)567 static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat)
568 {
569 u32 i;
570
571 for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
572 if (fmt_mappings[i].is_disabled)
573 continue;
574 if (pixelformat == fmt_mappings[i].pixelformat)
575 return fmt_mappings[i].malone_format;
576 }
577
578 return MALONE_FMT_NULL;
579 }
580
vpu_malone_check_fmt(enum vpu_core_type type,u32 pixelfmt)581 bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt)
582 {
583 if (!vpu_imx8q_check_fmt(type, pixelfmt))
584 return false;
585
586 if (pixelfmt == V4L2_PIX_FMT_NV12M_8L128 || pixelfmt == V4L2_PIX_FMT_NV12M_10BE_8L128)
587 return true;
588 if (vpu_malone_format_remap(pixelfmt) == MALONE_FMT_NULL)
589 return false;
590
591 return true;
592 }
593
vpu_malone_set_stream_cfg(struct vpu_shared_addr * shared,u32 instance,enum vpu_malone_format malone_format)594 static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared,
595 u32 instance,
596 enum vpu_malone_format malone_format)
597 {
598 struct malone_iface *iface = shared->iface;
599 u32 *curr_str_cfg = &iface->stream_config[instance];
600
601 *curr_str_cfg = 0;
602 STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg);
603 STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg);
604 STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg);
605 STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg);
606 STREAM_CONFIG_DERING_SET(0, curr_str_cfg);
607 STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg);
608 STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg);
609 STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg);
610 STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg);
611 STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg);
612 STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg);
613 STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg);
614 STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg);
615 STREAM_CONFIG_MCX_SET(1, curr_str_cfg);
616 STREAM_CONFIG_PES_SET(0, curr_str_cfg);
617 STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg);
618 }
619
vpu_malone_set_params(struct vpu_shared_addr * shared,u32 instance,struct vpu_decode_params * params)620 static int vpu_malone_set_params(struct vpu_shared_addr *shared,
621 u32 instance,
622 struct vpu_decode_params *params)
623 {
624 struct malone_iface *iface = shared->iface;
625 struct vpu_dec_ctrl *hc = shared->priv;
626 enum vpu_malone_format malone_format;
627
628 malone_format = vpu_malone_format_remap(params->codec_format);
629 if (WARN_ON(malone_format == MALONE_FMT_NULL))
630 return -EINVAL;
631 iface->udata_buffer[instance].base = params->udata.base;
632 iface->udata_buffer[instance].slot_size = params->udata.size;
633
634 vpu_malone_set_stream_cfg(shared, instance, malone_format);
635
636 if (malone_format == MALONE_FMT_JPG) {
637 //1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B
638 hc->jpg[instance].jpg_mjpeg_mode = 1;
639 //0: JPGD_MJPEG_PROGRESSIVE
640 hc->jpg[instance].jpg_mjpeg_interlaced = 0;
641 }
642
643 hc->codec_param[instance].disp_imm = params->b_dis_reorder ? 1 : 0;
644 hc->codec_param[instance].dbglog_enable = 0;
645 iface->dbglog_desc.level = 0;
646
647 if (params->b_non_frame)
648 iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL;
649 else
650 iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL;
651 iface->stream_buff_info[instance].stream_buffer_threshold = 0;
652 iface->stream_buff_info[instance].stream_pic_input_count = 0;
653
654 return 0;
655 }
656
vpu_malone_is_non_frame_mode(struct vpu_shared_addr * shared,u32 instance)657 static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, u32 instance)
658 {
659 struct malone_iface *iface = shared->iface;
660
661 if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL)
662 return true;
663
664 return false;
665 }
666
vpu_malone_update_params(struct vpu_shared_addr * shared,u32 instance,struct vpu_decode_params * params)667 static int vpu_malone_update_params(struct vpu_shared_addr *shared,
668 u32 instance,
669 struct vpu_decode_params *params)
670 {
671 struct malone_iface *iface = shared->iface;
672
673 if (params->end_flag)
674 iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag;
675 params->end_flag = 0;
676
677 return 0;
678 }
679
vpu_malone_set_decode_params(struct vpu_shared_addr * shared,u32 instance,struct vpu_decode_params * params,u32 update)680 int vpu_malone_set_decode_params(struct vpu_shared_addr *shared,
681 u32 instance,
682 struct vpu_decode_params *params,
683 u32 update)
684 {
685 if (!params)
686 return -EINVAL;
687
688 if (!update)
689 return vpu_malone_set_params(shared, instance, params);
690 else
691 return vpu_malone_update_params(shared, instance, params);
692 }
693
694 static struct vpu_pair malone_cmds[] = {
695 {VPU_CMD_ID_START, VID_API_CMD_START},
696 {VPU_CMD_ID_STOP, VID_API_CMD_STOP},
697 {VPU_CMD_ID_ABORT, VID_API_CMD_ABORT},
698 {VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF},
699 {VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT},
700 {VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET},
701 {VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC},
702 {VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE},
703 {VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS},
704 {VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS},
705 };
706
707 static struct vpu_pair malone_msgs[] = {
708 {VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE},
709 {VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE},
710 {VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED},
711 {VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE},
712 {VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST},
713 {VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED},
714 {VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND},
715 {VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE},
716 {VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND},
717 {VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED},
718 {VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY},
719 {VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF},
720 {VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF},
721 {VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW},
722 {VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR},
723 {VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM},
724 {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT},
725 {VPU_MSG_ID_PIC_SKIPPED, VID_API_EVENT_PIC_SKIPPED},
726 };
727
vpu_malone_pack_fs_alloc(struct vpu_rpc_event * pkt,struct vpu_fs_info * fs)728 static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt,
729 struct vpu_fs_info *fs)
730 {
731 const u32 fs_type[] = {
732 [MEM_RES_FRAME] = 0,
733 [MEM_RES_MBI] = 1,
734 [MEM_RES_DCP] = 2,
735 };
736
737 pkt->hdr.num = 7;
738 pkt->data[0] = fs->id | (fs->tag << 24);
739 pkt->data[1] = fs->luma_addr;
740 if (fs->type == MEM_RES_FRAME) {
741 /*
742 * if luma_addr equal to chroma_addr,
743 * means luma(plane[0]) and chromau(plane[1]) used the
744 * same fd -- usage of NXP codec2. Need to manually
745 * offset chroma addr.
746 */
747 if (fs->luma_addr == fs->chroma_addr)
748 fs->chroma_addr = fs->luma_addr + fs->luma_size;
749 pkt->data[2] = fs->luma_addr + fs->luma_size / 2;
750 pkt->data[3] = fs->chroma_addr;
751 pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2;
752 pkt->data[5] = fs->bytesperline;
753 } else {
754 pkt->data[2] = fs->luma_size;
755 pkt->data[3] = 0;
756 pkt->data[4] = 0;
757 pkt->data[5] = 0;
758 }
759 pkt->data[6] = fs_type[fs->type];
760 }
761
vpu_malone_pack_fs_release(struct vpu_rpc_event * pkt,struct vpu_fs_info * fs)762 static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt,
763 struct vpu_fs_info *fs)
764 {
765 pkt->hdr.num = 1;
766 pkt->data[0] = fs->id | (fs->tag << 24);
767 }
768
vpu_malone_pack_timestamp(struct vpu_rpc_event * pkt,struct vpu_ts_info * info)769 static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt,
770 struct vpu_ts_info *info)
771 {
772 struct timespec64 ts = ns_to_timespec64(info->timestamp);
773
774 pkt->hdr.num = 3;
775
776 pkt->data[0] = ts.tv_sec;
777 pkt->data[1] = ts.tv_nsec;
778 pkt->data[2] = info->size;
779 }
780
vpu_malone_pack_cmd(struct vpu_rpc_event * pkt,u32 index,u32 id,void * data)781 int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data)
782 {
783 int ret;
784
785 ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id);
786 if (ret < 0)
787 return ret;
788
789 pkt->hdr.id = ret;
790 pkt->hdr.num = 0;
791 pkt->hdr.index = index;
792
793 switch (id) {
794 case VPU_CMD_ID_FS_ALLOC:
795 vpu_malone_pack_fs_alloc(pkt, data);
796 break;
797 case VPU_CMD_ID_FS_RELEASE:
798 vpu_malone_pack_fs_release(pkt, data);
799 break;
800 case VPU_CMD_ID_TIMESTAMP:
801 vpu_malone_pack_timestamp(pkt, data);
802 break;
803 }
804
805 pkt->hdr.index = index;
806 return 0;
807 }
808
vpu_malone_convert_msg_id(u32 id)809 int vpu_malone_convert_msg_id(u32 id)
810 {
811 return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id);
812 }
813
vpu_malone_fill_planes(struct vpu_dec_codec_info * info)814 static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info)
815 {
816 u32 interlaced = info->progressive ? 0 : 1;
817
818 info->bytesperline[0] = 0;
819 info->sizeimage[0] = vpu_helper_get_plane_size(info->pixfmt,
820 info->decoded_width,
821 info->decoded_height,
822 0,
823 info->stride,
824 interlaced,
825 &info->bytesperline[0]);
826 info->bytesperline[1] = 0;
827 info->sizeimage[1] = vpu_helper_get_plane_size(info->pixfmt,
828 info->decoded_width,
829 info->decoded_height,
830 1,
831 info->stride,
832 interlaced,
833 &info->bytesperline[1]);
834 }
835
vpu_malone_init_seq_hdr(struct vpu_dec_codec_info * info)836 static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info)
837 {
838 u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT;
839
840 vpu_malone_fill_planes(info);
841
842 info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2;
843 info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI);
844
845 info->dcp_size = MALONE_DCP_SIZE_MAX;
846 if (chunks) {
847 u32 mb_num;
848 u32 mb_w;
849 u32 mb_h;
850
851 mb_w = DIV_ROUND_UP(info->decoded_width, 16);
852 mb_h = DIV_ROUND_UP(info->decoded_height, 16);
853 mb_num = mb_w * mb_h;
854 info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks;
855 info->dcp_size = clamp_t(u32, info->dcp_size,
856 MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX);
857 }
858 }
859
vpu_malone_unpack_seq_hdr(struct vpu_rpc_event * pkt,struct vpu_dec_codec_info * info)860 static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt,
861 struct vpu_dec_codec_info *info)
862 {
863 info->num_ref_frms = pkt->data[0];
864 info->num_dpb_frms = pkt->data[1];
865 info->num_dfe_area = pkt->data[2];
866 info->progressive = pkt->data[3];
867 info->width = pkt->data[5];
868 info->height = pkt->data[4];
869 info->decoded_width = pkt->data[12];
870 info->decoded_height = pkt->data[11];
871 info->frame_rate.numerator = 1000;
872 info->frame_rate.denominator = pkt->data[8];
873 info->dsp_asp_ratio = pkt->data[9];
874 info->level_idc = pkt->data[10];
875 info->bit_depth_luma = pkt->data[13];
876 info->bit_depth_chroma = pkt->data[14];
877 info->chroma_fmt = pkt->data[15];
878 info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]);
879 info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]);
880 info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]);
881 info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]);
882 info->vui_present = pkt->data[20];
883 info->mvc_num_views = pkt->data[21];
884 info->offset_x = pkt->data[23];
885 info->offset_y = pkt->data[25];
886 info->tag = pkt->data[27];
887 if (info->bit_depth_luma > 8)
888 info->pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128;
889 else
890 info->pixfmt = V4L2_PIX_FMT_NV12M_8L128;
891 if (info->frame_rate.numerator && info->frame_rate.denominator) {
892 unsigned long n, d;
893
894 rational_best_approximation(info->frame_rate.numerator,
895 info->frame_rate.denominator,
896 info->frame_rate.numerator,
897 info->frame_rate.denominator,
898 &n, &d);
899 info->frame_rate.numerator = n;
900 info->frame_rate.denominator = d;
901 }
902 vpu_malone_init_seq_hdr(info);
903 }
904
vpu_malone_unpack_pic_info(struct vpu_rpc_event * pkt,struct vpu_dec_pic_info * info)905 static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt,
906 struct vpu_dec_pic_info *info)
907 {
908 info->id = pkt->data[7];
909 info->luma = pkt->data[0];
910 info->start = pkt->data[10];
911 info->end = pkt->data[12];
912 info->pic_size = pkt->data[11];
913 info->stride = pkt->data[5];
914 info->consumed_count = pkt->data[13];
915 if (info->id == MALONE_SKIPPED_FRAME_ID)
916 info->skipped = 1;
917 else
918 info->skipped = 0;
919 }
920
vpu_malone_unpack_req_frame(struct vpu_rpc_event * pkt,struct vpu_fs_info * info)921 static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt,
922 struct vpu_fs_info *info)
923 {
924 info->type = pkt->data[1];
925 }
926
vpu_malone_unpack_rel_frame(struct vpu_rpc_event * pkt,struct vpu_fs_info * info)927 static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt,
928 struct vpu_fs_info *info)
929 {
930 info->id = pkt->data[0];
931 info->type = pkt->data[1];
932 info->not_displayed = pkt->data[2];
933 }
934
vpu_malone_unpack_buff_rdy(struct vpu_rpc_event * pkt,struct vpu_dec_pic_info * info)935 static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt,
936 struct vpu_dec_pic_info *info)
937 {
938 struct timespec64 ts = { pkt->data[9], pkt->data[10] };
939
940 info->id = pkt->data[0];
941 info->luma = pkt->data[1];
942 info->stride = pkt->data[3];
943 if (info->id == MALONE_SKIPPED_FRAME_ID)
944 info->skipped = 1;
945 else
946 info->skipped = 0;
947
948 info->timestamp = timespec64_to_ns(&ts);
949 }
950
vpu_malone_unpack_msg_data(struct vpu_rpc_event * pkt,void * data)951 int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data)
952 {
953 if (!pkt || !data)
954 return -EINVAL;
955
956 switch (pkt->hdr.id) {
957 case VID_API_EVENT_SEQ_HDR_FOUND:
958 vpu_malone_unpack_seq_hdr(pkt, data);
959 break;
960 case VID_API_EVENT_PIC_DECODED:
961 vpu_malone_unpack_pic_info(pkt, data);
962 break;
963 case VID_API_EVENT_REQ_FRAME_BUFF:
964 vpu_malone_unpack_req_frame(pkt, data);
965 break;
966 case VID_API_EVENT_REL_FRAME_BUFF:
967 vpu_malone_unpack_rel_frame(pkt, data);
968 break;
969 case VID_API_EVENT_FRAME_BUFF_RDY:
970 vpu_malone_unpack_buff_rdy(pkt, data);
971 break;
972 }
973
974 return 0;
975 }
976
977 static const struct malone_padding_scode padding_scodes[] = {
978 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264, {0x0B010000, 0}},
979 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}},
980 {SCODE_PADDING_EOS, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}},
981 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
982 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
983 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG2, {0xCC010000, 0x0}},
984 {SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}},
985 {SCODE_PADDING_EOS, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}},
986 {SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}},
987 {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}},
988 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}},
989 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}},
990 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}},
991 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}},
992 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
993 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
994 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG2, {0xb7010000, 0x0}},
995 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}},
996 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}},
997 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}},
998 {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}},
999 {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}},
1000 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}},
1001 {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}},
1002 };
1003
1004 static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0};
1005
get_padding_scode(u32 type,u32 fmt)1006 static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt)
1007 {
1008 const struct malone_padding_scode *s;
1009 int i;
1010
1011 for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) {
1012 s = &padding_scodes[i];
1013
1014 if (s->scode_type == type && s->pixelformat == fmt)
1015 return s;
1016 }
1017
1018 if (type != SCODE_PADDING_BUFFLUSH)
1019 return &padding_scode_dft;
1020
1021 return NULL;
1022 }
1023
vpu_malone_add_padding_scode(struct vpu_buffer * stream_buffer,struct vpu_malone_str_buffer __iomem * str_buf,u32 pixelformat,u32 scode_type)1024 static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer,
1025 struct vpu_malone_str_buffer __iomem *str_buf,
1026 u32 pixelformat, u32 scode_type)
1027 {
1028 u32 wptr;
1029 int size;
1030 int total_size = 0;
1031 const struct malone_padding_scode *ps;
1032 const u32 padding_size = 4096;
1033 int ret;
1034
1035 ps = get_padding_scode(scode_type, pixelformat);
1036 if (!ps)
1037 return -EINVAL;
1038
1039 wptr = readl(&str_buf->wptr);
1040 if (wptr < stream_buffer->phys || wptr > stream_buffer->phys + stream_buffer->length)
1041 return -EINVAL;
1042 if (wptr == stream_buffer->phys + stream_buffer->length)
1043 wptr = stream_buffer->phys;
1044 size = ALIGN(wptr, 4) - wptr;
1045 if (size)
1046 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
1047 total_size += size;
1048
1049 size = sizeof(ps->data);
1050 ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data);
1051 if (ret < 0)
1052 return -EINVAL;
1053 total_size += size;
1054
1055 size = padding_size - sizeof(ps->data);
1056 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
1057 total_size += size;
1058
1059 vpu_malone_update_wptr(str_buf, wptr);
1060 return total_size;
1061 }
1062
vpu_malone_add_scode(struct vpu_shared_addr * shared,u32 instance,struct vpu_buffer * stream_buffer,u32 pixelformat,u32 scode_type)1063 int vpu_malone_add_scode(struct vpu_shared_addr *shared,
1064 u32 instance,
1065 struct vpu_buffer *stream_buffer,
1066 u32 pixelformat,
1067 u32 scode_type)
1068 {
1069 struct vpu_dec_ctrl *hc = shared->priv;
1070 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
1071 int ret = -EINVAL;
1072
1073 switch (scode_type) {
1074 case SCODE_PADDING_EOS:
1075 case SCODE_PADDING_ABORT:
1076 case SCODE_PADDING_BUFFLUSH:
1077 ret = vpu_malone_add_padding_scode(stream_buffer, str_buf, pixelformat, scode_type);
1078 break;
1079 default:
1080 break;
1081 }
1082
1083 return ret;
1084 }
1085
1086 #define MALONE_PAYLOAD_HEADER_SIZE 16
1087 #define MALONE_CODEC_VERSION_ID 0x1
1088 #define MALONE_CODEC_ID_VC1_SIMPLE 0x10
1089 #define MALONE_CODEC_ID_VC1_MAIN 0x11
1090 #define MALONE_CODEC_ID_ARV8 0x28
1091 #define MALONE_CODEC_ID_ARV9 0x29
1092 #define MALONE_CODEC_ID_VP6 0x36
1093 #define MALONE_CODEC_ID_VP8 0x36
1094 #define MALONE_CODEC_ID_DIVX3 0x38
1095 #define MALONE_CODEC_ID_SPK 0x39
1096
1097 #define MALONE_VP8_IVF_SEQ_HEADER_LEN 32
1098 #define MALONE_VP8_IVF_FRAME_HEADER_LEN 8
1099
1100 #define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85
1101 #define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5
1102 #define MALONE_VC1_RCV_NUM_FRAMES 0xFF
1103 #define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4
1104 #define MALONE_VC1_RCV_SEQ_HEADER_LEN 20
1105 #define MALONE_VC1_RCV_PIC_HEADER_LEN 4
1106 #define MALONE_VC1_NAL_HEADER_LEN 4
1107 #define MALONE_VC1_CONTAIN_NAL(data) (((data) & 0x00FFFFFF) == 0x00010000)
1108
set_payload_hdr(u8 * dst,u32 scd_type,u32 codec_id,u32 buffer_size,u32 width,u32 height)1109 static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id,
1110 u32 buffer_size, u32 width, u32 height)
1111 {
1112 unsigned int payload_size;
1113 /* payload_size = buffer_size + itself_size(16) - start_code(4) */
1114 payload_size = buffer_size + 12;
1115
1116 dst[0] = 0x00;
1117 dst[1] = 0x00;
1118 dst[2] = 0x01;
1119 dst[3] = scd_type;
1120
1121 /* length */
1122 dst[4] = ((payload_size >> 16) & 0xff);
1123 dst[5] = ((payload_size >> 8) & 0xff);
1124 dst[6] = 0x4e;
1125 dst[7] = ((payload_size >> 0) & 0xff);
1126
1127 /* Codec ID and Version */
1128 dst[8] = codec_id;
1129 dst[9] = MALONE_CODEC_VERSION_ID;
1130
1131 /* width */
1132 dst[10] = ((width >> 8) & 0xff);
1133 dst[11] = ((width >> 0) & 0xff);
1134 dst[12] = 0x58;
1135
1136 /* height */
1137 dst[13] = ((height >> 8) & 0xff);
1138 dst[14] = ((height >> 0) & 0xff);
1139 dst[15] = 0x50;
1140 }
1141
set_vp8_ivf_seqhdr(u8 * dst,u32 width,u32 height)1142 static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height)
1143 {
1144 /* 0-3byte signature "DKIF" */
1145 dst[0] = 0x44;
1146 dst[1] = 0x4b;
1147 dst[2] = 0x49;
1148 dst[3] = 0x46;
1149 /* 4-5byte version: should be 0*/
1150 dst[4] = 0x00;
1151 dst[5] = 0x00;
1152 /* 6-7 length of Header */
1153 dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN;
1154 dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8;
1155 /* 8-11 VP8 fourcc */
1156 dst[8] = 0x56;
1157 dst[9] = 0x50;
1158 dst[10] = 0x38;
1159 dst[11] = 0x30;
1160 /* 12-13 width in pixels */
1161 dst[12] = width;
1162 dst[13] = width >> 8;
1163 /* 14-15 height in pixels */
1164 dst[14] = height;
1165 dst[15] = height >> 8;
1166 /* 16-19 frame rate */
1167 dst[16] = 0xe8;
1168 dst[17] = 0x03;
1169 dst[18] = 0x00;
1170 dst[19] = 0x00;
1171 /* 20-23 time scale */
1172 dst[20] = 0x01;
1173 dst[21] = 0x00;
1174 dst[22] = 0x00;
1175 dst[23] = 0x00;
1176 /* 24-27 number frames */
1177 dst[24] = 0xdf;
1178 dst[25] = 0xf9;
1179 dst[26] = 0x09;
1180 dst[27] = 0x00;
1181 /* 28-31 reserved */
1182 }
1183
set_vp8_ivf_pichdr(u8 * dst,u32 frame_size)1184 static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size)
1185 {
1186 /*
1187 * firmware just parse 64-bit timestamp(8 bytes).
1188 * As not transfer timestamp to firmware, use default value(ZERO).
1189 * No need to do anything here
1190 */
1191 }
1192
set_vc1_rcv_seqhdr(u8 * dst,u8 * src,u32 width,u32 height)1193 static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height)
1194 {
1195 u32 frames = MALONE_VC1_RCV_NUM_FRAMES;
1196 u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE;
1197
1198 /* 0-2 Number of frames, used default value 0xFF */
1199 dst[0] = frames;
1200 dst[1] = frames >> 8;
1201 dst[2] = frames >> 16;
1202
1203 /* 3 RCV version, used V1 */
1204 dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION;
1205
1206 /* 4-7 extension data size */
1207 dst[4] = ext_data_size;
1208 dst[5] = ext_data_size >> 8;
1209 dst[6] = ext_data_size >> 16;
1210 dst[7] = ext_data_size >> 24;
1211 /* 8-11 extension data */
1212 dst[8] = src[0];
1213 dst[9] = src[1];
1214 dst[10] = src[2];
1215 dst[11] = src[3];
1216
1217 /* height */
1218 dst[12] = height;
1219 dst[13] = (height >> 8) & 0xff;
1220 dst[14] = (height >> 16) & 0xff;
1221 dst[15] = (height >> 24) & 0xff;
1222 /* width */
1223 dst[16] = width;
1224 dst[17] = (width >> 8) & 0xff;
1225 dst[18] = (width >> 16) & 0xff;
1226 dst[19] = (width >> 24) & 0xff;
1227 }
1228
set_vc1_rcv_pichdr(u8 * dst,u32 buffer_size)1229 static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size)
1230 {
1231 dst[0] = buffer_size;
1232 dst[1] = buffer_size >> 8;
1233 dst[2] = buffer_size >> 16;
1234 dst[3] = buffer_size >> 24;
1235 }
1236
create_vc1_nal_pichdr(u8 * dst)1237 static void create_vc1_nal_pichdr(u8 *dst)
1238 {
1239 /* need insert nal header: special ID */
1240 dst[0] = 0x0;
1241 dst[1] = 0x0;
1242 dst[2] = 0x01;
1243 dst[3] = 0x0D;
1244 }
1245
vpu_malone_insert_scode_seq(struct malone_scode_t * scode,u32 codec_id,u32 ext_size)1246 static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
1247 {
1248 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
1249 int ret;
1250
1251 set_payload_hdr(hdr,
1252 SCODE_SEQUENCE,
1253 codec_id,
1254 ext_size,
1255 scode->inst->out_format.width,
1256 scode->inst->out_format.height);
1257 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1258 &scode->wptr,
1259 sizeof(hdr),
1260 hdr);
1261 if (ret < 0)
1262 return ret;
1263 return sizeof(hdr);
1264 }
1265
vpu_malone_insert_scode_pic(struct malone_scode_t * scode,u32 codec_id,u32 ext_size)1266 static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
1267 {
1268 u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
1269 int ret;
1270
1271 set_payload_hdr(hdr,
1272 SCODE_PICTURE,
1273 codec_id,
1274 ext_size + vb2_get_plane_payload(scode->vb, 0),
1275 scode->inst->out_format.width,
1276 scode->inst->out_format.height);
1277 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1278 &scode->wptr,
1279 sizeof(hdr),
1280 hdr);
1281 if (ret < 0)
1282 return ret;
1283 return sizeof(hdr);
1284 }
1285
vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t * scode)1286 static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode)
1287 {
1288 struct vb2_v4l2_buffer *vbuf;
1289 u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN];
1290 u32 *data = NULL;
1291 int ret;
1292
1293 vbuf = to_vb2_v4l2_buffer(scode->vb);
1294 data = vb2_plane_vaddr(scode->vb, 0);
1295
1296 if (scode->inst->total_input_count == 0 || vpu_vb_is_codecconfig(vbuf))
1297 return 0;
1298 if (MALONE_VC1_CONTAIN_NAL(*data))
1299 return 0;
1300
1301 create_vc1_nal_pichdr(nal_hdr);
1302 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1303 &scode->wptr,
1304 sizeof(nal_hdr),
1305 nal_hdr);
1306 if (ret < 0)
1307 return ret;
1308 return sizeof(nal_hdr);
1309 }
1310
vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t * scode)1311 static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode)
1312 {
1313 int ret;
1314 int size = 0;
1315 u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN];
1316
1317 if (scode->inst->total_input_count)
1318 return 0;
1319 scode->need_data = 0;
1320
1321 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, sizeof(rcv_seqhdr));
1322 if (ret < 0)
1323 return ret;
1324 size = ret;
1325
1326 set_vc1_rcv_seqhdr(rcv_seqhdr,
1327 vb2_plane_vaddr(scode->vb, 0),
1328 scode->inst->out_format.width,
1329 scode->inst->out_format.height);
1330 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1331 &scode->wptr,
1332 sizeof(rcv_seqhdr),
1333 rcv_seqhdr);
1334
1335 if (ret < 0)
1336 return ret;
1337 size += sizeof(rcv_seqhdr);
1338 return size;
1339 }
1340
vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t * scode)1341 static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode)
1342 {
1343 int ret;
1344 int size = 0;
1345 u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN];
1346
1347 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE,
1348 sizeof(rcv_pichdr));
1349 if (ret < 0)
1350 return ret;
1351 size = ret;
1352
1353 set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0));
1354 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1355 &scode->wptr,
1356 sizeof(rcv_pichdr),
1357 rcv_pichdr);
1358 if (ret < 0)
1359 return ret;
1360 size += sizeof(rcv_pichdr);
1361 return size;
1362 }
1363
vpu_malone_insert_scode_vp8_seq(struct malone_scode_t * scode)1364 static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode)
1365 {
1366 int ret;
1367 int size = 0;
1368 u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN];
1369
1370 ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
1371 if (ret < 0)
1372 return ret;
1373 size = ret;
1374
1375 set_vp8_ivf_seqhdr(ivf_hdr,
1376 scode->inst->out_format.width,
1377 scode->inst->out_format.height);
1378 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1379 &scode->wptr,
1380 sizeof(ivf_hdr),
1381 ivf_hdr);
1382 if (ret < 0)
1383 return ret;
1384 size += sizeof(ivf_hdr);
1385
1386 return size;
1387 }
1388
vpu_malone_insert_scode_vp8_pic(struct malone_scode_t * scode)1389 static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode)
1390 {
1391 int ret;
1392 int size = 0;
1393 u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0};
1394
1395 ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
1396 if (ret < 0)
1397 return ret;
1398 size = ret;
1399
1400 set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0));
1401 ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1402 &scode->wptr,
1403 sizeof(ivf_hdr),
1404 ivf_hdr);
1405 if (ret < 0)
1406 return ret;
1407 size += sizeof(ivf_hdr);
1408
1409 return size;
1410 }
1411
1412 static const struct malone_scode_handler scode_handlers[] = {
1413 {
1414 /* fix me, need to swap return operation after gstreamer swap */
1415 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L,
1416 .insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq,
1417 .insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic,
1418 },
1419 {
1420 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G,
1421 .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic,
1422 },
1423 {
1424 .pixelformat = V4L2_PIX_FMT_VP8,
1425 .insert_scode_seq = vpu_malone_insert_scode_vp8_seq,
1426 .insert_scode_pic = vpu_malone_insert_scode_vp8_pic,
1427 },
1428 };
1429
get_scode_handler(u32 pixelformat)1430 static const struct malone_scode_handler *get_scode_handler(u32 pixelformat)
1431 {
1432 int i;
1433
1434 for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) {
1435 if (scode_handlers[i].pixelformat == pixelformat)
1436 return &scode_handlers[i];
1437 }
1438
1439 return NULL;
1440 }
1441
vpu_malone_insert_scode(struct malone_scode_t * scode,u32 type)1442 static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type)
1443 {
1444 const struct malone_scode_handler *handler;
1445 int ret = 0;
1446
1447 if (!scode || !scode->inst || !scode->vb)
1448 return 0;
1449
1450 scode->need_data = 1;
1451 handler = get_scode_handler(scode->inst->out_format.pixfmt);
1452 if (!handler)
1453 return 0;
1454
1455 switch (type) {
1456 case SCODE_SEQUENCE:
1457 if (handler->insert_scode_seq)
1458 ret = handler->insert_scode_seq(scode);
1459 break;
1460 case SCODE_PICTURE:
1461 if (handler->insert_scode_pic)
1462 ret = handler->insert_scode_pic(scode);
1463 break;
1464 default:
1465 break;
1466 }
1467
1468 return ret;
1469 }
1470
vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem * str_buf,struct vpu_inst * inst,struct vb2_buffer * vb,u32 disp_imm)1471 static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem *str_buf,
1472 struct vpu_inst *inst, struct vb2_buffer *vb,
1473 u32 disp_imm)
1474 {
1475 struct malone_scode_t scode;
1476 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1477 u32 wptr = readl(&str_buf->wptr);
1478 int size = 0;
1479 int ret = 0;
1480
1481 /*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/
1482 scode.inst = inst;
1483 scode.vb = vb;
1484 scode.wptr = wptr;
1485 scode.need_data = 1;
1486 if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf))
1487 ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE);
1488
1489 if (ret < 0)
1490 return -ENOMEM;
1491 size += ret;
1492 wptr = scode.wptr;
1493 if (!scode.need_data) {
1494 vpu_malone_update_wptr(str_buf, wptr);
1495 return size;
1496 }
1497
1498 ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE);
1499 if (ret < 0)
1500 return -ENOMEM;
1501 size += ret;
1502 wptr = scode.wptr;
1503
1504 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
1505 &wptr,
1506 vb2_get_plane_payload(vb, 0),
1507 vb2_plane_vaddr(vb, 0));
1508 if (ret < 0)
1509 return -ENOMEM;
1510 size += vb2_get_plane_payload(vb, 0);
1511
1512 vpu_malone_update_wptr(str_buf, wptr);
1513
1514 if (disp_imm && !vpu_vb_is_codecconfig(vbuf)) {
1515 ret = vpu_malone_add_scode(inst->core->iface,
1516 inst->id,
1517 &inst->stream_buffer,
1518 inst->out_format.pixfmt,
1519 SCODE_PADDING_BUFFLUSH);
1520 if (ret < 0)
1521 return ret;
1522 size += ret;
1523 }
1524
1525 return size;
1526 }
1527
vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem * str_buf,struct vpu_inst * inst,struct vb2_buffer * vb)1528 static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem *str_buf,
1529 struct vpu_inst *inst, struct vb2_buffer *vb)
1530 {
1531 u32 wptr = readl(&str_buf->wptr);
1532 int ret = 0;
1533
1534 ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
1535 &wptr,
1536 vb2_get_plane_payload(vb, 0),
1537 vb2_plane_vaddr(vb, 0));
1538 if (ret < 0)
1539 return -ENOMEM;
1540
1541 vpu_malone_update_wptr(str_buf, wptr);
1542
1543 return ret;
1544 }
1545
vpu_malone_input_ts(struct vpu_inst * inst,s64 timestamp,u32 size)1546 static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size)
1547 {
1548 struct vpu_ts_info info;
1549
1550 memset(&info, 0, sizeof(info));
1551 info.timestamp = timestamp;
1552 info.size = size;
1553
1554 return vpu_session_fill_timestamp(inst, &info);
1555 }
1556
vpu_malone_input_frame(struct vpu_shared_addr * shared,struct vpu_inst * inst,struct vb2_buffer * vb)1557 int vpu_malone_input_frame(struct vpu_shared_addr *shared,
1558 struct vpu_inst *inst, struct vb2_buffer *vb)
1559 {
1560 struct vpu_dec_ctrl *hc = shared->priv;
1561 struct vb2_v4l2_buffer *vbuf;
1562 struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id];
1563 u32 disp_imm = hc->codec_param[inst->id].disp_imm;
1564 u32 size;
1565 int ret;
1566
1567 if (vpu_malone_is_non_frame_mode(shared, inst->id))
1568 ret = vpu_malone_input_stream_data(str_buf, inst, vb);
1569 else
1570 ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm);
1571 if (ret < 0)
1572 return ret;
1573 size = ret;
1574
1575 /*
1576 * if buffer only contain codec data, and the timestamp is invalid,
1577 * don't put the invalid timestamp to resync
1578 * merge the data to next frame
1579 */
1580 vbuf = to_vb2_v4l2_buffer(vb);
1581 if (vpu_vb_is_codecconfig(vbuf)) {
1582 inst->extra_size += size;
1583 return 0;
1584 }
1585 if (inst->extra_size) {
1586 size += inst->extra_size;
1587 inst->extra_size = 0;
1588 }
1589
1590 ret = vpu_malone_input_ts(inst, vb->timestamp, size);
1591 if (ret)
1592 return ret;
1593
1594 return 0;
1595 }
1596
vpu_malone_check_ready(struct vpu_shared_addr * shared,u32 instance)1597 static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance)
1598 {
1599 struct malone_iface *iface = shared->iface;
1600 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1601 u32 size = desc->end - desc->start;
1602 u32 rptr = desc->rptr;
1603 u32 wptr = desc->wptr;
1604 u32 used;
1605
1606 if (!size)
1607 return true;
1608
1609 used = (wptr + size - rptr) % size;
1610 if (used < (size / 2))
1611 return true;
1612
1613 return false;
1614 }
1615
vpu_malone_is_ready(struct vpu_shared_addr * shared,u32 instance)1616 bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance)
1617 {
1618 u32 cnt = 0;
1619
1620 while (!vpu_malone_check_ready(shared, instance)) {
1621 if (cnt > 30)
1622 return false;
1623 mdelay(1);
1624 cnt++;
1625 }
1626 return true;
1627 }
1628
vpu_malone_pre_cmd(struct vpu_shared_addr * shared,u32 instance)1629 int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance)
1630 {
1631 if (!vpu_malone_is_ready(shared, instance))
1632 return -EINVAL;
1633
1634 return 0;
1635 }
1636
vpu_malone_post_cmd(struct vpu_shared_addr * shared,u32 instance)1637 int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance)
1638 {
1639 struct malone_iface *iface = shared->iface;
1640 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1641
1642 desc->wptr++;
1643 if (desc->wptr == desc->end)
1644 desc->wptr = desc->start;
1645
1646 return 0;
1647 }
1648
vpu_malone_init_instance(struct vpu_shared_addr * shared,u32 instance)1649 int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance)
1650 {
1651 struct malone_iface *iface = shared->iface;
1652 struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1653
1654 desc->wptr = desc->rptr;
1655 if (desc->wptr == desc->end)
1656 desc->wptr = desc->start;
1657
1658 return 0;
1659 }
1660
vpu_malone_get_max_instance_count(struct vpu_shared_addr * shared)1661 u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared)
1662 {
1663 struct malone_iface *iface = shared->iface;
1664
1665 return iface->max_streams;
1666 }
1667
