1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "nbio_v7_9.h"
26 #include "amdgpu_ras.h"
27
28 #include "nbio/nbio_7_9_0_offset.h"
29 #include "nbio/nbio_7_9_0_sh_mask.h"
30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
31 #include <uapi/linux/kfd_ioctl.h>
32
33 #define NPS_MODE_MASK 0x000000FFL
34
35 /* Core 0 Port 0 counter */
36 #define smnPCIEP_NAK_COUNTER 0x1A340218
37
38 #define smnPCIE_PERF_CNTL_TXCLK3 0x1A38021c
39 #define smnPCIE_PERF_CNTL_TXCLK7 0x1A380888
40 #define smnPCIE_PERF_COUNT_CNTL 0x1A380200
41 #define smnPCIE_PERF_COUNT0_TXCLK3 0x1A380220
42 #define smnPCIE_PERF_COUNT0_TXCLK7 0x1A38088C
43 #define smnPCIE_PERF_COUNT0_UPVAL_TXCLK3 0x1A3808F8
44 #define smnPCIE_PERF_COUNT0_UPVAL_TXCLK7 0x1A380918
45
46
nbio_v7_9_remap_hdp_registers(struct amdgpu_device * adev)47 static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
48 {
49 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
50 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
51 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
52 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
53 }
54
nbio_v7_9_get_rev_id(struct amdgpu_device * adev)55 static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev)
56 {
57 u32 tmp;
58
59 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
60 tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, STRAP_ATI_REV_ID_DEV0_F0);
61
62 return tmp;
63 }
64
nbio_v7_9_mc_access_enable(struct amdgpu_device * adev,bool enable)65 static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)
66 {
67 if (enable)
68 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
69 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
70 else
71 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
72 }
73
nbio_v7_9_get_memsize(struct amdgpu_device * adev)74 static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev)
75 {
76 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
77 }
78
nbio_v7_9_sdma_doorbell_range(struct amdgpu_device * adev,int instance,bool use_doorbell,int doorbell_index,int doorbell_size)79 static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
80 bool use_doorbell, int doorbell_index, int doorbell_size)
81 {
82 u32 doorbell_range = 0, doorbell_ctrl = 0;
83 int aid_id, dev_inst;
84
85 dev_inst = GET_INST(SDMA0, instance);
86 aid_id = adev->sdma.instance[instance].aid_id;
87
88 if (use_doorbell == false)
89 return;
90
91 doorbell_range =
92 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
93 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index);
94 doorbell_range =
95 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
96 BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size);
97 doorbell_ctrl =
98 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
99 S2A_DOORBELL_PORT1_ENABLE, 1);
100 doorbell_ctrl =
101 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
102 S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size);
103
104 switch (dev_inst % adev->sdma.num_inst_per_aid) {
105 case 0:
106 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1,
107 4 * aid_id, doorbell_range);
108
109 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
110 S2A_DOORBELL_ENTRY_1_CTRL,
111 S2A_DOORBELL_PORT1_AWID, 0xe);
112 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
113 S2A_DOORBELL_ENTRY_1_CTRL,
114 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe);
115 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
116 S2A_DOORBELL_ENTRY_1_CTRL,
117 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
118 0x1);
119 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL,
120 aid_id, doorbell_ctrl);
121 break;
122 case 1:
123 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2,
124 4 * aid_id, doorbell_range);
125
126 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
127 S2A_DOORBELL_ENTRY_1_CTRL,
128 S2A_DOORBELL_PORT1_AWID, 0x8);
129 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
130 S2A_DOORBELL_ENTRY_1_CTRL,
131 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8);
132 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
133 S2A_DOORBELL_ENTRY_1_CTRL,
134 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
135 0x2);
136 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL,
137 aid_id, doorbell_ctrl);
138 break;
139 case 2:
140 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3,
141 4 * aid_id, doorbell_range);
142
143 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
144 S2A_DOORBELL_ENTRY_1_CTRL,
145 S2A_DOORBELL_PORT1_AWID, 0x9);
146 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
147 S2A_DOORBELL_ENTRY_1_CTRL,
148 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9);
149 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
150 S2A_DOORBELL_ENTRY_1_CTRL,
151 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
152 0x8);
153 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL,
154 aid_id, doorbell_ctrl);
155 break;
156 case 3:
157 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4,
158 4 * aid_id, doorbell_range);
159
160 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
161 S2A_DOORBELL_ENTRY_1_CTRL,
162 S2A_DOORBELL_PORT1_AWID, 0xa);
163 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
164 S2A_DOORBELL_ENTRY_1_CTRL,
165 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa);
166 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
167 S2A_DOORBELL_ENTRY_1_CTRL,
168 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
169 0x9);
170 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL,
171 aid_id, doorbell_ctrl);
172 break;
173 default:
174 break;
175 }
176
177 return;
178 }
179
nbio_v7_9_vcn_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index,int instance)180 static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
181 int doorbell_index, int instance)
182 {
183 u32 doorbell_range = 0, doorbell_ctrl = 0;
184 u32 aid_id = instance;
185
186 if (use_doorbell) {
187 doorbell_range = REG_SET_FIELD(doorbell_range,
188 DOORBELL0_CTRL_ENTRY_0,
189 BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
190 doorbell_index);
191 doorbell_range = REG_SET_FIELD(doorbell_range,
192 DOORBELL0_CTRL_ENTRY_0,
193 BIF_DOORBELL0_RANGE_SIZE_ENTRY,
194 0x9);
195 if (aid_id)
196 doorbell_range = REG_SET_FIELD(doorbell_range,
197 DOORBELL0_CTRL_ENTRY_0,
198 DOORBELL0_FENCE_ENABLE_ENTRY,
199 0x4);
200
201 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
202 S2A_DOORBELL_ENTRY_1_CTRL,
203 S2A_DOORBELL_PORT1_ENABLE, 1);
204 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
205 S2A_DOORBELL_ENTRY_1_CTRL,
206 S2A_DOORBELL_PORT1_AWID, 0x4);
207 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
208 S2A_DOORBELL_ENTRY_1_CTRL,
209 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4);
210 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
211 S2A_DOORBELL_ENTRY_1_CTRL,
212 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x9);
213 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
214 S2A_DOORBELL_ENTRY_1_CTRL,
215 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4);
216
217 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
218 aid_id, doorbell_range);
219 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
220 aid_id, doorbell_ctrl);
221 } else {
222 doorbell_range = REG_SET_FIELD(doorbell_range,
223 DOORBELL0_CTRL_ENTRY_0,
224 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
225 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
226 S2A_DOORBELL_ENTRY_1_CTRL,
227 S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
228
229 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
230 aid_id, doorbell_range);
231 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
232 aid_id, doorbell_ctrl);
233 }
234 }
235
nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)236 static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev,
237 bool enable)
238 {
239 /* Enable to allow doorbell pass thru on pre-silicon bare-metal */
240 WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff);
241 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
242 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
243 }
244
nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device * adev,bool enable)245 static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
246 bool enable)
247 {
248 u32 tmp = 0;
249
250 if (enable) {
251 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
252 DOORBELL_SELFRING_GPA_APER_EN, 1) |
253 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
254 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
255 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
256 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
257
258 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
259 lower_32_bits(adev->doorbell.base));
260 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
261 upper_32_bits(adev->doorbell.base));
262 }
263
264 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
265 }
266
nbio_v7_9_ih_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index)267 static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev,
268 bool use_doorbell, int doorbell_index)
269 {
270 u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0;
271
272 if (use_doorbell) {
273 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
274 DOORBELL0_CTRL_ENTRY_0,
275 BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
276 doorbell_index);
277 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
278 DOORBELL0_CTRL_ENTRY_0,
279 BIF_DOORBELL0_RANGE_SIZE_ENTRY,
280 0x8);
281
282 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
283 S2A_DOORBELL_ENTRY_1_CTRL,
284 S2A_DOORBELL_PORT1_ENABLE, 1);
285 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
286 S2A_DOORBELL_ENTRY_1_CTRL,
287 S2A_DOORBELL_PORT1_AWID, 0);
288 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
289 S2A_DOORBELL_ENTRY_1_CTRL,
290 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0);
291 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
292 S2A_DOORBELL_ENTRY_1_CTRL,
293 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8);
294 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
295 S2A_DOORBELL_ENTRY_1_CTRL,
296 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0);
297 } else {
298 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
299 DOORBELL0_CTRL_ENTRY_0,
300 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
301 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
302 S2A_DOORBELL_ENTRY_1_CTRL,
303 S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
304 }
305
306 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range);
307 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl);
308 }
309
310
nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)311 static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev,
312 bool enable)
313 {
314 }
315
nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)316 static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev,
317 bool enable)
318 {
319 }
320
nbio_v7_9_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)321 static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev,
322 u64 *flags)
323 {
324 }
325
nbio_v7_9_ih_control(struct amdgpu_device * adev)326 static void nbio_v7_9_ih_control(struct amdgpu_device *adev)
327 {
328 u32 interrupt_cntl;
329
330 /* setup interrupt control */
331 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
332 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
333 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
334 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
335 */
336 interrupt_cntl =
337 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
338 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
339 interrupt_cntl =
340 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
341 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
342 }
343
nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device * adev)344 static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev)
345 {
346 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
347 }
348
nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device * adev)349 static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev)
350 {
351 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
352 }
353
nbio_v7_9_get_pcie_index_offset(struct amdgpu_device * adev)354 static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev)
355 {
356 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
357 }
358
nbio_v7_9_get_pcie_data_offset(struct amdgpu_device * adev)359 static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev)
360 {
361 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
362 }
363
nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device * adev)364 static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev)
365 {
366 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI);
367 }
368
369 const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = {
370 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
371 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
372 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
373 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
374 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
375 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
376 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
377 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
378 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
379 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
380 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
381 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
382 .ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
383 .ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
384 .ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
385 .ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
386 .ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
387 .ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
388 };
389
nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device * adev,bool enable)390 static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev,
391 bool enable)
392 {
393 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL,
394 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
395 }
396
nbio_v7_9_get_compute_partition_mode(struct amdgpu_device * adev)397 static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev)
398 {
399 u32 tmp, px;
400
401 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
402 px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
403 PARTITION_MODE);
404
405 return px;
406 }
407
nbio_v7_9_get_memory_partition_mode(struct amdgpu_device * adev,u32 * supp_modes)408 static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,
409 u32 *supp_modes)
410 {
411 u32 tmp;
412
413 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
414 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
415
416 if (supp_modes) {
417 *supp_modes =
418 RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP);
419 }
420
421 return ffs(tmp);
422 }
423
nbio_v7_9_init_registers(struct amdgpu_device * adev)424 static void nbio_v7_9_init_registers(struct amdgpu_device *adev)
425 {
426 u32 inst_mask;
427 int i;
428
429 WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,
430 0xff & ~(adev->gfx.xcc_mask));
431
432 WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff);
433
434 inst_mask = adev->aid_mask & ~1U;
435 for_each_inst(i, inst_mask) {
436 WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i,
437 XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK);
438
439 }
440
441 if (!amdgpu_sriov_vf(adev)) {
442 u32 baco_cntl;
443 for_each_inst(i, adev->aid_mask) {
444 baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL);
445 if (baco_cntl & (BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
446 BIF_BX0_BACO_CNTL__BACO_EN_MASK)) {
447 baco_cntl &= ~(
448 BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
449 BIF_BX0_BACO_CNTL__BACO_EN_MASK);
450 dev_dbg(adev->dev,
451 "Unsetting baco dummy mode %x",
452 baco_cntl);
453 WREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL,
454 baco_cntl);
455 }
456 }
457 }
458 }
459
nbio_v7_9_get_pcie_replay_count(struct amdgpu_device * adev)460 static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev)
461 {
462 u32 val, nak_r, nak_g;
463
464 if (adev->flags & AMD_IS_APU)
465 return 0;
466
467 /* Get the number of NAKs received and generated */
468 val = RREG32_PCIE(smnPCIEP_NAK_COUNTER);
469 nak_r = val & 0xFFFF;
470 nak_g = val >> 16;
471
472 /* Add the total number of NAKs, i.e the number of replays */
473 return (nak_r + nak_g);
474 }
475
nbio_v7_9_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)476 static void nbio_v7_9_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
477 uint64_t *count1)
478 {
479 uint32_t perfctrrx = 0;
480 uint32_t perfctrtx = 0;
481
482 /* This reports 0 on APUs, so return to avoid writing/reading registers
483 * that may or may not be different from their GPU counterparts
484 */
485 if (adev->flags & AMD_IS_APU)
486 return;
487
488 /* Use TXCLK3 counter group for rx event */
489 /* Use TXCLK7 counter group for tx event */
490 /* Set the 2 events that we wish to watch, defined above */
491 /* 40 is event# for received msgs */
492 /* 2 is event# of posted requests sent */
493 perfctrrx = REG_SET_FIELD(perfctrrx, PCIE_PERF_CNTL_TXCLK3, EVENT0_SEL, 40);
494 perfctrtx = REG_SET_FIELD(perfctrtx, PCIE_PERF_CNTL_TXCLK7, EVENT0_SEL, 2);
495
496 /* Write to enable desired perf counters */
497 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctrrx);
498 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK7, perfctrtx);
499
500 /* Zero out and enable SHADOW_WR
501 * Write 0x6:
502 * Bit 1 = Global Shadow wr(1)
503 * Bit 2 = Global counter reset enable(1)
504 */
505 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006);
506
507 /* Enable Gloabl Counter
508 * Write 0x1:
509 * Bit 0 = Global Counter Enable(1)
510 */
511 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000001);
512
513 msleep(1000);
514
515 /* Disable Global Counter, Reset and enable SHADOW_WR
516 * Write 0x6:
517 * Bit 1 = Global Shadow wr(1)
518 * Bit 2 = Global counter reset enable(1)
519 */
520 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006);
521
522 /* Get the upper and lower count */
523 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) |
524 ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK3) << 32);
525 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK7) |
526 ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK7) << 32);
527 }
528
529 const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
530 .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
531 .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
532 .get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset,
533 .get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset,
534 .get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset,
535 .get_rev_id = nbio_v7_9_get_rev_id,
536 .mc_access_enable = nbio_v7_9_mc_access_enable,
537 .get_memsize = nbio_v7_9_get_memsize,
538 .sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range,
539 .vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range,
540 .enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture,
541 .enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture,
542 .ih_doorbell_range = nbio_v7_9_ih_doorbell_range,
543 .enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt,
544 .update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating,
545 .update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep,
546 .get_clockgating_state = nbio_v7_9_get_clockgating_state,
547 .ih_control = nbio_v7_9_ih_control,
548 .remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
549 .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
550 .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
551 .init_registers = nbio_v7_9_init_registers,
552 .get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count,
553 .get_pcie_usage = nbio_v7_9_get_pcie_usage,
554 };
555
nbio_v7_9_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)556 static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev,
557 void *ras_error_status)
558 {
559 return;
560 }
561
nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device * adev)562 static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
563 {
564 uint32_t bif_doorbell_intr_cntl;
565 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
566 struct ras_err_data err_data = {0, 0, 0, NULL};
567 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
568
569 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
570
571 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
572 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
573 /* driver has to clear the interrupt status when bif ring is disabled */
574 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
575 BIF_BX0_BIF_DOORBELL_INT_CNTL,
576 RAS_CNTLR_INTERRUPT_CLEAR, 1);
577 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
578
579 if (!ras->disable_ras_err_cnt_harvest) {
580 /*
581 * clear error status after ras_controller_intr
582 * according to hw team and count ue number
583 * for query
584 */
585 nbio_v7_9_query_ras_error_count(adev, &err_data);
586
587 /* logging on error cnt and printing for awareness */
588 obj->err_data.ue_count += err_data.ue_count;
589 obj->err_data.ce_count += err_data.ce_count;
590
591 if (err_data.ce_count)
592 dev_info(adev->dev, "%ld correctable hardware "
593 "errors detected in %s block, "
594 "no user action is needed.\n",
595 obj->err_data.ce_count,
596 get_ras_block_str(adev->nbio.ras_if));
597
598 if (err_data.ue_count)
599 dev_info(adev->dev, "%ld uncorrectable hardware "
600 "errors detected in %s block\n",
601 obj->err_data.ue_count,
602 get_ras_block_str(adev->nbio.ras_if));
603 }
604
605 dev_info(adev->dev, "RAS controller interrupt triggered "
606 "by NBIF error\n");
607
608 /* ras_controller_int is dedicated for nbif ras error,
609 * not the global interrupt for sync flood
610 */
611 amdgpu_ras_reset_gpu(adev);
612 }
613 }
614
nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device * adev)615 static void nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
616 {
617 uint32_t bif_doorbell_intr_cntl;
618
619 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
620
621 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
622 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
623 /* driver has to clear the interrupt status when bif ring is disabled */
624 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
625 BIF_BX0_BIF_DOORBELL_INT_CNTL,
626 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
627
628 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
629
630 amdgpu_ras_global_ras_isr(adev);
631 }
632 }
633
nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)634 static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev,
635 struct amdgpu_irq_src *src,
636 unsigned type,
637 enum amdgpu_interrupt_state state)
638 {
639 /* Dummy function, there is no initialization operation in driver */
640
641 return 0;
642 }
643
nbio_v7_9_process_ras_controller_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)644 static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev,
645 struct amdgpu_irq_src *source,
646 struct amdgpu_iv_entry *entry)
647 {
648 /* By design, the ih cookie for ras_controller_irq should be written
649 * to BIFring instead of general iv ring. However, due to known bif ring
650 * hw bug, it has to be disabled. There is no chance the process function
651 * will be involked. Just left it as a dummy one.
652 */
653 return 0;
654 }
655
nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)656 static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
657 struct amdgpu_irq_src *src,
658 unsigned type,
659 enum amdgpu_interrupt_state state)
660 {
661 /* Dummy function, there is no initialization operation in driver */
662
663 return 0;
664 }
665
nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)666 static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev,
667 struct amdgpu_irq_src *source,
668 struct amdgpu_iv_entry *entry)
669 {
670 /* By design, the ih cookie for err_event_athub_irq should be written
671 * to BIFring instead of general iv ring. However, due to known bif ring
672 * hw bug, it has to be disabled. There is no chance the process function
673 * will be involked. Just left it as a dummy one.
674 */
675 return 0;
676 }
677
678 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = {
679 .set = nbio_v7_9_set_ras_controller_irq_state,
680 .process = nbio_v7_9_process_ras_controller_irq,
681 };
682
683 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = {
684 .set = nbio_v7_9_set_ras_err_event_athub_irq_state,
685 .process = nbio_v7_9_process_err_event_athub_irq,
686 };
687
nbio_v7_9_init_ras_controller_interrupt(struct amdgpu_device * adev)688 static int nbio_v7_9_init_ras_controller_interrupt (struct amdgpu_device *adev)
689 {
690 int r;
691
692 /* init the irq funcs */
693 adev->nbio.ras_controller_irq.funcs =
694 &nbio_v7_9_ras_controller_irq_funcs;
695 adev->nbio.ras_controller_irq.num_types = 1;
696
697 /* register ras controller interrupt */
698 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
699 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
700 &adev->nbio.ras_controller_irq);
701
702 return r;
703 }
704
nbio_v7_9_init_ras_err_event_athub_interrupt(struct amdgpu_device * adev)705 static int nbio_v7_9_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
706 {
707
708 int r;
709
710 /* init the irq funcs */
711 adev->nbio.ras_err_event_athub_irq.funcs =
712 &nbio_v7_9_ras_err_event_athub_irq_funcs;
713 adev->nbio.ras_err_event_athub_irq.num_types = 1;
714
715 /* register ras err event athub interrupt */
716 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
717 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
718 &adev->nbio.ras_err_event_athub_irq);
719
720 return r;
721 }
722
723 const struct amdgpu_ras_block_hw_ops nbio_v7_9_ras_hw_ops = {
724 .query_ras_error_count = nbio_v7_9_query_ras_error_count,
725 };
726
727 struct amdgpu_nbio_ras nbio_v7_9_ras = {
728 .ras_block = {
729 .ras_comm = {
730 .name = "pcie_bif",
731 .block = AMDGPU_RAS_BLOCK__PCIE_BIF,
732 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
733 },
734 .hw_ops = &nbio_v7_9_ras_hw_ops,
735 .ras_late_init = amdgpu_nbio_ras_late_init,
736 },
737 .handle_ras_controller_intr_no_bifring = nbio_v7_9_handle_ras_controller_intr_no_bifring,
738 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring,
739 .init_ras_controller_interrupt = nbio_v7_9_init_ras_controller_interrupt,
740 .init_ras_err_event_athub_interrupt = nbio_v7_9_init_ras_err_event_athub_interrupt,
741 };
742
