1 /*
2 * AMD64 class Memory Controller kernel module
3 *
4 * Copyright (c) 2009 SoftwareBitMaker.
5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
6 *
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
9 */
10
11 #include <linux/module.h>
12 #include <linux/ctype.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/slab.h>
17 #include <linux/mmzone.h>
18 #include <linux/edac.h>
19 #include <asm/cpu_device_id.h>
20 #include <asm/msr.h>
21 #include "edac_module.h"
22 #include "mce_amd.h"
23
24 #define amd64_info(fmt, arg...) \
25 edac_printk(KERN_INFO, "amd64", fmt, ##arg)
26
27 #define amd64_warn(fmt, arg...) \
28 edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
29
30 #define amd64_err(fmt, arg...) \
31 edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
32
33 #define amd64_mc_warn(mci, fmt, arg...) \
34 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
35
36 #define amd64_mc_err(mci, fmt, arg...) \
37 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
38
39 /*
40 * Throughout the comments in this code, the following terms are used:
41 *
42 * SysAddr, DramAddr, and InputAddr
43 *
44 * These terms come directly from the amd64 documentation
45 * (AMD publication #26094). They are defined as follows:
46 *
47 * SysAddr:
48 * This is a physical address generated by a CPU core or a device
49 * doing DMA. If generated by a CPU core, a SysAddr is the result of
50 * a virtual to physical address translation by the CPU core's address
51 * translation mechanism (MMU).
52 *
53 * DramAddr:
54 * A DramAddr is derived from a SysAddr by subtracting an offset that
55 * depends on which node the SysAddr maps to and whether the SysAddr
56 * is within a range affected by memory hoisting. The DRAM Base
57 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
58 * determine which node a SysAddr maps to.
59 *
60 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
61 * is within the range of addresses specified by this register, then
62 * a value x from the DHAR is subtracted from the SysAddr to produce a
63 * DramAddr. Here, x represents the base address for the node that
64 * the SysAddr maps to plus an offset due to memory hoisting. See
65 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
66 * sys_addr_to_dram_addr() below for more information.
67 *
68 * If the SysAddr is not affected by the DHAR then a value y is
69 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
70 * base address for the node that the SysAddr maps to. See section
71 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
72 * information.
73 *
74 * InputAddr:
75 * A DramAddr is translated to an InputAddr before being passed to the
76 * memory controller for the node that the DramAddr is associated
77 * with. The memory controller then maps the InputAddr to a csrow.
78 * If node interleaving is not in use, then the InputAddr has the same
79 * value as the DramAddr. Otherwise, the InputAddr is produced by
80 * discarding the bits used for node interleaving from the DramAddr.
81 * See section 3.4.4 for more information.
82 *
83 * The memory controller for a given node uses its DRAM CS Base and
84 * DRAM CS Mask registers to map an InputAddr to a csrow. See
85 * sections 3.5.4 and 3.5.5 for more information.
86 */
87
88 #define EDAC_AMD64_VERSION "3.5.0"
89 #define EDAC_MOD_STR "amd64_edac"
90
91 /* Extended Model from CPUID, for CPU Revision numbers */
92 #define K8_REV_D 1
93 #define K8_REV_E 2
94 #define K8_REV_F 4
95
96 /* Hardware limit on ChipSelect rows per MC and processors per system */
97 #define NUM_CHIPSELECTS 8
98 #define DRAM_RANGES 8
99 #define NUM_CONTROLLERS 12
100
101 #define ON true
102 #define OFF false
103
104 /*
105 * PCI-defined configuration space registers
106 */
107 #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
108 #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
109 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
110 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
111 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
112 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
113 #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
114 #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
115 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
116 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
117 #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
118 #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466
119 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
120 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
121 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
122 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
123 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
124 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e
125 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
126 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
127 #define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650
128 #define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656
129 #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad
130 #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3
131 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a
132 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F6 0x1670
133
134 /*
135 * Function 1 - Address Map
136 */
137 #define DRAM_BASE_LO 0x40
138 #define DRAM_LIMIT_LO 0x44
139
140 /*
141 * F15 M30h D18F1x2[1C:00]
142 */
143 #define DRAM_CONT_BASE 0x200
144 #define DRAM_CONT_LIMIT 0x204
145
146 /*
147 * F15 M30h D18F1x2[4C:40]
148 */
149 #define DRAM_CONT_HIGH_OFF 0x240
150
151 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
152 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
153 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
154
155 #define DHAR 0xf0
156 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
157 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
158 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
159
160 /* NOTE: Extra mask bit vs K8 */
161 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
162
163 #define DCT_CFG_SEL 0x10C
164
165 #define DRAM_LOCAL_NODE_BASE 0x120
166 #define DRAM_LOCAL_NODE_LIM 0x124
167
168 #define DRAM_BASE_HI 0x140
169 #define DRAM_LIMIT_HI 0x144
170
171
172 /*
173 * Function 2 - DRAM controller
174 */
175 #define DCSB0 0x40
176 #define DCSB1 0x140
177 #define DCSB_CS_ENABLE BIT(0)
178
179 #define DCSM0 0x60
180 #define DCSM1 0x160
181
182 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
183 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
184
185 #define DRAM_CONTROL 0x78
186
187 #define DBAM0 0x80
188 #define DBAM1 0x180
189
190 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
191 #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
192
193 #define DBAM_MAX_VALUE 11
194
195 #define DCLR0 0x90
196 #define DCLR1 0x190
197 #define REVE_WIDTH_128 BIT(16)
198 #define WIDTH_128 BIT(11)
199
200 #define DCHR0 0x94
201 #define DCHR1 0x194
202 #define DDR3_MODE BIT(8)
203
204 #define DCT_SEL_LO 0x110
205 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
206 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
207
208 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
209
210 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
211 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
212
213 #define SWAP_INTLV_REG 0x10c
214
215 #define DCT_SEL_HI 0x114
216
217 #define F15H_M60H_SCRCTRL 0x1C8
218 #define F17H_SCR_BASE_ADDR 0x48
219 #define F17H_SCR_LIMIT_ADDR 0x4C
220
221 /*
222 * Function 3 - Misc Control
223 */
224 #define NBCTL 0x40
225
226 #define NBCFG 0x44
227 #define NBCFG_CHIPKILL BIT(23)
228 #define NBCFG_ECC_ENABLE BIT(22)
229
230 /* F3x48: NBSL */
231 #define F10_NBSL_EXT_ERR_ECC 0x8
232 #define NBSL_PP_OBS 0x2
233
234 #define SCRCTRL 0x58
235
236 #define F10_ONLINE_SPARE 0xB0
237 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
238 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
239
240 #define F10_NB_ARRAY_ADDR 0xB8
241 #define F10_NB_ARRAY_DRAM BIT(31)
242
243 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
244 #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
245
246 #define F10_NB_ARRAY_DATA 0xBC
247 #define F10_NB_ARR_ECC_WR_REQ BIT(17)
248 #define SET_NB_DRAM_INJECTION_WRITE(inj) \
249 (BIT(((inj.word) & 0xF) + 20) | \
250 F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
251 #define SET_NB_DRAM_INJECTION_READ(inj) \
252 (BIT(((inj.word) & 0xF) + 20) | \
253 BIT(16) | inj.bit_map)
254
255
256 #define NBCAP 0xE8
257 #define NBCAP_CHIPKILL BIT(4)
258 #define NBCAP_SECDED BIT(3)
259 #define NBCAP_DCT_DUAL BIT(0)
260
261 #define EXT_NB_MCA_CFG 0x180
262
263 /* MSRs */
264 #define MSR_MCGCTL_NBE BIT(4)
265
266 /* F17h */
267
268 /* F0: */
269 #define DF_DHAR 0x104
270
271 /* UMC CH register offsets */
272 #define UMCCH_BASE_ADDR 0x0
273 #define UMCCH_BASE_ADDR_SEC 0x10
274 #define UMCCH_ADDR_MASK 0x20
275 #define UMCCH_ADDR_MASK_SEC 0x28
276 #define UMCCH_ADDR_MASK_SEC_DDR5 0x30
277 #define UMCCH_ADDR_CFG 0x30
278 #define UMCCH_ADDR_CFG_DDR5 0x40
279 #define UMCCH_DIMM_CFG 0x80
280 #define UMCCH_DIMM_CFG_DDR5 0x90
281 #define UMCCH_UMC_CFG 0x100
282 #define UMCCH_SDP_CTRL 0x104
283 #define UMCCH_ECC_CTRL 0x14C
284 #define UMCCH_ECC_BAD_SYMBOL 0xD90
285 #define UMCCH_UMC_CAP 0xDF0
286 #define UMCCH_UMC_CAP_HI 0xDF4
287
288 /* UMC CH bitfields */
289 #define UMC_ECC_CHIPKILL_CAP BIT(31)
290 #define UMC_ECC_ENABLED BIT(30)
291
292 #define UMC_SDP_INIT BIT(31)
293
294 enum amd_families {
295 K8_CPUS = 0,
296 F10_CPUS,
297 F15_CPUS,
298 F15_M30H_CPUS,
299 F15_M60H_CPUS,
300 F16_CPUS,
301 F16_M30H_CPUS,
302 F17_CPUS,
303 F17_M10H_CPUS,
304 F17_M30H_CPUS,
305 F17_M60H_CPUS,
306 F17_M70H_CPUS,
307 F19_CPUS,
308 F19_M10H_CPUS,
309 F19_M50H_CPUS,
310 NUM_FAMILIES,
311 };
312
313 /* Error injection control structure */
314 struct error_injection {
315 u32 section;
316 u32 word;
317 u32 bit_map;
318 };
319
320 /* low and high part of PCI config space regs */
321 struct reg_pair {
322 u32 lo, hi;
323 };
324
325 /*
326 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
327 */
328 struct dram_range {
329 struct reg_pair base;
330 struct reg_pair lim;
331 };
332
333 /* A DCT chip selects collection */
334 struct chip_select {
335 u32 csbases[NUM_CHIPSELECTS];
336 u32 csbases_sec[NUM_CHIPSELECTS];
337 u8 b_cnt;
338
339 u32 csmasks[NUM_CHIPSELECTS];
340 u32 csmasks_sec[NUM_CHIPSELECTS];
341 u8 m_cnt;
342 };
343
344 struct amd64_umc {
345 u32 dimm_cfg; /* DIMM Configuration reg */
346 u32 umc_cfg; /* Configuration reg */
347 u32 sdp_ctrl; /* SDP Control reg */
348 u32 ecc_ctrl; /* DRAM ECC Control reg */
349 u32 umc_cap_hi; /* Capabilities High reg */
350
351 /* cache the dram_type */
352 enum mem_type dram_type;
353 };
354
355 struct amd64_pvt {
356 struct low_ops *ops;
357
358 /* pci_device handles which we utilize */
359 struct pci_dev *F0, *F1, *F2, *F3, *F6;
360
361 u16 mc_node_id; /* MC index of this MC node */
362 u8 fam; /* CPU family */
363 u8 model; /* ... model */
364 u8 stepping; /* ... stepping */
365
366 int ext_model; /* extended model value of this node */
367 int channel_count;
368
369 /* Raw registers */
370 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
371 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
372 u32 dchr0; /* DRAM Configuration High DCT0 reg */
373 u32 dchr1; /* DRAM Configuration High DCT1 reg */
374 u32 nbcap; /* North Bridge Capabilities */
375 u32 nbcfg; /* F10 North Bridge Configuration */
376 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
377 u32 dhar; /* DRAM Hoist reg */
378 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
379 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
380
381 /* one for each DCT/UMC */
382 struct chip_select csels[NUM_CONTROLLERS];
383
384 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
385 struct dram_range ranges[DRAM_RANGES];
386
387 u64 top_mem; /* top of memory below 4GB */
388 u64 top_mem2; /* top of memory above 4GB */
389
390 u32 dct_sel_lo; /* DRAM Controller Select Low */
391 u32 dct_sel_hi; /* DRAM Controller Select High */
392 u32 online_spare; /* On-Line spare Reg */
393
394 /* x4, x8, or x16 syndromes in use */
395 u8 ecc_sym_sz;
396
397 /* place to store error injection parameters prior to issue */
398 struct error_injection injection;
399
400 /*
401 * cache the dram_type
402 *
403 * NOTE: Don't use this for Family 17h and later.
404 * Use dram_type in struct amd64_umc instead.
405 */
406 enum mem_type dram_type;
407
408 struct amd64_umc *umc; /* UMC registers */
409 };
410
411 enum err_codes {
412 DECODE_OK = 0,
413 ERR_NODE = -1,
414 ERR_CSROW = -2,
415 ERR_CHANNEL = -3,
416 ERR_SYND = -4,
417 ERR_NORM_ADDR = -5,
418 };
419
420 struct err_info {
421 int err_code;
422 struct mem_ctl_info *src_mci;
423 int csrow;
424 int channel;
425 u16 syndrome;
426 u32 page;
427 u32 offset;
428 };
429
get_umc_base(u8 channel)430 static inline u32 get_umc_base(u8 channel)
431 {
432 /* chY: 0xY50000 */
433 return 0x50000 + (channel << 20);
434 }
435
get_dram_base(struct amd64_pvt * pvt,u8 i)436 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
437 {
438 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
439
440 if (boot_cpu_data.x86 == 0xf)
441 return addr;
442
443 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
444 }
445
get_dram_limit(struct amd64_pvt * pvt,u8 i)446 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
447 {
448 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
449
450 if (boot_cpu_data.x86 == 0xf)
451 return lim;
452
453 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
454 }
455
extract_syndrome(u64 status)456 static inline u16 extract_syndrome(u64 status)
457 {
458 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
459 }
460
dct_sel_interleave_addr(struct amd64_pvt * pvt)461 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
462 {
463 if (pvt->fam == 0x15 && pvt->model >= 0x30)
464 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
465 ((pvt->dct_sel_lo >> 6) & 0x3);
466
467 return ((pvt)->dct_sel_lo >> 6) & 0x3;
468 }
469 /*
470 * per-node ECC settings descriptor
471 */
472 struct ecc_settings {
473 u32 old_nbctl;
474 bool nbctl_valid;
475
476 struct flags {
477 unsigned long nb_mce_enable:1;
478 unsigned long nb_ecc_prev:1;
479 } flags;
480 };
481
482 /*
483 * Each of the PCI Device IDs types have their own set of hardware accessor
484 * functions and per device encoding/decoding logic.
485 */
486 struct low_ops {
487 int (*early_channel_count) (struct amd64_pvt *pvt);
488 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
489 struct err_info *);
490 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
491 unsigned cs_mode, int cs_mask_nr);
492 };
493
494 struct amd64_family_flags {
495 /*
496 * Indicates that the system supports the new register offsets, etc.
497 * first introduced with Family 19h Model 10h.
498 */
499 __u64 zn_regs_v2 : 1,
500
501 __reserved : 63;
502 };
503
504 struct amd64_family_type {
505 const char *ctl_name;
506 u16 f0_id, f1_id, f2_id, f6_id;
507 /* Maximum number of memory controllers per die/node. */
508 u8 max_mcs;
509 struct amd64_family_flags flags;
510 struct low_ops ops;
511 };
512
513 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
514 u32 *val, const char *func);
515 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
516 u32 val, const char *func);
517
518 #define amd64_read_pci_cfg(pdev, offset, val) \
519 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
520
521 #define amd64_write_pci_cfg(pdev, offset, val) \
522 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
523
524 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
525
526 /* Injection helpers */
disable_caches(void * dummy)527 static inline void disable_caches(void *dummy)
528 {
529 write_cr0(read_cr0() | X86_CR0_CD);
530 wbinvd();
531 }
532
enable_caches(void * dummy)533 static inline void enable_caches(void *dummy)
534 {
535 write_cr0(read_cr0() & ~X86_CR0_CD);
536 }
537
dram_intlv_en(struct amd64_pvt * pvt,unsigned int i)538 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
539 {
540 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
541 u32 tmp;
542 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
543 return (u8) tmp & 0xF;
544 }
545 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
546 }
547
dhar_valid(struct amd64_pvt * pvt)548 static inline u8 dhar_valid(struct amd64_pvt *pvt)
549 {
550 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
551 u32 tmp;
552 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
553 return (tmp >> 1) & BIT(0);
554 }
555 return (pvt)->dhar & BIT(0);
556 }
557
dct_sel_baseaddr(struct amd64_pvt * pvt)558 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
559 {
560 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
561 u32 tmp;
562 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
563 return (tmp >> 11) & 0x1FFF;
564 }
565 return (pvt)->dct_sel_lo & 0xFFFFF800;
566 }
567
