1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
42
43 #include <linux/pci_ids.h>
44
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
50 PCI_STATUS_PARITY)
51
52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
53 #define PCI_NUM_RESET_METHODS 7
54
55 #define PCI_RESET_PROBE true
56 #define PCI_RESET_DO_RESET false
57
58 /*
59 * The PCI interface treats multi-function devices as independent
60 * devices. The slot/function address of each device is encoded
61 * in a single byte as follows:
62 *
63 * 7:3 = slot
64 * 2:0 = function
65 *
66 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
67 * In the interest of not exposing interfaces to user-space unnecessarily,
68 * the following kernel-only defines are being added here.
69 */
70 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
73
74 /* pci_slot represents a physical slot */
75 struct pci_slot {
76 struct pci_bus *bus; /* Bus this slot is on */
77 struct list_head list; /* Node in list of slots */
78 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
79 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
80 struct kobject kobj;
81 };
82
pci_slot_name(const struct pci_slot * slot)83 static inline const char *pci_slot_name(const struct pci_slot *slot)
84 {
85 return kobject_name(&slot->kobj);
86 }
87
88 /* File state for mmap()s on /proc/bus/pci/X/Y */
89 enum pci_mmap_state {
90 pci_mmap_io,
91 pci_mmap_mem
92 };
93
94 /* For PCI devices, the region numbers are assigned this way: */
95 enum {
96 /* #0-5: standard PCI resources */
97 PCI_STD_RESOURCES,
98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
99
100 /* #6: expansion ROM resource */
101 PCI_ROM_RESOURCE,
102
103 /* Device-specific resources */
104 #ifdef CONFIG_PCI_IOV
105 PCI_IOV_RESOURCES,
106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
107 #endif
108
109 /* PCI-to-PCI (P2P) bridge windows */
110 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
111 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
112 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
113
114 /* CardBus bridge windows */
115 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
116 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
117 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
118 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
119
120 /* Total number of bridge resources for P2P and CardBus */
121 #define PCI_BRIDGE_RESOURCE_NUM 4
122
123 /* Resources assigned to buses behind the bridge */
124 PCI_BRIDGE_RESOURCES,
125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
126 PCI_BRIDGE_RESOURCE_NUM - 1,
127
128 /* Total resources associated with a PCI device */
129 PCI_NUM_RESOURCES,
130
131 /* Preserve this for compatibility */
132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
133 };
134
135 /**
136 * enum pci_interrupt_pin - PCI INTx interrupt values
137 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
138 * @PCI_INTERRUPT_INTA: PCI INTA pin
139 * @PCI_INTERRUPT_INTB: PCI INTB pin
140 * @PCI_INTERRUPT_INTC: PCI INTC pin
141 * @PCI_INTERRUPT_INTD: PCI INTD pin
142 *
143 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
144 * PCI_INTERRUPT_PIN register.
145 */
146 enum pci_interrupt_pin {
147 PCI_INTERRUPT_UNKNOWN,
148 PCI_INTERRUPT_INTA,
149 PCI_INTERRUPT_INTB,
150 PCI_INTERRUPT_INTC,
151 PCI_INTERRUPT_INTD,
152 };
153
154 /* The number of legacy PCI INTx interrupts */
155 #define PCI_NUM_INTX 4
156
157 /*
158 * pci_power_t values must match the bits in the Capabilities PME_Support
159 * and Control/Status PowerState fields in the Power Management capability.
160 */
161 typedef int __bitwise pci_power_t;
162
163 #define PCI_D0 ((pci_power_t __force) 0)
164 #define PCI_D1 ((pci_power_t __force) 1)
165 #define PCI_D2 ((pci_power_t __force) 2)
166 #define PCI_D3hot ((pci_power_t __force) 3)
167 #define PCI_D3cold ((pci_power_t __force) 4)
168 #define PCI_UNKNOWN ((pci_power_t __force) 5)
169 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
170
171 /* Remember to update this when the list above changes! */
172 extern const char *pci_power_names[];
173
pci_power_name(pci_power_t state)174 static inline const char *pci_power_name(pci_power_t state)
175 {
176 return pci_power_names[1 + (__force int) state];
177 }
178
179 /**
180 * typedef pci_channel_state_t
181 *
182 * The pci_channel state describes connectivity between the CPU and
183 * the PCI device. If some PCI bus between here and the PCI device
184 * has crashed or locked up, this info is reflected here.
185 */
186 typedef unsigned int __bitwise pci_channel_state_t;
187
188 enum {
189 /* I/O channel is in normal state */
190 pci_channel_io_normal = (__force pci_channel_state_t) 1,
191
192 /* I/O to channel is blocked */
193 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
194
195 /* PCI card is dead */
196 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
197 };
198
199 typedef unsigned int __bitwise pcie_reset_state_t;
200
201 enum pcie_reset_state {
202 /* Reset is NOT asserted (Use to deassert reset) */
203 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
204
205 /* Use #PERST to reset PCIe device */
206 pcie_warm_reset = (__force pcie_reset_state_t) 2,
207
208 /* Use PCIe Hot Reset to reset device */
209 pcie_hot_reset = (__force pcie_reset_state_t) 3
210 };
211
212 typedef unsigned short __bitwise pci_dev_flags_t;
213 enum pci_dev_flags {
214 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
215 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
216 /* Device configuration is irrevocably lost if disabled into D3 */
217 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
218 /* Provide indication device is assigned by a Virtual Machine Manager */
219 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
220 /* Flag for quirk use to store if quirk-specific ACS is enabled */
221 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
222 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
223 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
224 /* Do not use bus resets for device */
225 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
226 /* Do not use PM reset even if device advertises NoSoftRst- */
227 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
228 /* Get VPD from function 0 VPD */
229 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
230 /* A non-root bridge where translation occurs, stop alias search here */
231 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
232 /* Do not use FLR even if device advertises PCI_AF_CAP */
233 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
234 /* Don't use Relaxed Ordering for TLPs directed at this device */
235 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
236 };
237
238 enum pci_irq_reroute_variant {
239 INTEL_IRQ_REROUTE_VARIANT = 1,
240 MAX_IRQ_REROUTE_VARIANTS = 3
241 };
242
243 typedef unsigned short __bitwise pci_bus_flags_t;
244 enum pci_bus_flags {
245 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
246 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
247 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
248 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
249 };
250
251 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
252 enum pcie_link_width {
253 PCIE_LNK_WIDTH_RESRV = 0x00,
254 PCIE_LNK_X1 = 0x01,
255 PCIE_LNK_X2 = 0x02,
256 PCIE_LNK_X4 = 0x04,
257 PCIE_LNK_X8 = 0x08,
258 PCIE_LNK_X12 = 0x0c,
259 PCIE_LNK_X16 = 0x10,
260 PCIE_LNK_X32 = 0x20,
261 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
262 };
263
264 /* See matching string table in pci_speed_string() */
265 enum pci_bus_speed {
266 PCI_SPEED_33MHz = 0x00,
267 PCI_SPEED_66MHz = 0x01,
268 PCI_SPEED_66MHz_PCIX = 0x02,
269 PCI_SPEED_100MHz_PCIX = 0x03,
270 PCI_SPEED_133MHz_PCIX = 0x04,
271 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
272 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
273 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
274 PCI_SPEED_66MHz_PCIX_266 = 0x09,
275 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
276 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
277 AGP_UNKNOWN = 0x0c,
278 AGP_1X = 0x0d,
279 AGP_2X = 0x0e,
280 AGP_4X = 0x0f,
281 AGP_8X = 0x10,
282 PCI_SPEED_66MHz_PCIX_533 = 0x11,
283 PCI_SPEED_100MHz_PCIX_533 = 0x12,
284 PCI_SPEED_133MHz_PCIX_533 = 0x13,
285 PCIE_SPEED_2_5GT = 0x14,
286 PCIE_SPEED_5_0GT = 0x15,
287 PCIE_SPEED_8_0GT = 0x16,
288 PCIE_SPEED_16_0GT = 0x17,
289 PCIE_SPEED_32_0GT = 0x18,
290 PCIE_SPEED_64_0GT = 0x19,
291 PCI_SPEED_UNKNOWN = 0xff,
292 };
293
294 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
295 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
296
297 struct pci_vpd {
298 struct mutex lock;
299 unsigned int len;
300 u8 cap;
301 };
302
303 struct irq_affinity;
304 struct pcie_link_state;
305 struct pci_sriov;
306 struct pci_p2pdma;
307 struct rcec_ea;
308
309 /* The pci_dev structure describes PCI devices */
310 struct pci_dev {
311 struct list_head bus_list; /* Node in per-bus list */
312 struct pci_bus *bus; /* Bus this device is on */
313 struct pci_bus *subordinate; /* Bus this device bridges to */
314
315 void *sysdata; /* Hook for sys-specific extension */
316 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
317 struct pci_slot *slot; /* Physical slot this device is in */
318
319 unsigned int devfn; /* Encoded device & function index */
320 unsigned short vendor;
321 unsigned short device;
322 unsigned short subsystem_vendor;
323 unsigned short subsystem_device;
324 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
325 u8 revision; /* PCI revision, low byte of class word */
326 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
327 #ifdef CONFIG_PCIEAER
328 u16 aer_cap; /* AER capability offset */
329 struct aer_stats *aer_stats; /* AER stats for this device */
330 #endif
331 #ifdef CONFIG_PCIEPORTBUS
332 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
333 struct pci_dev *rcec; /* Associated RCEC device */
334 #endif
335 u32 devcap; /* PCIe Device Capabilities */
336 u8 pcie_cap; /* PCIe capability offset */
337 u8 msi_cap; /* MSI capability offset */
338 u8 msix_cap; /* MSI-X capability offset */
339 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
340 u8 rom_base_reg; /* Config register controlling ROM */
341 u8 pin; /* Interrupt pin this device uses */
342 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
343 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
344
345 struct pci_driver *driver; /* Driver bound to this device */
346 u64 dma_mask; /* Mask of the bits of bus address this
347 device implements. Normally this is
348 0xffffffff. You only need to change
349 this if your device has broken DMA
350 or supports 64-bit transfers. */
351
352 struct device_dma_parameters dma_parms;
353
354 pci_power_t current_state; /* Current operating state. In ACPI,
355 this is D0-D3, D0 being fully
356 functional, and D3 being off. */
357 unsigned int imm_ready:1; /* Supports Immediate Readiness */
358 u8 pm_cap; /* PM capability offset */
359 unsigned int pme_support:5; /* Bitmask of states from which PME#
360 can be generated */
361 unsigned int pme_poll:1; /* Poll device's PME status bit */
362 unsigned int d1_support:1; /* Low power state D1 is supported */
363 unsigned int d2_support:1; /* Low power state D2 is supported */
364 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
365 unsigned int no_d3cold:1; /* D3cold is forbidden */
366 unsigned int bridge_d3:1; /* Allow D3 for bridge */
367 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
368 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
369 decoding during BAR sizing */
370 unsigned int wakeup_prepared:1;
371 unsigned int runtime_d3cold:1; /* Whether go through runtime
372 D3cold, not set for devices
373 powered on/off by the
374 corresponding bridge */
375 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
376 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
377 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
378 controlled exclusively by
379 user sysfs */
380 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
381 bit manually */
382 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
383 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
384
385 #ifdef CONFIG_PCIEASPM
386 struct pcie_link_state *link_state; /* ASPM link state */
387 unsigned int ltr_path:1; /* Latency Tolerance Reporting
388 supported from root to here */
389 u16 l1ss; /* L1SS Capability pointer */
390 #endif
391 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
392 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
393
394 pci_channel_state_t error_state; /* Current connectivity state */
395 struct device dev; /* Generic device interface */
396
397 int cfg_size; /* Size of config space */
398
399 /*
400 * Instead of touching interrupt line and base address registers
401 * directly, use the values stored here. They might be different!
402 */
403 unsigned int irq;
404 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
405
406 bool match_driver; /* Skip attaching driver */
407
408 unsigned int transparent:1; /* Subtractive decode bridge */
409 unsigned int io_window:1; /* Bridge has I/O window */
410 unsigned int pref_window:1; /* Bridge has pref mem window */
411 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
412 unsigned int multifunction:1; /* Multi-function device */
413
414 unsigned int is_busmaster:1; /* Is busmaster */
415 unsigned int no_msi:1; /* May not use MSI */
416 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
417 unsigned int block_cfg_access:1; /* Config space access blocked */
418 unsigned int broken_parity_status:1; /* Generates false positive parity */
419 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
420 unsigned int msi_enabled:1;
421 unsigned int msix_enabled:1;
422 unsigned int ari_enabled:1; /* ARI forwarding */
423 unsigned int ats_enabled:1; /* Address Translation Svc */
424 unsigned int pasid_enabled:1; /* Process Address Space ID */
425 unsigned int pri_enabled:1; /* Page Request Interface */
426 unsigned int is_managed:1;
427 unsigned int needs_freset:1; /* Requires fundamental reset */
428 unsigned int state_saved:1;
429 unsigned int is_physfn:1;
430 unsigned int is_virtfn:1;
431 unsigned int is_hotplug_bridge:1;
432 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
433 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
434 /*
435 * Devices marked being untrusted are the ones that can potentially
436 * execute DMA attacks and similar. They are typically connected
437 * through external ports such as Thunderbolt but not limited to
438 * that. When an IOMMU is enabled they should be getting full
439 * mappings to make sure they cannot access arbitrary memory.
440 */
441 unsigned int untrusted:1;
442 /*
443 * Info from the platform, e.g., ACPI or device tree, may mark a
444 * device as "external-facing". An external-facing device is
445 * itself internal but devices downstream from it are external.
446 */
447 unsigned int external_facing:1;
448 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
449 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
450 unsigned int irq_managed:1;
451 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
452 unsigned int is_probed:1; /* Device probing in progress */
453 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
454 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
455 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
456 pci_dev_flags_t dev_flags;
457 atomic_t enable_cnt; /* pci_enable_device has been called */
458
459 u32 saved_config_space[16]; /* Config space saved at suspend time */
460 struct hlist_head saved_cap_space;
461 int rom_attr_enabled; /* Display of ROM attribute enabled? */
462 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
463 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
464
465 #ifdef CONFIG_HOTPLUG_PCI_PCIE
466 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
467 #endif
468 #ifdef CONFIG_PCIE_PTM
469 unsigned int ptm_root:1;
470 unsigned int ptm_enabled:1;
471 u8 ptm_granularity;
472 #endif
473 #ifdef CONFIG_PCI_MSI
474 const struct attribute_group **msi_irq_groups;
475 #endif
476 struct pci_vpd vpd;
477 #ifdef CONFIG_PCIE_DPC
478 u16 dpc_cap;
479 unsigned int dpc_rp_extensions:1;
480 u8 dpc_rp_log_size;
481 #endif
482 #ifdef CONFIG_PCI_ATS
483 union {
484 struct pci_sriov *sriov; /* PF: SR-IOV info */
485 struct pci_dev *physfn; /* VF: related PF */
486 };
487 u16 ats_cap; /* ATS Capability offset */
488 u8 ats_stu; /* ATS Smallest Translation Unit */
489 #endif
490 #ifdef CONFIG_PCI_PRI
491 u16 pri_cap; /* PRI Capability offset */
492 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
493 unsigned int pasid_required:1; /* PRG Response PASID Required */
494 #endif
495 #ifdef CONFIG_PCI_PASID
496 u16 pasid_cap; /* PASID Capability offset */
497 u16 pasid_features;
498 #endif
499 #ifdef CONFIG_PCI_P2PDMA
500 struct pci_p2pdma __rcu *p2pdma;
501 #endif
502 u16 acs_cap; /* ACS Capability offset */
503 phys_addr_t rom; /* Physical address if not from BAR */
504 size_t romlen; /* Length if not from BAR */
505 char *driver_override; /* Driver name to force a match */
506
507 unsigned long priv_flags; /* Private flags for the PCI driver */
508
509 /* These methods index pci_reset_fn_methods[] */
510 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
511 };
512
pci_physfn(struct pci_dev * dev)513 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
514 {
515 #ifdef CONFIG_PCI_IOV
516 if (dev->is_virtfn)
517 dev = dev->physfn;
518 #endif
519 return dev;
520 }
521
522 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
523
524 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
525 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
526
pci_channel_offline(struct pci_dev * pdev)527 static inline int pci_channel_offline(struct pci_dev *pdev)
528 {
529 return (pdev->error_state != pci_channel_io_normal);
530 }
531
532 /*
533 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
534 * Group number is limited to a 16-bit value, therefore (int)-1 is
535 * not a valid PCI domain number, and can be used as a sentinel
536 * value indicating ->domain_nr is not set by the driver (and
537 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
538 * pci_bus_find_domain_nr()).
539 */
540 #define PCI_DOMAIN_NR_NOT_SET (-1)
541
542 struct pci_host_bridge {
543 struct device dev;
544 struct pci_bus *bus; /* Root bus */
545 struct pci_ops *ops;
546 struct pci_ops *child_ops;
547 void *sysdata;
548 int busnr;
549 int domain_nr;
550 struct list_head windows; /* resource_entry */
551 struct list_head dma_ranges; /* dma ranges resource list */
552 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
553 int (*map_irq)(const struct pci_dev *, u8, u8);
554 void (*release_fn)(struct pci_host_bridge *);
555 void *release_data;
556 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
557 unsigned int no_ext_tags:1; /* No Extended Tags */
558 unsigned int native_aer:1; /* OS may use PCIe AER */
559 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
560 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
561 unsigned int native_pme:1; /* OS may use PCIe PME */
562 unsigned int native_ltr:1; /* OS may use PCIe LTR */
563 unsigned int native_dpc:1; /* OS may use PCIe DPC */
564 unsigned int preserve_config:1; /* Preserve FW resource setup */
565 unsigned int size_windows:1; /* Enable root bus sizing */
566 unsigned int msi_domain:1; /* Bridge wants MSI domain */
567
568 /* Resource alignment requirements */
569 resource_size_t (*align_resource)(struct pci_dev *dev,
570 const struct resource *res,
571 resource_size_t start,
572 resource_size_t size,
573 resource_size_t align);
574 unsigned long private[] ____cacheline_aligned;
575 };
576
577 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
578
pci_host_bridge_priv(struct pci_host_bridge * bridge)579 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
580 {
581 return (void *)bridge->private;
582 }
583
pci_host_bridge_from_priv(void * priv)584 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
585 {
586 return container_of(priv, struct pci_host_bridge, private);
587 }
588
589 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
590 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
591 size_t priv);
592 void pci_free_host_bridge(struct pci_host_bridge *bridge);
593 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
594
595 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
596 void (*release_fn)(struct pci_host_bridge *),
597 void *release_data);
598
599 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
600
601 /*
602 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
603 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
604 * buses below host bridges or subtractive decode bridges) go in the list.
605 * Use pci_bus_for_each_resource() to iterate through all the resources.
606 */
607
608 /*
609 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
610 * and there's no way to program the bridge with the details of the window.
611 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
612 * decode bit set, because they are explicit and can be programmed with _SRS.
613 */
614 #define PCI_SUBTRACTIVE_DECODE 0x1
615
616 struct pci_bus_resource {
617 struct list_head list;
618 struct resource *res;
619 unsigned int flags;
620 };
621
622 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
623
624 struct pci_bus {
625 struct list_head node; /* Node in list of buses */
626 struct pci_bus *parent; /* Parent bus this bridge is on */
627 struct list_head children; /* List of child buses */
628 struct list_head devices; /* List of devices on this bus */
629 struct pci_dev *self; /* Bridge device as seen by parent */
630 struct list_head slots; /* List of slots on this bus;
631 protected by pci_slot_mutex */
632 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
633 struct list_head resources; /* Address space routed to this bus */
634 struct resource busn_res; /* Bus numbers routed to this bus */
635
636 struct pci_ops *ops; /* Configuration access functions */
637 void *sysdata; /* Hook for sys-specific extension */
638 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
639
640 unsigned char number; /* Bus number */
641 unsigned char primary; /* Number of primary bridge */
642 unsigned char max_bus_speed; /* enum pci_bus_speed */
643 unsigned char cur_bus_speed; /* enum pci_bus_speed */
644 #ifdef CONFIG_PCI_DOMAINS_GENERIC
645 int domain_nr;
646 #endif
647
648 char name[48];
649
650 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
651 pci_bus_flags_t bus_flags; /* Inherited by child buses */
652 struct device *bridge;
653 struct device dev;
654 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
655 struct bin_attribute *legacy_mem; /* Legacy mem */
656 unsigned int is_added:1;
657 };
658
659 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
660
pci_dev_id(struct pci_dev * dev)661 static inline u16 pci_dev_id(struct pci_dev *dev)
662 {
663 return PCI_DEVID(dev->bus->number, dev->devfn);
664 }
665
666 /*
667 * Returns true if the PCI bus is root (behind host-PCI bridge),
668 * false otherwise
669 *
670 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
671 * This is incorrect because "virtual" buses added for SR-IOV (via
672 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
673 */
pci_is_root_bus(struct pci_bus * pbus)674 static inline bool pci_is_root_bus(struct pci_bus *pbus)
675 {
676 return !(pbus->parent);
677 }
678
679 /**
680 * pci_is_bridge - check if the PCI device is a bridge
681 * @dev: PCI device
682 *
683 * Return true if the PCI device is bridge whether it has subordinate
684 * or not.
685 */
pci_is_bridge(struct pci_dev * dev)686 static inline bool pci_is_bridge(struct pci_dev *dev)
687 {
688 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
689 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
690 }
691
692 #define for_each_pci_bridge(dev, bus) \
693 list_for_each_entry(dev, &bus->devices, bus_list) \
694 if (!pci_is_bridge(dev)) {} else
695
pci_upstream_bridge(struct pci_dev * dev)696 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
697 {
698 dev = pci_physfn(dev);
699 if (pci_is_root_bus(dev->bus))
700 return NULL;
701
702 return dev->bus->self;
703 }
704
705 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)706 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
707 {
708 return pci_dev->msi_enabled || pci_dev->msix_enabled;
709 }
710 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)711 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
712 #endif
713
714 /* Error values that may be returned by PCI functions */
715 #define PCIBIOS_SUCCESSFUL 0x00
716 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
717 #define PCIBIOS_BAD_VENDOR_ID 0x83
718 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
719 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
720 #define PCIBIOS_SET_FAILED 0x88
721 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
722
723 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)724 static inline int pcibios_err_to_errno(int err)
725 {
726 if (err <= PCIBIOS_SUCCESSFUL)
727 return err; /* Assume already errno */
728
729 switch (err) {
730 case PCIBIOS_FUNC_NOT_SUPPORTED:
731 return -ENOENT;
732 case PCIBIOS_BAD_VENDOR_ID:
733 return -ENOTTY;
734 case PCIBIOS_DEVICE_NOT_FOUND:
735 return -ENODEV;
736 case PCIBIOS_BAD_REGISTER_NUMBER:
737 return -EFAULT;
738 case PCIBIOS_SET_FAILED:
739 return -EIO;
740 case PCIBIOS_BUFFER_TOO_SMALL:
741 return -ENOSPC;
742 }
743
744 return -ERANGE;
745 }
746
747 /* Low-level architecture-dependent routines */
748
749 struct pci_ops {
750 int (*add_bus)(struct pci_bus *bus);
751 void (*remove_bus)(struct pci_bus *bus);
752 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
753 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
754 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
755 };
756
757 /*
758 * ACPI needs to be able to access PCI config space before we've done a
759 * PCI bus scan and created pci_bus structures.
760 */
761 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
762 int reg, int len, u32 *val);
763 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
764 int reg, int len, u32 val);
765
766 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
767 typedef u64 pci_bus_addr_t;
768 #else
769 typedef u32 pci_bus_addr_t;
770 #endif
771
772 struct pci_bus_region {
773 pci_bus_addr_t start;
774 pci_bus_addr_t end;
775 };
776
777 struct pci_dynids {
778 spinlock_t lock; /* Protects list, index */
779 struct list_head list; /* For IDs added at runtime */
780 };
781
782
783 /*
784 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
785 * a set of callbacks in struct pci_error_handlers, that device driver
786 * will be notified of PCI bus errors, and will be driven to recovery
787 * when an error occurs.
788 */
789
790 typedef unsigned int __bitwise pci_ers_result_t;
791
792 enum pci_ers_result {
793 /* No result/none/not supported in device driver */
794 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
795
796 /* Device driver can recover without slot reset */
797 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
798
799 /* Device driver wants slot to be reset */
800 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
801
802 /* Device has completely failed, is unrecoverable */
803 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
804
805 /* Device driver is fully recovered and operational */
806 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
807
808 /* No AER capabilities registered for the driver */
809 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
810 };
811
812 /* PCI bus error event callbacks */
813 struct pci_error_handlers {
814 /* PCI bus error detected on this device */
815 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
816 pci_channel_state_t error);
817
818 /* MMIO has been re-enabled, but not DMA */
819 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
820
821 /* PCI slot has been reset */
822 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
823
824 /* PCI function reset prepare or completed */
825 void (*reset_prepare)(struct pci_dev *dev);
826 void (*reset_done)(struct pci_dev *dev);
827
828 /* Device driver may resume normal operations */
829 void (*resume)(struct pci_dev *dev);
830 };
831
832
833 struct module;
834
835 /**
836 * struct pci_driver - PCI driver structure
837 * @node: List of driver structures.
838 * @name: Driver name.
839 * @id_table: Pointer to table of device IDs the driver is
840 * interested in. Most drivers should export this
841 * table using MODULE_DEVICE_TABLE(pci,...).
842 * @probe: This probing function gets called (during execution
843 * of pci_register_driver() for already existing
844 * devices or later if a new device gets inserted) for
845 * all PCI devices which match the ID table and are not
846 * "owned" by the other drivers yet. This function gets
847 * passed a "struct pci_dev \*" for each device whose
848 * entry in the ID table matches the device. The probe
849 * function returns zero when the driver chooses to
850 * take "ownership" of the device or an error code
851 * (negative number) otherwise.
852 * The probe function always gets called from process
853 * context, so it can sleep.
854 * @remove: The remove() function gets called whenever a device
855 * being handled by this driver is removed (either during
856 * deregistration of the driver or when it's manually
857 * pulled out of a hot-pluggable slot).
858 * The remove function always gets called from process
859 * context, so it can sleep.
860 * @suspend: Put device into low power state.
861 * @resume: Wake device from low power state.
862 * (Please see Documentation/power/pci.rst for descriptions
863 * of PCI Power Management and the related functions.)
864 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
865 * Intended to stop any idling DMA operations.
866 * Useful for enabling wake-on-lan (NIC) or changing
867 * the power state of a device before reboot.
868 * e.g. drivers/net/e100.c.
869 * @sriov_configure: Optional driver callback to allow configuration of
870 * number of VFs to enable via sysfs "sriov_numvfs" file.
871 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
872 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
873 * This will change MSI-X Table Size in the VF Message Control
874 * registers.
875 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
876 * MSI-X vectors available for distribution to the VFs.
877 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
878 * @groups: Sysfs attribute groups.
879 * @dev_groups: Attributes attached to the device that will be
880 * created once it is bound to the driver.
881 * @driver: Driver model structure.
882 * @dynids: List of dynamically added device IDs.
883 */
884 struct pci_driver {
885 struct list_head node;
886 const char *name;
887 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
888 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
889 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
890 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
891 int (*resume)(struct pci_dev *dev); /* Device woken up */
892 void (*shutdown)(struct pci_dev *dev);
893 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
894 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
895 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
896 const struct pci_error_handlers *err_handler;
897 const struct attribute_group **groups;
898 const struct attribute_group **dev_groups;
899 struct device_driver driver;
900 struct pci_dynids dynids;
901 };
902
903 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
904
905 /**
906 * PCI_DEVICE - macro used to describe a specific PCI device
907 * @vend: the 16 bit PCI Vendor ID
908 * @dev: the 16 bit PCI Device ID
909 *
910 * This macro is used to create a struct pci_device_id that matches a
911 * specific device. The subvendor and subdevice fields will be set to
912 * PCI_ANY_ID.
913 */
914 #define PCI_DEVICE(vend,dev) \
915 .vendor = (vend), .device = (dev), \
916 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
917
918 /**
919 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
920 * override_only flags.
921 * @vend: the 16 bit PCI Vendor ID
922 * @dev: the 16 bit PCI Device ID
923 * @driver_override: the 32 bit PCI Device override_only
924 *
925 * This macro is used to create a struct pci_device_id that matches only a
926 * driver_override device. The subvendor and subdevice fields will be set to
927 * PCI_ANY_ID.
928 */
929 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
930 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
931 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
932
933 /**
934 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
935 * "driver_override" PCI device.
936 * @vend: the 16 bit PCI Vendor ID
937 * @dev: the 16 bit PCI Device ID
938 *
939 * This macro is used to create a struct pci_device_id that matches a
940 * specific device. The subvendor and subdevice fields will be set to
941 * PCI_ANY_ID and the driver_override will be set to
942 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
943 */
944 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
945 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
946
947 /**
948 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
949 * @vend: the 16 bit PCI Vendor ID
950 * @dev: the 16 bit PCI Device ID
951 * @subvend: the 16 bit PCI Subvendor ID
952 * @subdev: the 16 bit PCI Subdevice ID
953 *
954 * This macro is used to create a struct pci_device_id that matches a
955 * specific device with subsystem information.
956 */
957 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
958 .vendor = (vend), .device = (dev), \
959 .subvendor = (subvend), .subdevice = (subdev)
960
961 /**
962 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
963 * @dev_class: the class, subclass, prog-if triple for this device
964 * @dev_class_mask: the class mask for this device
965 *
966 * This macro is used to create a struct pci_device_id that matches a
967 * specific PCI class. The vendor, device, subvendor, and subdevice
968 * fields will be set to PCI_ANY_ID.
969 */
970 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
971 .class = (dev_class), .class_mask = (dev_class_mask), \
972 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
973 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
974
975 /**
976 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
977 * @vend: the vendor name
978 * @dev: the 16 bit PCI Device ID
979 *
980 * This macro is used to create a struct pci_device_id that matches a
981 * specific PCI device. The subvendor, and subdevice fields will be set
982 * to PCI_ANY_ID. The macro allows the next field to follow as the device
983 * private data.
984 */
985 #define PCI_VDEVICE(vend, dev) \
986 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
987 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
988
989 /**
990 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
991 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
992 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
993 * @data: the driver data to be filled
994 *
995 * This macro is used to create a struct pci_device_id that matches a
996 * specific PCI device. The subvendor, and subdevice fields will be set
997 * to PCI_ANY_ID.
998 */
999 #define PCI_DEVICE_DATA(vend, dev, data) \
1000 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1001 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1002 .driver_data = (kernel_ulong_t)(data)
1003
1004 enum {
1005 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1006 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1007 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1008 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1009 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1010 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1011 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1012 };
1013
1014 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1015 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1016 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1017 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1018
1019 /* These external functions are only available when PCI support is enabled */
1020 #ifdef CONFIG_PCI
1021
1022 extern unsigned int pci_flags;
1023
pci_set_flags(int flags)1024 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)1025 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)1026 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)1027 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1028
1029 void pcie_bus_configure_settings(struct pci_bus *bus);
1030
1031 enum pcie_bus_config_types {
1032 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1033 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1034 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1035 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1036 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1037 };
1038
1039 extern enum pcie_bus_config_types pcie_bus_config;
1040
1041 extern struct bus_type pci_bus_type;
1042
1043 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1044 * code, or PCI core code. */
1045 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1046 /* Some device drivers need know if PCI is initiated */
1047 int no_pci_devices(void);
1048
1049 void pcibios_resource_survey_bus(struct pci_bus *bus);
1050 void pcibios_bus_add_device(struct pci_dev *pdev);
1051 void pcibios_add_bus(struct pci_bus *bus);
1052 void pcibios_remove_bus(struct pci_bus *bus);
1053 void pcibios_fixup_bus(struct pci_bus *);
1054 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1055 /* Architecture-specific versions may override this (weak) */
1056 char *pcibios_setup(char *str);
1057
1058 /* Used only when drivers/pci/setup.c is used */
1059 resource_size_t pcibios_align_resource(void *, const struct resource *,
1060 resource_size_t,
1061 resource_size_t);
1062
1063 /* Weak but can be overridden by arch */
1064 void pci_fixup_cardbus(struct pci_bus *);
1065
1066 /* Generic PCI functions used internally */
1067
1068 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1069 struct resource *res);
1070 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1071 struct pci_bus_region *region);
1072 void pcibios_scan_specific_bus(int busn);
1073 struct pci_bus *pci_find_bus(int domain, int busnr);
1074 void pci_bus_add_devices(const struct pci_bus *bus);
1075 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1076 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1077 struct pci_ops *ops, void *sysdata,
1078 struct list_head *resources);
1079 int pci_host_probe(struct pci_host_bridge *bridge);
1080 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1081 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1082 void pci_bus_release_busn_res(struct pci_bus *b);
1083 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1084 struct pci_ops *ops, void *sysdata,
1085 struct list_head *resources);
1086 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1087 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1088 int busnr);
1089 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1090 const char *name,
1091 struct hotplug_slot *hotplug);
1092 void pci_destroy_slot(struct pci_slot *slot);
1093 #ifdef CONFIG_SYSFS
1094 void pci_dev_assign_slot(struct pci_dev *dev);
1095 #else
pci_dev_assign_slot(struct pci_dev * dev)1096 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1097 #endif
1098 int pci_scan_slot(struct pci_bus *bus, int devfn);
1099 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1100 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1101 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1102 void pci_bus_add_device(struct pci_dev *dev);
1103 void pci_read_bridge_bases(struct pci_bus *child);
1104 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1105 struct resource *res);
1106 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1107 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1108 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1109 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1110 void pci_dev_put(struct pci_dev *dev);
1111 void pci_remove_bus(struct pci_bus *b);
1112 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1113 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1114 void pci_stop_root_bus(struct pci_bus *bus);
1115 void pci_remove_root_bus(struct pci_bus *bus);
1116 void pci_setup_cardbus(struct pci_bus *bus);
1117 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1118 void pci_sort_breadthfirst(void);
1119 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1120 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1121
1122 /* Generic PCI functions exported to card drivers */
1123
1124 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1125 u8 pci_find_capability(struct pci_dev *dev, int cap);
1126 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1127 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1128 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1129 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1130 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1131 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1132 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1133
1134 u64 pci_get_dsn(struct pci_dev *dev);
1135
1136 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1137 struct pci_dev *from);
1138 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1139 unsigned int ss_vendor, unsigned int ss_device,
1140 struct pci_dev *from);
1141 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1142 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1143 unsigned int devfn);
1144 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1145 int pci_dev_present(const struct pci_device_id *ids);
1146
1147 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1148 int where, u8 *val);
1149 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1150 int where, u16 *val);
1151 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1152 int where, u32 *val);
1153 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1154 int where, u8 val);
1155 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1156 int where, u16 val);
1157 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1158 int where, u32 val);
1159
1160 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1161 int where, int size, u32 *val);
1162 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1163 int where, int size, u32 val);
1164 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1165 int where, int size, u32 *val);
1166 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1167 int where, int size, u32 val);
1168
1169 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1170
1171 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1172 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1173 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1174 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1175 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1176 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1177
1178 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1179 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1180 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1181 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1182 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1183 u16 clear, u16 set);
1184 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1185 u32 clear, u32 set);
1186
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1187 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1188 u16 set)
1189 {
1190 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1191 }
1192
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1193 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1194 u32 set)
1195 {
1196 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1197 }
1198
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1199 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1200 u16 clear)
1201 {
1202 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1203 }
1204
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1205 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1206 u32 clear)
1207 {
1208 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1209 }
1210
1211 /* User-space driven config access */
1212 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1213 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1214 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1215 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1216 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1217 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1218
1219 int __must_check pci_enable_device(struct pci_dev *dev);
1220 int __must_check pci_enable_device_io(struct pci_dev *dev);
1221 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1222 int __must_check pci_reenable_device(struct pci_dev *);
1223 int __must_check pcim_enable_device(struct pci_dev *pdev);
1224 void pcim_pin_device(struct pci_dev *pdev);
1225
pci_intx_mask_supported(struct pci_dev * pdev)1226 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1227 {
1228 /*
1229 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1230 * writable and no quirk has marked the feature broken.
1231 */
1232 return !pdev->broken_intx_masking;
1233 }
1234
pci_is_enabled(struct pci_dev * pdev)1235 static inline int pci_is_enabled(struct pci_dev *pdev)
1236 {
1237 return (atomic_read(&pdev->enable_cnt) > 0);
1238 }
1239
pci_is_managed(struct pci_dev * pdev)1240 static inline int pci_is_managed(struct pci_dev *pdev)
1241 {
1242 return pdev->is_managed;
1243 }
1244
1245 void pci_disable_device(struct pci_dev *dev);
1246
1247 extern unsigned int pcibios_max_latency;
1248 void pci_set_master(struct pci_dev *dev);
1249 void pci_clear_master(struct pci_dev *dev);
1250
1251 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1252 int pci_set_cacheline_size(struct pci_dev *dev);
1253 int __must_check pci_set_mwi(struct pci_dev *dev);
1254 int __must_check pcim_set_mwi(struct pci_dev *dev);
1255 int pci_try_set_mwi(struct pci_dev *dev);
1256 void pci_clear_mwi(struct pci_dev *dev);
1257 void pci_disable_parity(struct pci_dev *dev);
1258 void pci_intx(struct pci_dev *dev, int enable);
1259 bool pci_check_and_mask_intx(struct pci_dev *dev);
1260 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1261 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1262 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1263 int pcix_get_max_mmrbc(struct pci_dev *dev);
1264 int pcix_get_mmrbc(struct pci_dev *dev);
1265 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1266 int pcie_get_readrq(struct pci_dev *dev);
1267 int pcie_set_readrq(struct pci_dev *dev, int rq);
1268 int pcie_get_mps(struct pci_dev *dev);
1269 int pcie_set_mps(struct pci_dev *dev, int mps);
1270 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1271 enum pci_bus_speed *speed,
1272 enum pcie_link_width *width);
1273 void pcie_print_link_status(struct pci_dev *dev);
1274 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1275 int pcie_flr(struct pci_dev *dev);
1276 int __pci_reset_function_locked(struct pci_dev *dev);
1277 int pci_reset_function(struct pci_dev *dev);
1278 int pci_reset_function_locked(struct pci_dev *dev);
1279 int pci_try_reset_function(struct pci_dev *dev);
1280 int pci_probe_reset_slot(struct pci_slot *slot);
1281 int pci_probe_reset_bus(struct pci_bus *bus);
1282 int pci_reset_bus(struct pci_dev *dev);
1283 void pci_reset_secondary_bus(struct pci_dev *dev);
1284 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1285 void pci_update_resource(struct pci_dev *dev, int resno);
1286 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1287 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1288 void pci_release_resource(struct pci_dev *dev, int resno);
pci_rebar_bytes_to_size(u64 bytes)1289 static inline int pci_rebar_bytes_to_size(u64 bytes)
1290 {
1291 bytes = roundup_pow_of_two(bytes);
1292
1293 /* Return BAR size as defined in the resizable BAR specification */
1294 return max(ilog2(bytes), 20) - 20;
1295 }
1296
1297 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1298 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1299 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1300 bool pci_device_is_present(struct pci_dev *pdev);
1301 void pci_ignore_hotplug(struct pci_dev *dev);
1302 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1303 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1304
1305 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1306 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1307 const char *fmt, ...);
1308 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1309
1310 /* ROM control related routines */
1311 int pci_enable_rom(struct pci_dev *pdev);
1312 void pci_disable_rom(struct pci_dev *pdev);
1313 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1314 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1315
1316 /* Power management related routines */
1317 int pci_save_state(struct pci_dev *dev);
1318 void pci_restore_state(struct pci_dev *dev);
1319 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1320 int pci_load_saved_state(struct pci_dev *dev,
1321 struct pci_saved_state *state);
1322 int pci_load_and_free_saved_state(struct pci_dev *dev,
1323 struct pci_saved_state **state);
1324 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1325 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1326 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1327 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1328 void pci_pme_active(struct pci_dev *dev, bool enable);
1329 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1330 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1331 int pci_prepare_to_sleep(struct pci_dev *dev);
1332 int pci_back_from_sleep(struct pci_dev *dev);
1333 bool pci_dev_run_wake(struct pci_dev *dev);
1334 void pci_d3cold_enable(struct pci_dev *dev);
1335 void pci_d3cold_disable(struct pci_dev *dev);
1336 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1337 void pci_resume_bus(struct pci_bus *bus);
1338 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1339
1340 /* For use by arch with custom probe code */
1341 void set_pcie_port_type(struct pci_dev *pdev);
1342 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1343
1344 /* Functions for PCI Hotplug drivers to use */
1345 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1346 unsigned int pci_rescan_bus(struct pci_bus *bus);
1347 void pci_lock_rescan_remove(void);
1348 void pci_unlock_rescan_remove(void);
1349
1350 /* Vital Product Data routines */
1351 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1352 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1353
1354 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1355 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1356 void pci_bus_assign_resources(const struct pci_bus *bus);
1357 void pci_bus_claim_resources(struct pci_bus *bus);
1358 void pci_bus_size_bridges(struct pci_bus *bus);
1359 int pci_claim_resource(struct pci_dev *, int);
1360 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1361 void pci_assign_unassigned_resources(void);
1362 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1363 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1364 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1365 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1366 void pdev_enable_device(struct pci_dev *);
1367 int pci_enable_resources(struct pci_dev *, int mask);
1368 void pci_assign_irq(struct pci_dev *dev);
1369 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1370 #define HAVE_PCI_REQ_REGIONS 2
1371 int __must_check pci_request_regions(struct pci_dev *, const char *);
1372 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1373 void pci_release_regions(struct pci_dev *);
1374 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1375 void pci_release_region(struct pci_dev *, int);
1376 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1377 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1378 void pci_release_selected_regions(struct pci_dev *, int);
1379
1380 /* drivers/pci/bus.c */
1381 void pci_add_resource(struct list_head *resources, struct resource *res);
1382 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1383 resource_size_t offset);
1384 void pci_free_resource_list(struct list_head *resources);
1385 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1386 unsigned int flags);
1387 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1388 void pci_bus_remove_resources(struct pci_bus *bus);
1389 int devm_request_pci_bus_resources(struct device *dev,
1390 struct list_head *resources);
1391
1392 /* Temporary until new and working PCI SBR API in place */
1393 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1394
1395 #define pci_bus_for_each_resource(bus, res, i) \
1396 for (i = 0; \
1397 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1398 i++)
1399
1400 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1401 struct resource *res, resource_size_t size,
1402 resource_size_t align, resource_size_t min,
1403 unsigned long type_mask,
1404 resource_size_t (*alignf)(void *,
1405 const struct resource *,
1406 resource_size_t,
1407 resource_size_t),
1408 void *alignf_data);
1409
1410
1411 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1412 resource_size_t size);
1413 unsigned long pci_address_to_pio(phys_addr_t addr);
1414 phys_addr_t pci_pio_to_address(unsigned long pio);
1415 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1416 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1417 phys_addr_t phys_addr);
1418 void pci_unmap_iospace(struct resource *res);
1419 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1420 resource_size_t offset,
1421 resource_size_t size);
1422 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1423 struct resource *res);
1424
pci_bus_address(struct pci_dev * pdev,int bar)1425 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1426 {
1427 struct pci_bus_region region;
1428
1429 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1430 return region.start;
1431 }
1432
1433 /* Proper probing supporting hot-pluggable devices */
1434 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1435 const char *mod_name);
1436
1437 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1438 #define pci_register_driver(driver) \
1439 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1440
1441 void pci_unregister_driver(struct pci_driver *dev);
1442
1443 /**
1444 * module_pci_driver() - Helper macro for registering a PCI driver
1445 * @__pci_driver: pci_driver struct
1446 *
1447 * Helper macro for PCI drivers which do not do anything special in module
1448 * init/exit. This eliminates a lot of boilerplate. Each module may only
1449 * use this macro once, and calling it replaces module_init() and module_exit()
1450 */
1451 #define module_pci_driver(__pci_driver) \
1452 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1453
1454 /**
1455 * builtin_pci_driver() - Helper macro for registering a PCI driver
1456 * @__pci_driver: pci_driver struct
1457 *
1458 * Helper macro for PCI drivers which do not do anything special in their
1459 * init code. This eliminates a lot of boilerplate. Each driver may only
1460 * use this macro once, and calling it replaces device_initcall(...)
1461 */
1462 #define builtin_pci_driver(__pci_driver) \
1463 builtin_driver(__pci_driver, pci_register_driver)
1464
1465 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1466 int pci_add_dynid(struct pci_driver *drv,
1467 unsigned int vendor, unsigned int device,
1468 unsigned int subvendor, unsigned int subdevice,
1469 unsigned int class, unsigned int class_mask,
1470 unsigned long driver_data);
1471 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1472 struct pci_dev *dev);
1473 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1474 int pass);
1475
1476 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1477 void *userdata);
1478 int pci_cfg_space_size(struct pci_dev *dev);
1479 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1480 void pci_setup_bridge(struct pci_bus *bus);
1481 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1482 unsigned long type);
1483
1484 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1485 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1486
1487 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1488 unsigned int command_bits, u32 flags);
1489
1490 /*
1491 * Virtual interrupts allow for more interrupts to be allocated
1492 * than the device has interrupts for. These are not programmed
1493 * into the device's MSI-X table and must be handled by some
1494 * other driver means.
1495 */
1496 #define PCI_IRQ_VIRTUAL (1 << 4)
1497
1498 #define PCI_IRQ_ALL_TYPES \
1499 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1500
1501 /* kmem_cache style wrapper around pci_alloc_consistent() */
1502
1503 #include <linux/dmapool.h>
1504
1505 #define pci_pool dma_pool
1506 #define pci_pool_create(name, pdev, size, align, allocation) \
1507 dma_pool_create(name, &pdev->dev, size, align, allocation)
1508 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1509 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1510 #define pci_pool_zalloc(pool, flags, handle) \
1511 dma_pool_zalloc(pool, flags, handle)
1512 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1513
1514 struct msix_entry {
1515 u32 vector; /* Kernel uses to write allocated vector */
1516 u16 entry; /* Driver uses to specify entry, OS writes */
1517 };
1518
1519 #ifdef CONFIG_PCI_MSI
1520 int pci_msi_vec_count(struct pci_dev *dev);
1521 void pci_disable_msi(struct pci_dev *dev);
1522 int pci_msix_vec_count(struct pci_dev *dev);
1523 void pci_disable_msix(struct pci_dev *dev);
1524 void pci_restore_msi_state(struct pci_dev *dev);
1525 int pci_msi_enabled(void);
1526 int pci_enable_msi(struct pci_dev *dev);
1527 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1528 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1529 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1530 struct msix_entry *entries, int nvec)
1531 {
1532 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1533 if (rc < 0)
1534 return rc;
1535 return 0;
1536 }
1537 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1538 unsigned int max_vecs, unsigned int flags,
1539 struct irq_affinity *affd);
1540
1541 void pci_free_irq_vectors(struct pci_dev *dev);
1542 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1543 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1544
1545 #else
pci_msi_vec_count(struct pci_dev * dev)1546 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1547 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1548 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1549 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1550 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1551 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1552 static inline int pci_enable_msi(struct pci_dev *dev)
1553 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1554 static inline int pci_enable_msix_range(struct pci_dev *dev,
1555 struct msix_entry *entries, int minvec, int maxvec)
1556 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1557 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1558 struct msix_entry *entries, int nvec)
1559 { return -ENOSYS; }
1560
1561 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1562 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1563 unsigned int max_vecs, unsigned int flags,
1564 struct irq_affinity *aff_desc)
1565 {
1566 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1567 return 1;
1568 return -ENOSPC;
1569 }
1570
pci_free_irq_vectors(struct pci_dev * dev)1571 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1572 {
1573 }
1574
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1575 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1576 {
1577 if (WARN_ON_ONCE(nr > 0))
1578 return -EINVAL;
1579 return dev->irq;
1580 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1581 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1582 int vec)
1583 {
1584 return cpu_possible_mask;
1585 }
1586 #endif
1587
1588 /**
1589 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1590 * @d: the INTx IRQ domain
1591 * @node: the DT node for the device whose interrupt we're translating
1592 * @intspec: the interrupt specifier data from the DT
1593 * @intsize: the number of entries in @intspec
1594 * @out_hwirq: pointer at which to write the hwirq number
1595 * @out_type: pointer at which to write the interrupt type
1596 *
1597 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1598 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1599 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1600 * INTx value to obtain the hwirq number.
1601 *
1602 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1603 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1604 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1605 struct device_node *node,
1606 const u32 *intspec,
1607 unsigned int intsize,
1608 unsigned long *out_hwirq,
1609 unsigned int *out_type)
1610 {
1611 const u32 intx = intspec[0];
1612
1613 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1614 return -EINVAL;
1615
1616 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1617 return 0;
1618 }
1619
1620 #ifdef CONFIG_PCIEPORTBUS
1621 extern bool pcie_ports_disabled;
1622 extern bool pcie_ports_native;
1623 #else
1624 #define pcie_ports_disabled true
1625 #define pcie_ports_native false
1626 #endif
1627
1628 #define PCIE_LINK_STATE_L0S BIT(0)
1629 #define PCIE_LINK_STATE_L1 BIT(1)
1630 #define PCIE_LINK_STATE_CLKPM BIT(2)
1631 #define PCIE_LINK_STATE_L1_1 BIT(3)
1632 #define PCIE_LINK_STATE_L1_2 BIT(4)
1633 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1634 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1635
1636 #ifdef CONFIG_PCIEASPM
1637 int pci_disable_link_state(struct pci_dev *pdev, int state);
1638 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1639 void pcie_no_aspm(void);
1640 bool pcie_aspm_support_enabled(void);
1641 bool pcie_aspm_enabled(struct pci_dev *pdev);
1642 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1643 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1644 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1645 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1646 { return 0; }
pcie_no_aspm(void)1647 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1648 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1649 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1650 #endif
1651
1652 #ifdef CONFIG_PCIEAER
1653 bool pci_aer_available(void);
1654 #else
pci_aer_available(void)1655 static inline bool pci_aer_available(void) { return false; }
1656 #endif
1657
1658 bool pci_ats_disabled(void);
1659
1660 #ifdef CONFIG_PCIE_PTM
1661 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1662 bool pcie_ptm_enabled(struct pci_dev *dev);
1663 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1664 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1665 { return -EINVAL; }
pcie_ptm_enabled(struct pci_dev * dev)1666 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1667 { return false; }
1668 #endif
1669
1670 void pci_cfg_access_lock(struct pci_dev *dev);
1671 bool pci_cfg_access_trylock(struct pci_dev *dev);
1672 void pci_cfg_access_unlock(struct pci_dev *dev);
1673
1674 int pci_dev_trylock(struct pci_dev *dev);
1675 void pci_dev_unlock(struct pci_dev *dev);
1676
1677 /*
1678 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1679 * a PCI domain is defined to be a set of PCI buses which share
1680 * configuration space.
1681 */
1682 #ifdef CONFIG_PCI_DOMAINS
1683 extern int pci_domains_supported;
1684 #else
1685 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1686 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1687 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1688 #endif /* CONFIG_PCI_DOMAINS */
1689
1690 /*
1691 * Generic implementation for PCI domain support. If your
1692 * architecture does not need custom management of PCI
1693 * domains then this implementation will be used
1694 */
1695 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1696 static inline int pci_domain_nr(struct pci_bus *bus)
1697 {
1698 return bus->domain_nr;
1699 }
1700 #ifdef CONFIG_ACPI
1701 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1702 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1703 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1704 { return 0; }
1705 #endif
1706 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1707 #endif
1708
1709 /* Some architectures require additional setup to direct VGA traffic */
1710 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1711 unsigned int command_bits, u32 flags);
1712 void pci_register_set_vga_state(arch_set_vga_state_t func);
1713
1714 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1715 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1716 {
1717 return pci_request_selected_regions(pdev,
1718 pci_select_bars(pdev, IORESOURCE_IO), name);
1719 }
1720
1721 static inline void
pci_release_io_regions(struct pci_dev * pdev)1722 pci_release_io_regions(struct pci_dev *pdev)
1723 {
1724 return pci_release_selected_regions(pdev,
1725 pci_select_bars(pdev, IORESOURCE_IO));
1726 }
1727
1728 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1729 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1730 {
1731 return pci_request_selected_regions(pdev,
1732 pci_select_bars(pdev, IORESOURCE_MEM), name);
1733 }
1734
1735 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1736 pci_release_mem_regions(struct pci_dev *pdev)
1737 {
1738 return pci_release_selected_regions(pdev,
1739 pci_select_bars(pdev, IORESOURCE_MEM));
1740 }
1741
1742 #else /* CONFIG_PCI is not enabled */
1743
pci_set_flags(int flags)1744 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1745 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1746 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1747 static inline int pci_has_flag(int flag) { return 0; }
1748
1749 /*
1750 * If the system does not have PCI, clearly these return errors. Define
1751 * these as simple inline functions to avoid hair in drivers.
1752 */
1753 #define _PCI_NOP(o, s, t) \
1754 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1755 int where, t val) \
1756 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1757
1758 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1759 _PCI_NOP(o, word, u16 x) \
1760 _PCI_NOP(o, dword, u32 x)
1761 _PCI_NOP_ALL(read, *)
1762 _PCI_NOP_ALL(write,)
1763
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1764 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1765 unsigned int device,
1766 struct pci_dev *from)
1767 { return NULL; }
1768
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1769 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1770 unsigned int device,
1771 unsigned int ss_vendor,
1772 unsigned int ss_device,
1773 struct pci_dev *from)
1774 { return NULL; }
1775
pci_get_class(unsigned int class,struct pci_dev * from)1776 static inline struct pci_dev *pci_get_class(unsigned int class,
1777 struct pci_dev *from)
1778 { return NULL; }
1779
1780 #define pci_dev_present(ids) (0)
1781 #define no_pci_devices() (1)
1782 #define pci_dev_put(dev) do { } while (0)
1783
pci_set_master(struct pci_dev * dev)1784 static inline void pci_set_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1785 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1786 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1787 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1788 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1789 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1790 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1791 struct module *owner,
1792 const char *mod_name)
1793 { return 0; }
pci_register_driver(struct pci_driver * drv)1794 static inline int pci_register_driver(struct pci_driver *drv)
1795 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1796 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1797 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1798 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1799 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1800 int cap)
1801 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1802 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1803 { return 0; }
1804
pci_get_dsn(struct pci_dev * dev)1805 static inline u64 pci_get_dsn(struct pci_dev *dev)
1806 { return 0; }
1807
1808 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1809 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1810 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1811 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1812 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1813 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1814 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1815 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1816 pm_message_t state)
1817 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1818 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1819 int enable)
1820 { return 0; }
1821
pci_find_resource(struct pci_dev * dev,struct resource * res)1822 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1823 struct resource *res)
1824 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1825 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1826 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1827 static inline void pci_release_regions(struct pci_dev *dev) { }
1828
pci_register_io_range(struct fwnode_handle * fwnode,phys_addr_t addr,resource_size_t size)1829 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1830 phys_addr_t addr, resource_size_t size)
1831 { return -EINVAL; }
1832
pci_address_to_pio(phys_addr_t addr)1833 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1834
pci_find_next_bus(const struct pci_bus * from)1835 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1836 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1837 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1838 unsigned int devfn)
1839 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1840 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1841 unsigned int bus, unsigned int devfn)
1842 { return NULL; }
1843
pci_domain_nr(struct pci_bus * bus)1844 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1845 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1846
1847 #define dev_is_pci(d) (false)
1848 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1849 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1850 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1851 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1852 struct device_node *node,
1853 const u32 *intspec,
1854 unsigned int intsize,
1855 unsigned long *out_hwirq,
1856 unsigned int *out_type)
1857 { return -EINVAL; }
1858
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1859 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1860 struct pci_dev *dev)
1861 { return NULL; }
pci_ats_disabled(void)1862 static inline bool pci_ats_disabled(void) { return true; }
1863
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1864 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1865 {
1866 return -EINVAL;
1867 }
1868
1869 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1870 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1871 unsigned int max_vecs, unsigned int flags,
1872 struct irq_affinity *aff_desc)
1873 {
1874 return -ENOSPC;
1875 }
1876 #endif /* CONFIG_PCI */
1877
1878 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1879 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1880 unsigned int max_vecs, unsigned int flags)
1881 {
1882 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1883 NULL);
1884 }
1885
1886 /* Include architecture-dependent settings and functions */
1887
1888 #include <asm/pci.h>
1889
1890 /* These two functions provide almost identical functionality. Depending
1891 * on the architecture, one will be implemented as a wrapper around the
1892 * other (in drivers/pci/mmap.c).
1893 *
1894 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1895 * is expected to be an offset within that region.
1896 *
1897 * pci_mmap_page_range() is the legacy architecture-specific interface,
1898 * which accepts a "user visible" resource address converted by
1899 * pci_resource_to_user(), as used in the legacy mmap() interface in
1900 * /proc/bus/pci/.
1901 */
1902 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1903 struct vm_area_struct *vma,
1904 enum pci_mmap_state mmap_state, int write_combine);
1905 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1906 struct vm_area_struct *vma,
1907 enum pci_mmap_state mmap_state, int write_combine);
1908
1909 #ifndef arch_can_pci_mmap_wc
1910 #define arch_can_pci_mmap_wc() 0
1911 #endif
1912
1913 #ifndef arch_can_pci_mmap_io
1914 #define arch_can_pci_mmap_io() 0
1915 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1916 #else
1917 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1918 #endif
1919
1920 #ifndef pci_root_bus_fwnode
1921 #define pci_root_bus_fwnode(bus) NULL
1922 #endif
1923
1924 /*
1925 * These helpers provide future and backwards compatibility
1926 * for accessing popular PCI BAR info
1927 */
1928 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1929 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1930 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1931 #define pci_resource_len(dev,bar) \
1932 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1933 \
1934 (pci_resource_end((dev), (bar)) - \
1935 pci_resource_start((dev), (bar)) + 1))
1936
1937 /*
1938 * Similar to the helpers above, these manipulate per-pci_dev
1939 * driver-specific data. They are really just a wrapper around
1940 * the generic device structure functions of these calls.
1941 */
pci_get_drvdata(struct pci_dev * pdev)1942 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1943 {
1944 return dev_get_drvdata(&pdev->dev);
1945 }
1946
pci_set_drvdata(struct pci_dev * pdev,void * data)1947 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1948 {
1949 dev_set_drvdata(&pdev->dev, data);
1950 }
1951
pci_name(const struct pci_dev * pdev)1952 static inline const char *pci_name(const struct pci_dev *pdev)
1953 {
1954 return dev_name(&pdev->dev);
1955 }
1956
1957 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1958 const struct resource *rsrc,
1959 resource_size_t *start, resource_size_t *end);
1960
1961 /*
1962 * The world is not perfect and supplies us with broken PCI devices.
1963 * For at least a part of these bugs we need a work-around, so both
1964 * generic (drivers/pci/quirks.c) and per-architecture code can define
1965 * fixup hooks to be called for particular buggy devices.
1966 */
1967
1968 struct pci_fixup {
1969 u16 vendor; /* Or PCI_ANY_ID */
1970 u16 device; /* Or PCI_ANY_ID */
1971 u32 class; /* Or PCI_ANY_ID */
1972 unsigned int class_shift; /* should be 0, 8, 16 */
1973 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1974 int hook_offset;
1975 #else
1976 void (*hook)(struct pci_dev *dev);
1977 #endif
1978 };
1979
1980 enum pci_fixup_pass {
1981 pci_fixup_early, /* Before probing BARs */
1982 pci_fixup_header, /* After reading configuration header */
1983 pci_fixup_final, /* Final phase of device fixups */
1984 pci_fixup_enable, /* pci_enable_device() time */
1985 pci_fixup_resume, /* pci_device_resume() */
1986 pci_fixup_suspend, /* pci_device_suspend() */
1987 pci_fixup_resume_early, /* pci_device_resume_early() */
1988 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1989 };
1990
1991 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1992 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1993 class_shift, hook) \
1994 __ADDRESSABLE(hook) \
1995 asm(".section " #sec ", \"a\" \n" \
1996 ".balign 16 \n" \
1997 ".short " #vendor ", " #device " \n" \
1998 ".long " #class ", " #class_shift " \n" \
1999 ".long " #hook " - . \n" \
2000 ".previous \n");
2001
2002 /*
2003 * Clang's LTO may rename static functions in C, but has no way to
2004 * handle such renamings when referenced from inline asm. To work
2005 * around this, create global C stubs for these cases.
2006 */
2007 #ifdef CONFIG_LTO_CLANG
2008 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2009 class_shift, hook, stub) \
2010 void __cficanonical stub(struct pci_dev *dev); \
2011 void __cficanonical stub(struct pci_dev *dev) \
2012 { \
2013 hook(dev); \
2014 } \
2015 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2016 class_shift, stub)
2017 #else
2018 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2019 class_shift, hook, stub) \
2020 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2021 class_shift, hook)
2022 #endif
2023
2024 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2025 class_shift, hook) \
2026 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2027 class_shift, hook, __UNIQUE_ID(hook))
2028 #else
2029 /* Anonymous variables would be nice... */
2030 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2031 class_shift, hook) \
2032 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2033 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2034 = { vendor, device, class, class_shift, hook };
2035 #endif
2036
2037 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2038 class_shift, hook) \
2039 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2040 hook, vendor, device, class, class_shift, hook)
2041 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2042 class_shift, hook) \
2043 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2044 hook, vendor, device, class, class_shift, hook)
2045 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2046 class_shift, hook) \
2047 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2048 hook, vendor, device, class, class_shift, hook)
2049 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2050 class_shift, hook) \
2051 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2052 hook, vendor, device, class, class_shift, hook)
2053 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2054 class_shift, hook) \
2055 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2056 resume##hook, vendor, device, class, class_shift, hook)
2057 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2058 class_shift, hook) \
2059 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2060 resume_early##hook, vendor, device, class, class_shift, hook)
2061 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2062 class_shift, hook) \
2063 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2064 suspend##hook, vendor, device, class, class_shift, hook)
2065 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2066 class_shift, hook) \
2067 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2068 suspend_late##hook, vendor, device, class, class_shift, hook)
2069
2070 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2071 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2072 hook, vendor, device, PCI_ANY_ID, 0, hook)
2073 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2074 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2075 hook, vendor, device, PCI_ANY_ID, 0, hook)
2076 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2078 hook, vendor, device, PCI_ANY_ID, 0, hook)
2079 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2080 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2081 hook, vendor, device, PCI_ANY_ID, 0, hook)
2082 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2083 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2084 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2085 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2086 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2087 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2088 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2089 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2090 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2091 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2092 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2093 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2094
2095 #ifdef CONFIG_PCI_QUIRKS
2096 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2097 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2098 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2099 struct pci_dev *dev) { }
2100 #endif
2101
2102 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2103 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2104 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2105 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2106 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2107 const char *name);
2108 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2109
2110 extern int pci_pci_problems;
2111 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2112 #define PCIPCI_TRITON 2
2113 #define PCIPCI_NATOMA 4
2114 #define PCIPCI_VIAETBF 8
2115 #define PCIPCI_VSFX 16
2116 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2117 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2118
2119 extern unsigned long pci_cardbus_io_size;
2120 extern unsigned long pci_cardbus_mem_size;
2121 extern u8 pci_dfl_cache_line_size;
2122 extern u8 pci_cache_line_size;
2123
2124 /* Architecture-specific versions may override these (weak) */
2125 void pcibios_disable_device(struct pci_dev *dev);
2126 void pcibios_set_master(struct pci_dev *dev);
2127 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2128 enum pcie_reset_state state);
2129 int pcibios_add_device(struct pci_dev *dev);
2130 void pcibios_release_device(struct pci_dev *dev);
2131 #ifdef CONFIG_PCI
2132 void pcibios_penalize_isa_irq(int irq, int active);
2133 #else
pcibios_penalize_isa_irq(int irq,int active)2134 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2135 #endif
2136 int pcibios_alloc_irq(struct pci_dev *dev);
2137 void pcibios_free_irq(struct pci_dev *dev);
2138 resource_size_t pcibios_default_alignment(void);
2139
2140 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2141 void __init pci_mmcfg_early_init(void);
2142 void __init pci_mmcfg_late_init(void);
2143 #else
pci_mmcfg_early_init(void)2144 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2145 static inline void pci_mmcfg_late_init(void) { }
2146 #endif
2147
2148 int pci_ext_cfg_avail(void);
2149
2150 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2151 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2152
2153 #ifdef CONFIG_PCI_IOV
2154 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2155 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2156
2157 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2158 void pci_disable_sriov(struct pci_dev *dev);
2159
2160 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2161 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2162 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2163 int pci_num_vf(struct pci_dev *dev);
2164 int pci_vfs_assigned(struct pci_dev *dev);
2165 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2166 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2167 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2168 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2169 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2170
2171 /* Arch may override these (weak) */
2172 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2173 int pcibios_sriov_disable(struct pci_dev *pdev);
2174 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2175 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2176 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2177 {
2178 return -ENOSYS;
2179 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2180 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2181 {
2182 return -ENOSYS;
2183 }
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2184 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2185 { return -ENODEV; }
2186
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2187 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2188 struct pci_dev *virtfn, int id)
2189 {
2190 return -ENODEV;
2191 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2192 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2193 {
2194 return -ENOSYS;
2195 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2196 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2197 int id) { }
pci_disable_sriov(struct pci_dev * dev)2198 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2199 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2200 static inline int pci_vfs_assigned(struct pci_dev *dev)
2201 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2202 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2203 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2204 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2205 { return 0; }
2206 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2207 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2208 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2209 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2210 #endif
2211
2212 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2213 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2214 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2215 #endif
2216
2217 /**
2218 * pci_pcie_cap - get the saved PCIe capability offset
2219 * @dev: PCI device
2220 *
2221 * PCIe capability offset is calculated at PCI device initialization
2222 * time and saved in the data structure. This function returns saved
2223 * PCIe capability offset. Using this instead of pci_find_capability()
2224 * reduces unnecessary search in the PCI configuration space. If you
2225 * need to calculate PCIe capability offset from raw device for some
2226 * reasons, please use pci_find_capability() instead.
2227 */
pci_pcie_cap(struct pci_dev * dev)2228 static inline int pci_pcie_cap(struct pci_dev *dev)
2229 {
2230 return dev->pcie_cap;
2231 }
2232
2233 /**
2234 * pci_is_pcie - check if the PCI device is PCI Express capable
2235 * @dev: PCI device
2236 *
2237 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2238 */
pci_is_pcie(struct pci_dev * dev)2239 static inline bool pci_is_pcie(struct pci_dev *dev)
2240 {
2241 return pci_pcie_cap(dev);
2242 }
2243
2244 /**
2245 * pcie_caps_reg - get the PCIe Capabilities Register
2246 * @dev: PCI device
2247 */
pcie_caps_reg(const struct pci_dev * dev)2248 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2249 {
2250 return dev->pcie_flags_reg;
2251 }
2252
2253 /**
2254 * pci_pcie_type - get the PCIe device/port type
2255 * @dev: PCI device
2256 */
pci_pcie_type(const struct pci_dev * dev)2257 static inline int pci_pcie_type(const struct pci_dev *dev)
2258 {
2259 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2260 }
2261
2262 /**
2263 * pcie_find_root_port - Get the PCIe root port device
2264 * @dev: PCI device
2265 *
2266 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2267 * for a given PCI/PCIe Device.
2268 */
pcie_find_root_port(struct pci_dev * dev)2269 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2270 {
2271 while (dev) {
2272 if (pci_is_pcie(dev) &&
2273 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2274 return dev;
2275 dev = pci_upstream_bridge(dev);
2276 }
2277
2278 return NULL;
2279 }
2280
2281 void pci_request_acs(void);
2282 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2283 bool pci_acs_path_enabled(struct pci_dev *start,
2284 struct pci_dev *end, u16 acs_flags);
2285 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2286
2287 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2288 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2289
2290 /* Large Resource Data Type Tag Item Names */
2291 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2292 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2293 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2294
2295 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2296 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2297 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2298
2299 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2300 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2301 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2302 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2303 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2304
2305 /**
2306 * pci_vpd_alloc - Allocate buffer and read VPD into it
2307 * @dev: PCI device
2308 * @size: pointer to field where VPD length is returned
2309 *
2310 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2311 */
2312 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2313
2314 /**
2315 * pci_vpd_find_id_string - Locate id string in VPD
2316 * @buf: Pointer to buffered VPD data
2317 * @len: The length of the buffer area in which to search
2318 * @size: Pointer to field where length of id string is returned
2319 *
2320 * Returns the index of the id string or -ENOENT if not found.
2321 */
2322 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2323
2324 /**
2325 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2326 * @buf: Pointer to buffered VPD data
2327 * @len: The length of the buffer area in which to search
2328 * @kw: The keyword to search for
2329 * @size: Pointer to field where length of found keyword data is returned
2330 *
2331 * Returns the index of the information field keyword data or -ENOENT if
2332 * not found.
2333 */
2334 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2335 const char *kw, unsigned int *size);
2336
2337 /**
2338 * pci_vpd_check_csum - Check VPD checksum
2339 * @buf: Pointer to buffered VPD data
2340 * @len: VPD size
2341 *
2342 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2343 */
2344 int pci_vpd_check_csum(const void *buf, unsigned int len);
2345
2346 /* PCI <-> OF binding helpers */
2347 #ifdef CONFIG_OF
2348 struct device_node;
2349 struct irq_domain;
2350 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2351 bool pci_host_of_has_msi_map(struct device *dev);
2352
2353 /* Arch may override this (weak) */
2354 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2355
2356 #else /* CONFIG_OF */
2357 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2358 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
pci_host_of_has_msi_map(struct device * dev)2359 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2360 #endif /* CONFIG_OF */
2361
2362 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2363 pci_device_to_OF_node(const struct pci_dev *pdev)
2364 {
2365 return pdev ? pdev->dev.of_node : NULL;
2366 }
2367
pci_bus_to_OF_node(struct pci_bus * bus)2368 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2369 {
2370 return bus ? bus->dev.of_node : NULL;
2371 }
2372
2373 #ifdef CONFIG_ACPI
2374 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2375
2376 void
2377 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2378 bool pci_pr3_present(struct pci_dev *pdev);
2379 #else
2380 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2381 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2382 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2383 #endif
2384
2385 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2386 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2387 {
2388 return pdev->dev.archdata.edev;
2389 }
2390 #endif
2391
2392 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2393 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2394 int pci_for_each_dma_alias(struct pci_dev *pdev,
2395 int (*fn)(struct pci_dev *pdev,
2396 u16 alias, void *data), void *data);
2397
2398 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2399 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2400 {
2401 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2402 }
pci_clear_dev_assigned(struct pci_dev * pdev)2403 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2404 {
2405 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2406 }
pci_is_dev_assigned(struct pci_dev * pdev)2407 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2408 {
2409 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2410 }
2411
2412 /**
2413 * pci_ari_enabled - query ARI forwarding status
2414 * @bus: the PCI bus
2415 *
2416 * Returns true if ARI forwarding is enabled.
2417 */
pci_ari_enabled(struct pci_bus * bus)2418 static inline bool pci_ari_enabled(struct pci_bus *bus)
2419 {
2420 return bus->self && bus->self->ari_enabled;
2421 }
2422
2423 /**
2424 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2425 * @pdev: PCI device to check
2426 *
2427 * Walk upwards from @pdev and check for each encountered bridge if it's part
2428 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2429 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2430 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2431 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2432 {
2433 struct pci_dev *parent = pdev;
2434
2435 if (pdev->is_thunderbolt)
2436 return true;
2437
2438 while ((parent = pci_upstream_bridge(parent)))
2439 if (parent->is_thunderbolt)
2440 return true;
2441
2442 return false;
2443 }
2444
2445 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2446 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2447 #endif
2448
2449 /* Provide the legacy pci_dma_* API */
2450 #include <linux/pci-dma-compat.h>
2451
2452 #define pci_printk(level, pdev, fmt, arg...) \
2453 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2454
2455 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2456 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2457 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2458 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2459 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2460 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2461 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2462 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2463
2464 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2465 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2466
2467 #define pci_info_ratelimited(pdev, fmt, arg...) \
2468 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2469
2470 #define pci_WARN(pdev, condition, fmt, arg...) \
2471 WARN(condition, "%s %s: " fmt, \
2472 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2473
2474 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2475 WARN_ONCE(condition, "%s %s: " fmt, \
2476 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2477
2478 #endif /* LINUX_PCI_H */
2479
