1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/linkage.h>
3 #include <linux/errno.h>
4 #include <linux/signal.h>
5 #include <linux/sched.h>
6 #include <linux/ioport.h>
7 #include <linux/interrupt.h>
8 #include <linux/irq.h>
9 #include <linux/timex.h>
10 #include <linux/random.h>
11 #include <linux/kprobes.h>
12 #include <linux/init.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/device.h>
15 #include <linux/bitops.h>
16 #include <linux/acpi.h>
17 #include <linux/io.h>
18 #include <linux/delay.h>
19
20 #include <linux/atomic.h>
21 #include <asm/timer.h>
22 #include <asm/hw_irq.h>
23 #include <asm/pgtable.h>
24 #include <asm/desc.h>
25 #include <asm/apic.h>
26 #include <asm/setup.h>
27 #include <asm/i8259.h>
28 #include <asm/traps.h>
29 #include <asm/prom.h>
30
31 /*
32 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
33 * (these are usually mapped to vectors 0x30-0x3f)
34 */
35
36 /*
37 * The IO-APIC gives us many more interrupt sources. Most of these
38 * are unused but an SMP system is supposed to have enough memory ...
39 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
40 * across the spectrum, so we really want to be prepared to get all
41 * of these. Plus, more powerful systems might have more than 64
42 * IO-APIC registers.
43 *
44 * (these are usually mapped into the 0x30-0xff vector range)
45 */
46
47 /*
48 * IRQ2 is cascade interrupt to second interrupt controller
49 */
50 static struct irqaction irq2 = {
51 .handler = no_action,
52 .name = "cascade",
53 .flags = IRQF_NO_THREAD,
54 };
55
56 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
57 [0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
58 };
59
init_ISA_irqs(void)60 void __init init_ISA_irqs(void)
61 {
62 struct irq_chip *chip = legacy_pic->chip;
63 int i;
64
65 /*
66 * Try to set up the through-local-APIC virtual wire mode earlier.
67 *
68 * On some 32-bit UP machines, whose APIC has been disabled by BIOS
69 * and then got re-enabled by "lapic", it hangs at boot time without this.
70 */
71 init_bsp_APIC();
72
73 legacy_pic->init(0);
74
75 for (i = 0; i < nr_legacy_irqs(); i++)
76 irq_set_chip_and_handler(i, chip, handle_level_irq);
77 }
78
init_IRQ(void)79 void __init init_IRQ(void)
80 {
81 int i;
82
83 /*
84 * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
85 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
86 * then this configuration will likely be static after the boot. If
87 * these IRQ's are handled by more mordern controllers like IO-APIC,
88 * then this vector space can be freed and re-used dynamically as the
89 * irq's migrate etc.
90 */
91 for (i = 0; i < nr_legacy_irqs(); i++)
92 per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
93
94 BUG_ON(irq_init_percpu_irqstack(smp_processor_id()));
95
96 x86_init.irqs.intr_init();
97 }
98
native_init_IRQ(void)99 void __init native_init_IRQ(void)
100 {
101 /* Execute any quirks before the call gates are initialised: */
102 x86_init.irqs.pre_vector_init();
103
104 idt_setup_apic_and_irq_gates();
105 lapic_assign_system_vectors();
106
107 if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
108 setup_irq(2, &irq2);
109 }
110
