1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef _ASM_X86_APIC_H
3 #define _ASM_X86_APIC_H
4
5 #include <linux/cpumask.h>
6
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/apicdef.h>
10 #include <linux/atomic.h>
11 #include <asm/fixmap.h>
12 #include <asm/mpspec.h>
13 #include <asm/msr.h>
14 #include <asm/hardirq.h>
15
16 #define ARCH_APICTIMER_STOPS_ON_C3 1
17
18 /*
19 * Debugging macros
20 */
21 #define APIC_QUIET 0
22 #define APIC_VERBOSE 1
23 #define APIC_DEBUG 2
24
25 /* Macros for apic_extnmi which controls external NMI masking */
26 #define APIC_EXTNMI_BSP 0 /* Default */
27 #define APIC_EXTNMI_ALL 1
28 #define APIC_EXTNMI_NONE 2
29
30 /*
31 * Define the default level of output to be very little
32 * This can be turned up by using apic=verbose for more
33 * information and apic=debug for _lots_ of information.
34 * apic_verbosity is defined in apic.c
35 */
36 #define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
38 printk(s, ##a); \
39 } while (0)
40
41
42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43 extern void generic_apic_probe(void);
44 #else
generic_apic_probe(void)45 static inline void generic_apic_probe(void)
46 {
47 }
48 #endif
49
50 #ifdef CONFIG_X86_LOCAL_APIC
51
52 extern int apic_verbosity;
53 extern int local_apic_timer_c2_ok;
54
55 extern int disable_apic;
56 extern unsigned int lapic_timer_period;
57
58 extern enum apic_intr_mode_id apic_intr_mode;
59 enum apic_intr_mode_id {
60 APIC_PIC,
61 APIC_VIRTUAL_WIRE,
62 APIC_VIRTUAL_WIRE_NO_CONFIG,
63 APIC_SYMMETRIC_IO,
64 APIC_SYMMETRIC_IO_NO_ROUTING
65 };
66
67 #ifdef CONFIG_SMP
68 extern void __inquire_remote_apic(int apicid);
69 #else /* CONFIG_SMP */
__inquire_remote_apic(int apicid)70 static inline void __inquire_remote_apic(int apicid)
71 {
72 }
73 #endif /* CONFIG_SMP */
74
default_inquire_remote_apic(int apicid)75 static inline void default_inquire_remote_apic(int apicid)
76 {
77 if (apic_verbosity >= APIC_DEBUG)
78 __inquire_remote_apic(apicid);
79 }
80
81 /*
82 * With 82489DX we can't rely on apic feature bit
83 * retrieved via cpuid but still have to deal with
84 * such an apic chip so we assume that SMP configuration
85 * is found from MP table (64bit case uses ACPI mostly
86 * which set smp presence flag as well so we are safe
87 * to use this helper too).
88 */
apic_from_smp_config(void)89 static inline bool apic_from_smp_config(void)
90 {
91 return smp_found_config && !disable_apic;
92 }
93
94 /*
95 * Basic functions accessing APICs.
96 */
97 #ifdef CONFIG_PARAVIRT
98 #include <asm/paravirt.h>
99 #endif
100
101 extern int setup_profiling_timer(unsigned int);
102
native_apic_mem_write(u32 reg,u32 v)103 static inline void native_apic_mem_write(u32 reg, u32 v)
104 {
105 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
106
107 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
108 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
109 ASM_OUTPUT2("0" (v), "m" (*addr)));
110 }
111
native_apic_mem_read(u32 reg)112 static inline u32 native_apic_mem_read(u32 reg)
113 {
114 return *((volatile u32 *)(APIC_BASE + reg));
115 }
116
117 extern void native_apic_wait_icr_idle(void);
118 extern u32 native_safe_apic_wait_icr_idle(void);
119 extern void native_apic_icr_write(u32 low, u32 id);
120 extern u64 native_apic_icr_read(void);
121
apic_is_x2apic_enabled(void)122 static inline bool apic_is_x2apic_enabled(void)
123 {
124 u64 msr;
125
126 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
127 return false;
128 return msr & X2APIC_ENABLE;
129 }
130
131 extern void enable_IR_x2apic(void);
132
133 extern int get_physical_broadcast(void);
134
135 extern int lapic_get_maxlvt(void);
136 extern void clear_local_APIC(void);
137 extern void disconnect_bsp_APIC(int virt_wire_setup);
138 extern void disable_local_APIC(void);
139 extern void apic_soft_disable(void);
140 extern void lapic_shutdown(void);
141 extern void sync_Arb_IDs(void);
142 extern void init_bsp_APIC(void);
143 extern void apic_intr_mode_init(void);
144 extern void init_apic_mappings(void);
145 void register_lapic_address(unsigned long address);
146 extern void setup_boot_APIC_clock(void);
147 extern void setup_secondary_APIC_clock(void);
148 extern void lapic_update_tsc_freq(void);
149
150 #ifdef CONFIG_X86_64
apic_force_enable(unsigned long addr)151 static inline int apic_force_enable(unsigned long addr)
152 {
153 return -1;
154 }
155 #else
156 extern int apic_force_enable(unsigned long addr);
157 #endif
158
159 extern void apic_ap_setup(void);
160
161 /*
162 * On 32bit this is mach-xxx local
163 */
164 #ifdef CONFIG_X86_64
165 extern int apic_is_clustered_box(void);
166 #else
apic_is_clustered_box(void)167 static inline int apic_is_clustered_box(void)
168 {
169 return 0;
170 }
171 #endif
172
173 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
174 extern void lapic_assign_system_vectors(void);
175 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
176 extern void lapic_online(void);
177 extern void lapic_offline(void);
178 extern bool apic_needs_pit(void);
179
180 extern void apic_send_IPI_allbutself(unsigned int vector);
181
182 #else /* !CONFIG_X86_LOCAL_APIC */
lapic_shutdown(void)183 static inline void lapic_shutdown(void) { }
184 #define local_apic_timer_c2_ok 1
init_apic_mappings(void)185 static inline void init_apic_mappings(void) { }
disable_local_APIC(void)186 static inline void disable_local_APIC(void) { }
187 # define setup_boot_APIC_clock x86_init_noop
188 # define setup_secondary_APIC_clock x86_init_noop
lapic_update_tsc_freq(void)189 static inline void lapic_update_tsc_freq(void) { }
init_bsp_APIC(void)190 static inline void init_bsp_APIC(void) { }
apic_intr_mode_init(void)191 static inline void apic_intr_mode_init(void) { }
lapic_assign_system_vectors(void)192 static inline void lapic_assign_system_vectors(void) { }
lapic_assign_legacy_vector(unsigned int i,bool r)193 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
apic_needs_pit(void)194 static inline bool apic_needs_pit(void) { return true; }
195 #endif /* !CONFIG_X86_LOCAL_APIC */
196
197 #ifdef CONFIG_X86_X2APIC
198 /*
199 * Make previous memory operations globally visible before
200 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
201 * mfence for this.
202 */
x2apic_wrmsr_fence(void)203 static inline void x2apic_wrmsr_fence(void)
204 {
205 asm volatile("mfence" : : : "memory");
206 }
207
native_apic_msr_write(u32 reg,u32 v)208 static inline void native_apic_msr_write(u32 reg, u32 v)
209 {
210 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
211 reg == APIC_LVR)
212 return;
213
214 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
215 }
216
native_apic_msr_eoi_write(u32 reg,u32 v)217 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
218 {
219 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
220 }
221
native_apic_msr_read(u32 reg)222 static inline u32 native_apic_msr_read(u32 reg)
223 {
224 u64 msr;
225
226 if (reg == APIC_DFR)
227 return -1;
228
229 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
230 return (u32)msr;
231 }
232
native_x2apic_wait_icr_idle(void)233 static inline void native_x2apic_wait_icr_idle(void)
234 {
235 /* no need to wait for icr idle in x2apic */
236 return;
237 }
238
native_safe_x2apic_wait_icr_idle(void)239 static inline u32 native_safe_x2apic_wait_icr_idle(void)
240 {
241 /* no need to wait for icr idle in x2apic */
242 return 0;
243 }
244
native_x2apic_icr_write(u32 low,u32 id)245 static inline void native_x2apic_icr_write(u32 low, u32 id)
246 {
247 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
248 }
249
native_x2apic_icr_read(void)250 static inline u64 native_x2apic_icr_read(void)
251 {
252 unsigned long val;
253
254 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
255 return val;
256 }
257
258 extern int x2apic_mode;
259 extern int x2apic_phys;
260 extern void __init check_x2apic(void);
261 extern void x2apic_setup(void);
x2apic_enabled(void)262 static inline int x2apic_enabled(void)
263 {
264 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
265 }
266
267 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
268 #else /* !CONFIG_X86_X2APIC */
check_x2apic(void)269 static inline void check_x2apic(void) { }
x2apic_setup(void)270 static inline void x2apic_setup(void) { }
x2apic_enabled(void)271 static inline int x2apic_enabled(void) { return 0; }
272
273 #define x2apic_mode (0)
274 #define x2apic_supported() (0)
275 #endif /* !CONFIG_X86_X2APIC */
276
277 struct irq_data;
278
279 /*
280 * Copyright 2004 James Cleverdon, IBM.
281 *
282 * Generic APIC sub-arch data struct.
283 *
284 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
285 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
286 * James Cleverdon.
287 */
288 struct apic {
289 /* Hotpath functions first */
290 void (*eoi_write)(u32 reg, u32 v);
291 void (*native_eoi_write)(u32 reg, u32 v);
292 void (*write)(u32 reg, u32 v);
293 u32 (*read)(u32 reg);
294
295 /* IPI related functions */
296 void (*wait_icr_idle)(void);
297 u32 (*safe_wait_icr_idle)(void);
298
299 void (*send_IPI)(int cpu, int vector);
300 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
301 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
302 void (*send_IPI_allbutself)(int vector);
303 void (*send_IPI_all)(int vector);
304 void (*send_IPI_self)(int vector);
305
306 /* dest_logical is used by the IPI functions */
307 u32 dest_logical;
308 u32 disable_esr;
309 u32 irq_delivery_mode;
310 u32 irq_dest_mode;
311
312 u32 (*calc_dest_apicid)(unsigned int cpu);
313
314 /* ICR related functions */
315 u64 (*icr_read)(void);
316 void (*icr_write)(u32 low, u32 high);
317
318 /* Probe, setup and smpboot functions */
319 int (*probe)(void);
320 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
321 int (*apic_id_valid)(u32 apicid);
322 int (*apic_id_registered)(void);
323
324 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
325 void (*init_apic_ldr)(void);
326 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
327 void (*setup_apic_routing)(void);
328 int (*cpu_present_to_apicid)(int mps_cpu);
329 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
330 int (*check_phys_apicid_present)(int phys_apicid);
331 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
332
333 u32 (*get_apic_id)(unsigned long x);
334 u32 (*set_apic_id)(unsigned int id);
335
336 /* wakeup_secondary_cpu */
337 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
338
339 void (*inquire_remote_apic)(int apicid);
340
341 #ifdef CONFIG_X86_32
342 /*
343 * Called very early during boot from get_smp_config(). It should
344 * return the logical apicid. x86_[bios]_cpu_to_apicid is
345 * initialized before this function is called.
346 *
347 * If logical apicid can't be determined that early, the function
348 * may return BAD_APICID. Logical apicid will be configured after
349 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
350 * won't be applied properly during early boot in this case.
351 */
352 int (*x86_32_early_logical_apicid)(int cpu);
353 #endif
354 char *name;
355 };
356
357 /*
358 * Pointer to the local APIC driver in use on this system (there's
359 * always just one such driver in use - the kernel decides via an
360 * early probing process which one it picks - and then sticks to it):
361 */
362 extern struct apic *apic;
363
364 /*
365 * APIC drivers are probed based on how they are listed in the .apicdrivers
366 * section. So the order is important and enforced by the ordering
367 * of different apic driver files in the Makefile.
368 *
369 * For the files having two apic drivers, we use apic_drivers()
370 * to enforce the order with in them.
371 */
372 #define apic_driver(sym) \
373 static const struct apic *__apicdrivers_##sym __used \
374 __aligned(sizeof(struct apic *)) \
375 __section(.apicdrivers) = { &sym }
376
377 #define apic_drivers(sym1, sym2) \
378 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
379 __aligned(sizeof(struct apic *)) \
380 __section(.apicdrivers) = { &sym1, &sym2 }
381
382 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
383
384 /*
385 * APIC functionality to boot other CPUs - only used on SMP:
386 */
387 #ifdef CONFIG_SMP
388 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
389 extern int lapic_can_unplug_cpu(void);
390 #endif
391
392 #ifdef CONFIG_X86_LOCAL_APIC
393
apic_read(u32 reg)394 static inline u32 apic_read(u32 reg)
395 {
396 return apic->read(reg);
397 }
398
apic_write(u32 reg,u32 val)399 static inline void apic_write(u32 reg, u32 val)
400 {
401 apic->write(reg, val);
402 }
403
apic_eoi(void)404 static inline void apic_eoi(void)
405 {
406 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
407 }
408
apic_icr_read(void)409 static inline u64 apic_icr_read(void)
410 {
411 return apic->icr_read();
412 }
413
apic_icr_write(u32 low,u32 high)414 static inline void apic_icr_write(u32 low, u32 high)
415 {
416 apic->icr_write(low, high);
417 }
418
apic_wait_icr_idle(void)419 static inline void apic_wait_icr_idle(void)
420 {
421 apic->wait_icr_idle();
422 }
423
safe_apic_wait_icr_idle(void)424 static inline u32 safe_apic_wait_icr_idle(void)
425 {
426 return apic->safe_wait_icr_idle();
427 }
428
429 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
430
431 #else /* CONFIG_X86_LOCAL_APIC */
432
apic_read(u32 reg)433 static inline u32 apic_read(u32 reg) { return 0; }
apic_write(u32 reg,u32 val)434 static inline void apic_write(u32 reg, u32 val) { }
apic_eoi(void)435 static inline void apic_eoi(void) { }
apic_icr_read(void)436 static inline u64 apic_icr_read(void) { return 0; }
apic_icr_write(u32 low,u32 high)437 static inline void apic_icr_write(u32 low, u32 high) { }
apic_wait_icr_idle(void)438 static inline void apic_wait_icr_idle(void) { }
safe_apic_wait_icr_idle(void)439 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
apic_set_eoi_write(void (* eoi_write)(u32 reg,u32 v))440 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
441
442 #endif /* CONFIG_X86_LOCAL_APIC */
443
444 extern void apic_ack_irq(struct irq_data *data);
445
ack_APIC_irq(void)446 static inline void ack_APIC_irq(void)
447 {
448 /*
449 * ack_APIC_irq() actually gets compiled as a single instruction
450 * ... yummie.
451 */
452 apic_eoi();
453 }
454
default_get_apic_id(unsigned long x)455 static inline unsigned default_get_apic_id(unsigned long x)
456 {
457 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
458
459 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
460 return (x >> 24) & 0xFF;
461 else
462 return (x >> 24) & 0x0F;
463 }
464
465 /*
466 * Warm reset vector position:
467 */
468 #define TRAMPOLINE_PHYS_LOW 0x467
469 #define TRAMPOLINE_PHYS_HIGH 0x469
470
471 extern void generic_bigsmp_probe(void);
472
473 #ifdef CONFIG_X86_LOCAL_APIC
474
475 #include <asm/smp.h>
476
477 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
478
479 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
480
481 extern struct apic apic_noop;
482
read_apic_id(void)483 static inline unsigned int read_apic_id(void)
484 {
485 unsigned int reg = apic_read(APIC_ID);
486
487 return apic->get_apic_id(reg);
488 }
489
490 extern int default_apic_id_valid(u32 apicid);
491 extern int default_acpi_madt_oem_check(char *, char *);
492 extern void default_setup_apic_routing(void);
493
494 extern u32 apic_default_calc_apicid(unsigned int cpu);
495 extern u32 apic_flat_calc_apicid(unsigned int cpu);
496
497 extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
498 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
499 extern int default_cpu_present_to_apicid(int mps_cpu);
500 extern int default_check_phys_apicid_present(int phys_apicid);
501
502 #endif /* CONFIG_X86_LOCAL_APIC */
503
504 #ifdef CONFIG_SMP
505 bool apic_id_is_primary_thread(unsigned int id);
506 void apic_smt_update(void);
507 #else
apic_id_is_primary_thread(unsigned int id)508 static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
apic_smt_update(void)509 static inline void apic_smt_update(void) { }
510 #endif
511
512 extern void irq_enter(void);
513 extern void irq_exit(void);
514
entering_irq(void)515 static inline void entering_irq(void)
516 {
517 irq_enter();
518 kvm_set_cpu_l1tf_flush_l1d();
519 }
520
entering_ack_irq(void)521 static inline void entering_ack_irq(void)
522 {
523 entering_irq();
524 ack_APIC_irq();
525 }
526
ipi_entering_ack_irq(void)527 static inline void ipi_entering_ack_irq(void)
528 {
529 irq_enter();
530 ack_APIC_irq();
531 kvm_set_cpu_l1tf_flush_l1d();
532 }
533
exiting_irq(void)534 static inline void exiting_irq(void)
535 {
536 irq_exit();
537 }
538
exiting_ack_irq(void)539 static inline void exiting_ack_irq(void)
540 {
541 ack_APIC_irq();
542 irq_exit();
543 }
544
545 extern void ioapic_zap_locks(void);
546
547 #endif /* _ASM_X86_APIC_H */
548
