1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
4 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
5 *
6 * Credits:
7 * David Woodhouse for adding multichip support
8 *
9 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
10 * rework for 2K page size chips
11 *
12 * This file contains all legacy helpers/code that should be removed
13 * at some point.
14 */
15
16 #include <linux/delay.h>
17 #include <linux/io.h>
18 #include <linux/nmi.h>
19
20 #include "internals.h"
21
22 /**
23 * nand_read_byte - [DEFAULT] read one byte from the chip
24 * @chip: NAND chip object
25 *
26 * Default read function for 8bit buswidth
27 */
nand_read_byte(struct nand_chip * chip)28 static uint8_t nand_read_byte(struct nand_chip *chip)
29 {
30 return readb(chip->legacy.IO_ADDR_R);
31 }
32
33 /**
34 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
35 * @chip: NAND chip object
36 *
37 * Default read function for 16bit buswidth with endianness conversion.
38 *
39 */
nand_read_byte16(struct nand_chip * chip)40 static uint8_t nand_read_byte16(struct nand_chip *chip)
41 {
42 return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R));
43 }
44
45 /**
46 * nand_select_chip - [DEFAULT] control CE line
47 * @chip: NAND chip object
48 * @chipnr: chipnumber to select, -1 for deselect
49 *
50 * Default select function for 1 chip devices.
51 */
nand_select_chip(struct nand_chip * chip,int chipnr)52 static void nand_select_chip(struct nand_chip *chip, int chipnr)
53 {
54 switch (chipnr) {
55 case -1:
56 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
57 0 | NAND_CTRL_CHANGE);
58 break;
59 case 0:
60 break;
61
62 default:
63 BUG();
64 }
65 }
66
67 /**
68 * nand_write_byte - [DEFAULT] write single byte to chip
69 * @chip: NAND chip object
70 * @byte: value to write
71 *
72 * Default function to write a byte to I/O[7:0]
73 */
nand_write_byte(struct nand_chip * chip,uint8_t byte)74 static void nand_write_byte(struct nand_chip *chip, uint8_t byte)
75 {
76 chip->legacy.write_buf(chip, &byte, 1);
77 }
78
79 /**
80 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
81 * @chip: NAND chip object
82 * @byte: value to write
83 *
84 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
85 */
nand_write_byte16(struct nand_chip * chip,uint8_t byte)86 static void nand_write_byte16(struct nand_chip *chip, uint8_t byte)
87 {
88 uint16_t word = byte;
89
90 /*
91 * It's not entirely clear what should happen to I/O[15:8] when writing
92 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
93 *
94 * When the host supports a 16-bit bus width, only data is
95 * transferred at the 16-bit width. All address and command line
96 * transfers shall use only the lower 8-bits of the data bus. During
97 * command transfers, the host may place any value on the upper
98 * 8-bits of the data bus. During address transfers, the host shall
99 * set the upper 8-bits of the data bus to 00h.
100 *
101 * One user of the write_byte callback is nand_set_features. The
102 * four parameters are specified to be written to I/O[7:0], but this is
103 * neither an address nor a command transfer. Let's assume a 0 on the
104 * upper I/O lines is OK.
105 */
106 chip->legacy.write_buf(chip, (uint8_t *)&word, 2);
107 }
108
109 /**
110 * nand_write_buf - [DEFAULT] write buffer to chip
111 * @chip: NAND chip object
112 * @buf: data buffer
113 * @len: number of bytes to write
114 *
115 * Default write function for 8bit buswidth.
116 */
nand_write_buf(struct nand_chip * chip,const uint8_t * buf,int len)117 static void nand_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
118 {
119 iowrite8_rep(chip->legacy.IO_ADDR_W, buf, len);
120 }
121
122 /**
123 * nand_read_buf - [DEFAULT] read chip data into buffer
124 * @chip: NAND chip object
125 * @buf: buffer to store date
126 * @len: number of bytes to read
127 *
128 * Default read function for 8bit buswidth.
129 */
nand_read_buf(struct nand_chip * chip,uint8_t * buf,int len)130 static void nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
131 {
132 ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
133 }
134
135 /**
136 * nand_write_buf16 - [DEFAULT] write buffer to chip
137 * @chip: NAND chip object
138 * @buf: data buffer
139 * @len: number of bytes to write
140 *
141 * Default write function for 16bit buswidth.
142 */
nand_write_buf16(struct nand_chip * chip,const uint8_t * buf,int len)143 static void nand_write_buf16(struct nand_chip *chip, const uint8_t *buf,
144 int len)
145 {
146 u16 *p = (u16 *) buf;
147
148 iowrite16_rep(chip->legacy.IO_ADDR_W, p, len >> 1);
149 }
150
151 /**
152 * nand_read_buf16 - [DEFAULT] read chip data into buffer
153 * @chip: NAND chip object
154 * @buf: buffer to store date
155 * @len: number of bytes to read
156 *
157 * Default read function for 16bit buswidth.
158 */
nand_read_buf16(struct nand_chip * chip,uint8_t * buf,int len)159 static void nand_read_buf16(struct nand_chip *chip, uint8_t *buf, int len)
160 {
161 u16 *p = (u16 *) buf;
162
163 ioread16_rep(chip->legacy.IO_ADDR_R, p, len >> 1);
164 }
165
166 /**
167 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
168 * @chip: NAND chip object
169 * @timeo: Timeout
170 *
171 * Helper function for nand_wait_ready used when needing to wait in interrupt
172 * context.
173 */
panic_nand_wait_ready(struct nand_chip * chip,unsigned long timeo)174 static void panic_nand_wait_ready(struct nand_chip *chip, unsigned long timeo)
175 {
176 int i;
177
178 /* Wait for the device to get ready */
179 for (i = 0; i < timeo; i++) {
180 if (chip->legacy.dev_ready(chip))
181 break;
182 touch_softlockup_watchdog();
183 mdelay(1);
184 }
185 }
186
187 /**
188 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
189 * @chip: NAND chip object
190 *
191 * Wait for the ready pin after a command, and warn if a timeout occurs.
192 */
nand_wait_ready(struct nand_chip * chip)193 void nand_wait_ready(struct nand_chip *chip)
194 {
195 unsigned long timeo = 400;
196
197 if (in_interrupt() || oops_in_progress)
198 return panic_nand_wait_ready(chip, timeo);
199
200 /* Wait until command is processed or timeout occurs */
201 timeo = jiffies + msecs_to_jiffies(timeo);
202 do {
203 if (chip->legacy.dev_ready(chip))
204 return;
205 cond_resched();
206 } while (time_before(jiffies, timeo));
207
208 if (!chip->legacy.dev_ready(chip))
209 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
210 }
211 EXPORT_SYMBOL_GPL(nand_wait_ready);
212
213 /**
214 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
215 * @chip: NAND chip object
216 * @timeo: Timeout in ms
217 *
218 * Wait for status ready (i.e. command done) or timeout.
219 */
nand_wait_status_ready(struct nand_chip * chip,unsigned long timeo)220 static void nand_wait_status_ready(struct nand_chip *chip, unsigned long timeo)
221 {
222 int ret;
223
224 timeo = jiffies + msecs_to_jiffies(timeo);
225 do {
226 u8 status;
227
228 ret = nand_read_data_op(chip, &status, sizeof(status), true,
229 false);
230 if (ret)
231 return;
232
233 if (status & NAND_STATUS_READY)
234 break;
235 touch_softlockup_watchdog();
236 } while (time_before(jiffies, timeo));
237 };
238
239 /**
240 * nand_command - [DEFAULT] Send command to NAND device
241 * @chip: NAND chip object
242 * @command: the command to be sent
243 * @column: the column address for this command, -1 if none
244 * @page_addr: the page address for this command, -1 if none
245 *
246 * Send command to NAND device. This function is used for small page devices
247 * (512 Bytes per page).
248 */
nand_command(struct nand_chip * chip,unsigned int command,int column,int page_addr)249 static void nand_command(struct nand_chip *chip, unsigned int command,
250 int column, int page_addr)
251 {
252 struct mtd_info *mtd = nand_to_mtd(chip);
253 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
254
255 /* Write out the command to the device */
256 if (command == NAND_CMD_SEQIN) {
257 int readcmd;
258
259 if (column >= mtd->writesize) {
260 /* OOB area */
261 column -= mtd->writesize;
262 readcmd = NAND_CMD_READOOB;
263 } else if (column < 256) {
264 /* First 256 bytes --> READ0 */
265 readcmd = NAND_CMD_READ0;
266 } else {
267 column -= 256;
268 readcmd = NAND_CMD_READ1;
269 }
270 chip->legacy.cmd_ctrl(chip, readcmd, ctrl);
271 ctrl &= ~NAND_CTRL_CHANGE;
272 }
273 if (command != NAND_CMD_NONE)
274 chip->legacy.cmd_ctrl(chip, command, ctrl);
275
276 /* Address cycle, when necessary */
277 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
278 /* Serially input address */
279 if (column != -1) {
280 /* Adjust columns for 16 bit buswidth */
281 if (chip->options & NAND_BUSWIDTH_16 &&
282 !nand_opcode_8bits(command))
283 column >>= 1;
284 chip->legacy.cmd_ctrl(chip, column, ctrl);
285 ctrl &= ~NAND_CTRL_CHANGE;
286 }
287 if (page_addr != -1) {
288 chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
289 ctrl &= ~NAND_CTRL_CHANGE;
290 chip->legacy.cmd_ctrl(chip, page_addr >> 8, ctrl);
291 if (chip->options & NAND_ROW_ADDR_3)
292 chip->legacy.cmd_ctrl(chip, page_addr >> 16, ctrl);
293 }
294 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
295 NAND_NCE | NAND_CTRL_CHANGE);
296
297 /*
298 * Program and erase have their own busy handlers status and sequential
299 * in needs no delay
300 */
301 switch (command) {
302
303 case NAND_CMD_NONE:
304 case NAND_CMD_PAGEPROG:
305 case NAND_CMD_ERASE1:
306 case NAND_CMD_ERASE2:
307 case NAND_CMD_SEQIN:
308 case NAND_CMD_STATUS:
309 case NAND_CMD_READID:
310 case NAND_CMD_SET_FEATURES:
311 return;
312
313 case NAND_CMD_RESET:
314 if (chip->legacy.dev_ready)
315 break;
316 udelay(chip->legacy.chip_delay);
317 chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
318 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
319 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
320 NAND_NCE | NAND_CTRL_CHANGE);
321 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
322 nand_wait_status_ready(chip, 250);
323 return;
324
325 /* This applies to read commands */
326 case NAND_CMD_READ0:
327 /*
328 * READ0 is sometimes used to exit GET STATUS mode. When this
329 * is the case no address cycles are requested, and we can use
330 * this information to detect that we should not wait for the
331 * device to be ready.
332 */
333 if (column == -1 && page_addr == -1)
334 return;
335 fallthrough;
336 default:
337 /*
338 * If we don't have access to the busy pin, we apply the given
339 * command delay
340 */
341 if (!chip->legacy.dev_ready) {
342 udelay(chip->legacy.chip_delay);
343 return;
344 }
345 }
346 /*
347 * Apply this short delay always to ensure that we do wait tWB in
348 * any case on any machine.
349 */
350 ndelay(100);
351
352 nand_wait_ready(chip);
353 }
354
nand_ccs_delay(struct nand_chip * chip)355 static void nand_ccs_delay(struct nand_chip *chip)
356 {
357 const struct nand_sdr_timings *sdr =
358 nand_get_sdr_timings(nand_get_interface_config(chip));
359
360 /*
361 * The controller already takes care of waiting for tCCS when the RNDIN
362 * or RNDOUT command is sent, return directly.
363 */
364 if (!(chip->options & NAND_WAIT_TCCS))
365 return;
366
367 /*
368 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
369 * (which should be safe for all NANDs).
370 */
371 if (nand_controller_can_setup_interface(chip))
372 ndelay(sdr->tCCS_min / 1000);
373 else
374 ndelay(500);
375 }
376
377 /**
378 * nand_command_lp - [DEFAULT] Send command to NAND large page device
379 * @chip: NAND chip object
380 * @command: the command to be sent
381 * @column: the column address for this command, -1 if none
382 * @page_addr: the page address for this command, -1 if none
383 *
384 * Send command to NAND device. This is the version for the new large page
385 * devices. We don't have the separate regions as we have in the small page
386 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
387 */
nand_command_lp(struct nand_chip * chip,unsigned int command,int column,int page_addr)388 static void nand_command_lp(struct nand_chip *chip, unsigned int command,
389 int column, int page_addr)
390 {
391 struct mtd_info *mtd = nand_to_mtd(chip);
392
393 /* Emulate NAND_CMD_READOOB */
394 if (command == NAND_CMD_READOOB) {
395 column += mtd->writesize;
396 command = NAND_CMD_READ0;
397 }
398
399 /* Command latch cycle */
400 if (command != NAND_CMD_NONE)
401 chip->legacy.cmd_ctrl(chip, command,
402 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
403
404 if (column != -1 || page_addr != -1) {
405 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
406
407 /* Serially input address */
408 if (column != -1) {
409 /* Adjust columns for 16 bit buswidth */
410 if (chip->options & NAND_BUSWIDTH_16 &&
411 !nand_opcode_8bits(command))
412 column >>= 1;
413 chip->legacy.cmd_ctrl(chip, column, ctrl);
414 ctrl &= ~NAND_CTRL_CHANGE;
415
416 /* Only output a single addr cycle for 8bits opcodes. */
417 if (!nand_opcode_8bits(command))
418 chip->legacy.cmd_ctrl(chip, column >> 8, ctrl);
419 }
420 if (page_addr != -1) {
421 chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
422 chip->legacy.cmd_ctrl(chip, page_addr >> 8,
423 NAND_NCE | NAND_ALE);
424 if (chip->options & NAND_ROW_ADDR_3)
425 chip->legacy.cmd_ctrl(chip, page_addr >> 16,
426 NAND_NCE | NAND_ALE);
427 }
428 }
429 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
430 NAND_NCE | NAND_CTRL_CHANGE);
431
432 /*
433 * Program and erase have their own busy handlers status, sequential
434 * in and status need no delay.
435 */
436 switch (command) {
437
438 case NAND_CMD_NONE:
439 case NAND_CMD_CACHEDPROG:
440 case NAND_CMD_PAGEPROG:
441 case NAND_CMD_ERASE1:
442 case NAND_CMD_ERASE2:
443 case NAND_CMD_SEQIN:
444 case NAND_CMD_STATUS:
445 case NAND_CMD_READID:
446 case NAND_CMD_SET_FEATURES:
447 return;
448
449 case NAND_CMD_RNDIN:
450 nand_ccs_delay(chip);
451 return;
452
453 case NAND_CMD_RESET:
454 if (chip->legacy.dev_ready)
455 break;
456 udelay(chip->legacy.chip_delay);
457 chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
458 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
459 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
460 NAND_NCE | NAND_CTRL_CHANGE);
461 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
462 nand_wait_status_ready(chip, 250);
463 return;
464
465 case NAND_CMD_RNDOUT:
466 /* No ready / busy check necessary */
467 chip->legacy.cmd_ctrl(chip, NAND_CMD_RNDOUTSTART,
468 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
469 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
470 NAND_NCE | NAND_CTRL_CHANGE);
471
472 nand_ccs_delay(chip);
473 return;
474
475 case NAND_CMD_READ0:
476 /*
477 * READ0 is sometimes used to exit GET STATUS mode. When this
478 * is the case no address cycles are requested, and we can use
479 * this information to detect that READSTART should not be
480 * issued.
481 */
482 if (column == -1 && page_addr == -1)
483 return;
484
485 chip->legacy.cmd_ctrl(chip, NAND_CMD_READSTART,
486 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
487 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
488 NAND_NCE | NAND_CTRL_CHANGE);
489 fallthrough; /* This applies to read commands */
490 default:
491 /*
492 * If we don't have access to the busy pin, we apply the given
493 * command delay.
494 */
495 if (!chip->legacy.dev_ready) {
496 udelay(chip->legacy.chip_delay);
497 return;
498 }
499 }
500
501 /*
502 * Apply this short delay always to ensure that we do wait tWB in
503 * any case on any machine.
504 */
505 ndelay(100);
506
507 nand_wait_ready(chip);
508 }
509
510 /**
511 * nand_get_set_features_notsupp - set/get features stub returning -ENOTSUPP
512 * @chip: nand chip info structure
513 * @addr: feature address.
514 * @subfeature_param: the subfeature parameters, a four bytes array.
515 *
516 * Should be used by NAND controller drivers that do not support the SET/GET
517 * FEATURES operations.
518 */
nand_get_set_features_notsupp(struct nand_chip * chip,int addr,u8 * subfeature_param)519 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
520 u8 *subfeature_param)
521 {
522 return -ENOTSUPP;
523 }
524 EXPORT_SYMBOL(nand_get_set_features_notsupp);
525
526 /**
527 * nand_wait - [DEFAULT] wait until the command is done
528 * @chip: NAND chip structure
529 *
530 * Wait for command done. This applies to erase and program only.
531 */
nand_wait(struct nand_chip * chip)532 static int nand_wait(struct nand_chip *chip)
533 {
534
535 unsigned long timeo = 400;
536 u8 status;
537 int ret;
538
539 /*
540 * Apply this short delay always to ensure that we do wait tWB in any
541 * case on any machine.
542 */
543 ndelay(100);
544
545 ret = nand_status_op(chip, NULL);
546 if (ret)
547 return ret;
548
549 if (in_interrupt() || oops_in_progress)
550 panic_nand_wait(chip, timeo);
551 else {
552 timeo = jiffies + msecs_to_jiffies(timeo);
553 do {
554 if (chip->legacy.dev_ready) {
555 if (chip->legacy.dev_ready(chip))
556 break;
557 } else {
558 ret = nand_read_data_op(chip, &status,
559 sizeof(status), true,
560 false);
561 if (ret)
562 return ret;
563
564 if (status & NAND_STATUS_READY)
565 break;
566 }
567 cond_resched();
568 } while (time_before(jiffies, timeo));
569 }
570
571 ret = nand_read_data_op(chip, &status, sizeof(status), true, false);
572 if (ret)
573 return ret;
574
575 /* This can happen if in case of timeout or buggy dev_ready */
576 WARN_ON(!(status & NAND_STATUS_READY));
577 return status;
578 }
579
nand_legacy_set_defaults(struct nand_chip * chip)580 void nand_legacy_set_defaults(struct nand_chip *chip)
581 {
582 unsigned int busw = chip->options & NAND_BUSWIDTH_16;
583
584 if (nand_has_exec_op(chip))
585 return;
586
587 /* check for proper chip_delay setup, set 20us if not */
588 if (!chip->legacy.chip_delay)
589 chip->legacy.chip_delay = 20;
590
591 /* check, if a user supplied command function given */
592 if (!chip->legacy.cmdfunc)
593 chip->legacy.cmdfunc = nand_command;
594
595 /* check, if a user supplied wait function given */
596 if (chip->legacy.waitfunc == NULL)
597 chip->legacy.waitfunc = nand_wait;
598
599 if (!chip->legacy.select_chip)
600 chip->legacy.select_chip = nand_select_chip;
601
602 /* If called twice, pointers that depend on busw may need to be reset */
603 if (!chip->legacy.read_byte || chip->legacy.read_byte == nand_read_byte)
604 chip->legacy.read_byte = busw ? nand_read_byte16 : nand_read_byte;
605 if (!chip->legacy.write_buf || chip->legacy.write_buf == nand_write_buf)
606 chip->legacy.write_buf = busw ? nand_write_buf16 : nand_write_buf;
607 if (!chip->legacy.write_byte || chip->legacy.write_byte == nand_write_byte)
608 chip->legacy.write_byte = busw ? nand_write_byte16 : nand_write_byte;
609 if (!chip->legacy.read_buf || chip->legacy.read_buf == nand_read_buf)
610 chip->legacy.read_buf = busw ? nand_read_buf16 : nand_read_buf;
611 }
612
nand_legacy_adjust_cmdfunc(struct nand_chip * chip)613 void nand_legacy_adjust_cmdfunc(struct nand_chip *chip)
614 {
615 struct mtd_info *mtd = nand_to_mtd(chip);
616
617 /* Do not replace user supplied command function! */
618 if (mtd->writesize > 512 && chip->legacy.cmdfunc == nand_command)
619 chip->legacy.cmdfunc = nand_command_lp;
620 }
621
nand_legacy_check_hooks(struct nand_chip * chip)622 int nand_legacy_check_hooks(struct nand_chip *chip)
623 {
624 /*
625 * ->legacy.cmdfunc() is legacy and will only be used if ->exec_op() is
626 * not populated.
627 */
628 if (nand_has_exec_op(chip))
629 return 0;
630
631 /*
632 * Default functions assigned for ->legacy.cmdfunc() and
633 * ->legacy.select_chip() both expect ->legacy.cmd_ctrl() to be
634 * populated.
635 */
636 if ((!chip->legacy.cmdfunc || !chip->legacy.select_chip) &&
637 !chip->legacy.cmd_ctrl) {
638 pr_err("->legacy.cmd_ctrl() should be provided\n");
639 return -EINVAL;
640 }
641
642 return 0;
643 }
644
