1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
4 */
5
6 #include <linux/module.h>
7 #include <linux/clk.h>
8 #include <linux/clkdev.h>
9 #include <linux/io.h>
10 #include <linux/err.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <soc/imx/revision.h>
14 #include <soc/imx/timer.h>
15 #include <asm/irq.h>
16
17 #include "clk.h"
18
19 #define MX31_CCM_BASE_ADDR 0x53f80000
20 #define MX31_GPT1_BASE_ADDR 0x53f90000
21 #define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
22
23 #define MXC_CCM_CCMR 0x00
24 #define MXC_CCM_PDR0 0x04
25 #define MXC_CCM_PDR1 0x08
26 #define MXC_CCM_MPCTL 0x10
27 #define MXC_CCM_UPCTL 0x14
28 #define MXC_CCM_SRPCTL 0x18
29 #define MXC_CCM_CGR0 0x20
30 #define MXC_CCM_CGR1 0x24
31 #define MXC_CCM_CGR2 0x28
32 #define MXC_CCM_PMCR0 0x5c
33
34 static const char *mcu_main_sel[] = { "spll", "mpll", };
35 static const char *per_sel[] = { "per_div", "ipg", };
36 static const char *csi_sel[] = { "upll", "spll", };
37 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
38
39 enum mx31_clks {
40 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
41 per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
42 fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
43 iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
44 uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
45 mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
46 sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
47 uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
48 gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
49 };
50
51 static struct clk *clk[clk_max];
52 static struct clk_onecell_data clk_data;
53
54 static struct clk ** const uart_clks[] __initconst = {
55 &clk[ipg],
56 &clk[uart1_gate],
57 &clk[uart2_gate],
58 &clk[uart3_gate],
59 &clk[uart4_gate],
60 &clk[uart5_gate],
61 NULL
62 };
63
_mx31_clocks_init(void __iomem * base,unsigned long fref)64 static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref)
65 {
66 clk[dummy] = imx_clk_fixed("dummy", 0);
67 clk[ckih] = imx_clk_fixed("ckih", fref);
68 clk[ckil] = imx_clk_fixed("ckil", 32768);
69 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL);
70 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL);
71 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL);
72 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
73 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
74 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
75 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
76 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
77 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
78 clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
79 clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
80 clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
81 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
82 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
83 clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
84 clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
85 clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
86 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
87 clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
88 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
89 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
90 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
91 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
92 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
93 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
94 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
95 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
96 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
97 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
98 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
99 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
100 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
101 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
102 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
103 clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
104 clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
105 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
106 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
107 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
108 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
109 clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
110 clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
111 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
112 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
113 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
114 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
115 clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
116 clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
117 clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
118 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
119 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
120 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
121 clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
122 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
123 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
124 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
125
126 imx_check_clocks(clk, ARRAY_SIZE(clk));
127
128 clk_set_parent(clk[csi], clk[upll]);
129 clk_prepare_enable(clk[emi_gate]);
130 clk_prepare_enable(clk[iim_gate]);
131 mx31_revision();
132 clk_disable_unprepare(clk[iim_gate]);
133 }
134
mx31_clocks_init(unsigned long fref)135 int __init mx31_clocks_init(unsigned long fref)
136 {
137 void __iomem *base;
138
139 base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K);
140 if (!base)
141 panic("%s: failed to map registers\n", __func__);
142
143 _mx31_clocks_init(base, fref);
144
145 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
146 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
147 clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
148 clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
149 clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
150 clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
151 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
152 clk_register_clkdev(clk[ckil], "ref", "imx21-rtc");
153 clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");
154 clk_register_clkdev(clk[epit1_gate], "epit", NULL);
155 clk_register_clkdev(clk[epit2_gate], "epit", NULL);
156 clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");
157 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
158 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
159 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
160 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
161 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
162 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
163 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
164 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
165 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
166 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
167 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
168 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
169 clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27");
170 clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27");
171 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
172 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
173 /* i.mx31 has the i.mx21 type uart */
174 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
175 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
176 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
177 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
178 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
179 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
180 clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
181 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
182 clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
183 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
184 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
185 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
186 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
187 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
188 clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0");
189 clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1");
190 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
191 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
192 clk_register_clkdev(clk[firi_gate], "firi", NULL);
193 clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
194 clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
195 clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
196 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
197 clk_register_clkdev(clk[iim_gate], "iim", NULL);
198
199
200 imx_register_uart_clocks(uart_clks);
201 mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);
202
203 return 0;
204 }
205
mx31_clocks_init_dt(struct device_node * np)206 static void __init mx31_clocks_init_dt(struct device_node *np)
207 {
208 struct device_node *osc_np;
209 u32 fref = 26000000; /* default */
210 void __iomem *ccm;
211
212 for_each_compatible_node(osc_np, NULL, "fixed-clock") {
213 if (!of_device_is_compatible(osc_np, "fsl,imx-osc26m"))
214 continue;
215
216 if (!of_property_read_u32(osc_np, "clock-frequency", &fref)) {
217 of_node_put(osc_np);
218 break;
219 }
220 }
221
222 ccm = of_iomap(np, 0);
223 if (!ccm)
224 panic("%s: failed to map registers\n", __func__);
225
226 _mx31_clocks_init(ccm, fref);
227
228 clk_data.clks = clk;
229 clk_data.clk_num = ARRAY_SIZE(clk);
230 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
231 }
232
233 CLK_OF_DECLARE(imx31_ccm, "fsl,imx31-ccm", mx31_clocks_init_dt);
234
