1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88E6xxx Switch Global (1) Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11 #include <linux/bitfield.h>
12
13 #include "chip.h"
14 #include "global1.h"
15
mv88e6xxx_g1_read(struct mv88e6xxx_chip * chip,int reg,u16 * val)16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
17 {
18 int addr = chip->info->global1_addr;
19
20 return mv88e6xxx_read(chip, addr, reg, val);
21 }
22
mv88e6xxx_g1_write(struct mv88e6xxx_chip * chip,int reg,u16 val)23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
24 {
25 int addr = chip->info->global1_addr;
26
27 return mv88e6xxx_write(chip, addr, reg, val);
28 }
29
mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip * chip,int reg,int bit,int val)30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
31 bit, int val)
32 {
33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
34 bit, val);
35 }
36
mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip * chip,int reg,u16 mask,u16 val)37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
38 u16 mask, u16 val)
39 {
40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
41 mask, val);
42 }
43
44 /* Offset 0x00: Switch Global Status Register */
45
mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip * chip)46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
47 {
48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
49 MV88E6185_G1_STS_PPU_STATE_MASK,
50 MV88E6185_G1_STS_PPU_STATE_DISABLED);
51 }
52
mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip * chip)53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
54 {
55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
56 MV88E6185_G1_STS_PPU_STATE_MASK,
57 MV88E6185_G1_STS_PPU_STATE_POLLING);
58 }
59
mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip * chip)60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
61 {
62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
63
64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
65 }
66
mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip * chip)67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
68 {
69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
70
71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11
72 * is set to a one when all units inside the device (ATU, VTU, etc.)
73 * have finished their initialization and are ready to accept frames.
74 */
75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
76 }
77
mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip * chip)78 void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip)
79 {
80 const unsigned long timeout = jiffies + 1 * HZ;
81 u16 val;
82 int err;
83
84 /* Wait up to 1 second for the switch to finish reading the
85 * EEPROM.
86 */
87 while (time_before(jiffies, timeout)) {
88 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
89 if (err) {
90 dev_err(chip->dev, "Error reading status");
91 return;
92 }
93
94 /* If the switch is still resetting, it may not
95 * respond on the bus, and so MDIO read returns
96 * 0xffff. Differentiate between that, and waiting for
97 * the EEPROM to be done by bit 0 being set.
98 */
99 if (val != 0xffff &&
100 val & BIT(MV88E6XXX_G1_STS_IRQ_EEPROM_DONE))
101 return;
102
103 usleep_range(1000, 2000);
104 }
105
106 dev_err(chip->dev, "Timeout waiting for EEPROM done");
107 }
108
109 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
110 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
111 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
112 */
mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip * chip,u8 * addr)113 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
114 {
115 u16 reg;
116 int err;
117
118 reg = (addr[0] << 8) | addr[1];
119 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
120 if (err)
121 return err;
122
123 reg = (addr[2] << 8) | addr[3];
124 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
125 if (err)
126 return err;
127
128 reg = (addr[4] << 8) | addr[5];
129 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
130 if (err)
131 return err;
132
133 return 0;
134 }
135
136 /* Offset 0x04: Switch Global Control Register */
137
mv88e6185_g1_reset(struct mv88e6xxx_chip * chip)138 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
139 {
140 u16 val;
141 int err;
142
143 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
144 * the PPU, including re-doing PHY detection and initialization
145 */
146 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
147 if (err)
148 return err;
149
150 val |= MV88E6XXX_G1_CTL1_SW_RESET;
151 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
152
153 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
154 if (err)
155 return err;
156
157 err = mv88e6xxx_g1_wait_init_ready(chip);
158 if (err)
159 return err;
160
161 return mv88e6185_g1_wait_ppu_polling(chip);
162 }
163
mv88e6250_g1_reset(struct mv88e6xxx_chip * chip)164 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
165 {
166 u16 val;
167 int err;
168
169 /* Set the SWReset bit 15 */
170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
171 if (err)
172 return err;
173
174 val |= MV88E6XXX_G1_CTL1_SW_RESET;
175
176 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
177 if (err)
178 return err;
179
180 return mv88e6xxx_g1_wait_init_ready(chip);
181 }
182
mv88e6352_g1_reset(struct mv88e6xxx_chip * chip)183 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
184 {
185 int err;
186
187 err = mv88e6250_g1_reset(chip);
188 if (err)
189 return err;
190
191 return mv88e6352_g1_wait_ppu_polling(chip);
192 }
193
mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip * chip)194 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
195 {
196 u16 val;
197 int err;
198
199 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
200 if (err)
201 return err;
202
203 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
204
205 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
206 if (err)
207 return err;
208
209 return mv88e6185_g1_wait_ppu_polling(chip);
210 }
211
mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip * chip)212 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
213 {
214 u16 val;
215 int err;
216
217 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
218 if (err)
219 return err;
220
221 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
222
223 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
224 if (err)
225 return err;
226
227 return mv88e6185_g1_wait_ppu_disabled(chip);
228 }
229
mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip * chip,int mtu)230 int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
231 {
232 u16 val;
233 int err;
234
235 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
236 if (err)
237 return err;
238
239 val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632;
240
241 if (mtu > 1518)
242 val |= MV88E6185_G1_CTL1_MAX_FRAME_1632;
243
244 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
245 }
246
247 /* Offset 0x10: IP-PRI Mapping Register 0
248 * Offset 0x11: IP-PRI Mapping Register 1
249 * Offset 0x12: IP-PRI Mapping Register 2
250 * Offset 0x13: IP-PRI Mapping Register 3
251 * Offset 0x14: IP-PRI Mapping Register 4
252 * Offset 0x15: IP-PRI Mapping Register 5
253 * Offset 0x16: IP-PRI Mapping Register 6
254 * Offset 0x17: IP-PRI Mapping Register 7
255 */
256
mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip * chip)257 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
258 {
259 int err;
260
261 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
262 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
263 if (err)
264 return err;
265
266 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
267 if (err)
268 return err;
269
270 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
271 if (err)
272 return err;
273
274 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
275 if (err)
276 return err;
277
278 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
279 if (err)
280 return err;
281
282 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
283 if (err)
284 return err;
285
286 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
287 if (err)
288 return err;
289
290 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
291 if (err)
292 return err;
293
294 return 0;
295 }
296
297 /* Offset 0x18: IEEE-PRI Register */
298
mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip * chip)299 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
300 {
301 /* Reset the IEEE Tag priorities to defaults */
302 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
303 }
304
mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip * chip)305 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
306 {
307 /* Reset the IEEE Tag priorities to defaults */
308 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
309 }
310
311 /* Offset 0x1a: Monitor Control */
312 /* Offset 0x1a: Monitor & MGMT Control on some devices */
313
mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)314 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
315 enum mv88e6xxx_egress_direction direction,
316 int port)
317 {
318 int *dest_port_chip;
319 u16 reg;
320 int err;
321
322 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
323 if (err)
324 return err;
325
326 switch (direction) {
327 case MV88E6XXX_EGRESS_DIR_INGRESS:
328 dest_port_chip = &chip->ingress_dest_port;
329 reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
330 reg |= port <<
331 __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
332 break;
333 case MV88E6XXX_EGRESS_DIR_EGRESS:
334 dest_port_chip = &chip->egress_dest_port;
335 reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
336 reg |= port <<
337 __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
338 break;
339 default:
340 return -EINVAL;
341 }
342
343 err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
344 if (!err)
345 *dest_port_chip = port;
346
347 return err;
348 }
349
350 /* Older generations also call this the ARP destination. It has been
351 * generalized in more modern devices such that more than ARP can
352 * egress it
353 */
mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip * chip,int port)354 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
355 {
356 u16 reg;
357 int err;
358
359 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
360 if (err)
361 return err;
362
363 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
364 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
365
366 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
367 }
368
mv88e6390_g1_monitor_write(struct mv88e6xxx_chip * chip,u16 pointer,u8 data)369 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
370 u16 pointer, u8 data)
371 {
372 u16 reg;
373
374 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
375
376 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
377 }
378
mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)379 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
380 enum mv88e6xxx_egress_direction direction,
381 int port)
382 {
383 int *dest_port_chip;
384 u16 ptr;
385 int err;
386
387 switch (direction) {
388 case MV88E6XXX_EGRESS_DIR_INGRESS:
389 dest_port_chip = &chip->ingress_dest_port;
390 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
391 break;
392 case MV88E6XXX_EGRESS_DIR_EGRESS:
393 dest_port_chip = &chip->egress_dest_port;
394 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
395 break;
396 default:
397 return -EINVAL;
398 }
399
400 err = mv88e6390_g1_monitor_write(chip, ptr, port);
401 if (!err)
402 *dest_port_chip = port;
403
404 return err;
405 }
406
mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip * chip,int port)407 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
408 {
409 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
410
411 /* Use the default high priority for management frames sent to
412 * the CPU.
413 */
414 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
415
416 return mv88e6390_g1_monitor_write(chip, ptr, port);
417 }
418
mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip * chip)419 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
420 {
421 u16 ptr;
422 int err;
423
424 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
425 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
426 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
427 if (err)
428 return err;
429
430 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
431 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
432 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
433 if (err)
434 return err;
435
436 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
437 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
438 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
439 if (err)
440 return err;
441
442 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
443 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
444 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
445 if (err)
446 return err;
447
448 return 0;
449 }
450
451 /* Offset 0x1c: Global Control 2 */
452
mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip * chip,u16 mask,u16 val)453 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
454 u16 val)
455 {
456 u16 reg;
457 int err;
458
459 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®);
460 if (err)
461 return err;
462
463 reg &= ~mask;
464 reg |= val & mask;
465
466 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
467 }
468
mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip * chip,int port)469 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
470 {
471 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
472
473 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
474 }
475
mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip * chip)476 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
477 {
478 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
479 MV88E6085_G1_CTL2_RM_ENABLE, 0);
480 }
481
mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip * chip)482 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
483 {
484 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
485 MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
486 }
487
mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip * chip)488 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
489 {
490 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
491 MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
492 }
493
mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip * chip)494 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
495 {
496 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
497 MV88E6390_G1_CTL2_HIST_MODE_RX |
498 MV88E6390_G1_CTL2_HIST_MODE_TX);
499 }
500
mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip * chip,int index)501 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
502 {
503 return mv88e6xxx_g1_ctl2_mask(chip,
504 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
505 index);
506 }
507
508 /* Offset 0x1d: Statistics Operation 2 */
509
mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip * chip)510 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
511 {
512 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
513
514 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
515 }
516
mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip * chip)517 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
518 {
519 u16 val;
520 int err;
521
522 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
523 if (err)
524 return err;
525
526 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
527
528 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
529
530 return err;
531 }
532
mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)533 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
534 {
535 int err;
536
537 /* Snapshot the hardware statistics counters for this port. */
538 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
539 MV88E6XXX_G1_STATS_OP_BUSY |
540 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
541 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
542 if (err)
543 return err;
544
545 /* Wait for the snapshotting to complete. */
546 return mv88e6xxx_g1_stats_wait(chip);
547 }
548
mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)549 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
550 {
551 port = (port + 1) << 5;
552
553 return mv88e6xxx_g1_stats_snapshot(chip, port);
554 }
555
mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip * chip,int port)556 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
557 {
558 int err;
559
560 port = (port + 1) << 5;
561
562 /* Snapshot the hardware statistics counters for this port. */
563 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
564 MV88E6XXX_G1_STATS_OP_BUSY |
565 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
566 if (err)
567 return err;
568
569 /* Wait for the snapshotting to complete. */
570 return mv88e6xxx_g1_stats_wait(chip);
571 }
572
mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip * chip,int stat,u32 * val)573 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
574 {
575 u32 value;
576 u16 reg;
577 int err;
578
579 *val = 0;
580
581 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
582 MV88E6XXX_G1_STATS_OP_BUSY |
583 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
584 if (err)
585 return;
586
587 err = mv88e6xxx_g1_stats_wait(chip);
588 if (err)
589 return;
590
591 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
592 if (err)
593 return;
594
595 value = reg << 16;
596
597 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
598 if (err)
599 return;
600
601 *val = value | reg;
602 }
603
mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip * chip)604 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
605 {
606 int err;
607 u16 val;
608
609 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
610 if (err)
611 return err;
612
613 /* Keep the histogram mode bits */
614 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
615 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
616
617 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
618 if (err)
619 return err;
620
621 /* Wait for the flush to complete. */
622 return mv88e6xxx_g1_stats_wait(chip);
623 }
624
