1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mt8183-afe-clk.c -- Mediatek 8183 afe clock ctrl
4 //
5 // Copyright (c) 2018 MediaTek Inc.
6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8 #include <linux/clk.h>
9
10 #include "mt8183-afe-common.h"
11 #include "mt8183-afe-clk.h"
12 #include "mt8183-reg.h"
13
14 enum {
15 CLK_AFE = 0,
16 CLK_TML,
17 CLK_APLL22M,
18 CLK_APLL24M,
19 CLK_APLL1_TUNER,
20 CLK_APLL2_TUNER,
21 CLK_I2S1_BCLK_SW,
22 CLK_I2S2_BCLK_SW,
23 CLK_I2S3_BCLK_SW,
24 CLK_I2S4_BCLK_SW,
25 CLK_INFRA_SYS_AUDIO,
26 CLK_MUX_AUDIO,
27 CLK_MUX_AUDIOINTBUS,
28 CLK_TOP_SYSPLL_D2_D4,
29 /* apll related mux */
30 CLK_TOP_MUX_AUD_1,
31 CLK_TOP_APLL1_CK,
32 CLK_TOP_MUX_AUD_2,
33 CLK_TOP_APLL2_CK,
34 CLK_TOP_MUX_AUD_ENG1,
35 CLK_TOP_APLL1_D8,
36 CLK_TOP_MUX_AUD_ENG2,
37 CLK_TOP_APLL2_D8,
38 CLK_TOP_I2S0_M_SEL,
39 CLK_TOP_I2S1_M_SEL,
40 CLK_TOP_I2S2_M_SEL,
41 CLK_TOP_I2S3_M_SEL,
42 CLK_TOP_I2S4_M_SEL,
43 CLK_TOP_I2S5_M_SEL,
44 CLK_TOP_APLL12_DIV0,
45 CLK_TOP_APLL12_DIV1,
46 CLK_TOP_APLL12_DIV2,
47 CLK_TOP_APLL12_DIV3,
48 CLK_TOP_APLL12_DIV4,
49 CLK_TOP_APLL12_DIVB,
50 CLK_CLK26M,
51 CLK_NUM
52 };
53
54 static const char *aud_clks[CLK_NUM] = {
55 [CLK_AFE] = "aud_afe_clk",
56 [CLK_TML] = "aud_tml_clk",
57 [CLK_APLL22M] = "aud_apll22m_clk",
58 [CLK_APLL24M] = "aud_apll24m_clk",
59 [CLK_APLL1_TUNER] = "aud_apll1_tuner_clk",
60 [CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
61 [CLK_I2S1_BCLK_SW] = "aud_i2s1_bclk_sw",
62 [CLK_I2S2_BCLK_SW] = "aud_i2s2_bclk_sw",
63 [CLK_I2S3_BCLK_SW] = "aud_i2s3_bclk_sw",
64 [CLK_I2S4_BCLK_SW] = "aud_i2s4_bclk_sw",
65 [CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
66 [CLK_MUX_AUDIO] = "top_mux_audio",
67 [CLK_MUX_AUDIOINTBUS] = "top_mux_aud_intbus",
68 [CLK_TOP_SYSPLL_D2_D4] = "top_syspll_d2_d4",
69 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
70 [CLK_TOP_APLL1_CK] = "top_apll1_ck",
71 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
72 [CLK_TOP_APLL2_CK] = "top_apll2_ck",
73 [CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
74 [CLK_TOP_APLL1_D8] = "top_apll1_d8",
75 [CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
76 [CLK_TOP_APLL2_D8] = "top_apll2_d8",
77 [CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
78 [CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
79 [CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
80 [CLK_TOP_I2S3_M_SEL] = "top_i2s3_m_sel",
81 [CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
82 [CLK_TOP_I2S5_M_SEL] = "top_i2s5_m_sel",
83 [CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
84 [CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
85 [CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
86 [CLK_TOP_APLL12_DIV3] = "top_apll12_div3",
87 [CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
88 [CLK_TOP_APLL12_DIVB] = "top_apll12_divb",
89 [CLK_CLK26M] = "top_clk26m_clk",
90 };
91
mt8183_init_clock(struct mtk_base_afe * afe)92 int mt8183_init_clock(struct mtk_base_afe *afe)
93 {
94 struct mt8183_afe_private *afe_priv = afe->platform_priv;
95 int i;
96
97 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
98 GFP_KERNEL);
99 if (!afe_priv->clk)
100 return -ENOMEM;
101
102 for (i = 0; i < CLK_NUM; i++) {
103 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
104 if (IS_ERR(afe_priv->clk[i])) {
105 dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
106 __func__, aud_clks[i],
107 PTR_ERR(afe_priv->clk[i]));
108 return PTR_ERR(afe_priv->clk[i]);
109 }
110 }
111
112 return 0;
113 }
114
mt8183_afe_enable_clock(struct mtk_base_afe * afe)115 int mt8183_afe_enable_clock(struct mtk_base_afe *afe)
116 {
117 struct mt8183_afe_private *afe_priv = afe->platform_priv;
118 int ret;
119
120 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
121 if (ret) {
122 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
123 __func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
124 goto CLK_INFRA_SYS_AUDIO_ERR;
125 }
126
127 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
128 if (ret) {
129 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
130 __func__, aud_clks[CLK_MUX_AUDIO], ret);
131 goto CLK_MUX_AUDIO_ERR;
132 }
133
134 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
135 afe_priv->clk[CLK_CLK26M]);
136 if (ret) {
137 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
138 __func__, aud_clks[CLK_MUX_AUDIO],
139 aud_clks[CLK_CLK26M], ret);
140 goto CLK_MUX_AUDIO_ERR;
141 }
142
143 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
144 if (ret) {
145 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
146 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
147 goto CLK_MUX_AUDIO_INTBUS_ERR;
148 }
149
150 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
151 afe_priv->clk[CLK_TOP_SYSPLL_D2_D4]);
152 if (ret) {
153 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
154 __func__, aud_clks[CLK_MUX_AUDIOINTBUS],
155 aud_clks[CLK_TOP_SYSPLL_D2_D4], ret);
156 goto CLK_MUX_AUDIO_INTBUS_ERR;
157 }
158
159 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
160 if (ret) {
161 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
162 __func__, aud_clks[CLK_AFE], ret);
163 goto CLK_AFE_ERR;
164 }
165
166 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S1_BCLK_SW]);
167 if (ret) {
168 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
169 __func__, aud_clks[CLK_I2S1_BCLK_SW], ret);
170 goto CLK_I2S1_BCLK_SW_ERR;
171 }
172
173 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S2_BCLK_SW]);
174 if (ret) {
175 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
176 __func__, aud_clks[CLK_I2S2_BCLK_SW], ret);
177 goto CLK_I2S2_BCLK_SW_ERR;
178 }
179
180 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S3_BCLK_SW]);
181 if (ret) {
182 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
183 __func__, aud_clks[CLK_I2S3_BCLK_SW], ret);
184 goto CLK_I2S3_BCLK_SW_ERR;
185 }
186
187 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S4_BCLK_SW]);
188 if (ret) {
189 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
190 __func__, aud_clks[CLK_I2S4_BCLK_SW], ret);
191 goto CLK_I2S4_BCLK_SW_ERR;
192 }
193
194 return 0;
195
196 CLK_I2S4_BCLK_SW_ERR:
197 clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
198 CLK_I2S3_BCLK_SW_ERR:
199 clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
200 CLK_I2S2_BCLK_SW_ERR:
201 clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
202 CLK_I2S1_BCLK_SW_ERR:
203 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
204 CLK_AFE_ERR:
205 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
206 CLK_MUX_AUDIO_INTBUS_ERR:
207 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
208 CLK_MUX_AUDIO_ERR:
209 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
210 CLK_INFRA_SYS_AUDIO_ERR:
211 return ret;
212 }
213
mt8183_afe_disable_clock(struct mtk_base_afe * afe)214 int mt8183_afe_disable_clock(struct mtk_base_afe *afe)
215 {
216 struct mt8183_afe_private *afe_priv = afe->platform_priv;
217
218 clk_disable_unprepare(afe_priv->clk[CLK_I2S4_BCLK_SW]);
219 clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
220 clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
221 clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
222 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
223 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
224 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
225 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
226
227 return 0;
228 }
229
230 /* apll */
apll1_mux_setting(struct mtk_base_afe * afe,bool enable)231 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
232 {
233 struct mt8183_afe_private *afe_priv = afe->platform_priv;
234 int ret;
235
236 if (enable) {
237 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
238 if (ret) {
239 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
240 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
241 goto ERR_ENABLE_CLK_TOP_MUX_AUD_1;
242 }
243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
244 afe_priv->clk[CLK_TOP_APLL1_CK]);
245 if (ret) {
246 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
247 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
248 aud_clks[CLK_TOP_APLL1_CK], ret);
249 goto ERR_SELECT_CLK_TOP_MUX_AUD_1;
250 }
251
252 /* 180.6336 / 8 = 22.5792MHz */
253 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
254 if (ret) {
255 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
256 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
257 goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1;
258 }
259 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
260 afe_priv->clk[CLK_TOP_APLL1_D8]);
261 if (ret) {
262 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
263 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
264 aud_clks[CLK_TOP_APLL1_D8], ret);
265 goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG1;
266 }
267 } else {
268 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
269 afe_priv->clk[CLK_CLK26M]);
270 if (ret) {
271 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
272 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
273 aud_clks[CLK_CLK26M], ret);
274 goto EXIT;
275 }
276 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
277
278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
279 afe_priv->clk[CLK_CLK26M]);
280 if (ret) {
281 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
282 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
283 aud_clks[CLK_CLK26M], ret);
284 goto EXIT;
285 }
286 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
287 }
288
289 return 0;
290
291 ERR_SELECT_CLK_TOP_MUX_AUD_ENG1:
292 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
293 afe_priv->clk[CLK_CLK26M]);
294 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
295 ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1:
296 ERR_SELECT_CLK_TOP_MUX_AUD_1:
297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
298 afe_priv->clk[CLK_CLK26M]);
299 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
300 ERR_ENABLE_CLK_TOP_MUX_AUD_1:
301 EXIT:
302 return ret;
303 }
304
apll2_mux_setting(struct mtk_base_afe * afe,bool enable)305 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
306 {
307 struct mt8183_afe_private *afe_priv = afe->platform_priv;
308 int ret;
309
310 if (enable) {
311 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
312 if (ret) {
313 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
314 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
315 goto ERR_ENABLE_CLK_TOP_MUX_AUD_2;
316 }
317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
318 afe_priv->clk[CLK_TOP_APLL2_CK]);
319 if (ret) {
320 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
321 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
322 aud_clks[CLK_TOP_APLL2_CK], ret);
323 goto ERR_SELECT_CLK_TOP_MUX_AUD_2;
324 }
325
326 /* 196.608 / 8 = 24.576MHz */
327 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
328 if (ret) {
329 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
330 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
331 goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2;
332 }
333 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
334 afe_priv->clk[CLK_TOP_APLL2_D8]);
335 if (ret) {
336 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
337 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
338 aud_clks[CLK_TOP_APLL2_D8], ret);
339 goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG2;
340 }
341 } else {
342 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
343 afe_priv->clk[CLK_CLK26M]);
344 if (ret) {
345 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
346 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
347 aud_clks[CLK_CLK26M], ret);
348 goto EXIT;
349 }
350 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
351
352 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
353 afe_priv->clk[CLK_CLK26M]);
354 if (ret) {
355 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
356 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
357 aud_clks[CLK_CLK26M], ret);
358 goto EXIT;
359 }
360 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
361 }
362
363 return 0;
364
365 ERR_SELECT_CLK_TOP_MUX_AUD_ENG2:
366 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
367 afe_priv->clk[CLK_CLK26M]);
368 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
369 ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2:
370 ERR_SELECT_CLK_TOP_MUX_AUD_2:
371 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
372 afe_priv->clk[CLK_CLK26M]);
373 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
374 ERR_ENABLE_CLK_TOP_MUX_AUD_2:
375 EXIT:
376 return ret;
377 }
378
mt8183_apll1_enable(struct mtk_base_afe * afe)379 int mt8183_apll1_enable(struct mtk_base_afe *afe)
380 {
381 struct mt8183_afe_private *afe_priv = afe->platform_priv;
382 int ret;
383
384 /* setting for APLL */
385 apll1_mux_setting(afe, true);
386
387 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
388 if (ret) {
389 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
390 __func__, aud_clks[CLK_APLL22M], ret);
391 goto ERR_CLK_APLL22M;
392 }
393
394 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
395 if (ret) {
396 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
397 __func__, aud_clks[CLK_APLL1_TUNER], ret);
398 goto ERR_CLK_APLL1_TUNER;
399 }
400
401 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
402 0x0000FFF7, 0x00000832);
403 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
404
405 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
406 AFE_22M_ON_MASK_SFT,
407 0x1 << AFE_22M_ON_SFT);
408
409 return 0;
410
411 ERR_CLK_APLL1_TUNER:
412 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
413 ERR_CLK_APLL22M:
414 return ret;
415 }
416
mt8183_apll1_disable(struct mtk_base_afe * afe)417 void mt8183_apll1_disable(struct mtk_base_afe *afe)
418 {
419 struct mt8183_afe_private *afe_priv = afe->platform_priv;
420
421 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
422 AFE_22M_ON_MASK_SFT,
423 0x0 << AFE_22M_ON_SFT);
424
425 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);
426
427 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
428 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
429
430 apll1_mux_setting(afe, false);
431 }
432
mt8183_apll2_enable(struct mtk_base_afe * afe)433 int mt8183_apll2_enable(struct mtk_base_afe *afe)
434 {
435 struct mt8183_afe_private *afe_priv = afe->platform_priv;
436 int ret;
437
438 /* setting for APLL */
439 apll2_mux_setting(afe, true);
440
441 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
442 if (ret) {
443 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
444 __func__, aud_clks[CLK_APLL24M], ret);
445 goto ERR_CLK_APLL24M;
446 }
447
448 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
449 if (ret) {
450 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
451 __func__, aud_clks[CLK_APLL2_TUNER], ret);
452 goto ERR_CLK_APLL2_TUNER;
453 }
454
455 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
456 0x0000FFF7, 0x00000634);
457 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
458
459 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
460 AFE_24M_ON_MASK_SFT,
461 0x1 << AFE_24M_ON_SFT);
462
463 return 0;
464
465 ERR_CLK_APLL2_TUNER:
466 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
467 ERR_CLK_APLL24M:
468 return ret;
469 }
470
mt8183_apll2_disable(struct mtk_base_afe * afe)471 void mt8183_apll2_disable(struct mtk_base_afe *afe)
472 {
473 struct mt8183_afe_private *afe_priv = afe->platform_priv;
474
475 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
476 AFE_24M_ON_MASK_SFT,
477 0x0 << AFE_24M_ON_SFT);
478
479 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);
480
481 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
482 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
483
484 apll2_mux_setting(afe, false);
485 }
486
mt8183_get_apll_rate(struct mtk_base_afe * afe,int apll)487 int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll)
488 {
489 return (apll == MT8183_APLL1) ? 180633600 : 196608000;
490 }
491
mt8183_get_apll_by_rate(struct mtk_base_afe * afe,int rate)492 int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
493 {
494 return ((rate % 8000) == 0) ? MT8183_APLL2 : MT8183_APLL1;
495 }
496
mt8183_get_apll_by_name(struct mtk_base_afe * afe,const char * name)497 int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
498 {
499 if (strcmp(name, APLL1_W_NAME) == 0)
500 return MT8183_APLL1;
501 else
502 return MT8183_APLL2;
503 }
504
505 /* mck */
506 struct mt8183_mck_div {
507 int m_sel_id;
508 int div_clk_id;
509 };
510
511 static const struct mt8183_mck_div mck_div[MT8183_MCK_NUM] = {
512 [MT8183_I2S0_MCK] = {
513 .m_sel_id = CLK_TOP_I2S0_M_SEL,
514 .div_clk_id = CLK_TOP_APLL12_DIV0,
515 },
516 [MT8183_I2S1_MCK] = {
517 .m_sel_id = CLK_TOP_I2S1_M_SEL,
518 .div_clk_id = CLK_TOP_APLL12_DIV1,
519 },
520 [MT8183_I2S2_MCK] = {
521 .m_sel_id = CLK_TOP_I2S2_M_SEL,
522 .div_clk_id = CLK_TOP_APLL12_DIV2,
523 },
524 [MT8183_I2S3_MCK] = {
525 .m_sel_id = CLK_TOP_I2S3_M_SEL,
526 .div_clk_id = CLK_TOP_APLL12_DIV3,
527 },
528 [MT8183_I2S4_MCK] = {
529 .m_sel_id = CLK_TOP_I2S4_M_SEL,
530 .div_clk_id = CLK_TOP_APLL12_DIV4,
531 },
532 [MT8183_I2S4_BCK] = {
533 .m_sel_id = -1,
534 .div_clk_id = CLK_TOP_APLL12_DIVB,
535 },
536 [MT8183_I2S5_MCK] = {
537 .m_sel_id = -1,
538 .div_clk_id = -1,
539 },
540 };
541
mt8183_mck_enable(struct mtk_base_afe * afe,int mck_id,int rate)542 int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
543 {
544 struct mt8183_afe_private *afe_priv = afe->platform_priv;
545 int apll = mt8183_get_apll_by_rate(afe, rate);
546 int apll_clk_id = apll == MT8183_APLL1 ?
547 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
548 int m_sel_id = mck_div[mck_id].m_sel_id;
549 int div_clk_id = mck_div[mck_id].div_clk_id;
550 int ret;
551
552 /* i2s5 mck not support */
553 if (mck_id == MT8183_I2S5_MCK)
554 return 0;
555
556 /* select apll */
557 if (m_sel_id >= 0) {
558 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
559 if (ret) {
560 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
561 __func__, aud_clks[m_sel_id], ret);
562 goto ERR_ENABLE_MCLK;
563 }
564 ret = clk_set_parent(afe_priv->clk[m_sel_id],
565 afe_priv->clk[apll_clk_id]);
566 if (ret) {
567 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
568 __func__, aud_clks[m_sel_id],
569 aud_clks[apll_clk_id], ret);
570 goto ERR_SELECT_MCLK;
571 }
572 }
573
574 /* enable div, set rate */
575 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
576 if (ret) {
577 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
578 __func__, aud_clks[div_clk_id], ret);
579 goto ERR_ENABLE_MCLK_DIV;
580 }
581 ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
582 if (ret) {
583 dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
584 __func__, aud_clks[div_clk_id],
585 rate, ret);
586 goto ERR_SET_MCLK_RATE;
587 }
588
589 return 0;
590
591 ERR_SET_MCLK_RATE:
592 clk_disable_unprepare(afe_priv->clk[div_clk_id]);
593 ERR_ENABLE_MCLK_DIV:
594 ERR_SELECT_MCLK:
595 if (m_sel_id >= 0)
596 clk_disable_unprepare(afe_priv->clk[m_sel_id]);
597 ERR_ENABLE_MCLK:
598 return ret;
599 }
600
mt8183_mck_disable(struct mtk_base_afe * afe,int mck_id)601 void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id)
602 {
603 struct mt8183_afe_private *afe_priv = afe->platform_priv;
604 int m_sel_id = mck_div[mck_id].m_sel_id;
605 int div_clk_id = mck_div[mck_id].div_clk_id;
606
607 /* i2s5 mck not support */
608 if (mck_id == MT8183_I2S5_MCK)
609 return;
610
611 clk_disable_unprepare(afe_priv->clk[div_clk_id]);
612 if (m_sel_id >= 0)
613 clk_disable_unprepare(afe_priv->clk[m_sel_id]);
614 }
615
