1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/platform_device.h>
7 #include <linux/pci.h>
8
9 #include "mt7915.h"
10 #include "mac.h"
11 #include "../trace.h"
12
13 static const u32 mt7915_reg[] = {
14 [INT_SOURCE_CSR] = 0xd7010,
15 [INT_MASK_CSR] = 0xd7014,
16 [INT1_SOURCE_CSR] = 0xd7088,
17 [INT1_MASK_CSR] = 0xd708c,
18 [INT_MCU_CMD_SOURCE] = 0xd51f0,
19 [INT_MCU_CMD_EVENT] = 0x3108,
20 [WFDMA0_ADDR] = 0xd4000,
21 [WFDMA0_PCIE1_ADDR] = 0xd8000,
22 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
23 [CBTOP1_PHY_END] = 0x77ffffff,
24 [INFRA_MCU_ADDR_END] = 0x7c3fffff,
25 [FW_EXCEPTION_ADDR] = 0x219848,
26 [SWDEF_BASE_ADDR] = 0x41f200,
27 };
28
29 static const u32 mt7916_reg[] = {
30 [INT_SOURCE_CSR] = 0xd4200,
31 [INT_MASK_CSR] = 0xd4204,
32 [INT1_SOURCE_CSR] = 0xd8200,
33 [INT1_MASK_CSR] = 0xd8204,
34 [INT_MCU_CMD_SOURCE] = 0xd41f0,
35 [INT_MCU_CMD_EVENT] = 0x2108,
36 [WFDMA0_ADDR] = 0xd4000,
37 [WFDMA0_PCIE1_ADDR] = 0xd8000,
38 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
39 [CBTOP1_PHY_END] = 0x7fffffff,
40 [INFRA_MCU_ADDR_END] = 0x7c085fff,
41 [FW_EXCEPTION_ADDR] = 0x022050bc,
42 [SWDEF_BASE_ADDR] = 0x411400,
43 };
44
45 static const u32 mt7986_reg[] = {
46 [INT_SOURCE_CSR] = 0x24200,
47 [INT_MASK_CSR] = 0x24204,
48 [INT1_SOURCE_CSR] = 0x28200,
49 [INT1_MASK_CSR] = 0x28204,
50 [INT_MCU_CMD_SOURCE] = 0x241f0,
51 [INT_MCU_CMD_EVENT] = 0x54000108,
52 [WFDMA0_ADDR] = 0x24000,
53 [WFDMA0_PCIE1_ADDR] = 0x28000,
54 [WFDMA_EXT_CSR_ADDR] = 0x27000,
55 [CBTOP1_PHY_END] = 0x7fffffff,
56 [INFRA_MCU_ADDR_END] = 0x7c085fff,
57 [FW_EXCEPTION_ADDR] = 0x02204ffc,
58 [SWDEF_BASE_ADDR] = 0x411400,
59 };
60
61 static const u32 mt7915_offs[] = {
62 [TMAC_CDTR] = 0x090,
63 [TMAC_ODTR] = 0x094,
64 [TMAC_ATCR] = 0x098,
65 [TMAC_TRCR0] = 0x09c,
66 [TMAC_ICR0] = 0x0a4,
67 [TMAC_ICR1] = 0x0b4,
68 [TMAC_CTCR0] = 0x0f4,
69 [TMAC_TFCR0] = 0x1e0,
70 [MDP_BNRCFR0] = 0x070,
71 [MDP_BNRCFR1] = 0x074,
72 [ARB_DRNGR0] = 0x194,
73 [ARB_SCR] = 0x080,
74 [RMAC_MIB_AIRTIME14] = 0x3b8,
75 [AGG_AWSCR0] = 0x05c,
76 [AGG_PCR0] = 0x06c,
77 [AGG_ACR0] = 0x084,
78 [AGG_ACR4] = 0x08c,
79 [AGG_MRCR] = 0x098,
80 [AGG_ATCR1] = 0x0f0,
81 [AGG_ATCR3] = 0x0f4,
82 [LPON_UTTR0] = 0x080,
83 [LPON_UTTR1] = 0x084,
84 [LPON_FRCR] = 0x314,
85 [MIB_SDR3] = 0x014,
86 [MIB_SDR4] = 0x018,
87 [MIB_SDR5] = 0x01c,
88 [MIB_SDR7] = 0x024,
89 [MIB_SDR8] = 0x028,
90 [MIB_SDR9] = 0x02c,
91 [MIB_SDR10] = 0x030,
92 [MIB_SDR11] = 0x034,
93 [MIB_SDR12] = 0x038,
94 [MIB_SDR13] = 0x03c,
95 [MIB_SDR14] = 0x040,
96 [MIB_SDR15] = 0x044,
97 [MIB_SDR16] = 0x048,
98 [MIB_SDR17] = 0x04c,
99 [MIB_SDR18] = 0x050,
100 [MIB_SDR19] = 0x054,
101 [MIB_SDR20] = 0x058,
102 [MIB_SDR21] = 0x05c,
103 [MIB_SDR22] = 0x060,
104 [MIB_SDR23] = 0x064,
105 [MIB_SDR24] = 0x068,
106 [MIB_SDR25] = 0x06c,
107 [MIB_SDR27] = 0x074,
108 [MIB_SDR28] = 0x078,
109 [MIB_SDR29] = 0x07c,
110 [MIB_SDRVEC] = 0x080,
111 [MIB_SDR31] = 0x084,
112 [MIB_SDR32] = 0x088,
113 [MIB_SDRMUBF] = 0x090,
114 [MIB_DR8] = 0x0c0,
115 [MIB_DR9] = 0x0c4,
116 [MIB_DR11] = 0x0cc,
117 [MIB_MB_SDR0] = 0x100,
118 [MIB_MB_SDR1] = 0x104,
119 [TX_AGG_CNT] = 0x0a8,
120 [TX_AGG_CNT2] = 0x164,
121 [MIB_ARNG] = 0x4b8,
122 [WTBLON_TOP_WDUCR] = 0x0,
123 [WTBL_UPDATE] = 0x030,
124 [PLE_FL_Q_EMPTY] = 0x0b0,
125 [PLE_FL_Q_CTRL] = 0x1b0,
126 [PLE_AC_QEMPTY] = 0x500,
127 [PLE_FREEPG_CNT] = 0x100,
128 [PLE_FREEPG_HEAD_TAIL] = 0x104,
129 [PLE_PG_HIF_GROUP] = 0x110,
130 [PLE_HIF_PG_INFO] = 0x114,
131 [AC_OFFSET] = 0x040,
132 [ETBF_PAR_RPT0] = 0x068,
133 };
134
135 static const u32 mt7916_offs[] = {
136 [TMAC_CDTR] = 0x0c8,
137 [TMAC_ODTR] = 0x0cc,
138 [TMAC_ATCR] = 0x00c,
139 [TMAC_TRCR0] = 0x010,
140 [TMAC_ICR0] = 0x014,
141 [TMAC_ICR1] = 0x018,
142 [TMAC_CTCR0] = 0x114,
143 [TMAC_TFCR0] = 0x0e4,
144 [MDP_BNRCFR0] = 0x090,
145 [MDP_BNRCFR1] = 0x094,
146 [ARB_DRNGR0] = 0x1e0,
147 [ARB_SCR] = 0x000,
148 [RMAC_MIB_AIRTIME14] = 0x0398,
149 [AGG_AWSCR0] = 0x030,
150 [AGG_PCR0] = 0x040,
151 [AGG_ACR0] = 0x054,
152 [AGG_ACR4] = 0x05c,
153 [AGG_MRCR] = 0x068,
154 [AGG_ATCR1] = 0x1a8,
155 [AGG_ATCR3] = 0x080,
156 [LPON_UTTR0] = 0x360,
157 [LPON_UTTR1] = 0x364,
158 [LPON_FRCR] = 0x37c,
159 [MIB_SDR3] = 0x698,
160 [MIB_SDR4] = 0x788,
161 [MIB_SDR5] = 0x780,
162 [MIB_SDR7] = 0x5a8,
163 [MIB_SDR8] = 0x78c,
164 [MIB_SDR9] = 0x024,
165 [MIB_SDR10] = 0x76c,
166 [MIB_SDR11] = 0x790,
167 [MIB_SDR12] = 0x558,
168 [MIB_SDR13] = 0x560,
169 [MIB_SDR14] = 0x564,
170 [MIB_SDR15] = 0x568,
171 [MIB_SDR16] = 0x7fc,
172 [MIB_SDR17] = 0x800,
173 [MIB_SDR18] = 0x030,
174 [MIB_SDR19] = 0x5ac,
175 [MIB_SDR20] = 0x5b0,
176 [MIB_SDR21] = 0x5b4,
177 [MIB_SDR22] = 0x770,
178 [MIB_SDR23] = 0x774,
179 [MIB_SDR24] = 0x778,
180 [MIB_SDR25] = 0x77c,
181 [MIB_SDR27] = 0x080,
182 [MIB_SDR28] = 0x084,
183 [MIB_SDR29] = 0x650,
184 [MIB_SDRVEC] = 0x5a8,
185 [MIB_SDR31] = 0x55c,
186 [MIB_SDR32] = 0x7a8,
187 [MIB_SDRMUBF] = 0x7ac,
188 [MIB_DR8] = 0x56c,
189 [MIB_DR9] = 0x570,
190 [MIB_DR11] = 0x574,
191 [MIB_MB_SDR0] = 0x688,
192 [MIB_MB_SDR1] = 0x690,
193 [TX_AGG_CNT] = 0x7dc,
194 [TX_AGG_CNT2] = 0x7ec,
195 [MIB_ARNG] = 0x0b0,
196 [WTBLON_TOP_WDUCR] = 0x200,
197 [WTBL_UPDATE] = 0x230,
198 [PLE_FL_Q_EMPTY] = 0x360,
199 [PLE_FL_Q_CTRL] = 0x3e0,
200 [PLE_AC_QEMPTY] = 0x600,
201 [PLE_FREEPG_CNT] = 0x380,
202 [PLE_FREEPG_HEAD_TAIL] = 0x384,
203 [PLE_PG_HIF_GROUP] = 0x00c,
204 [PLE_HIF_PG_INFO] = 0x388,
205 [AC_OFFSET] = 0x080,
206 [ETBF_PAR_RPT0] = 0x100,
207 };
208
209 static const struct mt76_connac_reg_map mt7915_reg_map[] = {
210 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
211 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
212 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
213 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
214 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
215 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
216 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
217 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
218 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
219 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
220 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
221 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
222 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
223 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
224 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
225 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
226 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
227 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
228 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
229 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
230 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
231 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
232 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
233 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
234 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
235 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
236 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
237 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
238 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
239 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
240 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
241 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
242 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
243 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
244 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
245 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
246 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
247 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
248 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
249 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
250 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
251 { 0x0, 0x0, 0x0 }, /* imply end of search */
252 };
253
254 static const struct mt76_connac_reg_map mt7916_reg_map[] = {
255 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
256 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
257 { 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */
258 { 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
259 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
260 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
261 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
262 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
263 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
264 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
265 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
266 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
267 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
268 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
269 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
270 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
271 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
272 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
273 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
274 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
275 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
276 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
277 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
278 { 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
279 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
280 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
281 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */
282 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
283 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
284 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
285 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
286 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
287 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
288 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
289 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
290 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
291 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
292 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
293 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
294 { 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
295 { 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */
296 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
297 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
298 { 0x0, 0x0, 0x0 }, /* imply end of search */
299 };
300
301 static const struct mt76_connac_reg_map mt7986_reg_map[] = {
302 { 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
303 { 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
304 { 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */
305 { 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */
306 { 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
307 { 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
308 { 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
309 { 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
310 { 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */
311 { 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
312 { 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
313 { 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
314 { 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
315 { 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
316 { 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
317 { 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
318 { 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
319 { 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
320 { 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
321 { 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
322 { 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
323 { 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
324 { 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
325 { 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
326 { 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
327 { 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */
328 { 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */
329 { 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
330 { 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
331 { 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
332 { 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
333 { 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
334 { 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
335 { 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
336 { 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
337 { 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
338 { 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
339 { 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
340 { 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
341 { 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
342 { 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */
343 { 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */
344 { 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */
345 { 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */
346 { 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */
347 { 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */
348 { 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */
349 { 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */
350 { 0x0, 0x0, 0x0 }, /* imply end of search */
351 };
352
mt7915_reg_map_l1(struct mt7915_dev * dev,u32 addr)353 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
354 {
355 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
356 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
357 u32 l1_remap;
358
359 if (is_mt7986(&dev->mt76))
360 return MT_CONN_INFRA_OFFSET(addr);
361
362 l1_remap = is_mt7915(&dev->mt76) ?
363 MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916;
364
365 dev->bus_ops->rmw(&dev->mt76, l1_remap,
366 MT_HIF_REMAP_L1_MASK,
367 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
368 /* use read to push write */
369 dev->bus_ops->rr(&dev->mt76, l1_remap);
370
371 return MT_HIF_REMAP_BASE_L1 + offset;
372 }
373
mt7915_reg_map_l2(struct mt7915_dev * dev,u32 addr)374 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr)
375 {
376 u32 offset, base;
377
378 if (is_mt7915(&dev->mt76)) {
379 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
380 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
381
382 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
383 MT_HIF_REMAP_L2_MASK,
384 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base));
385
386 /* use read to push write */
387 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
388 } else {
389 u32 ofs = is_mt7986(&dev->mt76) ? 0x400000 : 0;
390
391 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr);
392 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr);
393
394 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs,
395 MT_HIF_REMAP_L2_MASK_MT7916,
396 FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base));
397
398 /* use read to push write */
399 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs);
400
401 offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs);
402 }
403
404 return offset;
405 }
406
__mt7915_reg_addr(struct mt7915_dev * dev,u32 addr)407 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
408 {
409 int i;
410
411 if (addr < 0x100000)
412 return addr;
413
414 if (!dev->reg.map) {
415 dev_err(dev->mt76.dev, "err: reg_map is null\n");
416 return addr;
417 }
418
419 for (i = 0; i < dev->reg.map_size; i++) {
420 u32 ofs;
421
422 if (addr < dev->reg.map[i].phys)
423 continue;
424
425 ofs = addr - dev->reg.map[i].phys;
426 if (ofs > dev->reg.map[i].size)
427 continue;
428
429 return dev->reg.map[i].maps + ofs;
430 }
431
432 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
433 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
434 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
435 return mt7915_reg_map_l1(dev, addr);
436
437 if (dev_is_pci(dev->mt76.dev) &&
438 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
439 (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END)))
440 return mt7915_reg_map_l1(dev, addr);
441
442 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
443 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
444 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
445 return mt7915_reg_map_l1(dev, addr);
446 }
447
448 return mt7915_reg_map_l2(dev, addr);
449 }
450
mt7915_rr(struct mt76_dev * mdev,u32 offset)451 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset)
452 {
453 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
454 u32 addr = __mt7915_reg_addr(dev, offset);
455
456 return dev->bus_ops->rr(mdev, addr);
457 }
458
mt7915_wr(struct mt76_dev * mdev,u32 offset,u32 val)459 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val)
460 {
461 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
462 u32 addr = __mt7915_reg_addr(dev, offset);
463
464 dev->bus_ops->wr(mdev, addr, val);
465 }
466
mt7915_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)467 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
468 {
469 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
470 u32 addr = __mt7915_reg_addr(dev, offset);
471
472 return dev->bus_ops->rmw(mdev, addr, mask, val);
473 }
474
mt7915_mmio_init(struct mt76_dev * mdev,void __iomem * mem_base,u32 device_id)475 static int mt7915_mmio_init(struct mt76_dev *mdev,
476 void __iomem *mem_base,
477 u32 device_id)
478 {
479 struct mt76_bus_ops *bus_ops;
480 struct mt7915_dev *dev;
481
482 dev = container_of(mdev, struct mt7915_dev, mt76);
483 mt76_mmio_init(&dev->mt76, mem_base);
484
485 switch (device_id) {
486 case 0x7915:
487 dev->reg.reg_rev = mt7915_reg;
488 dev->reg.offs_rev = mt7915_offs;
489 dev->reg.map = mt7915_reg_map;
490 dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map);
491 break;
492 case 0x7906:
493 dev->reg.reg_rev = mt7916_reg;
494 dev->reg.offs_rev = mt7916_offs;
495 dev->reg.map = mt7916_reg_map;
496 dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map);
497 break;
498 case 0x7986:
499 dev->reg.reg_rev = mt7986_reg;
500 dev->reg.offs_rev = mt7916_offs;
501 dev->reg.map = mt7986_reg_map;
502 dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map);
503 break;
504 default:
505 return -EINVAL;
506 }
507
508 dev->bus_ops = dev->mt76.bus;
509 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
510 GFP_KERNEL);
511 if (!bus_ops)
512 return -ENOMEM;
513
514 bus_ops->rr = mt7915_rr;
515 bus_ops->wr = mt7915_wr;
516 bus_ops->rmw = mt7915_rmw;
517 dev->mt76.bus = bus_ops;
518
519 mdev->rev = (device_id << 16) |
520 (mt76_rr(dev, MT_HW_REV) & 0xff);
521 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
522
523 return 0;
524 }
525
mt7915_dual_hif_set_irq_mask(struct mt7915_dev * dev,bool write_reg,u32 clear,u32 set)526 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev,
527 bool write_reg,
528 u32 clear, u32 set)
529 {
530 struct mt76_dev *mdev = &dev->mt76;
531 unsigned long flags;
532
533 spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
534
535 mdev->mmio.irqmask &= ~clear;
536 mdev->mmio.irqmask |= set;
537
538 if (write_reg) {
539 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
540 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
541 }
542
543 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
544 }
545
mt7915_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)546 static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
547 enum mt76_rxq_id q)
548 {
549 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
550
551 mt7915_irq_enable(dev, MT_INT_RX(q));
552 }
553
554 /* TODO: support 2/4/6/8 MSI-X vectors */
mt7915_irq_tasklet(struct tasklet_struct * t)555 static void mt7915_irq_tasklet(struct tasklet_struct *t)
556 {
557 struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet);
558 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
559 u32 intr, intr1, mask;
560
561 if (mtk_wed_device_active(wed)) {
562 mtk_wed_device_irq_set_mask(wed, 0);
563 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
564 } else {
565 mt76_wr(dev, MT_INT_MASK_CSR, 0);
566 if (dev->hif2)
567 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
568
569 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
570 intr &= dev->mt76.mmio.irqmask;
571 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
572 }
573
574 if (dev->hif2) {
575 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
576 intr1 &= dev->mt76.mmio.irqmask;
577 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
578
579 intr |= intr1;
580 }
581
582 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
583
584 mask = intr & MT_INT_RX_DONE_ALL;
585 if (intr & MT_INT_TX_DONE_MCU)
586 mask |= MT_INT_TX_DONE_MCU;
587
588 mt7915_irq_disable(dev, mask);
589
590 if (intr & MT_INT_TX_DONE_MCU)
591 napi_schedule(&dev->mt76.tx_napi);
592
593 if (intr & MT_INT_RX(MT_RXQ_MAIN))
594 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
595
596 if (intr & MT_INT_RX(MT_RXQ_BAND1))
597 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]);
598
599 if (intr & MT_INT_RX(MT_RXQ_MCU))
600 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
601
602 if (intr & MT_INT_RX(MT_RXQ_MCU_WA))
603 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
604
605 if (!is_mt7915(&dev->mt76) &&
606 (intr & MT_INT_RX(MT_RXQ_MAIN_WA)))
607 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]);
608
609 if (intr & MT_INT_RX(MT_RXQ_BAND1_WA))
610 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]);
611
612 if (intr & MT_INT_MCU_CMD) {
613 u32 val = mt76_rr(dev, MT_MCU_CMD);
614
615 mt76_wr(dev, MT_MCU_CMD, val);
616 if (val & MT_MCU_CMD_ERROR_MASK) {
617 dev->reset_state = val;
618 queue_work(dev->mt76.wq, &dev->reset_work);
619 wake_up(&dev->reset_wait);
620 }
621 }
622 }
623
mt7915_irq_handler(int irq,void * dev_instance)624 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
625 {
626 struct mt7915_dev *dev = dev_instance;
627 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
628
629 if (mtk_wed_device_active(wed)) {
630 mtk_wed_device_irq_set_mask(wed, 0);
631 } else {
632 mt76_wr(dev, MT_INT_MASK_CSR, 0);
633 if (dev->hif2)
634 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
635 }
636
637 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
638 return IRQ_NONE;
639
640 tasklet_schedule(&dev->irq_tasklet);
641
642 return IRQ_HANDLED;
643 }
644
mt7915_mmio_probe(struct device * pdev,void __iomem * mem_base,u32 device_id)645 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
646 void __iomem *mem_base, u32 device_id)
647 {
648 static const struct mt76_driver_ops drv_ops = {
649 /* txwi_size = txd size + txp size */
650 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
651 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
652 .survey_flags = SURVEY_INFO_TIME_TX |
653 SURVEY_INFO_TIME_RX |
654 SURVEY_INFO_TIME_BSS_RX,
655 .token_size = MT7915_TOKEN_SIZE,
656 .tx_prepare_skb = mt7915_tx_prepare_skb,
657 .tx_complete_skb = mt76_connac_tx_complete_skb,
658 .rx_skb = mt7915_queue_rx_skb,
659 .rx_check = mt7915_rx_check,
660 .rx_poll_complete = mt7915_rx_poll_complete,
661 .sta_ps = mt7915_sta_ps,
662 .sta_add = mt7915_mac_sta_add,
663 .sta_remove = mt7915_mac_sta_remove,
664 .update_survey = mt7915_update_channel,
665 };
666 struct mt7915_dev *dev;
667 struct mt76_dev *mdev;
668 int ret;
669
670 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops);
671 if (!mdev)
672 return ERR_PTR(-ENOMEM);
673
674 dev = container_of(mdev, struct mt7915_dev, mt76);
675
676 ret = mt7915_mmio_init(mdev, mem_base, device_id);
677 if (ret)
678 goto error;
679
680 tasklet_setup(&dev->irq_tasklet, mt7915_irq_tasklet);
681
682 return dev;
683
684 error:
685 mt76_free_device(&dev->mt76);
686
687 return ERR_PTR(ret);
688 }
689
mt7915_init(void)690 static int __init mt7915_init(void)
691 {
692 int ret;
693
694 ret = pci_register_driver(&mt7915_hif_driver);
695 if (ret)
696 return ret;
697
698 ret = pci_register_driver(&mt7915_pci_driver);
699 if (ret)
700 goto error_pci;
701
702 if (IS_ENABLED(CONFIG_MT7986_WMAC)) {
703 ret = platform_driver_register(&mt7986_wmac_driver);
704 if (ret)
705 goto error_wmac;
706 }
707
708 return 0;
709
710 error_wmac:
711 pci_unregister_driver(&mt7915_pci_driver);
712 error_pci:
713 pci_unregister_driver(&mt7915_hif_driver);
714
715 return ret;
716 }
717
mt7915_exit(void)718 static void __exit mt7915_exit(void)
719 {
720 if (IS_ENABLED(CONFIG_MT7986_WMAC))
721 platform_driver_unregister(&mt7986_wmac_driver);
722
723 pci_unregister_driver(&mt7915_pci_driver);
724 pci_unregister_driver(&mt7915_hif_driver);
725 }
726
727 module_init(mt7915_init);
728 module_exit(mt7915_exit);
729 MODULE_LICENSE("Dual BSD/GPL");
730
