1 /*
2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <asm/unaligned.h>
18 #include "mt76x2.h"
19 #include "mt76x2_eeprom.h"
20
21 #define EE_FIELD(_name, _value) [MT_EE_##_name] = (_value) | 1
22
23 static int
mt76x2_eeprom_copy(struct mt76x2_dev * dev,enum mt76x2_eeprom_field field,void * dest,int len)24 mt76x2_eeprom_copy(struct mt76x2_dev *dev, enum mt76x2_eeprom_field field,
25 void *dest, int len)
26 {
27 if (field + len > dev->mt76.eeprom.size)
28 return -1;
29
30 memcpy(dest, dev->mt76.eeprom.data + field, len);
31 return 0;
32 }
33
34 static int
mt76x2_eeprom_get_macaddr(struct mt76x2_dev * dev)35 mt76x2_eeprom_get_macaddr(struct mt76x2_dev *dev)
36 {
37 void *src = dev->mt76.eeprom.data + MT_EE_MAC_ADDR;
38
39 memcpy(dev->mt76.macaddr, src, ETH_ALEN);
40 return 0;
41 }
42
mt76x2_eeprom_parse_hw_cap(struct mt76x2_dev * dev)43 void mt76x2_eeprom_parse_hw_cap(struct mt76x2_dev *dev)
44 {
45 u16 val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_0);
46
47 switch (FIELD_GET(MT_EE_NIC_CONF_0_BOARD_TYPE, val)) {
48 case BOARD_TYPE_5GHZ:
49 dev->mt76.cap.has_5ghz = true;
50 break;
51 case BOARD_TYPE_2GHZ:
52 dev->mt76.cap.has_2ghz = true;
53 break;
54 default:
55 dev->mt76.cap.has_2ghz = true;
56 dev->mt76.cap.has_5ghz = true;
57 break;
58 }
59 }
60 EXPORT_SYMBOL_GPL(mt76x2_eeprom_parse_hw_cap);
61
62 static int
mt76x2_efuse_read(struct mt76x2_dev * dev,u16 addr,u8 * data)63 mt76x2_efuse_read(struct mt76x2_dev *dev, u16 addr, u8 *data)
64 {
65 u32 val;
66 int i;
67
68 val = mt76_rr(dev, MT_EFUSE_CTRL);
69 val &= ~(MT_EFUSE_CTRL_AIN |
70 MT_EFUSE_CTRL_MODE);
71 val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf);
72 val |= MT_EFUSE_CTRL_KICK;
73 mt76_wr(dev, MT_EFUSE_CTRL, val);
74
75 if (!mt76_poll(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000))
76 return -ETIMEDOUT;
77
78 udelay(2);
79
80 val = mt76_rr(dev, MT_EFUSE_CTRL);
81 if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) {
82 memset(data, 0xff, 16);
83 return 0;
84 }
85
86 for (i = 0; i < 4; i++) {
87 val = mt76_rr(dev, MT_EFUSE_DATA(i));
88 put_unaligned_le32(val, data + 4 * i);
89 }
90
91 return 0;
92 }
93
94 static int
mt76x2_get_efuse_data(struct mt76x2_dev * dev,void * buf,int len)95 mt76x2_get_efuse_data(struct mt76x2_dev *dev, void *buf, int len)
96 {
97 int ret, i;
98
99 for (i = 0; i + 16 <= len; i += 16) {
100 ret = mt76x2_efuse_read(dev, i, buf + i);
101 if (ret)
102 return ret;
103 }
104
105 return 0;
106 }
107
108 static bool
mt76x2_has_cal_free_data(struct mt76x2_dev * dev,u8 * efuse)109 mt76x2_has_cal_free_data(struct mt76x2_dev *dev, u8 *efuse)
110 {
111 u16 *efuse_w = (u16 *) efuse;
112
113 if (efuse_w[MT_EE_NIC_CONF_0] != 0)
114 return false;
115
116 if (efuse_w[MT_EE_XTAL_TRIM_1] == 0xffff)
117 return false;
118
119 if (efuse_w[MT_EE_TX_POWER_DELTA_BW40] != 0)
120 return false;
121
122 if (efuse_w[MT_EE_TX_POWER_0_START_2G] == 0xffff)
123 return false;
124
125 if (efuse_w[MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA] != 0)
126 return false;
127
128 if (efuse_w[MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE] == 0xffff)
129 return false;
130
131 return true;
132 }
133
134 static void
mt76x2_apply_cal_free_data(struct mt76x2_dev * dev,u8 * efuse)135 mt76x2_apply_cal_free_data(struct mt76x2_dev *dev, u8 *efuse)
136 {
137 #define GROUP_5G(_id) \
138 MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
139 MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1, \
140 MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
141 MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1
142
143 static const u8 cal_free_bytes[] = {
144 MT_EE_XTAL_TRIM_1,
145 MT_EE_TX_POWER_EXT_PA_5G + 1,
146 MT_EE_TX_POWER_0_START_2G,
147 MT_EE_TX_POWER_0_START_2G + 1,
148 MT_EE_TX_POWER_1_START_2G,
149 MT_EE_TX_POWER_1_START_2G + 1,
150 GROUP_5G(0),
151 GROUP_5G(1),
152 GROUP_5G(2),
153 GROUP_5G(3),
154 GROUP_5G(4),
155 GROUP_5G(5),
156 MT_EE_RF_2G_TSSI_OFF_TXPOWER,
157 MT_EE_RF_2G_RX_HIGH_GAIN + 1,
158 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN,
159 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN + 1,
160 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN,
161 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN + 1,
162 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN,
163 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN + 1,
164 };
165 u8 *eeprom = dev->mt76.eeprom.data;
166 u8 prev_grp0[4] = {
167 eeprom[MT_EE_TX_POWER_0_START_5G],
168 eeprom[MT_EE_TX_POWER_0_START_5G + 1],
169 eeprom[MT_EE_TX_POWER_1_START_5G],
170 eeprom[MT_EE_TX_POWER_1_START_5G + 1]
171 };
172 u16 val;
173 int i;
174
175 if (!mt76x2_has_cal_free_data(dev, efuse))
176 return;
177
178 for (i = 0; i < ARRAY_SIZE(cal_free_bytes); i++) {
179 int offset = cal_free_bytes[i];
180
181 eeprom[offset] = efuse[offset];
182 }
183
184 if (!(efuse[MT_EE_TX_POWER_0_START_5G] |
185 efuse[MT_EE_TX_POWER_0_START_5G + 1]))
186 memcpy(eeprom + MT_EE_TX_POWER_0_START_5G, prev_grp0, 2);
187 if (!(efuse[MT_EE_TX_POWER_1_START_5G] |
188 efuse[MT_EE_TX_POWER_1_START_5G + 1]))
189 memcpy(eeprom + MT_EE_TX_POWER_1_START_5G, prev_grp0 + 2, 2);
190
191 val = get_unaligned_le16(efuse + MT_EE_BT_RCAL_RESULT);
192 if (val != 0xffff)
193 eeprom[MT_EE_BT_RCAL_RESULT] = val & 0xff;
194
195 val = get_unaligned_le16(efuse + MT_EE_BT_VCDL_CALIBRATION);
196 if (val != 0xffff)
197 eeprom[MT_EE_BT_VCDL_CALIBRATION + 1] = val >> 8;
198
199 val = get_unaligned_le16(efuse + MT_EE_BT_PMUCFG);
200 if (val != 0xffff)
201 eeprom[MT_EE_BT_PMUCFG] = val & 0xff;
202 }
203
mt76x2_check_eeprom(struct mt76x2_dev * dev)204 static int mt76x2_check_eeprom(struct mt76x2_dev *dev)
205 {
206 u16 val = get_unaligned_le16(dev->mt76.eeprom.data);
207
208 if (!val)
209 val = get_unaligned_le16(dev->mt76.eeprom.data + MT_EE_PCI_ID);
210
211 switch (val) {
212 case 0x7662:
213 case 0x7612:
214 return 0;
215 default:
216 dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n", val);
217 return -EINVAL;
218 }
219 }
220
221 static int
mt76x2_eeprom_load(struct mt76x2_dev * dev)222 mt76x2_eeprom_load(struct mt76x2_dev *dev)
223 {
224 void *efuse;
225 bool found;
226 int ret;
227
228 ret = mt76_eeprom_init(&dev->mt76, MT7662_EEPROM_SIZE);
229 if (ret < 0)
230 return ret;
231
232 found = ret;
233 if (found)
234 found = !mt76x2_check_eeprom(dev);
235
236 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, MT7662_EEPROM_SIZE,
237 GFP_KERNEL);
238 dev->mt76.otp.size = MT7662_EEPROM_SIZE;
239 if (!dev->mt76.otp.data)
240 return -ENOMEM;
241
242 efuse = dev->mt76.otp.data;
243
244 if (mt76x2_get_efuse_data(dev, efuse, MT7662_EEPROM_SIZE))
245 goto out;
246
247 if (found) {
248 mt76x2_apply_cal_free_data(dev, efuse);
249 } else {
250 /* FIXME: check if efuse data is complete */
251 found = true;
252 memcpy(dev->mt76.eeprom.data, efuse, MT7662_EEPROM_SIZE);
253 }
254
255 out:
256 if (!found)
257 return -ENOENT;
258
259 return 0;
260 }
261
262 static inline int
mt76x2_sign_extend(u32 val,unsigned int size)263 mt76x2_sign_extend(u32 val, unsigned int size)
264 {
265 bool sign = val & BIT(size - 1);
266
267 val &= BIT(size - 1) - 1;
268
269 return sign ? val : -val;
270 }
271
272 static inline int
mt76x2_sign_extend_optional(u32 val,unsigned int size)273 mt76x2_sign_extend_optional(u32 val, unsigned int size)
274 {
275 bool enable = val & BIT(size);
276
277 return enable ? mt76x2_sign_extend(val, size) : 0;
278 }
279
280 static bool
field_valid(u8 val)281 field_valid(u8 val)
282 {
283 return val != 0 && val != 0xff;
284 }
285
286 static void
mt76x2_set_rx_gain_group(struct mt76x2_dev * dev,u8 val)287 mt76x2_set_rx_gain_group(struct mt76x2_dev *dev, u8 val)
288 {
289 s8 *dest = dev->cal.rx.high_gain;
290
291 if (!field_valid(val)) {
292 dest[0] = 0;
293 dest[1] = 0;
294 return;
295 }
296
297 dest[0] = mt76x2_sign_extend(val, 4);
298 dest[1] = mt76x2_sign_extend(val >> 4, 4);
299 }
300
301 static void
mt76x2_set_rssi_offset(struct mt76x2_dev * dev,int chain,u8 val)302 mt76x2_set_rssi_offset(struct mt76x2_dev *dev, int chain, u8 val)
303 {
304 s8 *dest = dev->cal.rx.rssi_offset;
305
306 if (!field_valid(val)) {
307 dest[chain] = 0;
308 return;
309 }
310
311 dest[chain] = mt76x2_sign_extend_optional(val, 7);
312 }
313
314 static enum mt76x2_cal_channel_group
mt76x2_get_cal_channel_group(int channel)315 mt76x2_get_cal_channel_group(int channel)
316 {
317 if (channel >= 184 && channel <= 196)
318 return MT_CH_5G_JAPAN;
319 if (channel <= 48)
320 return MT_CH_5G_UNII_1;
321 if (channel <= 64)
322 return MT_CH_5G_UNII_2;
323 if (channel <= 114)
324 return MT_CH_5G_UNII_2E_1;
325 if (channel <= 144)
326 return MT_CH_5G_UNII_2E_2;
327 return MT_CH_5G_UNII_3;
328 }
329
330 static u8
mt76x2_get_5g_rx_gain(struct mt76x2_dev * dev,u8 channel)331 mt76x2_get_5g_rx_gain(struct mt76x2_dev *dev, u8 channel)
332 {
333 enum mt76x2_cal_channel_group group;
334
335 group = mt76x2_get_cal_channel_group(channel);
336 switch (group) {
337 case MT_CH_5G_JAPAN:
338 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN);
339 case MT_CH_5G_UNII_1:
340 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8;
341 case MT_CH_5G_UNII_2:
342 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN);
343 case MT_CH_5G_UNII_2E_1:
344 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8;
345 case MT_CH_5G_UNII_2E_2:
346 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN);
347 default:
348 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8;
349 }
350 }
351
mt76x2_read_rx_gain(struct mt76x2_dev * dev)352 void mt76x2_read_rx_gain(struct mt76x2_dev *dev)
353 {
354 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
355 int channel = chan->hw_value;
356 s8 lna_5g[3], lna_2g;
357 u8 lna;
358 u16 val;
359
360 if (chan->band == NL80211_BAND_2GHZ)
361 val = mt76x2_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN) >> 8;
362 else
363 val = mt76x2_get_5g_rx_gain(dev, channel);
364
365 mt76x2_set_rx_gain_group(dev, val);
366
367 if (chan->band == NL80211_BAND_2GHZ) {
368 val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_2G_0);
369 mt76x2_set_rssi_offset(dev, 0, val);
370 mt76x2_set_rssi_offset(dev, 1, val >> 8);
371 } else {
372 val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_5G_0);
373 mt76x2_set_rssi_offset(dev, 0, val);
374 mt76x2_set_rssi_offset(dev, 1, val >> 8);
375 }
376
377 val = mt76x2_eeprom_get(dev, MT_EE_LNA_GAIN);
378 lna_2g = val & 0xff;
379 lna_5g[0] = val >> 8;
380
381 val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_2G_1);
382 lna_5g[1] = val >> 8;
383
384 val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_5G_1);
385 lna_5g[2] = val >> 8;
386
387 if (!field_valid(lna_5g[1]))
388 lna_5g[1] = lna_5g[0];
389
390 if (!field_valid(lna_5g[2]))
391 lna_5g[2] = lna_5g[0];
392
393 dev->cal.rx.mcu_gain = (lna_2g & 0xff);
394 dev->cal.rx.mcu_gain |= (lna_5g[0] & 0xff) << 8;
395 dev->cal.rx.mcu_gain |= (lna_5g[1] & 0xff) << 16;
396 dev->cal.rx.mcu_gain |= (lna_5g[2] & 0xff) << 24;
397
398 val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1);
399 if (val & MT_EE_NIC_CONF_1_LNA_EXT_2G)
400 lna_2g = 0;
401 if (val & MT_EE_NIC_CONF_1_LNA_EXT_5G)
402 memset(lna_5g, 0, sizeof(lna_5g));
403
404 if (chan->band == NL80211_BAND_2GHZ)
405 lna = lna_2g;
406 else if (channel <= 64)
407 lna = lna_5g[0];
408 else if (channel <= 128)
409 lna = lna_5g[1];
410 else
411 lna = lna_5g[2];
412
413 if (lna == 0xff)
414 lna = 0;
415
416 dev->cal.rx.lna_gain = mt76x2_sign_extend(lna, 8);
417 }
418 EXPORT_SYMBOL_GPL(mt76x2_read_rx_gain);
419
420 static s8
mt76x2_rate_power_val(u8 val)421 mt76x2_rate_power_val(u8 val)
422 {
423 if (!field_valid(val))
424 return 0;
425
426 return mt76x2_sign_extend_optional(val, 7);
427 }
428
mt76x2_get_rate_power(struct mt76x2_dev * dev,struct mt76_rate_power * t,struct ieee80211_channel * chan)429 void mt76x2_get_rate_power(struct mt76x2_dev *dev, struct mt76_rate_power *t,
430 struct ieee80211_channel *chan)
431 {
432 bool is_5ghz;
433 u16 val;
434
435 is_5ghz = chan->band == NL80211_BAND_5GHZ;
436
437 memset(t, 0, sizeof(*t));
438
439 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_CCK);
440 t->cck[0] = t->cck[1] = mt76x2_rate_power_val(val);
441 t->cck[2] = t->cck[3] = mt76x2_rate_power_val(val >> 8);
442
443 if (is_5ghz)
444 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_6M);
445 else
446 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_6M);
447 t->ofdm[0] = t->ofdm[1] = mt76x2_rate_power_val(val);
448 t->ofdm[2] = t->ofdm[3] = mt76x2_rate_power_val(val >> 8);
449
450 if (is_5ghz)
451 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_24M);
452 else
453 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_24M);
454 t->ofdm[4] = t->ofdm[5] = mt76x2_rate_power_val(val);
455 t->ofdm[6] = t->ofdm[7] = mt76x2_rate_power_val(val >> 8);
456
457 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS0);
458 t->ht[0] = t->ht[1] = mt76x2_rate_power_val(val);
459 t->ht[2] = t->ht[3] = mt76x2_rate_power_val(val >> 8);
460
461 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS4);
462 t->ht[4] = t->ht[5] = mt76x2_rate_power_val(val);
463 t->ht[6] = t->ht[7] = mt76x2_rate_power_val(val >> 8);
464
465 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS8);
466 t->ht[8] = t->ht[9] = mt76x2_rate_power_val(val);
467 t->ht[10] = t->ht[11] = mt76x2_rate_power_val(val >> 8);
468
469 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS12);
470 t->ht[12] = t->ht[13] = mt76x2_rate_power_val(val);
471 t->ht[14] = t->ht[15] = mt76x2_rate_power_val(val >> 8);
472
473 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS0);
474 t->vht[0] = t->vht[1] = mt76x2_rate_power_val(val);
475 t->vht[2] = t->vht[3] = mt76x2_rate_power_val(val >> 8);
476
477 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS4);
478 t->vht[4] = t->vht[5] = mt76x2_rate_power_val(val);
479 t->vht[6] = t->vht[7] = mt76x2_rate_power_val(val >> 8);
480
481 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS8);
482 if (!is_5ghz)
483 val >>= 8;
484 t->vht[8] = t->vht[9] = mt76x2_rate_power_val(val >> 8);
485 }
486 EXPORT_SYMBOL_GPL(mt76x2_get_rate_power);
487
mt76x2_get_max_rate_power(struct mt76_rate_power * r)488 int mt76x2_get_max_rate_power(struct mt76_rate_power *r)
489 {
490 int i;
491 s8 ret = 0;
492
493 for (i = 0; i < sizeof(r->all); i++)
494 ret = max(ret, r->all[i]);
495
496 return ret;
497 }
498 EXPORT_SYMBOL_GPL(mt76x2_get_max_rate_power);
499
500 static void
mt76x2_get_power_info_2g(struct mt76x2_dev * dev,struct mt76x2_tx_power_info * t,struct ieee80211_channel * chan,int chain,int offset)501 mt76x2_get_power_info_2g(struct mt76x2_dev *dev, struct mt76x2_tx_power_info *t,
502 struct ieee80211_channel *chan, int chain, int offset)
503 {
504 int channel = chan->hw_value;
505 int delta_idx;
506 u8 data[6];
507 u16 val;
508
509 if (channel < 6)
510 delta_idx = 3;
511 else if (channel < 11)
512 delta_idx = 4;
513 else
514 delta_idx = 5;
515
516 mt76x2_eeprom_copy(dev, offset, data, sizeof(data));
517
518 t->chain[chain].tssi_slope = data[0];
519 t->chain[chain].tssi_offset = data[1];
520 t->chain[chain].target_power = data[2];
521 t->chain[chain].delta = mt76x2_sign_extend_optional(data[delta_idx], 7);
522
523 val = mt76x2_eeprom_get(dev, MT_EE_RF_2G_TSSI_OFF_TXPOWER);
524 t->target_power = val >> 8;
525 }
526
527 static void
mt76x2_get_power_info_5g(struct mt76x2_dev * dev,struct mt76x2_tx_power_info * t,struct ieee80211_channel * chan,int chain,int offset)528 mt76x2_get_power_info_5g(struct mt76x2_dev *dev, struct mt76x2_tx_power_info *t,
529 struct ieee80211_channel *chan, int chain, int offset)
530 {
531 int channel = chan->hw_value;
532 enum mt76x2_cal_channel_group group;
533 int delta_idx;
534 u16 val;
535 u8 data[5];
536
537 group = mt76x2_get_cal_channel_group(channel);
538 offset += group * MT_TX_POWER_GROUP_SIZE_5G;
539
540 if (channel >= 192)
541 delta_idx = 4;
542 else if (channel >= 184)
543 delta_idx = 3;
544 else if (channel < 44)
545 delta_idx = 3;
546 else if (channel < 52)
547 delta_idx = 4;
548 else if (channel < 58)
549 delta_idx = 3;
550 else if (channel < 98)
551 delta_idx = 4;
552 else if (channel < 106)
553 delta_idx = 3;
554 else if (channel < 116)
555 delta_idx = 4;
556 else if (channel < 130)
557 delta_idx = 3;
558 else if (channel < 149)
559 delta_idx = 4;
560 else if (channel < 157)
561 delta_idx = 3;
562 else
563 delta_idx = 4;
564
565 mt76x2_eeprom_copy(dev, offset, data, sizeof(data));
566
567 t->chain[chain].tssi_slope = data[0];
568 t->chain[chain].tssi_offset = data[1];
569 t->chain[chain].target_power = data[2];
570 t->chain[chain].delta = mt76x2_sign_extend_optional(data[delta_idx], 7);
571
572 val = mt76x2_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN);
573 t->target_power = val & 0xff;
574 }
575
mt76x2_get_power_info(struct mt76x2_dev * dev,struct mt76x2_tx_power_info * t,struct ieee80211_channel * chan)576 void mt76x2_get_power_info(struct mt76x2_dev *dev,
577 struct mt76x2_tx_power_info *t,
578 struct ieee80211_channel *chan)
579 {
580 u16 bw40, bw80;
581
582 memset(t, 0, sizeof(*t));
583
584 bw40 = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
585 bw80 = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80);
586
587 if (chan->band == NL80211_BAND_5GHZ) {
588 bw40 >>= 8;
589 mt76x2_get_power_info_5g(dev, t, chan, 0,
590 MT_EE_TX_POWER_0_START_5G);
591 mt76x2_get_power_info_5g(dev, t, chan, 1,
592 MT_EE_TX_POWER_1_START_5G);
593 } else {
594 mt76x2_get_power_info_2g(dev, t, chan, 0,
595 MT_EE_TX_POWER_0_START_2G);
596 mt76x2_get_power_info_2g(dev, t, chan, 1,
597 MT_EE_TX_POWER_1_START_2G);
598 }
599
600 if (mt76x2_tssi_enabled(dev) || !field_valid(t->target_power))
601 t->target_power = t->chain[0].target_power;
602
603 t->delta_bw40 = mt76x2_rate_power_val(bw40);
604 t->delta_bw80 = mt76x2_rate_power_val(bw80);
605 }
606 EXPORT_SYMBOL_GPL(mt76x2_get_power_info);
607
mt76x2_get_temp_comp(struct mt76x2_dev * dev,struct mt76x2_temp_comp * t)608 int mt76x2_get_temp_comp(struct mt76x2_dev *dev, struct mt76x2_temp_comp *t)
609 {
610 enum nl80211_band band = dev->mt76.chandef.chan->band;
611 u16 val, slope;
612 u8 bounds;
613
614 memset(t, 0, sizeof(*t));
615
616 if (!mt76x2_temp_tx_alc_enabled(dev))
617 return -EINVAL;
618
619 if (!mt76x2_ext_pa_enabled(dev, band))
620 return -EINVAL;
621
622 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G) >> 8;
623 t->temp_25_ref = val & 0x7f;
624 if (band == NL80211_BAND_5GHZ) {
625 slope = mt76x2_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_5G);
626 bounds = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G);
627 } else {
628 slope = mt76x2_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_2G);
629 bounds = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80) >> 8;
630 }
631
632 t->high_slope = slope & 0xff;
633 t->low_slope = slope >> 8;
634 t->lower_bound = 0 - (bounds & 0xf);
635 t->upper_bound = (bounds >> 4) & 0xf;
636
637 return 0;
638 }
639 EXPORT_SYMBOL_GPL(mt76x2_get_temp_comp);
640
mt76x2_ext_pa_enabled(struct mt76x2_dev * dev,enum nl80211_band band)641 bool mt76x2_ext_pa_enabled(struct mt76x2_dev *dev, enum nl80211_band band)
642 {
643 u16 conf0 = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_0);
644
645 if (band == NL80211_BAND_5GHZ)
646 return !(conf0 & MT_EE_NIC_CONF_0_PA_INT_5G);
647 else
648 return !(conf0 & MT_EE_NIC_CONF_0_PA_INT_2G);
649 }
650 EXPORT_SYMBOL_GPL(mt76x2_ext_pa_enabled);
651
mt76x2_eeprom_init(struct mt76x2_dev * dev)652 int mt76x2_eeprom_init(struct mt76x2_dev *dev)
653 {
654 int ret;
655
656 ret = mt76x2_eeprom_load(dev);
657 if (ret)
658 return ret;
659
660 mt76x2_eeprom_parse_hw_cap(dev);
661 mt76x2_eeprom_get_macaddr(dev);
662 mt76_eeprom_override(&dev->mt76);
663 dev->mt76.macaddr[0] &= ~BIT(1);
664
665 return 0;
666 }
667 EXPORT_SYMBOL_GPL(mt76x2_eeprom_init);
668
669 MODULE_LICENSE("Dual BSD/GPL");
670
