1 /*
2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/delay.h>
18 #include "mt76x2.h"
19 #include "mt76x2_eeprom.h"
20 #include "mt76x2_mcu.h"
21
22 static void
mt76x2_mac_pbf_init(struct mt76x2_dev * dev)23 mt76x2_mac_pbf_init(struct mt76x2_dev *dev)
24 {
25 u32 val;
26
27 val = MT_PBF_SYS_CTRL_MCU_RESET |
28 MT_PBF_SYS_CTRL_DMA_RESET |
29 MT_PBF_SYS_CTRL_MAC_RESET |
30 MT_PBF_SYS_CTRL_PBF_RESET |
31 MT_PBF_SYS_CTRL_ASY_RESET;
32
33 mt76_set(dev, MT_PBF_SYS_CTRL, val);
34 mt76_clear(dev, MT_PBF_SYS_CTRL, val);
35
36 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
37 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
38 }
39
40 static void
mt76x2_fixup_xtal(struct mt76x2_dev * dev)41 mt76x2_fixup_xtal(struct mt76x2_dev *dev)
42 {
43 u16 eep_val;
44 s8 offset = 0;
45
46 eep_val = mt76x2_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
47
48 offset = eep_val & 0x7f;
49 if ((eep_val & 0xff) == 0xff)
50 offset = 0;
51 else if (eep_val & 0x80)
52 offset = 0 - offset;
53
54 eep_val >>= 8;
55 if (eep_val == 0x00 || eep_val == 0xff) {
56 eep_val = mt76x2_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
57 eep_val &= 0xff;
58
59 if (eep_val == 0x00 || eep_val == 0xff)
60 eep_val = 0x14;
61 }
62
63 eep_val &= 0x7f;
64 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
65 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
66
67 eep_val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
68 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
69 case 0:
70 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
71 break;
72 case 1:
73 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
74 break;
75 default:
76 break;
77 }
78 }
79
80 static void
mt76x2_init_beacon_offsets(struct mt76x2_dev * dev)81 mt76x2_init_beacon_offsets(struct mt76x2_dev *dev)
82 {
83 u16 base = MT_BEACON_BASE;
84 u32 regs[4] = {};
85 int i;
86
87 for (i = 0; i < 16; i++) {
88 u16 addr = dev->beacon_offsets[i];
89
90 regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4));
91 }
92
93 for (i = 0; i < 4; i++)
94 mt76_wr(dev, MT_BCN_OFFSET(i), regs[i]);
95 }
96
mt76x2_mac_reset(struct mt76x2_dev * dev,bool hard)97 static int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
98 {
99 static const u8 null_addr[ETH_ALEN] = {};
100 const u8 *macaddr = dev->mt76.macaddr;
101 u32 val;
102 int i, k;
103
104 if (!mt76x2_wait_for_mac(dev))
105 return -ETIMEDOUT;
106
107 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
108
109 val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
110 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
111 MT_WPDMA_GLO_CFG_RX_DMA_EN |
112 MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
113 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
114 val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
115
116 mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
117
118 mt76x2_mac_pbf_init(dev);
119 mt76_write_mac_initvals(dev);
120 mt76x2_fixup_xtal(dev);
121
122 mt76_clear(dev, MT_MAC_SYS_CTRL,
123 MT_MAC_SYS_CTRL_RESET_CSR |
124 MT_MAC_SYS_CTRL_RESET_BBP);
125
126 if (is_mt7612(dev))
127 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
128
129 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
130 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
131
132 mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
133 mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
134 usleep_range(5000, 10000);
135 mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
136
137 mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
138 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
139
140 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(macaddr));
141 mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(macaddr + 4));
142
143 mt76_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(macaddr));
144 mt76_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(macaddr + 4) |
145 FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 beacons */
146 MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT);
147
148 /* Fire a pre-TBTT interrupt 8 ms before TBTT */
149 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
150 8 << 4);
151 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
152 MT_DFS_GP_INTERVAL);
153 mt76_wr(dev, MT_INT_TIMER_EN, 0);
154
155 mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xffff);
156 if (!hard)
157 return 0;
158
159 for (i = 0; i < 256 / 32; i++)
160 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);
161
162 for (i = 0; i < 256; i++)
163 mt76x2_mac_wcid_setup(dev, i, 0, NULL);
164
165 for (i = 0; i < MT_MAX_VIFS; i++)
166 mt76x2_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL);
167
168 for (i = 0; i < 16; i++)
169 for (k = 0; k < 4; k++)
170 mt76x2_mac_shared_key_setup(dev, i, k, NULL);
171
172 for (i = 0; i < 8; i++) {
173 mt76x2_mac_set_bssid(dev, i, null_addr);
174 mt76x2_mac_set_beacon(dev, i, NULL);
175 }
176
177 for (i = 0; i < 16; i++)
178 mt76_rr(dev, MT_TX_STAT_FIFO);
179
180 mt76_wr(dev, MT_CH_TIME_CFG,
181 MT_CH_TIME_CFG_TIMER_EN |
182 MT_CH_TIME_CFG_TX_AS_BUSY |
183 MT_CH_TIME_CFG_RX_AS_BUSY |
184 MT_CH_TIME_CFG_NAV_AS_BUSY |
185 MT_CH_TIME_CFG_EIFS_AS_BUSY |
186 FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
187
188 mt76x2_init_beacon_offsets(dev);
189
190 mt76x2_set_tx_ackto(dev);
191
192 return 0;
193 }
194
mt76x2_mac_start(struct mt76x2_dev * dev)195 int mt76x2_mac_start(struct mt76x2_dev *dev)
196 {
197 int i;
198
199 for (i = 0; i < 16; i++)
200 mt76_rr(dev, MT_TX_AGG_CNT(i));
201
202 for (i = 0; i < 16; i++)
203 mt76_rr(dev, MT_TX_STAT_FIFO);
204
205 memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats));
206
207 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
208 wait_for_wpdma(dev);
209 usleep_range(50, 100);
210
211 mt76_set(dev, MT_WPDMA_GLO_CFG,
212 MT_WPDMA_GLO_CFG_TX_DMA_EN |
213 MT_WPDMA_GLO_CFG_RX_DMA_EN);
214
215 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
216
217 mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
218
219 mt76_wr(dev, MT_MAC_SYS_CTRL,
220 MT_MAC_SYS_CTRL_ENABLE_TX |
221 MT_MAC_SYS_CTRL_ENABLE_RX);
222
223 mt76x2_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
224 MT_INT_TX_STAT);
225
226 return 0;
227 }
228
mt76x2_mac_resume(struct mt76x2_dev * dev)229 void mt76x2_mac_resume(struct mt76x2_dev *dev)
230 {
231 mt76_wr(dev, MT_MAC_SYS_CTRL,
232 MT_MAC_SYS_CTRL_ENABLE_TX |
233 MT_MAC_SYS_CTRL_ENABLE_RX);
234 }
235
236 static void
mt76x2_power_on_rf_patch(struct mt76x2_dev * dev)237 mt76x2_power_on_rf_patch(struct mt76x2_dev *dev)
238 {
239 mt76_set(dev, 0x10130, BIT(0) | BIT(16));
240 udelay(1);
241
242 mt76_clear(dev, 0x1001c, 0xff);
243 mt76_set(dev, 0x1001c, 0x30);
244
245 mt76_wr(dev, 0x10014, 0x484f);
246 udelay(1);
247
248 mt76_set(dev, 0x10130, BIT(17));
249 udelay(125);
250
251 mt76_clear(dev, 0x10130, BIT(16));
252 udelay(50);
253
254 mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
255 }
256
257 static void
mt76x2_power_on_rf(struct mt76x2_dev * dev,int unit)258 mt76x2_power_on_rf(struct mt76x2_dev *dev, int unit)
259 {
260 int shift = unit ? 8 : 0;
261
262 /* Enable RF BG */
263 mt76_set(dev, 0x10130, BIT(0) << shift);
264 udelay(10);
265
266 /* Enable RFDIG LDO/AFE/ABB/ADDA */
267 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
268 udelay(10);
269
270 /* Switch RFDIG power to internal LDO */
271 mt76_clear(dev, 0x10130, BIT(2) << shift);
272 udelay(10);
273
274 mt76x2_power_on_rf_patch(dev);
275
276 mt76_set(dev, 0x530, 0xf);
277 }
278
279 static void
mt76x2_power_on(struct mt76x2_dev * dev)280 mt76x2_power_on(struct mt76x2_dev *dev)
281 {
282 u32 val;
283
284 /* Turn on WL MTCMOS */
285 mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
286
287 val = MT_WLAN_MTC_CTRL_STATE_UP |
288 MT_WLAN_MTC_CTRL_PWR_ACK |
289 MT_WLAN_MTC_CTRL_PWR_ACK_S;
290
291 mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
292
293 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
294 udelay(10);
295
296 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
297 udelay(10);
298
299 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
300 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
301
302 /* Turn on AD/DA power down */
303 mt76_clear(dev, 0x11204, BIT(3));
304
305 /* WLAN function enable */
306 mt76_set(dev, 0x10080, BIT(0));
307
308 /* Release BBP software reset */
309 mt76_clear(dev, 0x10064, BIT(18));
310
311 mt76x2_power_on_rf(dev, 0);
312 mt76x2_power_on_rf(dev, 1);
313 }
314
mt76x2_set_tx_ackto(struct mt76x2_dev * dev)315 void mt76x2_set_tx_ackto(struct mt76x2_dev *dev)
316 {
317 u8 ackto, sifs, slottime = dev->slottime;
318
319 /* As defined by IEEE 802.11-2007 17.3.8.6 */
320 slottime += 3 * dev->coverage_class;
321 mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG,
322 MT_BKOFF_SLOT_CFG_SLOTTIME, slottime);
323
324 sifs = mt76_get_field(dev, MT_XIFS_TIME_CFG,
325 MT_XIFS_TIME_CFG_OFDM_SIFS);
326
327 ackto = slottime + sifs;
328 mt76_rmw_field(dev, MT_TX_TIMEOUT_CFG,
329 MT_TX_TIMEOUT_CFG_ACKTO, ackto);
330 }
331
mt76x2_init_hardware(struct mt76x2_dev * dev)332 int mt76x2_init_hardware(struct mt76x2_dev *dev)
333 {
334 static const u16 beacon_offsets[16] = {
335 /* 1024 byte per beacon */
336 0xc000,
337 0xc400,
338 0xc800,
339 0xcc00,
340 0xd000,
341 0xd400,
342 0xd800,
343 0xdc00,
344
345 /* BSS idx 8-15 not used for beacons */
346 0xc000,
347 0xc000,
348 0xc000,
349 0xc000,
350 0xc000,
351 0xc000,
352 0xc000,
353 0xc000,
354 };
355 u32 val;
356 int ret;
357
358 dev->beacon_offsets = beacon_offsets;
359 tasklet_init(&dev->pre_tbtt_tasklet, mt76x2_pre_tbtt_tasklet,
360 (unsigned long) dev);
361
362 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
363 val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
364 MT_WPDMA_GLO_CFG_BIG_ENDIAN |
365 MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
366 val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
367 mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
368
369 mt76x2_reset_wlan(dev, true);
370 mt76x2_power_on(dev);
371
372 ret = mt76x2_eeprom_init(dev);
373 if (ret)
374 return ret;
375
376 ret = mt76x2_mac_reset(dev, true);
377 if (ret)
378 return ret;
379
380 dev->rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
381
382 ret = mt76x2_dma_init(dev);
383 if (ret)
384 return ret;
385
386 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
387 ret = mt76x2_mac_start(dev);
388 if (ret)
389 return ret;
390
391 ret = mt76x2_mcu_init(dev);
392 if (ret)
393 return ret;
394
395 mt76x2_mac_stop(dev, false);
396
397 return 0;
398 }
399
mt76x2_stop_hardware(struct mt76x2_dev * dev)400 void mt76x2_stop_hardware(struct mt76x2_dev *dev)
401 {
402 cancel_delayed_work_sync(&dev->cal_work);
403 cancel_delayed_work_sync(&dev->mac_work);
404 mt76x2_mcu_set_radio_state(dev, false);
405 mt76x2_mac_stop(dev, false);
406 }
407
mt76x2_cleanup(struct mt76x2_dev * dev)408 void mt76x2_cleanup(struct mt76x2_dev *dev)
409 {
410 tasklet_disable(&dev->dfs_pd.dfs_tasklet);
411 tasklet_disable(&dev->pre_tbtt_tasklet);
412 mt76x2_stop_hardware(dev);
413 mt76x2_dma_cleanup(dev);
414 mt76x2_mcu_cleanup(dev);
415 }
416
mt76x2_alloc_device(struct device * pdev)417 struct mt76x2_dev *mt76x2_alloc_device(struct device *pdev)
418 {
419 static const struct mt76_driver_ops drv_ops = {
420 .txwi_size = sizeof(struct mt76x2_txwi),
421 .update_survey = mt76x2_update_channel,
422 .tx_prepare_skb = mt76x2_tx_prepare_skb,
423 .tx_complete_skb = mt76x2_tx_complete_skb,
424 .rx_skb = mt76x2_queue_rx_skb,
425 .rx_poll_complete = mt76x2_rx_poll_complete,
426 .sta_ps = mt76x2_sta_ps,
427 };
428 struct mt76x2_dev *dev;
429 struct mt76_dev *mdev;
430
431 mdev = mt76_alloc_device(sizeof(*dev), &mt76x2_ops);
432 if (!mdev)
433 return NULL;
434
435 dev = container_of(mdev, struct mt76x2_dev, mt76);
436 mdev->dev = pdev;
437 mdev->drv = &drv_ops;
438 mutex_init(&dev->mutex);
439 spin_lock_init(&dev->irq_lock);
440
441 return dev;
442 }
443
mt76x2_regd_notifier(struct wiphy * wiphy,struct regulatory_request * request)444 static void mt76x2_regd_notifier(struct wiphy *wiphy,
445 struct regulatory_request *request)
446 {
447 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
448 struct mt76x2_dev *dev = hw->priv;
449
450 mt76x2_dfs_set_domain(dev, request->dfs_region);
451 }
452
453 static const struct ieee80211_iface_limit if_limits[] = {
454 {
455 .max = 1,
456 .types = BIT(NL80211_IFTYPE_ADHOC)
457 }, {
458 .max = 8,
459 .types = BIT(NL80211_IFTYPE_STATION) |
460 #ifdef CONFIG_MAC80211_MESH
461 BIT(NL80211_IFTYPE_MESH_POINT) |
462 #endif
463 BIT(NL80211_IFTYPE_AP)
464 },
465 };
466
467 static const struct ieee80211_iface_combination if_comb[] = {
468 {
469 .limits = if_limits,
470 .n_limits = ARRAY_SIZE(if_limits),
471 .max_interfaces = 8,
472 .num_different_channels = 1,
473 .beacon_int_infra_match = true,
474 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
475 BIT(NL80211_CHAN_WIDTH_20) |
476 BIT(NL80211_CHAN_WIDTH_40) |
477 BIT(NL80211_CHAN_WIDTH_80),
478 }
479 };
480
mt76x2_led_set_config(struct mt76_dev * mt76,u8 delay_on,u8 delay_off)481 static void mt76x2_led_set_config(struct mt76_dev *mt76, u8 delay_on,
482 u8 delay_off)
483 {
484 struct mt76x2_dev *dev = container_of(mt76, struct mt76x2_dev,
485 mt76);
486 u32 val;
487
488 val = MT_LED_STATUS_DURATION(0xff) |
489 MT_LED_STATUS_OFF(delay_off) |
490 MT_LED_STATUS_ON(delay_on);
491
492 mt76_wr(dev, MT_LED_S0(mt76->led_pin), val);
493 mt76_wr(dev, MT_LED_S1(mt76->led_pin), val);
494
495 val = MT_LED_CTRL_REPLAY(mt76->led_pin) |
496 MT_LED_CTRL_KICK(mt76->led_pin);
497 if (mt76->led_al)
498 val |= MT_LED_CTRL_POLARITY(mt76->led_pin);
499 mt76_wr(dev, MT_LED_CTRL, val);
500 }
501
mt76x2_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)502 static int mt76x2_led_set_blink(struct led_classdev *led_cdev,
503 unsigned long *delay_on,
504 unsigned long *delay_off)
505 {
506 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
507 led_cdev);
508 u8 delta_on, delta_off;
509
510 delta_off = max_t(u8, *delay_off / 10, 1);
511 delta_on = max_t(u8, *delay_on / 10, 1);
512
513 mt76x2_led_set_config(mt76, delta_on, delta_off);
514 return 0;
515 }
516
mt76x2_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)517 static void mt76x2_led_set_brightness(struct led_classdev *led_cdev,
518 enum led_brightness brightness)
519 {
520 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
521 led_cdev);
522
523 if (!brightness)
524 mt76x2_led_set_config(mt76, 0, 0xff);
525 else
526 mt76x2_led_set_config(mt76, 0xff, 0);
527 }
528
mt76x2_register_device(struct mt76x2_dev * dev)529 int mt76x2_register_device(struct mt76x2_dev *dev)
530 {
531 struct ieee80211_hw *hw = mt76_hw(dev);
532 struct wiphy *wiphy = hw->wiphy;
533 void *status_fifo;
534 int fifo_size;
535 int i, ret;
536
537 fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x2_tx_status));
538 status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);
539 if (!status_fifo)
540 return -ENOMEM;
541
542 kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
543 INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate);
544 INIT_DELAYED_WORK(&dev->mac_work, mt76x2_mac_work);
545
546 mt76x2_init_device(dev);
547
548 ret = mt76x2_init_hardware(dev);
549 if (ret)
550 return ret;
551
552 for (i = 0; i < ARRAY_SIZE(dev->macaddr_list); i++) {
553 u8 *addr = dev->macaddr_list[i].addr;
554
555 memcpy(addr, dev->mt76.macaddr, ETH_ALEN);
556
557 if (!i)
558 continue;
559
560 addr[0] |= BIT(1);
561 addr[0] ^= ((i - 1) << 2);
562 }
563 wiphy->addresses = dev->macaddr_list;
564 wiphy->n_addresses = ARRAY_SIZE(dev->macaddr_list);
565
566 wiphy->iface_combinations = if_comb;
567 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
568
569 wiphy->reg_notifier = mt76x2_regd_notifier;
570
571 wiphy->interface_modes =
572 BIT(NL80211_IFTYPE_STATION) |
573 BIT(NL80211_IFTYPE_AP) |
574 #ifdef CONFIG_MAC80211_MESH
575 BIT(NL80211_IFTYPE_MESH_POINT) |
576 #endif
577 BIT(NL80211_IFTYPE_ADHOC);
578
579 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
580
581 mt76x2_dfs_init_detector(dev);
582
583 /* init led callbacks */
584 dev->mt76.led_cdev.brightness_set = mt76x2_led_set_brightness;
585 dev->mt76.led_cdev.blink_set = mt76x2_led_set_blink;
586
587 ret = mt76_register_device(&dev->mt76, true, mt76x2_rates,
588 ARRAY_SIZE(mt76x2_rates));
589 if (ret)
590 goto fail;
591
592 mt76x2_init_debugfs(dev);
593 mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband);
594 mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband);
595
596 return 0;
597
598 fail:
599 mt76x2_stop_hardware(dev);
600 return ret;
601 }
602
603
604
